TI1 DRA746BPGABCRQ1 Dra75x, dra74x infotainment applications processor silicon revision 2.0 Datasheet

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DRA744, DRA745, DRA746
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
DRA75x, DRA74x Infotainment Applications Processor
Silicon Revision 2.0
1 Device Overview
1.1
Features
1
• Architecture Designed for Infotainment
Applications
• Video, Image, and Graphics Processing Support
– Full-HD Video (1920 × 1080p, 60 fps)
– Multiple Video Input and Video Output
– 2D and 3D Graphics
• ARM® Dual Cortex®-A15 Microprocessor
Subsystem
• Up to two C66x™ Floating-Point VLIW DSP
– Fully Object-Code Compatible With C67x™ and
C64x+™
– Up to Thirty-two 16 x 16-Bit Fixed-Point
Multiplies per Cycle
• Up to 2.5MB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• Two DDR2/DDR3/DDR3L Memory Interface
(EMIF) Modules
– Supports up to DDR2-800 and DDR3-1066
– Up to 2GB Supported per EMIF
• Two ARM® Dual Cortex®-M4 Image Processing
Units (IPUs)
• Up to Two Embedded Vision Engines (EVEs)
• IVA Subsystem
• Display Subsystem
– Display Controller With DMA Engine and up to
Three Pipelines
– HDMI™ Encoder: HDMI 1.4a and DVI 1.0
Compliant
• Video Processing Engine (VPE)
• 2D-Graphics Accelerator (BB2D) Subsystem
– Vivante™ GC320 Core
• Dual-Core PowerVR® SGX544™ 3D GPU
• Three Video Input Port (VIP) Modules
– Support for up to 10 Multiplexed Input Ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA)
Controller
• 2-Port Gigabit Ethernet (GMAC)
• Sixteen 32-Bit General-Purpose Timers
• 32-Bit MPU Watchdog Timer
• Five Inter-Integrated Circuit (I2C) Ports
• HDQ™/1-Wire® Interface
• SATA Interface
• Media Local Bus (MLB) Subsystem
• Ten Configurable UART/IrDA/CIR Modules
• Four Multichannel Serial Peripheral Interfaces
(MCSPIs)
• Quad SPI (QSPI)
• Multichannel Audio Serial Port (MCASP)
• SuperSpeed USB 3.0 Dual-Role Device
• PCI-Express® 2.0 Subsystems With Two 5-Gbps
Lanes
– One 2-lane Gen2-Compliant Port
– or Two 1-lane Gen2-Compliant Ports
• Dual Controller Area Network (DCAN) Modules
– CAN 2.0B Protocol
• Up to 247 General-Purpose I/O (GPIO) Pins
• Real-Time Clock Subsystem (RTCSS)
• Devise security features
– Hardware Crypto accelerators and DMA
– Firewalls
– JTAG lock
– Secure keys
– Secure ROM and boot
• Power, Reset, and Clock Management
• On-Chip Debug With CTools Technology
• 28-nm CMOS Technology
• 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA
(ABC)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
1.2
•
•
•
•
Applications
Human-Machine Interface (HMI)
Navigation
Digital and Analog Radio
Rear Seat Entertainment
1.3
www.ti.com
•
•
•
Multimedia Playback
Web Browsing
ADAS Integration
Description
DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense
processing needs of the modern infotainment-enabled automobile experiences.
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers
(ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming,
and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully
integrated mixed processor solution. The devices also combine programmable video processing with a
highly integrated peripheral set.
Programmability is provided by dual-core ARM Cortex-A15 RISC CPUs with Neon™ extension, TI C66x
VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The ARM allows
developers to keep control functions separate from other algorithms programmed on the DSP and
coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the ARM, DSP, and EVE coprocessor,
including C compilers and a debugging interface for visibility into source code.
The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.
Device Information
2
PART NUMBER
PACKAGE
BODY SIZE
DRA74x
FCBGA (760)
23.0 mm × 23.0 mm
DRA75x
FCBGA (760)
23.0 mm × 23.0 mm
Device Overview
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1.4
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Functional Block Diagram
Figure 1-1 is functional block diagram for the device.
DRA75x / DRA74x
(2x ARM
Cortex–A15)
Co-Processor
DSP1 C66x
Co-Processors
GPU
(Dual-Core
SGX544 3D)
VIP2
2x MMU
sDMA
LCD1
1xGFX / 3xVID
Blend / Scale
VIP3
VPE
HD ATL
2x VCP
Display Subsystem
IPU1
(Dual Cortex–M4)
(GC 320 2D)
VIP1
EDMA
DSP2 C66x
Co-Processors
BB2D
Radio Accelerators
2x EVE
Analytic
Processors
IVA HD
1080p Video
MPU
IPU2
(Dual Cortex–M4)
LCD2
LCD3
HDMI 1.4a
High-Speed Interconnect
Connectivity
System
Spinlock
Timers x16
1x USB 3.0
Mailbox x13
WDT
FS/HS/SS
Dual Mode w/PHY
GPIO x8
RTC SS
PWM SS x3
HDQ
KBD
3x USB 2.0
Dual Mode FS/HS
1x w/ PHY
2x w/ ULPI
QSPI
McSPI x4
McASP x8
DCAN x2
I2C x5
MediaLB /
MOST150
GMAC AVB
Program/Data Storage
Serial Interfaces
UART x10
PCIe SS x2
MMC / SD x4
256KiB
ROM
up to 2.5MiB
RAM w/ ECC GPMC / ELM
SATA
OCMC
DMM
EMIF x2
2x 32b
(NAND/NOR/
DDR2/3 w/ECC(1)
Async)
intro_001
Figure 1-1. DRA75x, DRA74x Block Diagram
(1) ECC is only available on EMIF1.
Device Overview
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
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Table of Contents
1
Device Overview ......................................... 1
7.12
Inter-Integrated Circuit Interface (I2C) ............. 260
1.1
Features .............................................. 1
1.2
Applications ........................................... 2
7.13
7.14
1.3
Description ............................................ 2
HDQ / 1-Wire Interface (HDQ1W) ................. 263
Universal Asynchronous Receiver Transmitter
(UART) ............................................. 265
7.15
Multichannel Serial Peripheral Interface (MCSPI)
266
7.16
Quad Serial Peripheral Interface (QSPI)
..........
Multichannel Audio Serial Port (McASP) ..........
Universal Serial Bus (USB) ........................
Serial Advanced Technology Attachment (SATA) .
272
........................... 3
Revision History ......................................... 5
Device Comparison ..................................... 6
3.1
Device Comparison Table ............................ 6
3.2
Related Products ..................................... 9
Terminal Configuration and Functions ............ 10
4.1
Terminal Assignment ................................ 10
4.2
Ball Characteristics .................................. 11
4.3
Multiplexing Characteristics ......................... 80
4.4
Signal Descriptions .................................. 98
Specifications ......................................... 140
5.1
Absolute Maximum Ratings........................ 140
5.2
ESD Ratings ....................................... 141
5.3
Power on Hour (POH) Limits ...................... 141
5.4
Recommended Operating Conditions ............. 143
5.5
Operating Performance Points ..................... 146
5.6
Power Consumption Summary .................... 167
5.7
Electrical Characteristics ........................... 168
5.8
Thermal Resistance Characteristics ............... 177
5.9
Power Supply Sequences ......................... 178
Clock Specifications ................................. 190
6.1
Input Clock Specifications ......................... 191
6.2
DPLLs, DLLs Specifications ....................... 199
1.4
2
3
4
5
6
7
Functional Block Diagram
Timing Requirements and Switching
Characteristics ........................................ 203
7.1
Timing Test Conditions ............................ 203
7.2
Interface Clock Specifications
.....................
Timing Parameters and Information ...............
7.3
7.4
4
203
203
Recommended Clock and Control Signal Transition
Behavior............................................ 205
7.17
7.18
7.19
7.20
8
298
300
Peripheral Component Interconnect Express
(PCIe) .............................................. 300
7.21
Controller Area Network Interface (DCAN) ........ 301
7.22
Ethernet Interface (GMAC_SW) ................... 302
7.23
Media Local Bus (MLB) interface .................. 312
7.24
eMMC/SD/SDIO
7.25
General-Purpose Interface (GPIO) ................ 342
7.26
Audio Tracking Logic (ATL) ........................ 342
7.27
System and Miscellaneous interfaces ............. 343
7.28
Test Interfaces ..................................... 343
...................................
315
Applications, Implementation, and Layout ...... 348
........................................
8.1
Introduction
8.2
Power Optimizations ............................... 349
8.3
Core Power Domains .............................. 363
8.4
Single-Ended Interfaces
8.5
Differential Interfaces
8.6
8.7
9
278
...........................
..............................
Clock Routing Guidelines ..........................
348
374
376
397
DDR2/DDR3 Board Design and Layout
Guidelines .......................................... 399
Device and Documentation Support .............. 434
9.1
Device Nomenclature .............................. 434
9.2
Tools and Software ................................ 436
9.3
Documentation Support ............................ 436
9.4
Receiving Notification of Documentation Updates. 437
9.5
Related Links
9.6
Community Resources............................. 438
......................................
437
7.5
Virtual and Manual I/O Timing Modes ............. 205
7.6
Video Input Ports (VIP) ............................ 208
9.7
Trademarks ........................................ 438
7.7
7.8
Display Subsystem – Video Output Ports ......... 226
Display Subsystem – High-Definition Multimedia
Interface (HDMI) ................................... 237
9.8
Electrostatic Discharge Caution
9.9
Export Control Notice .............................. 438
9.10
Glossary............................................ 438
7.9
External Memory Interface (EMIF)................. 237
7.10
General-Purpose Memory Controller (GPMC) ..... 237
7.11
Timers .............................................. 259
Table of Contents
...................
438
10 Mechanical Packaging and Orderable
Information ............................................. 439
10.1
Mechanical Data ................................... 439
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
2 Revision History
Changes from December 18, 2015 to April 14, 2016 (from * Revision (December 2015) to A Revision)
•
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•
•
•
•
•
•
•
•
•
•
•
•
•
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•
•
•
•
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Page
Device security features are added in Device Overview section ............................................................... 1
Added ”Related Products” section .................................................................................................. 9
Added footnotes to the vout3_* signals which are muxed on vddshv6 power balls in Table 4-2 Ball Characteristics . 13
Added footnotes to the vout3_* signals which are muxed on vddshv6 power balls in Table 4-5 DSS Signal
Descriptions ........................................................................................................................ 103
Signal Descriptions updated to remove redundancy .......................................................................... 106
Text in ESD Ratings table clarified .............................................................................................. 141
Note (5) in Table 5-7 is updated ................................................................................................. 148
Added “Power Consumption Summary” section ............................................................................... 167
Notes 9, 12 and 13 in Figure 5-1 are updated ................................................................................. 180
Notes 9, 12 and 13 in Figure 5-4 are updated ................................................................................. 187
Fixed some of the descriptions on GPMC and QSPI Manual Modes names in Table 7-2 “Modes Summary” ....... 205
Added new Manual Modes for: VOUT1, VOUT2 IOSET1, VOUT2 IOSET2 and VOUT3. Removed
DSS_VIRTUAL1 ................................................................................................................... 205
New Timing information available for: Video Input Ports (VIP), Display Subsystem – Video Output Ports,
Multichannel Serial Peripheral Interface (MCSPI), Quad Serial Peripheral Interface (QSPI) and eMMC/SD/SDIO. . 205
Corrected references for McASP Virtual modes in Table 7-2 “Modes Summary” ........................................ 205
Removed all vin4b_* signals from Table 7-9 Manual Functions Mapping for VIP2 ....................................... 216
A caution and two notes are added in “Display Subsystem – Video Output Ports“ section stating that VOUT
signals are recommended to use the default SLEWCONTROL settings. Slow SLEWCONTROL should be used
instead. .............................................................................................................................. 226
Flipped the "Parameter" entries for D5 and D6 in Table 7-16 ............................................................... 226
Added footnotes to the vout3_* signals which muxed on vddshv6 power balls in Table 7-18 VOUT3 IOSETs. ..... 229
A new caution is added in “Quad Serial Peripheral Interface” subsection ................................................. 272
QSPI time value Q7 direction on Figure 7-37 through Figure 7-40 is updated to start prior CS ....................... 274
Added Table 7-53 through Table 7-60 to clarify the MCASP Virtual Timing Mode usage ............................... 284
An update is performed in the “Peripheral Component Interconnect Express (PCIe)” section. ......................... 300
Updated information for TPS65917 as supported PMIC ..................................................................... 367
Aligning "Device and Documentation Support" section with new flow ...................................................... 434
Аdded SR 2.0 in Table 9-1 ....................................................................................................... 435
Added ”Related Links” section ................................................................................................... 437
Revision History
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
3 Device Comparison
3.1
Device Comparison Table
Table 3-1 shows a comparison between devices, highlighting the differences.
Table 3-1. Device Comparison
Device
Features
Jacinto 6 EX
Jacinto 6 EP
Jacinto 6
DRA756
DRA755
DRA754
DRA752
DRA751
DRA750
DRA746
DRA745
DRA744
P
L
J
P
L
J
P
L
J
Processors/ Accelerators
Speed Grades
MPU core 0
Yes
Yes
Yes
MPU core 1
Yes
Yes
Yes
DSP1
Yes
Yes
Yes
DSP2
Yes
Yes
No
BB2D
Yes
Yes
Yes
VOUT1
Yes
Yes
Yes
VOUT2
Yes
Yes
Yes
VOUT3
Yes
Yes
Yes
HDMI
Yes
Yes
Yes
EVE1
Yes
No
No
EVE2
Yes
No
No
ARM Dual Cortex-M4 Image Processing Unit
(IPU)
IPU1
Yes
Yes
Yes
IPU2
Yes
Yes
Yes
Image Video Accelarator (IVA)
IVA
Yes
Yes
Yes
SGX544 Dual-Core 3D Graphics Processing
Unit (GPU)
GPU
Yes
Yes
Yes
ARM Dual Cortex-A15 Microprocessor
Subsystem (MPU)
C66x VLIW DSP
BitBLT 2D Hardware Acceleration Engine
(BB2D)
Display Subsystem
Embedded Vision Engine (EVE)
6
Device Comparison
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 3-1. Device Comparison (continued)
Device
Features
Jacinto 6 EX
DRA756
DRA755
Jacinto 6 EP
DRA754
DRA752
DRA751
Jacinto 6
DRA750
DRA746
DRA745
DRA744
vin1a
Yes
Yes
vin1b
Yes
Yes
No
vin2a
Yes
Yes
Yes
vin2b
Yes
Yes
Yes
vin3a
Yes
Yes
Yes
vin3b
Yes
Yes
Yes
vin4a
Yes
Yes
Yes
vin4b
Yes
Yes
Yes
vin5a
Yes
Yes
No
vin6a
Yes
Yes
No
VPE
Yes
Yes
Yes
OCMC_RAM1
512KB
512KB
512KB
OCMC_RAM2
1MB
No
No
OCMC_RAM3
1MB
No
No
GPMC
Yes
Yes
Yes
EMIF1
up to 2GB (with optional SECDED)
up to 2GB (with optional SECDED)
up to 2GB
EMIF2
up to 2GB
up to 2GB
up to 2GB
DMM
Yes
Yes
Yes
ATL
Yes
Yes
Yes
VCP1
Yes
Yes
Yes
VCP2
Yes
Yes
Yes
DCAN1
Yes
Yes
Yes
DCAN2
Yes
Yes
Yes
Enhanced DMA (EDMA)
EDMA
Yes
Yes
Yes
System DMA (DMA_SYSTEM)
DMA_SYSTEM
Yes
Yes
Yes
GMAC_SW[0]
MII, RMII, or RGMII
MII, RMII, or RGMII
MII, RMII, or RGMII
GMAC_SW[1]
MII, RMII, or RGMII
MII, RMII, or RGMII
MII, RMII, or RGMII
up to 247
up to 247
up to 247
VIP1
Video Input Port (VIP)
VIP2
VIP3
Video Processing Engine (VPE)
No
Program/Data Storage
On-Chip Shared Memory (RAM)
General-Purpose Memory Controller (GPMC)
DDR2/DDR3 Memory Controller (2)
Dynamic Memory Manager (DMM)
Radio Support
Audio Tracking Logic (ATL)
Viterbi Coprocessor (VCP)
Peripherals
Dual Controller Area Network Interface (DCAN)
Ethernet Subsystem (Ethernet SS)
General-Purpose I/O (GPIO)
GPIO
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Device Comparison
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DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
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Table 3-1. Device Comparison (continued)
Device
Features
Jacinto 6 EX
DRA756
Inter-Integrated Circuit Interface (I2C)
I2C
System Mailbox Module
MAILBOX
Media Local Bus Subsystem (MLBSS)
MLB
Multichannel Audio Serial Port (McASP)
MultiMedia Card/Secure Digital/Secure Digital
Input Output Interface (MMC/SD/SDIO)
PCI-Express 2.0 Port with Integrated PHY
DRA755
5
Jacinto 6 EP
DRA754
DRA752
DRA751
Jacinto 6
DRA750
5
DRA746
DRA745
13
13
13
Yes
Yes
Yes
McASP1
16 serializers
16 serializers
16 serializers
McASP2
16 serializers
16 serializers
16 serializers
McASP3
4 serializers
4 serializers
4 serializers
McASP4
4 serializers
4 serializers
4 serializers
McASP5
4 serializers
4 serializers
4 serializers
McASP6
4 serializers
4 serializers
4 serializers
McASP7
4 serializers
4 serializers
4 serializers
McASP8
4 serializers
4 serializers
4 serializers
MMC1
1x UHSI 4b
1x UHSI 4b
1x UHSI 4b
MMC2
1x eMMC 8b
1x eMMC 8b
1x eMMC 8b
MMC3
1x SDIO 8b
1x SDIO 8b
1x SDIO 8b
MMC4
1x SDIO 4b
1x SDIO 4b
1x SDIO 4b
PCIe_SS1
Yes
Yes
Yes (Single-lane mode)
PCIe_SS2
Yes
Yes
No
SATA
SATA
Yes
Yes
Yes
Real-Time Clock Subsystem (RTCSS)
RTCSS
Yes
Yes
Yes
4
4
4
Multichannel Serial Peripheral Interface (McSPI) McSPI
HDQ1W
HDQ1W
Yes
Yes
Yes
Quad SPI (QSPI)
QSPI
Yes
Yes
Yes
Spinlock Module
SPINLOCK
Yes
Yes
Yes
Keyboard Controller (KBD)
KBD
Yes
Yes
Yes
Timers, General-Purpose
TIMER
16
16
16
Timer, Watchdog
WATCHDOG
TIMER
Yes
Yes
Yes
PWMSS1
Yes
Yes
Yes
PWMSS2
Yes
Yes
Yes
PWMSS3
Yes
Yes
Yes
10
10
10
Pulse-Width Modulation Subsystem (PWMSS)
Universal Asynchronous Receiver/Transmitter
(UART)
8
Device Comparison
DRA744
5
UART
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 3-1. Device Comparison (continued)
Device
Features
Jacinto 6 EX
DRA756
Universal Serial Bus (USB3.0)
Universal Serial Bus (USB2.0)
DRA755
Jacinto 6 EP
DRA754
DRA752
DRA751
Jacinto 6
DRA750
DRA746
DRA745
USB1
(SuperSpeed,
Dual-Role-Device
[DRD])
Yes
Yes
Yes
USB2 (HighSpeed,
Dual-Role-Device
[DRD], with
embedded HS
PHY)
Yes
Yes
Yes
USB3 (HighSpeed,
OTG2.0, with
ULPI)
Yes
Yes
Yes
USB4 (HighSpeed,
OTG2.0, with
ULPI)
Yes
Yes
Yes(1)
DRA744
(1) USB4 will not be supported on some pin-compatible roadmap devices. USB3 will be mapped to these balls instead. Pin compatibility can be maintained in the future by either not using
USB4, or via software change to use USB4 on this device, but USB3 on these balls in the future.
(2) In the Unified L3 memory map, there is maximum of 2GB of SDRAM space which is available to all L3 initiators including MPU (MPU, GPU, DSP, IVA, DMA, etc). Typically this space is
interleaved across both EMIFs to optimize memory performance. If a system populates > 2GB of physical memory, that additional addressable space can be accessed only by the MPU
via the ARM V7 Large Physical Address Extensions (LPAE).
3.2
Related Products
Automotive Processors
DRAx Infotainment SoCs The "Jacinto 6" family of infotainment processors (DRA7xx), paired with robust software and ecosystem offering bring
unprecedented feature-rich, in-vehicle infotainment, instrument cluster and telematics features to the next generation automobiles.
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Device Comparison
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DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
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4 Terminal Configuration and Functions
4.1
Terminal Assignment
Figure 4-1 shows the ball locations for the 760 plastic ball grid array (PBGA) package and are used in
conjunction with Table 4-2 through Table 4-34 to locate signal names and ball grid numbers.
Figure 4-1. ABC S-PBGA-N760 Package (Bottom View)
NOTE
The following bottom balls are not connected: AF7 / AF10 / AF13 / AF16 / AF19 / AE4 /
AE25 / AB26 / W3 / W26 / T3 / T26 / N3 / N26 / K3 / K26 / G3 / D4 / D25 / C10 / C13 / C16 /
C19 / C22.
These balls do not exist on the package.
4.1.1
Unused Balls Connection Requirements
This section describes the Unused/Reserved balls connection requirements.
NOTE
The following balls are reserved: A27 / K14 / Y5 / Y10 / B28
These balls must be left unconnected.
NOTE
All unused power supply balls must be supplied with the voltages specified in the
Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are
included in Section 4.4, Signal Descriptions.
Table 4-1. Unused Balls Specific Connection Requirements
10
Balls
Connection Requirements
AE15 / AC15 / AE14 / D20 / AD17 / AC17 / AC16 / AB16 / V27
These balls must be connected to GND through an external pull
resistor if unused
E20 / D21 / E23 / C20 / C21 / AF14 / V28 / F18
These balls must be connect to the corresponding power supply
through an external pull resistor if unused
Terminal Configuration and Functions
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-1. Unused Balls Specific Connection Requirements (continued)
Balls
Connection Requirements
AB17
These balls must be connected to F22 (porz) if unused
NOTE
All other unused signal balls with a Pad Configuration Register can be left unconnected with
their internal pullup or pulldown resistor enabled.
NOTE
All other unused signal balls without Pad Configuration Register can be left unconnected.
4.2
Ball Characteristics
Table 4-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list
describes the table column headers:
1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the
signal name in muxmode 0).
NOTE
Table 4-2 does not take into account the subsystem multiplexing signals. Subsystem
multiplexing signals are described in Section 4.4, Signal Descriptions.
NOTE
In the Driver off mode, the buffer is configured in high-impedance.
4. 74x: This column shows if the functionality is applicable for DRA74x devices. Note that the ball
characteristics table presents the functionality of DRA75x device. An empty box means "Yes".
5. MUXMODE: Multiplexing mode number:
(a) MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function
mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily
the default muxmode.
NOTE
The default mode is the mode at the release of the reset; also see the RESET REL.
MUXMODE column.
(b) MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some
muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only
MUXMODE values which correspond to defined functions should be used.
6. TYPE: Signal type and direction:
– I = Input
– O = Output
– IO = Input or Output
– D = Open drain
– DS = Differential Signaling
– A = Analog
– PWR = Power
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– GND = Ground
– CAP = LDO Capacitor
7. BALL RESET STATE: The state of the terminal at power-on reset:
– drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
– drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
– OFF: High-impedance
– PD: High-impedance with an active pulldown resistor
– PU: High-impedance with an active pullup resistor
8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also
mapped to the PRCM SYS_WARM_OUT_RST signal)
– drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
– drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated)
– drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
– OFF: High-impedance
– PD: High-impedance with an active pulldown resistor
– PU: High-impedance with an active pullup resistor
NOTE
For more information on the CORE_PWRON_RET_RST reset signal and its reset sources,
see the Power Reset and Clock Management / PRCM Reset Management Functional
Description section of the Device TRM.
9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the
rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
10. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply).
11. POWER: The voltage supply that powers the terminal IO buffers.
12. HYS: Indicates if the input buffer is with hysteresis:
– Yes: With hysteresis
– No: Without hysteresis
An empty box means "Yes".
NOTE
For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.
13. BUFFER TYPE: Drive strength of the associated output buffer.
NOTE
For programmable buffer strength:
– The default value is given in Table 4-2.
– A note describes all possible values according to the selected muxmode.
14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.
Pullup and pulldown resistors can be enabled or disabled via software.
15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or
logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
– 0: Logic 0 driven on the peripheral's input signal port.
– 1: Logic 1 driven on the peripheral's input signal port.
– blank: Not Applicable.
12
Terminal Configuration and Functions
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NOTE
Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration. (Hi-Z mode is
not an input signal.)
NOTE
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that
pad’s behavior is undefined. This should be avoided.
CAUTION
Peripherals exposed in Ball Characteristics Table and Multiplexing
Characteristics Table represent functionality of a DRA75x device. Not all
exposed peripherals are supported on DRA7xx devices. For peripherals
supported on DRA7xx family of products please refer to Table 3-1, Device
Comparison.
NOTE
Some of the DDR1 and DDR2 signals have an additional state change at the release of porz.
The state that the signals change to at the release of porz is as follows:
drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_nck, ddr1_casn, ddr1_rasn,
ddr1_wen, ddr1_ba[2:0], ddr1_a[15:0], ddr2_csn0, ddr2_ck, ddr2_nck, ddr2_casn, ddr2_rasn,
ddr2_wen, ddr2_ba[2:0], ddr2_a[15:0].
OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0],
ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0], ddr2_dqm[3:0], ddr2_dqs[3:0], ddr2_dqsn[3:0],
ddr2_d[31:0].
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
K9
cap_vbbldo_dspeve
cap_vbbldo_dspeve
CAP
Y14
cap_vbbldo_gpu
cap_vbbldo_gpu
CAP
R20
cap_vbbldo_iva
cap_vbbldo_iva
CAP
J16
cap_vbbldo_mpu
cap_vbbldo_mpu
CAP
L9
cap_vddram_core1
cap_vddram_core1
CAP
J19
cap_vddram_core2
cap_vddram_core2
CAP
Y15
cap_vddram_core3
cap_vddram_core3
CAP
P19
cap_vddram_core4
cap_vddram_core4
CAP
Y16
cap_vddram_core5
cap_vddram_core5
CAP
J10
cap_vddram_dspeve1
cap_vddram_dspeve1
CAP
J9
cap_vddram_dspeve2
cap_vddram_dspeve2
CAP
Y13
cap_vddram_gpu
cap_vddram_gpu
CAP
T20
cap_vddram_iva
cap_vddram_iva
CAP
K16
cap_vddram_mpu1
cap_vddram_mpu1
CAP
K19
cap_vddram_mpu2
cap_vddram_mpu2
G19
dcan1_rx
dcan1_rx
0
IO
uart8_txd
2
O
mmc2_sdwp
3
I
sata1_led
4
O
hdmi1_cec
6
IO
gpio1_15
14
IO
Driver off
15
I
dcan1_tx
0
IO
uart8_rxd
2
I
mmc2_sdcd
3
I
hdmi1_hpd
6
I
gpio1_14
14
IO
Driver off
15
I
G20
dcan1_tx
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
CAP
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
1
ddr1_a0
ddr1_a0
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AC19
ddr1_a1
ddr1_a1
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AD21
ddr1_a10
ddr1_a10
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AD22
ddr1_a11
ddr1_a11
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AC21
ddr1_a12
ddr1_a12
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
Terminal Configuration and Functions
1
0
AD20
14
DSIS [15]
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
AF18
ddr1_a13
ddr1_a13
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AE17
ddr1_a14
ddr1_a14
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AD18
ddr1_a15
ddr1_a15
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AC20
ddr1_a2
ddr1_a2
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AB19
ddr1_a3
ddr1_a3
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AF21
ddr1_a4
ddr1_a4
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AH22
ddr1_a5
ddr1_a5
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AG23
ddr1_a6
ddr1_a6
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AE21
ddr1_a7
ddr1_a7
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AF22
ddr1_a8
ddr1_a8
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AE22
ddr1_a9
ddr1_a9
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AF17
ddr1_ba0
ddr1_ba0
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AE18
ddr1_ba1
ddr1_ba1
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AB18
ddr1_ba2
ddr1_ba2
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AC18
ddr1_casn
ddr1_casn
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AG24
ddr1_ck
ddr1_ck
0
O
PD
drive clk
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AG22
ddr1_cke
ddr1_cke
0
O
PD
drive 0
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AH23
ddr1_csn0
ddr1_csn0
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AF25
ddr1_d0
ddr1_d0
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AF26
ddr1_d1
ddr1_d1
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AG27
ddr1_d10
ddr1_d10
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AF28
ddr1_d11
ddr1_d11
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AE26
ddr1_d12
ddr1_d12
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
DSIS [15]
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
AC25
ddr1_d13
ddr1_d13
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AC24
ddr1_d14
ddr1_d14
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AD25
ddr1_d15
ddr1_d15
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
V20
ddr1_d16
ddr1_d16
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
W20
ddr1_d17
ddr1_d17
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AB28
ddr1_d18
ddr1_d18
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AC28
ddr1_d19
ddr1_d19
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AG26
ddr1_d2
ddr1_d2
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AC27
ddr1_d20
ddr1_d20
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
Y19
ddr1_d21
ddr1_d21
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AB27
ddr1_d22
ddr1_d22
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
Y20
ddr1_d23
ddr1_d23
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AA23
ddr1_d24
ddr1_d24
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
Y22
ddr1_d25
ddr1_d25
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
Y23
ddr1_d26
ddr1_d26
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AA24
ddr1_d27
ddr1_d27
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
Y24
ddr1_d28
ddr1_d28
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AA26
ddr1_d29
ddr1_d29
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AH26
ddr1_d3
ddr1_d3
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AA25
ddr1_d30
ddr1_d30
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AA28
ddr1_d31
ddr1_d31
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AF24
ddr1_d4
ddr1_d4
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AE24
ddr1_d5
ddr1_d5
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
16
Terminal Configuration and Functions
DSIS [15]
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
AF23
ddr1_d6
ddr1_d6
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AE23
ddr1_d7
ddr1_d7
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AC23
ddr1_d8
ddr1_d8
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AF27
ddr1_d9
ddr1_d9
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AD23
ddr1_dqm0
ddr1_dqm0
0
O
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AB23
ddr1_dqm1
ddr1_dqm1
0
O
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AC26
ddr1_dqm2
ddr1_dqm2
0
O
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AA27
ddr1_dqm3
ddr1_dqm3
0
O
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
V26
ddr1_dqm_ecc
ddr1_dqm_ecc
0
O
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AH25
ddr1_dqs0
ddr1_dqs0
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
AE27
ddr1_dqs1
ddr1_dqs1
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
AD27
ddr1_dqs2
ddr1_dqs2
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
Y28
ddr1_dqs3
ddr1_dqs3
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
AG25
ddr1_dqsn0
ddr1_dqsn0
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
AE28
ddr1_dqsn1
ddr1_dqsn1
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
AD28
ddr1_dqsn2
ddr1_dqsn2
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
Y27
ddr1_dqsn3
ddr1_dqsn3
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
V28
ddr1_dqsn_ecc
ddr1_dqsn_ecc
No
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
V27
ddr1_dqs_ecc
ddr1_dqs_ecc
No
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
NA
LVCMOS
DDR
Pux/PDy
W22
ddr1_ecc_d0
ddr1_ecc_d0
No
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
V23
ddr1_ecc_d1
ddr1_ecc_d1
No
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
W19
ddr1_ecc_d2
ddr1_ecc_d2
No
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
W23
ddr1_ecc_d3
ddr1_ecc_d3
No
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
No
DSIS [15]
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
Copyright © 2015–2016, Texas Instruments Incorporated
17
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Y25
ddr1_ecc_d4
ddr1_ecc_d4
No
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
V24
ddr1_ecc_d5
ddr1_ecc_d5
No
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
V25
ddr1_ecc_d6
ddr1_ecc_d6
No
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
Y26
ddr1_ecc_d7
ddr1_ecc_d7
No
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AH24
ddr1_nck
ddr1_nck
0
O
PD
drive clk
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AE20
ddr1_odt0
ddr1_odt0
0
O
PD
drive 0
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AF20
ddr1_rasn
ddr1_rasn
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
AG21
ddr1_rst
ddr1_rst
0
O
PD
drive 0
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
Y18
ddr1_vref0
ddr1_vref0
0
PWR
OFF
OFF
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
NA
AH21
ddr1_wen
ddr1_wen
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr1
No
LVCMOS
DDR
Pux/PDy
R25
ddr2_a0
ddr2_a0
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
R26
ddr2_a1
ddr2_a1
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
N23
ddr2_a10
ddr2_a10
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
P26
ddr2_a11
ddr2_a11
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
N28
ddr2_a12
ddr2_a12
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
T22
ddr2_a13
ddr2_a13
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
R22
ddr2_a14
ddr2_a14
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
U22
ddr2_a15
ddr2_a15
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
R28
ddr2_a2
ddr2_a2
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
R27
ddr2_a3
ddr2_a3
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
P23
ddr2_a4
ddr2_a4
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
P22
ddr2_a5
ddr2_a5
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
P25
ddr2_a6
ddr2_a6
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
18
Terminal Configuration and Functions
DSIS [15]
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
N20
ddr2_a7
ddr2_a7
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
P27
ddr2_a8
ddr2_a8
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
N27
ddr2_a9
ddr2_a9
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
U23
ddr2_ba0
ddr2_ba0
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
U27
ddr2_ba1
ddr2_ba1
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
U26
ddr2_ba2
ddr2_ba2
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
U28
ddr2_casn
ddr2_casn
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
T28
ddr2_ck
ddr2_ck
0
O
PD
drive clk
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
U24
ddr2_cke
ddr2_cke
0
O
PD
drive 0
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
P24
ddr2_csn0
ddr2_csn0
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
E26
ddr2_d0
ddr2_d0
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
G25
ddr2_d1
ddr2_d1
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
H24
ddr2_d10
ddr2_d10
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
H26
ddr2_d11
ddr2_d11
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
G26
ddr2_d12
ddr2_d12
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
J25
ddr2_d13
ddr2_d13
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
J26
ddr2_d14
ddr2_d14
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
J24
ddr2_d15
ddr2_d15
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
L22
ddr2_d16
ddr2_d16
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
K20
ddr2_d17
ddr2_d17
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
K21
ddr2_d18
ddr2_d18
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
L23
ddr2_d19
ddr2_d19
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
F25
ddr2_d2
ddr2_d2
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
DSIS [15]
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
Copyright © 2015–2016, Texas Instruments Incorporated
19
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
L24
ddr2_d20
ddr2_d20
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
J23
ddr2_d21
ddr2_d21
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
K22
ddr2_d22
ddr2_d22
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
J20
ddr2_d23
ddr2_d23
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
L27
ddr2_d24
ddr2_d24
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
L26
ddr2_d25
ddr2_d25
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
L25
ddr2_d26
ddr2_d26
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
L28
ddr2_d27
ddr2_d27
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
M23
ddr2_d28
ddr2_d28
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
M24
ddr2_d29
ddr2_d29
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
F24
ddr2_d3
ddr2_d3
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
M25
ddr2_d30
ddr2_d30
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
M26
ddr2_d31
ddr2_d31
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
F26
ddr2_d4
ddr2_d4
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
F27
ddr2_d5
ddr2_d5
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
E27
ddr2_d6
ddr2_d6
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
E28
ddr2_d7
ddr2_d7
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
H23
ddr2_d8
ddr2_d8
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
H25
ddr2_d9
ddr2_d9
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
F28
ddr2_dqm0
ddr2_dqm0
0
O
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
G24
ddr2_dqm1
ddr2_dqm1
0
O
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
K23
ddr2_dqm2
ddr2_dqm2
0
O
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
M22
ddr2_dqm3
ddr2_dqm3
0
O
PU
PU
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
20
Terminal Configuration and Functions
DSIS [15]
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
G28
ddr2_dqs0
ddr2_dqs0
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr2
NA
LVCMOS
DDR
Pux/PDy
H27
ddr2_dqs1
ddr2_dqs1
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr2
NA
LVCMOS
DDR
Pux/PDy
K27
ddr2_dqs2
ddr2_dqs2
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr2
NA
LVCMOS
DDR
Pux/PDy
M28
ddr2_dqs3
ddr2_dqs3
0
IO
PD
PD
1.35/1.5/1.8 vdds_ddr2
NA
LVCMOS
DDR
Pux/PDy
G27
ddr2_dqsn0
ddr2_dqsn0
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
NA
LVCMOS
DDR
Pux/PDy
H28
ddr2_dqsn1
ddr2_dqsn1
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
NA
LVCMOS
DDR
Pux/PDy
K28
ddr2_dqsn2
ddr2_dqsn2
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
NA
LVCMOS
DDR
Pux/PDy
M27
ddr2_dqsn3
ddr2_dqsn3
0
IO
PU
PU
1.35/1.5/1.8 vdds_ddr2
NA
LVCMOS
DDR
Pux/PDy
T27
ddr2_nck
ddr2_nck
0
O
PD
drive clk
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
R23
ddr2_odt0
ddr2_odt0
0
O
PD
drive 0
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
T23
ddr2_rasn
ddr2_rasn
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
R24
ddr2_rst
ddr2_rst
0
O
PD
drive 0
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
N22
ddr2_vref0
ddr2_vref0
0
PWR
OFF
OFF
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
NA
U25
ddr2_wen
ddr2_wen
0
O
PD
drive 1
(OFF)
1.35/1.5/1.8 vdds_ddr2
No
LVCMOS
DDR
Pux/PDy
G21
emu0
emu0
0
IO
PU
PU
0
1.8/3.3
vddshv3
Yes
14
IO
Dual
Voltage
LVCMOS
PU/PD
gpio8_30
emu1
0
IO
PU
PU
0
1.8/3.3
vddshv3
Yes
14
IO
Dual
Voltage
LVCMOS
PU/PD
gpio8_31
gpio6_10
0
IO
PU
PU
15
1.8/3.3
vddshv7
Yes
1
O
Dual
Voltage
LVCMOS
PU/PD
mdio_mclk
i2c3_sda
2
IO
1
usb3_ulpi_d7
3
IO
0
vin2b_hsync1
4
I
D24
AC5
emu1
gpio6_10
vin5a_clk0
9
I
ehrpwm2A
No
10
O
gpio6_10
14
IO
Driver off
15
I
1
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AB4
BALL NAME [2]
gpio6_11
SIGNAL NAME [3]
F20
F21
22
gpio6_14
gpio6_15
gpio6_16
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PU
15
1.8/3.3
POWER
[11]
vddshv7
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
DSIS [15]
0
IO
mdio_d
1
IO
i2c3_scl
2
IO
1
usb3_ulpi_d6
3
IO
0
vin2b_vsync1
4
I
PU/PD
1
9
I
ehrpwm2B
10
O
gpio6_11
14
IO
Driver off
15
I
gpio6_14
0
IO
mcasp1_axr8
1
IO
dcan2_tx
2
IO
1
uart10_rxd
3
I
1
vout2_hsync
6
O
vin4a_hsync0
8
I
0
i2c3_sda
9
IO
1
timer1
10
IO
gpio6_14
14
IO
Driver off
15
I
gpio6_15
0
IO
mcasp1_axr9
1
IO
dcan2_rx
2
IO
uart10_txd
3
O
vout2_vsync
6
O
vin4a_vsync0
8
I
0
i2c3_scl
9
IO
1
timer2
10
IO
gpio6_15
14
IO
Driver off
15
I
gpio6_16
0
IO
mcasp1_axr10
1
IO
vout2_fld
6
O
vin4a_fld0
8
I
clkout1
9
O
timer3
10
IO
gpio6_16
14
IO
Driver off
15
I
Terminal Configuration and Functions
No
PU
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
gpio6_11
vin5a_de0
E21
74x [4]
0
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
0
PU/PD
0
1
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
R6
T9
N9
P9
BALL NAME [2]
gpmc_a0
gpmc_a1
gpmc_a10
gpmc_a11
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
O
I
vout3_d16
3
O
vin4a_d0
4
I
0
vin4b_d0
6
I
0
i2c4_scl
7
IO
1
uart5_rxd
8
I
1
gpio7_3
14
IO
Driver off
15
I
gpmc_a1
0
O
vin3a_d17
2
I
vout3_d17
3
O
vin4a_d1
4
I
0
vin4b_d1
6
I
0
i2c4_sda
7
IO
1
uart5_txd
8
O
gpio7_4
14
IO
Driver off
15
I
gpmc_a10
0
O
vin3a_de0
2
I
vout3_de
3
O
vin4b_clk1
6
I
timer10
7
IO
spi4_d0
8
IO
gpio2_0
14
IO
Driver off
15
I
gpmc_a11
0
O
vin3a_fld0
2
I
vout3_fld
3
O
vin4a_fld0
4
I
0
vin4b_de1
6
I
0
timer9
7
IO
spi4_cs0
8
IO
gpio2_1
14
IO
Driver off
15
I
PD
PD
15
1.8/3.3
vddshv10
vddshv10
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
2
1.8/3.3
vddshv10
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
vin3a_d16
PD
15
HYS [12]
gpmc_a0
PD
PD
POWER
[11]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
0
PU/PD
0
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
P4
R3
T2
U2
U1
24
BALL NAME [2]
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
15
1.8/3.3
POWER
[11]
vddshv10
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
DSIS [15]
gpmc_a12
0
O
vin4a_clk0
4
I
gpmc_a0
5
O
vin4b_fld1
6
I
timer8
7
IO
spi4_cs1
8
IO
1
dma_evt1
9
I
0
gpio2_2
14
IO
Driver off
15
I
gpmc_a13
0
O
qspi1_rtclk
1
I
vin4a_hsync0
4
I
timer7
7
IO
spi4_cs2
8
IO
1
dma_evt2
9
I
0
gpio2_3
14
IO
Driver off
15
I
gpmc_a14
0
O
qspi1_d3
1
I
vin4a_vsync0
4
I
timer6
7
IO
spi4_cs3
8
IO
gpio2_4
14
IO
Driver off
15
I
gpmc_a15
0
O
qspi1_d2
1
I
vin4a_d8
4
I
timer5
7
IO
gpio2_5
14
IO
Driver off
15
I
gpmc_a16
0
O
qspi1_d0
1
IO
vin4a_d9
4
I
gpio2_6
14
IO
Driver off
15
I
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PU/PD
0
0
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
Copyright © 2015–2016, Texas Instruments Incorporated
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
P3
R2
K7
T6
M7
BALL NAME [2]
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a2
gpmc_a20
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv10
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
DSIS [15]
gpmc_a17
0
O
qspi1_d1
1
I
PU/PD
vin4a_d10
4
I
gpio2_7
14
IO
Driver off
15
I
gpmc_a18
0
O
qspi1_sclk
1
O
vin4a_d11
4
I
gpio2_8
14
IO
Driver off
15
I
gpmc_a19
0
O
mmc2_dat4
1
IO
gpmc_a13
2
O
vin4a_d12
4
I
0
vin3b_d0
6
I
0
gpio2_9
14
IO
Driver off
15
I
gpmc_a2
0
O
vin3a_d18
2
I
vout3_d18
3
O
vin4a_d2
4
I
0
vin4b_d2
6
I
0
uart7_rxd
7
I
1
uart5_ctsn
8
I
1
gpio7_5
14
IO
Driver off
15
I
gpmc_a20
0
O
mmc2_dat5
1
IO
gpmc_a14
2
O
vin4a_d13
4
I
0
vin3b_d1
6
I
0
gpio2_10
14
IO
Driver off
15
I
0
0
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
0
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv11
vddshv10
vddshv11
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
1
PU/PD
0
PU/PD
1
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
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www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
J5
K6
J7
J4
J6
26
BALL NAME [2]
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
IO
gpmc_a15
2
O
vin4a_d14
4
I
0
vin3b_d2
6
I
0
gpio2_11
14
IO
Driver off
15
I
gpmc_a22
0
O
mmc2_dat7
1
IO
gpmc_a16
2
O
vin4a_d15
4
I
0
vin3b_d3
6
I
0
gpio2_12
14
IO
Driver off
15
I
gpmc_a23
0
O
mmc2_clk
1
IO
gpmc_a17
2
O
vin4a_fld0
4
I
0
vin3b_d4
6
I
0
gpio2_13
14
IO
Driver off
15
I
gpmc_a24
0
O
mmc2_dat0
1
IO
gpmc_a18
2
O
vin4a_d8
4
I
0
vin3b_d5
6
I
0
gpio2_14
14
IO
Driver off
15
I
gpmc_a25
0
O
mmc2_dat1
1
IO
gpmc_a19
2
O
vin4a_d9
4
I
0
vin3b_d6
6
I
0
gpio2_15
14
IO
Driver off
15
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv11
vddshv11
vddshv11
vddshv11
Yes
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
O
1.8/3.3
vddshv11
PULL
UP/DOWN
TYPE [14]
1
15
1.8/3.3
BUFFER
TYPE [13]
0
PD
15
HYS [12]
mmc2_dat6
PD
PD
POWER
[11]
gpmc_a21
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
1
PU/PD
1
PU/PD
1
PU/PD
1
PU/PD
1
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DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
H4
H5
T7
P6
BALL NAME [2]
gpmc_a26
gpmc_a27
gpmc_a3
gpmc_a4
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
O
IO
gpmc_a20
2
O
vin4a_d10
4
I
0
vin3b_d7
6
I
0
gpio2_16
14
IO
Driver off
15
I
gpmc_a27
0
O
mmc2_dat3
1
IO
gpmc_a21
2
O
vin4a_d11
4
I
0
vin3b_hsync1
6
I
0
gpio2_17
14
IO
Driver off
15
I
gpmc_a3
0
O
qspi1_cs2
1
O
vin3a_d19
2
I
vout3_d19
3
O
vin4a_d3
4
I
0
vin4b_d3
6
I
0
uart7_txd
7
O
uart5_rtsn
8
O
gpio7_6
14
IO
Driver off
15
I
gpmc_a4
0
O
qspi1_cs3
1
O
vin3a_d20
2
I
vout3_d20
3
O
vin4a_d4
4
I
0
vin4b_d4
6
I
0
i2c5_scl
7
IO
1
uart6_rxd
8
I
1
gpio1_26
14
IO
Driver off
15
I
PD
PD
15
1.8/3.3
vddshv11
vddshv10
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
1
1.8/3.3
vddshv11
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
mmc2_dat2
PD
15
HYS [12]
gpmc_a26
PD
PD
POWER
[11]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
1
PU/PD
1
PU/PD
1
0
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
1
0
Terminal Configuration and Functions
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
R9
R5
P5
N7
28
BALL NAME [2]
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
I
vout3_d21
3
O
vin4a_d5
4
I
0
vin4b_d5
6
I
0
i2c5_sda
7
IO
1
uart6_txd
8
O
gpio1_27
14
IO
Driver off
15
I
gpmc_a6
0
O
vin3a_d22
2
I
vout3_d22
3
O
vin4a_d6
4
I
0
vin4b_d6
6
I
0
uart8_rxd
7
I
1
uart6_ctsn
8
I
1
gpio1_28
14
IO
Driver off
15
I
gpmc_a7
0
O
vin3a_d23
2
I
vout3_d23
3
O
vin4a_d7
4
I
0
vin4b_d7
6
I
0
uart8_txd
7
O
uart6_rtsn
8
O
gpio1_29
14
IO
Driver off
15
I
gpmc_a8
0
O
vin3a_hsync0
2
I
vout3_hsync
3
O
vin4b_hsync1
6
I
timer12
7
IO
spi4_sclk
8
IO
gpio1_30
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
O
1.8/3.3
vddshv10
PULL
UP/DOWN
TYPE [14]
2
15
1.8/3.3
BUFFER
TYPE [13]
0
PD
15
HYS [12]
vin3a_d21
PD
PD
POWER
[11]
gpmc_a5
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
0
PU/PD
0
PU/PD
0
PU/PD
0
0
0
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
R4
M6
M2
J1
J2
H1
BALL NAME [2]
gpmc_a9
gpmc_ad0
gpmc_ad1
gpmc_ad10
gpmc_ad11
gpmc_ad12
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
gpmc_a9
0
O
vin3a_vsync0
2
I
vout3_vsync
3
O
vin4b_vsync1
6
I
timer11
7
IO
spi4_d1
8
IO
gpio1_31
14
IO
Driver off
15
I
gpmc_ad0
0
IO
vin3a_d0
2
I
vout3_d0
3
O
gpio1_6
14
IO
sysboot0
15
I
gpmc_ad1
0
IO
vin3a_d1
2
I
vout3_d1
3
O
gpio1_7
14
IO
sysboot1
15
I
gpmc_ad10
0
IO
vin3a_d10
2
I
vout3_d10
3
O
gpio7_28
14
IO
sysboot10
15
I
gpmc_ad11
0
IO
vin3a_d11
2
I
vout3_d11
3
O
gpio7_29
14
IO
sysboot11
15
I
gpmc_ad12
0
IO
vin3a_d12
2
I
vout3_d12
3
O
gpio1_18
14
IO
sysboot12
15
I
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv10
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
DSIS [15]
PU/PD
0
0
0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
Yes
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
0
0
0
0
0
0
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DRA754, DRA755, DRA756
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
J3
H2
H3
L5
M1
L6
L4
30
BALL NAME [2]
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
gpmc_ad13
0
IO
vin3a_d13
2
I
vout3_d13
3
O
gpio1_19
14
IO
sysboot13
15
I
gpmc_ad14
0
IO
vin3a_d14
2
I
vout3_d14
3
O
gpio1_20
14
IO
sysboot14
15
I
gpmc_ad15
0
IO
vin3a_d15
2
I
vout3_d15
3
O
gpio1_21
14
IO
sysboot15
15
I
gpmc_ad2
0
IO
vin3a_d2
2
I
vout3_d2
3
O
gpio1_8
14
IO
sysboot2
15
I
gpmc_ad3
0
IO
vin3a_d3
2
I
vout3_d3
3
O
gpio1_9
14
IO
sysboot3
15
I
gpmc_ad4
0
IO
vin3a_d4
2
I
vout3_d4
3
O
gpio1_10
14
IO
sysboot4
15
I
gpmc_ad5
0
IO
vin3a_d5
2
I
vout3_d5
3
O
gpio1_11
14
IO
sysboot5
15
I
Terminal Configuration and Functions
BALL
RESET
STATE [7]
OFF
OFF
OFF
OFF
OFF
OFF
OFF
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
POWER
[11]
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
HYS [12]
Yes
Yes
Yes
Yes
Yes
Yes
Yes
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
L3
L2
L1
K2
N1
BALL NAME [2]
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_advn_ale
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
OFF
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
IO
I
vout3_d6
3
O
gpio1_12
14
IO
sysboot6
15
I
gpmc_ad7
0
IO
vin3a_d7
2
I
vout3_d7
3
O
gpio1_13
14
IO
sysboot7
15
I
gpmc_ad8
0
IO
vin3a_d8
2
I
vout3_d8
3
O
gpio7_18
14
IO
sysboot8
15
I
gpmc_ad9
0
IO
vin3a_d9
2
I
vout3_d9
3
O
gpio7_19
14
IO
sysboot9
15
I
gpmc_advn_ale
0
O
gpmc_cs6
1
O
clkout2
2
O
gpmc_wait1
3
I
1
vin4a_vsync0
4
I
0
gpmc_a2
5
O
gpmc_a23
6
O
timer3
7
IO
i2c3_sda
8
IO
1
dma_evt2
9
I
0
gpio2_23
14
IO
Driver off
15
I
OFF
OFF
PU
OFF
OFF
PU
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
vddshv10
Yes
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
2
1.8/3.3
vddshv10
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
vin3a_d6
OFF
15
HYS [12]
gpmc_ad6
OFF
OFF
POWER
[11]
0
0
0
0
0
0
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
N6
BALL NAME [2]
gpmc_ben0
SIGNAL NAME [3]
gpmc_ben1
T1
32
gpmc_clk
gpmc_cs0
TYPE [6]
0
O
gpmc_cs4
1
O
No
BALL
RESET
STATE [7]
PU
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PU
15
1.8/3.3
POWER
[11]
vddshv10
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
DSIS [15]
PU/PD
3
I
0
vin3b_de1
6
I
0
timer2
7
IO
dma_evt3
9
I
gpio2_26
14
IO
Driver off
15
I
gpmc_ben1
0
O
gpmc_cs5
1
O
vin1b_de1
P7
MUXMODE
[5]
gpmc_ben0
vin1b_hsync1
M4
74x [4]
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
3
I
0
vin3b_clk1
4
I
0
gpmc_a3
5
O
vin3b_fld1
6
I
timer1
7
IO
dma_evt4
9
I
gpio2_27
14
IO
Driver off
15
I
gpmc_clk
0
IO
gpmc_cs7
1
O
clkout1
2
O
gpmc_wait1
3
I
1
vin4a_hsync0
4
I
0
vin4a_de0
5
I
0
vin3b_clk1
6
I
0
timer4
7
IO
i2c3_scl
8
IO
1
dma_evt1
9
I
0
gpio2_22
14
IO
Driver off
15
I
gpmc_cs0
0
O
gpio2_19
14
IO
Driver off
15
I
Terminal Configuration and Functions
No
0
0
0
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv10
vddshv10
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
0
PU/PD
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
H6
P2
P1
M5
N2
M3
BALL NAME [2]
gpmc_cs1
gpmc_cs2
gpmc_cs3
gpmc_oen_ren
gpmc_wait0
gpmc_wen
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PU
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
O
IO
gpmc_a22
2
O
vin4a_de0
4
I
0
vin3b_vsync1
6
I
0
gpio2_18
14
IO
Driver off
15
I
gpmc_cs2
0
O
qspi1_cs0
1
O
gpio2_20
14
IO
Driver off
15
I
gpmc_cs3
0
O
qspi1_cs1
1
O
vin3a_clk0
2
I
vout3_clk
3
O
gpmc_a1
5
O
gpio2_21
14
IO
Driver off
15
I
gpmc_oen_ren
0
O
gpio2_24
14
IO
Driver off
15
I
gpmc_wait0
0
I
gpio2_28
14
IO
Driver off
15
I
gpmc_wen
0
O
gpio2_25
14
IO
PU
PU
15
1.8/3.3
vddshv10
vddshv10
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
1
1.8/3.3
vddshv11
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
mmc2_cmd
PU
15
HYS [12]
gpmc_cs1
PU
PU
POWER
[11]
PU/PD
1
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
1
1
0
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual
Voltage
LVCMOS
PU/PD
Driver off
15
I
AG16
hdmi1_clockx
hdmi1_clockx
0
O
1.8
vdda_hdmi NA
HDMIPHY
PDy
AH16
hdmi1_clocky
hdmi1_clocky
0
O
1.8
vdda_hdmi NA
HDMIPHY
PDy
AG17
hdmi1_data0x
hdmi1_data0x
0
O
1.8
vdda_hdmi NA
HDMIPHY
PDy
AH17
hdmi1_data0y
hdmi1_data0y
0
O
1.8
vdda_hdmi NA
HDMIPHY
PDy
AG18
hdmi1_data1x
hdmi1_data1x
0
O
1.8
vdda_hdmi NA
HDMIPHY
PDy
AH18
hdmi1_data1y
hdmi1_data1y
0
O
1.8
vdda_hdmi NA
HDMIPHY
PDy
AG19
hdmi1_data2x
hdmi1_data2x
0
O
1.8
vdda_hdmi NA
HDMIPHY
PDy
AH19
hdmi1_data2y
hdmi1_data2y
0
O
1.8
vdda_hdmi NA
HDMIPHY
PDy
1
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
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www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
C20
i2c1_scl
i2c1_scl
0
IO
OFF
OFF
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
I2C
PU/PD
C21
i2c1_sda
i2c1_sda
0
IO
OFF
OFF
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
I2C
PU/PD
F17
i2c2_scl
i2c2_scl
0
IO
OFF
OFF
15
1.8/3.3
vddshv3
Yes
1
1
IO
Driver off
15
I
Dual
Voltage
LVCMOS
I2C
PU/PD
hdmi1_ddc_sda
i2c2_sda
0
IO
OFF
OFF
15
1.8/3.3
vddshv3
Yes
1
1
IO
Dual
Voltage
LVCMOS
I2C
PU/PD
hdmi1_ddc_scl
C25
i2c2_sda
Driver off
15
I
AH15
ljcb_clkn
ljcb_clkn
0
IO
1.8
vdda_pcie
NA
LJCB
NA
AG15
ljcb_clkp
ljcb_clkp
0
IO
1.8
vdda_pcie
NA
LJCB
NA
B14
mcasp1_aclkr
mcasp1_aclkr
0
IO
1.8/3.3
vddshv3
Yes
PU/PD
mcasp7_axr2
1
IO
Dual
Voltage
LVCMOS
vout2_d0
6
O
vin4a_d0
8
I
0
i2c4_sda
10
IO
1
gpio5_0
14
IO
Driver off
15
I
mcasp1_aclkx
0
IO
7
I
i2c3_sda
10
IO
gpio7_31
14
IO
Driver off
15
I
mcasp1_axr0
0
IO
uart6_rxd
3
I
7
I
0
i2c5_sda
10
IO
1
gpio5_2
14
IO
Driver off
15
I
C14
mcasp1_aclkx
vin6a_fld0
G12
mcasp1_axr0
vin6a_vsync0
34
Terminal Configuration and Functions
No
No
PD
PD
PD
PD
15
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
0
0
PU/PD
0
0
1
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
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DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
F12
BALL NAME [2]
mcasp1_axr1
SIGNAL NAME [3]
mcasp1_axr10
0
IO
3
O
No
mcasp1_axr13
15
1.8/3.3
vddshv3
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
0
I
0
IO
1
gpio5_3
14
IO
Driver off
15
I
mcasp1_axr10
0
IO
mcasp6_aclkx
1
IO
mcasp6_aclkr
2
IO
3
IO
0
7
I
0
timer7
10
IO
gpio5_12
14
IO
Driver off
15
I
mcasp1_axr11
0
IO
mcasp6_fsx
1
IO
mcasp6_fsr
2
IO
3
IO
1
7
I
0
timer8
10
IO
gpio4_17
14
IO
Driver off
15
I
mcasp1_axr12
0
IO
mcasp7_axr0
1
IO
spi3_cs1
3
IO
1
7
I
0
timer9
10
IO
gpio4_18
14
IO
Driver off
15
I
mcasp1_axr13
0
IO
mcasp7_axr1
1
IO
7
I
timer10
10
IO
gpio6_4
14
IO
Driver off
15
I
vin6a_d11
A13
PD
POWER
[11]
10
vin6a_d12
mcasp1_axr12
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
7
No
spi3_cs0
E14
BALL
RESET
STATE [7]
i2c5_scl
vin6a_d13
mcasp1_axr11
TYPE [6]
uart6_txd
spi3_d0
A12
MUXMODE
[5]
mcasp1_axr1
vin6a_hsync0
B13
74x [4]
vin6a_d10
No
No
No
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
0
0
PU/PD
0
0
PU/PD
0
0
PU/PD
0
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
G14
BALL NAME [2]
mcasp1_axr14
SIGNAL NAME [3]
mcasp1_axr15
J11
E12
36
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
TYPE [6]
0
IO
mcasp7_aclkx
1
IO
mcasp7_aclkr
2
IO
7
I
timer11
10
IO
gpio6_5
14
IO
Driver off
15
I
mcasp1_axr15
0
IO
mcasp7_fsx
1
IO
mcasp7_fsr
2
IO
vin6a_d8
G13
MUXMODE
[5]
mcasp1_axr14
vin6a_d9
F14
74x [4]
No
7
I
timer12
10
IO
gpio6_6
14
IO
Driver off
15
I
mcasp1_axr2
0
IO
mcasp6_axr2
1
IO
uart6_ctsn
3
I
vout2_d2
6
O
vin4a_d2
8
I
gpio5_4
14
IO
Driver off
15
I
mcasp1_axr3
0
IO
mcasp6_axr3
1
IO
uart6_rtsn
3
O
vout2_d3
6
O
vin4a_d3
8
I
gpio5_5
14
IO
Driver off
15
I
mcasp1_axr4
0
IO
mcasp4_axr2
1
IO
vout2_d4
6
O
vin4a_d4
8
I
gpio5_6
14
IO
Driver off
15
I
Terminal Configuration and Functions
No
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv3
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
F13
C12
D12
B12
BALL NAME [2]
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_axr8
SIGNAL NAME [3]
mcasp1_axr9
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
1.8/3.3
vddshv3
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
IO
1
IO
vout2_d5
6
O
vin4a_d5
8
I
gpio5_7
14
IO
Driver off
15
I
mcasp1_axr6
0
IO
mcasp5_axr2
1
IO
vout2_d6
6
O
vin4a_d6
8
I
gpio5_8
14
IO
Driver off
15
I
mcasp1_axr7
0
IO
mcasp5_axr3
1
IO
vout2_d7
6
O
vin4a_d7
8
I
timer4
10
IO
gpio5_9
14
IO
Driver off
15
I
mcasp1_axr8
0
IO
mcasp6_axr0
1
IO
spi3_sclk
3
IO
0
7
I
0
timer5
10
IO
gpio5_10
14
IO
Driver off
15
I
mcasp1_axr9
0
IO
mcasp6_axr1
1
IO
spi3_d1
3
IO
0
7
I
0
timer6
10
IO
gpio5_11
14
IO
Driver off
15
I
No
15
HYS [12]
0
vin6a_d14
PD
POWER
[11]
mcasp4_axr3
No
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
mcasp1_axr5
vin6a_d15
A11
74x [4]
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
0
0
PU/PD
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
J14
D14
BALL NAME [2]
mcasp1_fsr
mcasp1_fsx
SIGNAL NAME [3]
A19
mcasp2_aclkr
mcasp2_aclkx
A15
C15
mcasp2_axr0
mcasp2_axr1
mcasp2_axr2
BALL
RESET
STATE [7]
O
vin4a_d1
8
I
0
i2c4_scl
10
IO
1
gpio5_1
14
IO
Driver off
15
I
mcasp1_fsx
0
IO
7
I
i2c3_scl
10
IO
gpio7_30
14
IO
Driver off
15
I
mcasp2_aclkr
0
IO
mcasp8_axr2
1
IO
vout2_d8
6
O
vin4a_d8
8
I
Driver off
15
I
0
IO
7
I
Driver off
15
I
mcasp2_axr0
0
IO
vout2_d10
6
O
vin4a_d10
8
I
Driver off
15
I
mcasp2_axr1
0
IO
vout2_d11
6
O
vin4a_d11
8
I
Driver off
15
I
mcasp2_axr2
0
IO
mcasp3_axr2
1
IO
7
I
gpio6_8
14
IO
Driver off
15
I
mcasp2_aclkx
Terminal Configuration and Functions
No
No
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
6
1.8/3.3
vddshv3
PULL
UP/DOWN
TYPE [14]
vout2_d1
15
1.8/3.3
BUFFER
TYPE [13]
IO
PD
15
HYS [12]
IO
PD
PD
POWER
[11]
1
No
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
0
vin6a_d5
38
TYPE [6]
mcasp7_axr3
vin6a_d7
B15
MUXMODE
[5]
mcasp1_fsr
vin6a_de0
E15
74x [4]
0
0
PU/PD
0
0
1
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
A16
BALL NAME [2]
mcasp2_axr3
SIGNAL NAME [3]
B16
B17
A17
A20
mcasp2_axr4
mcasp2_axr5
mcasp2_axr6
mcasp2_axr7
mcasp2_fsr
MUXMODE
[5]
TYPE [6]
mcasp2_axr3
0
IO
mcasp3_axr3
1
IO
7
I
gpio6_9
14
IO
Driver off
15
I
mcasp2_axr4
0
IO
mcasp8_axr0
1
IO
vout2_d12
6
O
vin4a_d12
8
I
gpio1_4
14
IO
Driver off
15
I
mcasp2_axr5
0
IO
mcasp8_axr1
1
IO
vout2_d13
6
O
vin4a_d13
8
I
gpio6_7
14
IO
Driver off
15
I
mcasp2_axr6
0
IO
mcasp8_aclkx
1
IO
mcasp8_aclkr
2
IO
vout2_d14
6
O
vin4a_d14
8
I
gpio2_29
14
IO
Driver off
15
I
mcasp2_axr7
0
IO
mcasp8_fsx
1
IO
mcasp8_fsr
2
IO
vout2_d15
6
O
vin4a_d15
8
I
gpio1_5
14
IO
Driver off
15
I
mcasp2_fsr
0
IO
mcasp8_axr3
1
IO
vout2_d9
6
O
vin4a_d9
8
I
Driver off
15
I
vin6a_d4
D15
74x [4]
No
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv3
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
A18
BALL NAME [2]
mcasp2_fsx
SIGNAL NAME [3]
mcasp2_fsx
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
0
IO
1
IO
mcasp2_axr12
2
IO
0
uart7_rxd
3
I
1
7
I
0
gpio5_13
14
IO
Driver off
15
I
mcasp3_axr0
0
IO
mcasp2_axr14
2
IO
uart7_ctsn
3
I
1
uart5_rxd
4
I
1
7
I
0
Driver off
15
I
mcasp3_axr1
0
IO
mcasp2_axr15
2
IO
uart7_rtsn
3
O
No
mcasp3_fsx
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
0
0
PU/PD
0
0
0
PU/PD
0
0
4
O
vin6a_d0
No
7
I
0
vin5a_fld0
No
9
I
0
Driver off
15
I
mcasp3_fsx
0
IO
mcasp3_fsr
1
IO
mcasp2_axr13
2
IO
uart7_txd
3
O
vin6a_d2
40
PD
vddshv3
Yes
DSIS [15]
mcasp3_aclkr
1.8/3.3
vddshv3
PULL
UP/DOWN
TYPE [14]
mcasp3_aclkx
15
1.8/3.3
BUFFER
TYPE [13]
I
PD
15
HYS [12]
15
PD
PD
POWER
[11]
Driver off
No
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
I
No
uart5_txd
F15
BALL
RESET
STATE [7]
IO
vin6a_d1
C17
TYPE [6]
7
vin6a_d3
B19
MUXMODE
[5]
0
vin6a_d6
B18
74x [4]
7
I
gpio5_14
14
IO
Driver off
15
I
Terminal Configuration and Functions
No
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
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DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
C18
BALL NAME [2]
mcasp4_aclkx
SIGNAL NAME [3]
74x [4]
2
IO
0
3
I
1
i2c4_sda
4
IO
1
vout2_d16
6
O
8
I
0
9
I
0
Driver off
15
I
mcasp4_axr0
0
IO
spi3_d0
2
IO
uart8_ctsn
3
I
1
uart4_rxd
4
I
1
vout2_d18
6
O
8
I
0
9
I
0
Driver off
15
I
mcasp4_axr1
0
IO
spi3_cs0
2
IO
uart8_rtsn
3
O
uart4_txd
4
O
vout2_d19
6
O
vin4a_d19
8
I
0
9
I
0
Driver off
15
I
mcasp4_fsx
0
IO
mcasp4_fsr
1
IO
spi3_d1
2
IO
uart8_txd
3
O
i2c4_scl
4
IO
vout2_d17
6
O
8
I
0
9
I
0
15
I
vin5a_d13
mcasp4_axr1
vin5a_d12
A21
mcasp4_fsx
No
No
vin4a_d17
vin5a_d14
Driver off
No
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
uart8_rxd
1.8/3.3
vddshv3
PULL
UP/DOWN
TYPE [14]
spi3_sclk
15
1.8/3.3
BUFFER
TYPE [13]
IO
PD
15
HYS [12]
IO
PD
PD
POWER
[11]
1
No
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
0
vin4a_d18
D17
BALL
RESET
STATE [7]
mcasp4_aclkr
vin5a_d15
mcasp4_axr0
TYPE [6]
mcasp4_aclkx
vin4a_d16
G16
MUXMODE
[5]
PU/PD
0
0
0
PU/PD
0
1
PU/PD
0
0
1
Terminal Configuration and Functions
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AA3
BALL NAME [2]
mcasp5_aclkx
SIGNAL NAME [3]
74x [4]
2
IO
0
3
I
1
i2c5_sda
4
IO
1
mlb_clk
5
I
1
vout2_d20
6
O
8
I
0
9
I
0
Driver off
15
I
mcasp5_axr0
0
IO
spi4_d0
2
IO
uart9_ctsn
3
I
1
uart3_rxd
4
I
1
mlb_sig
5
IO
1
vout2_d22
6
O
8
I
0
9
I
0
Driver off
15
I
mcasp5_axr1
0
IO
spi4_cs0
2
IO
uart9_rtsn
3
O
uart3_txd
4
O
mlb_dat
5
IO
vout2_d23
6
O
8
I
0
9
I
0
Driver off
15
I
mcasp5_fsx
0
IO
mcasp5_fsr
1
IO
spi4_d1
2
IO
uart9_txd
3
O
i2c5_scl
4
IO
vout2_d21
6
O
8
I
0
9
I
0
15
I
vin5a_d9
mcasp5_axr1
No
vin4a_d23
vin5a_d8
AB9
mcasp5_fsx
No
vin4a_d21
vin5a_d10
Driver off
42
Terminal Configuration and Functions
No
PD
PD
15
1.8/3.3
vddshv7
vddshv7
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
uart9_rxd
1.8/3.3
vddshv7
PULL
UP/DOWN
TYPE [14]
spi4_sclk
15
1.8/3.3
BUFFER
TYPE [13]
IO
PD
15
HYS [12]
IO
PD
PD
POWER
[11]
1
No
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
0
vin4a_d22
AA4
BALL
RESET
STATE [7]
mcasp5_aclkr
vin5a_d11
mcasp5_axr0
TYPE [6]
mcasp5_aclkx
vin4a_d20
AB3
MUXMODE
[5]
PU/PD
0
0
0
PU/PD
0
1
1
PD
PD
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
U4
V1
BALL NAME [2]
mdio_d
mdio_mclk
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PU
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
IO
I
mii0_txer
3
O
0
vin2a_d0
4
I
0
vin4b_d0
5
I
0
gpio5_16
14
IO
Driver off
15
I
mdio_mclk
0
O
uart3_rtsn
1
O
mii0_col
3
I
vin2a_clk0
4
I
vin4b_clk1
5
I
gpio5_15
14
IO
vddshv9
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
1
1.8/3.3
vddshv9
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
uart3_ctsn
PU
15
HYS [12]
mdio_d
PU
PU
POWER
[11]
1
1
PU/PD
1
0
0
Driver off
15
I
AB2
mlbp_clk_n
mlbp_clk_n
0
I
1.8
vdds_mlbp
No
ILVDS18
NA
AB1
mlbp_clk_p
mlbp_clk_p
0
I
1.8
vdds_mlbp
No
ILVDS18
NA
AA2
mlbp_dat_n
mlbp_dat_n
0
IO
OFF
OFF
1.8
vdds_mlbp
No
BMLB18
NA
AA1
mlbp_dat_p
mlbp_dat_p
0
IO
OFF
OFF
1.8
vdds_mlbp
No
BMLB18
NA
AC2
mlbp_sig_n
mlbp_sig_n
0
IO
OFF
OFF
1.8
vdds_mlbp
No
BMLB18
NA
AC1
mlbp_sig_p
mlbp_sig_p
0
IO
OFF
OFF
1.8
vdds_mlbp
No
BMLB18
NA
W6
mmc1_clk
mmc1_clk
0
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO1833
PU/PD
1
gpio6_21
14
IO
Driver off
15
I
mmc1_cmd
0
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO1833
PU/PD
1
gpio6_22
14
IO
Driver off
15
I
mmc1_dat0
0
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO1833
PU/PD
1
gpio6_23
14
IO
Driver off
15
I
mmc1_dat1
0
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO1833
PU/PD
1
gpio6_24
14
IO
Driver off
15
I
mmc1_dat2
0
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO1833
PU/PD
1
gpio6_25
14
IO
Driver off
15
I
Y6
AA6
Y4
AA5
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
Y3
W7
Y9
AD4
BALL NAME [2]
mmc1_dat3
mmc1_sdcd
mmc1_sdwp
mmc3_clk
SIGNAL NAME [3]
mmc3_cmd
mmc3_dat0
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
0
IO
14
IO
Driver off
15
I
mmc1_sdcd
0
I
uart6_rxd
3
I
i2c4_sda
4
IO
gpio6_27
14
IO
Driver off
15
I
mmc1_sdwp
0
I
uart6_txd
3
O
i2c4_scl
4
IO
gpio6_28
14
IO
Driver off
15
I
mmc3_clk
0
IO
usb3_ulpi_d5
3
IO
vin2b_d7
4
I
0
9
I
0
ehrpwm2_tripzone_input
10
IO
0
gpio6_29
14
IO
Driver off
15
I
mmc3_cmd
0
IO
spi3_sclk
1
IO
usb3_ulpi_d4
3
IO
0
vin2b_d6
4
I
0
9
I
0
eCAP2_in_PWM2_out
10
IO
0
gpio6_30
14
IO
Driver off
15
I
mmc3_dat0
0
IO
spi3_d1
1
IO
uart5_rxd
2
I
1
usb3_ulpi_d3
3
IO
0
vin2b_d5
4
I
0
9
I
0
eQEP3A_in
10
I
0
gpio6_31
14
IO
Driver off
15
I
vin5a_d5
44
TYPE [6]
gpio6_26
vin5a_d6
AC7
MUXMODE
[5]
mmc1_dat3
vin5a_d7
AC4
74x [4]
Terminal Configuration and Functions
No
No
No
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO1833
PU/PD
1
PU
PU
15
1.8/3.3
vddshv8
Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
1
PD
PD
15
1.8/3.3
vddshv8
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
PU
PU
PU
PU
PU
PU
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv7
vddshv7
vddshv7
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
1
0
PU/PD
1
0
PU/PD
1
0
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AC6
BALL NAME [2]
mmc3_dat1
SIGNAL NAME [3]
mmc3_dat2
mmc3_dat3
mmc3_dat4
BALL
RESET
STATE [7]
O
usb3_ulpi_d2
3
IO
0
vin2b_d4
4
I
0
9
I
0
eQEP3B_in
10
I
0
gpio7_0
14
IO
Driver off
15
I
mmc3_dat2
0
IO
spi3_cs0
1
IO
uart5_ctsn
2
I
1
usb3_ulpi_d1
3
IO
0
vin2b_d3
4
I
0
9
I
0
eQEP3_index
10
IO
0
gpio7_1
14
IO
Driver off
15
I
mmc3_dat3
0
IO
spi3_cs1
1
IO
uart5_rtsn
2
O
usb3_ulpi_d0
3
IO
0
vin2b_d2
4
I
0
9
I
0
eQEP3_strobe
10
IO
0
gpio7_2
14
IO
Driver off
15
I
mmc3_dat4
0
IO
spi4_sclk
1
IO
uart10_rxd
2
I
1
usb3_ulpi_nxt
3
I
0
vin2b_d1
4
I
0
9
I
0
ehrpwm3A
10
O
gpio1_22
14
IO
Driver off
15
I
vin5a_d1
No
No
No
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv7
vddshv7
vddshv7
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
2
1.8/3.3
vddshv7
PULL
UP/DOWN
TYPE [14]
uart5_txd
15
1.8/3.3
BUFFER
TYPE [13]
IO
PU
15
HYS [12]
IO
PU
PU
POWER
[11]
1
No
PU
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
0
vin5a_d2
AC8
TYPE [6]
spi3_d0
vin5a_d3
AC3
MUXMODE
[5]
mmc3_dat1
vin5a_d4
AC9
74x [4]
1
0
PU/PD
1
1
PU/PD
1
1
PU/PD
1
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AD6
BALL NAME [2]
mmc3_dat5
SIGNAL NAME [3]
mmc3_dat6
BALL
RESET
STATE [7]
O
usb3_ulpi_dir
3
I
0
vin2b_d0
4
I
0
9
I
0
ehrpwm3B
10
O
gpio1_23
14
IO
Driver off
15
I
mmc3_dat6
0
IO
spi4_d0
1
IO
uart10_ctsn
2
I
usb3_ulpi_stp
3
O
4
I
9
I
0
ehrpwm3_tripzone_input
10
IO
0
gpio1_24
14
IO
Driver off
15
I
mmc3_dat7
0
IO
spi4_cs0
1
IO
uart10_rtsn
2
O
usb3_ulpi_clk
3
I
vin2b_clk1
4
I
vin5a_vsync0
No
No
vddshv7
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
1
0
PU/PD
1
0
1
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
0
9
I
0
eCAP3_in_PWM3_out
10
IO
0
gpio1_25
14
IO
Driver off
15
I
D21
nmin_dsp
nmin_dsp
0
I
PD
PD
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
Y11
on_off
on_off
0
O
PU
drive 1
(OFF)
1.8/3.3
vddshv5
Yes
BC1833IHH PU/PD
V
AG13
pcie_rxn0
pcie_rxn0
0
I
OFF
OFF
1.8
vdda_pcie0
AG11
pcie_rxn1
pcie_rxn1
0
I
OFF
OFF
1.8
vdda_pcie1
AH13
pcie_rxp0
pcie_rxp0
0
I
OFF
OFF
1.8
vdda_pcie0
AH11
pcie_rxp1
pcie_rxp1
0
I
OFF
OFF
1.8
vdda_pcie1
AG14
pcie_txn0
pcie_txn0
0
O
1.8
vdda_pcie0
AG12
pcie_txn1
pcie_txn1
0
O
1.8
vdda_pcie1
46
DSIS [15]
2
1.8/3.3
vddshv7
PULL
UP/DOWN
TYPE [14]
uart10_txd
15
1.8/3.3
BUFFER
TYPE [13]
IO
PU
15
HYS [12]
IO
PU
PU
POWER
[11]
1
No
PU
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
0
vin5a_hsync0
mmc3_dat7
TYPE [6]
spi4_d1
vin2b_de1
AB5
MUXMODE
[5]
mmc3_dat5
vin5a_d0
AB8
74x [4]
Terminal Configuration and Functions
No
No
No
PU/PD
Copyright © 2015–2016, Texas Instruments Incorporated
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
AH14
pcie_txp0
pcie_txp0
AH12
pcie_txp1
pcie_txp1
F22
porz
E23
U5
V5
W2
Y2
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
0
O
1.8
vdda_pcie0
0
O
1.8
vdda_pcie1
porz
0
I
1.8/3.3
vddshv3
Yes
IHHV1833
PU/PD
resetn
resetn
0
I
PU
PU
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
rgmii0_rxc
rgmii0_rxc
0
I
PD
PD
1.8/3.3
vddshv9
Yes
2
O
Dual
Voltage
LVCMOS
PU/PD
rmii1_txen
mii0_txclk
3
I
0
vin2a_d5
4
I
0
vin4b_d5
5
I
0
usb4_ulpi_d2
6
IO
0
gpio5_26
14
IO
Driver off
15
I
rgmii0_rxctl
0
I
rmii1_txd1
2
O
mii0_txd3
3
O
vin2a_d6
4
I
0
vin4b_d6
5
I
0
usb4_ulpi_d3
6
IO
0
gpio5_27
14
IO
Driver off
15
I
rgmii0_rxd0
0
I
rmii0_txd0
1
O
mii0_txd0
3
O
vin2a_fld0
4
I
vin4b_fld1
5
I
0
usb4_ulpi_d7
6
IO
0
gpio5_31
14
IO
Driver off
15
I
rgmii0_rxd1
0
I
rmii0_txd1
1
O
mii0_txd1
3
O
vin2a_d9
4
I
0
usb4_ulpi_d6
6
IO
0
gpio5_30
14
IO
Driver off
15
I
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
No
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv9
vddshv9
vddshv9
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0
0
Terminal Configuration and Functions
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Copyright © 2015–2016, Texas Instruments Incorporated
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
V3
V4
W9
V9
48
BALL NAME [2]
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
rgmii0_txctl
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
O
mii0_txen
3
O
vin2a_d8
4
I
0
usb4_ulpi_d5
6
IO
0
gpio5_29
14
IO
Driver off
15
I
rgmii0_rxd3
0
I
rmii1_txd0
2
O
mii0_txd2
3
O
vin2a_d7
4
I
0
vin4b_d7
5
I
0
usb4_ulpi_d4
6
IO
0
gpio5_28
14
IO
Driver off
15
I
rgmii0_txc
0
O
uart3_ctsn
1
I
rmii1_rxd1
2
I
0
mii0_rxd3
3
I
0
vin2a_d3
4
I
0
vin4b_d3
5
I
0
usb4_ulpi_clk
6
I
0
spi3_d0
7
IO
0
spi4_cs2
8
IO
1
gpio5_20
14
IO
Driver off
15
I
rgmii0_txctl
0
O
uart3_rtsn
1
O
rmii1_rxd0
2
I
0
mii0_rxd2
3
I
0
vin2a_d4
4
I
0
vin4b_d4
5
I
0
usb4_ulpi_stp
6
O
spi3_cs0
7
IO
1
spi4_cs3
8
IO
1
gpio5_21
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv9
vddshv9
vddshv9
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
I
1.8/3.3
vddshv9
PULL
UP/DOWN
TYPE [14]
1
15
1.8/3.3
BUFFER
TYPE [13]
0
PD
15
HYS [12]
rmii0_txen
PD
PD
POWER
[11]
rgmii0_rxd2
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PU/PD
0
0
PU/PD
1
PU/PD
Copyright © 2015–2016, Texas Instruments Incorporated
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
U6
V6
U7
BALL NAME [2]
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
O
I
mii0_rxd0
3
I
0
vin2a_d10
4
I
0
usb4_ulpi_d1
6
IO
0
spi4_cs0
7
IO
1
uart4_rtsn
8
O
gpio5_25
14
IO
Driver off
15
I
rgmii0_txd1
0
O
rmii0_rxd1
1
I
mii0_rxd1
3
I
vin2a_vsync0
4
I
vin4b_vsync1
5
I
0
usb4_ulpi_d0
6
IO
0
spi4_d0
7
IO
0
uart4_ctsn
8
IO
1
gpio5_24
14
IO
Driver off
15
I
rgmii0_txd2
0
O
rmii0_rxer
1
I
mii0_rxer
3
I
vin2a_hsync0
4
I
vin4b_hsync1
5
I
0
usb4_ulpi_nxt
6
I
0
spi4_d1
7
IO
0
uart4_txd
8
O
gpio5_23
14
IO
Driver off
15
I
vddshv9
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
1
1.8/3.3
vddshv9
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
rmii0_rxd0
PD
15
HYS [12]
rgmii0_txd0
PD
PD
POWER
[11]
Dual
Voltage
LVCMOS
PU/PD
0
PU/PD
0
0
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
V7
U3
BALL NAME [2]
rgmii0_txd3
RMII_MHZ_50_CLK
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv9
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
rgmii0_txd3
0
O
rmii0_crs
1
I
mii0_crs
3
I
vin2a_de0
4
I
PU/PD
vin4b_de1
5
I
0
usb4_ulpi_dir
6
I
0
spi4_sclk
7
IO
0
uart4_rxd
8
I
1
gpio5_22
14
IO
Driver off
15
I
RMII_MHZ_50_CLK
0
IO
vin2a_d11
4
I
gpio5_17
14
IO
0
0
PD
PD
Driver off
15
I
F23
rstoutn
rstoutn
0
O
PD
drive 1
(OFF)
E18
rtck
rtck
0
O
PU
gpio8_29
14
IO
drive clk
(OFF)
15
0
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
rtc_iso
rtc_iso
0
I
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
AE14
rtc_osc_xi_clkin32
rtc_osc_xi_clkin32
0
I
1.8
vdda_rtc
No
LVCMOS
OSC
NA
AD14
rtc_osc_xo
rtc_osc_xo
0
O
1.8
vdda_rtc
No
LVCMOS
OSC
NA
AB17
rtc_porz
rtc_porz
0
I
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
AH9
sata1_rxn0
sata1_rxn0
0
I
OFF
OFF
1.8
vdda_sata
NA
SATAPHY
NA
AG9
sata1_rxp0
sata1_rxp0
0
I
OFF
OFF
1.8
vdda_sata
NA
SATAPHY
NA
AG10
sata1_txn0
sata1_txn0
0
O
1.8
vdda_sata
NA
SATAPHY
NA
AH10
sata1_txp0
sata1_txp0
0
O
1.8
vdda_sata
NA
SATAPHY
NA
A24
spi1_cs0
spi1_cs0
0
IO
gpio7_10
14
IO
Driver off
15
I
spi1_cs1
0
IO
sata1_led
2
O
spi2_cs1
3
IO
gpio7_11
14
IO
Driver off
15
I
50
spi1_cs1
Terminal Configuration and Functions
0
0
AF14
A22
DSIS [15]
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
B21
B20
B25
F16
A25
B24
G17
BALL NAME [2]
spi1_cs2
spi1_cs3
spi1_d0
spi1_d1
spi1_sclk
spi2_cs0
spi2_d0
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PU
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
IO
I
mmc3_sdcd
2
I
1
spi2_cs2
3
IO
1
dcan2_tx
4
IO
1
mdio_mclk
5
O
1
hdmi1_hpd
6
I
gpio7_12
14
IO
Driver off
15
I
spi1_cs3
0
IO
uart4_txd
1
O
mmc3_sdwp
2
I
0
spi2_cs3
3
IO
1
dcan2_rx
4
IO
1
mdio_d
5
IO
1
hdmi1_cec
6
IO
gpio7_13
14
IO
Driver off
15
I
spi1_d0
0
IO
gpio7_9
14
IO
Driver off
15
I
spi1_d1
0
IO
gpio7_8
14
IO
Driver off
15
I
spi1_sclk
0
IO
gpio7_7
14
IO
Driver off
15
I
spi2_cs0
0
IO
uart3_rtsn
1
O
uart5_txd
2
O
gpio7_17
14
IO
Driver off
15
I
spi2_d0
0
IO
uart3_ctsn
1
I
uart5_rxd
2
I
gpio7_16
14
IO
Driver off
15
I
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
1
1.8/3.3
vddshv3
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
uart4_rxd
PU
15
HYS [12]
spi1_cs2
PU
PU
POWER
[11]
1
1
PU/PD
1
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
1
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
B22
A26
BALL NAME [2]
spi2_d1
spi2_sclk
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
spi2_d1
0
IO
uart3_txd
1
O
gpio7_15
14
IO
Driver off
15
I
spi2_sclk
0
IO
uart3_rxd
1
I
gpio7_14
14
IO
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
Driver off
15
I
E20
tclk
tclk
0
I
PU
PU
0
1.8/3.3
vddshv3
Yes
IQ1833
PU/PD
D23
tdi
tdi
0
I
PU
PU
0
1.8/3.3
vddshv3
Yes
PU/PD
gpio8_27
14
I
Dual
Voltage
LVCMOS
tdo
0
O
PU
PU
0
1.8/3.3
vddshv3
Yes
14
IO
Dual
Voltage
LVCMOS
PU/PD
gpio8_28
0
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1.8/3.3
vddshv4
Yes
Dual
Voltage
LVCMOS
PU/PD
F19
tdo
F18
tms
tms
0
IO
OFF
OFF
D20
trstn
trstn
0
I
PD
PD
E25
uart1_ctsn
uart1_ctsn
0
I
PU
PU
uart9_rxd
2
I
mmc4_clk
3
IO
gpio7_24
14
IO
Driver off
15
I
uart1_rtsn
0
O
uart9_txd
2
O
mmc4_cmd
3
IO
gpio7_25
14
IO
Driver off
15
I
uart1_rxd
0
I
mmc4_sdcd
3
I
gpio7_22
14
IO
Driver off
15
I
uart1_txd
0
O
mmc4_sdwp
3
I
gpio7_23
14
IO
Driver off
15
I
C27
B27
C26
52
uart1_rtsn
uart1_rxd
uart1_txd
Terminal Configuration and Functions
DSIS [15]
15
1
1
1
PU
PU
15
1.8/3.3
vddshv4
Yes
Dual
Voltage
LVCMOS
PU/PD
1
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv4
vddshv4
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
1
1
0
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
D27
C28
D28
D26
BALL NAME [2]
uart2_ctsn
uart2_rtsn
uart2_rxd
uart2_txd
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PU
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
I
I
mmc4_dat2
3
IO
1
uart10_rxd
4
I
1
uart1_dtrn
5
O
gpio1_16
14
IO
Driver off
15
I
uart2_rtsn
0
O
uart3_txd
1
O
uart3_irtx
2
O
mmc4_dat3
3
IO
uart10_txd
4
O
uart1_rin
5
I
gpio1_17
14
IO
Driver off
15
I
uart3_ctsn
1
I
uart3_rctx
2
O
mmc4_dat0
3
IO
1
uart2_rxd
4
I
1
uart1_dcdn
5
I
1
gpio7_26
14
IO
Driver off
15
I
uart2_txd
0
O
uart3_rtsn
1
O
uart3_sd
2
O
mmc4_dat1
3
IO
uart2_txd
4
O
uart1_dsrn
5
I
gpio7_27
14
IO
Driver off
15
I
vddshv4
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
2
1.8/3.3
vddshv4
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
uart3_rxd
PU
15
HYS [12]
uart2_ctsn
PU
PU
POWER
[11]
1
1
PU/PD
1
1
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv4
vddshv4
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
1
PU/PD
1
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
V2
Y1
BALL NAME [2]
uart3_rxd
uart3_txd
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
I
I
mii0_rxdv
3
I
0
vin2a_d1
4
I
0
vin4b_d1
5
I
0
spi3_sclk
7
IO
0
gpio5_18
14
IO
Driver off
15
I
uart3_txd
0
O
rmii1_rxer
2
I
mii0_rxclk
3
I
0
vin2a_d2
4
I
0
vin4b_d2
5
I
0
spi3_d1
7
IO
0
spi4_cs1
8
IO
1
gpio5_19
14
IO
vddshv9
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
PU/PD
0
Driver off
15
I
usb1_dm
usb1_dm
0
IO
OFF
OFF
3.3
vdda33v_us NA
b1
USB3PHY
NA
AD12
usb1_dp
usb1_dp
0
IO
OFF
OFF
3.3
vdda33v_us NA
b1
USB3PHY
NA
AB10
usb1_drvvbus
usb1_drvvbus
0
O
PD
PD
1.8/3.3
vddshv6
7
IO
Dual
Voltage
LVCMOS
PU/PD
timer16
gpio6_12
14
IO
Driver off
15
I
15
Yes
AF11
usb2_dm
usb2_dm
0
IO
3.3
vdda33v_us No
b2
USB2PHY
NA
AE11
usb2_dp
usb2_dp
0
IO
3.3
vdda33v_us No
b2
USB2PHY
NA
AC10
usb2_drvvbus
usb2_drvvbus
0
O
1.8/3.3
vddshv6
7
IO
Dual
Voltage
LVCMOS
PU/PD
timer15
gpio6_13
14
IO
Driver off
15
I
PD
PD
15
AF12
usb_rxn0
usb_rxn0
0
I
OFF
OFF
1.8
vdda_usb1
AE12
usb_rxp0
usb_rxp0
0
I
OFF
OFF
1.8
vdda_usb1
AC11
usb_txn0
usb_txn0
0
O
1.8
vdda_usb1
AD11
usb_txp0
usb_txp0
0
O
1.8
vdda_usb1
Terminal Configuration and Functions
Yes
1
0
AC12
54
DSIS [15]
2
1.8/3.3
vddshv9
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
rmii1_crs
PD
15
HYS [12]
uart3_rxd
PD
PD
POWER
[11]
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
H13, H14, J17, J18, vdd
L7, L8, N10, N13,
P11, P12, P13,
R11, R16, R19,
T13, T16, T19,
U13, U16, U8, U9,
V16, V8
vdd
PWR
AA12
vdda33v_usb1
vdda33v_usb1
PWR
Y12
vdda33v_usb2
vdda33v_usb2
PWR
M14
vdda_abe_per
vdda_abe_per
PWR
P16
vdda_ddr
vdda_ddr
PWR
N11
vdda_debug
vdda_debug
PWR
N12
vdda_dsp_eve
vdda_dsp_eve
PWR
P15
vdda_gmac_core
vdda_gmac_core
PWR
R14
vdda_gpu
vdda_gpu
PWR
Y17
vdda_hdmi
vdda_hdmi
PWR
R17
vdda_iva
vdda_iva
PWR
N16
vdda_mpu
vdda_mpu
PWR
AD16, AE16
vdda_osc
vdda_osc
PWR
W14
vdda_pcie
vdda_pcie
PWR
AA17
vdda_pcie0
vdda_pcie0
PWR
AA16
vdda_pcie1
vdda_pcie1
PWR
AB13
vdda_rtc
vdda_rtc
PWR
V13
vdda_sata
vdda_sata
PWR
AA13
vdda_usb1
vdda_usb1
PWR
AB12
vdda_usb2
vdda_usb2
PWR
W12
vdda_usb3
vdda_usb3
PWR
P14
vdda_video
vdda_video
PWR
G18, H17, M8, M9, vdds18v
N8, P8, R8, T8,
V21, V22, W17,
W18
vdds18v
PWR
AA18, AA19, W21,
Y21
vdds18v_ddr1
vdds18v_ddr1
PWR
J21, J22, N21, P20, vdds18v_ddr2
P21
vdds18v_ddr2
PWR
E3, E5, G4, G5, H8, vddshv1
H9
vddshv1
PWR
N4, N5, P10, R10,
R7, T4, T5
vddshv10
vddshv10
PWR
J8, K8
vddshv11
vddshv11
PWR
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
Terminal Configuration and Functions
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Copyright © 2015–2016, Texas Instruments Incorporated
55
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
B6, D10, E10, H10, vddshv2
H11
vddshv2
PWR
B23, D16, D22,
E16, E22, G15,
H15, H16, H18,
H19
vddshv3
vddshv3
PWR
C24
vddshv4
vddshv4
PWR
V12
vddshv5
vddshv5
PWR
AD5, AD7, AE7,
AF5
vddshv6
vddshv6
PWR
AB6, AB7
vddshv7
vddshv7
PWR
W8, Y8
vddshv8
vddshv8
PWR
U10, W4, W5
vddshv9
vddshv9
PWR
AA21, AA22, AB21, vdds_ddr1
AB22, AB24, AB25,
AC22, AD26, AG20,
AG28, AH27, W16,
W27
vdds_ddr1
PWR
E24, G22, G23,
vdds_ddr2
H20, H21, H22,
J27, L20, L21, M20,
M21, T24, T25
vdds_ddr2
PWR
AA7, Y7
vdds_mlbp
PWR
J13, K10, K11, K12, vdd_dspeve
K13, L10, L11, L12,
M10, M11, M12,
M13
vdds_mlbp
vdd_dspeve
PWR
U11, U12, V10,
V11, V14, W10,
W11, W13
vdd_gpu
PWR
U18, U19, V18, V19 vdd_iva
vdd_iva
PWR
K17, K18, L15, L16, vdd_mpu
L17, L18, L19, M15,
M16, M17, M18,
N17, N18, P17,
P18, R18
vdd_mpu
PWR
AB15
vdd_rtc
vdd_rtc
AG8
vin1a_clk0
vin1a_clk0
vdd_gpu
0
I
No
3
O
vout3_fld (9)
No
4
O
gpio2_30
Yes (7)
14
IO
15
I
Driver off
56
Terminal Configuration and Functions
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
PWR
No
vout3_d16
BALL
RESET
STATE [7]
(9)
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AE8
BALL NAME [2]
vin1a_d0
SIGNAL NAME [3]
74x [4]
vin1a_d1
No
0
I
vout3_d7 (9)
No
3
O
vout3_d23 (9)
No
4
O
uart8_rxd
No
5
I
ehrpwm1A
No
10
O
gpio3_4
Yes (7)
14
IO
15
I
vin1a_d1
No
0
I
vout3_d6 (9)
No
3
O
vout3_d22 (9)
No
4
O
uart8_txd
No
5
O
ehrpwm1B
No
10
O
gpio3_5
Yes (7)
14
IO
15
I
Driver off
AG3
vin1a_d10
vin1a_d10
No
0
I
vin1b_d5
No
1
I
vout3_d13 (9)
No
4
O
kbd_row4
No
9
I
gpio3_14
Yes (7)
14
IO
Driver off
AG5
vin1a_d11
15
I
vin1a_d11
No
0
I
vin1b_d4
No
1
I
vout3_d12 (9)
No
4
O
gpmc_a23
No
5
O
kbd_row5
No
9
I
14
IO
gpio3_15
Yes
(7)
Driver off
AF2
vin1a_d12
TYPE [6]
vin1a_d0
Driver off
AD8
MUXMODE
[5]
15
I
vin1a_d12
No
0
I
vin1b_d3
No
1
I
usb3_ulpi_d7
No
2
IO
vout3_d11 (9)
No
4
O
gpmc_a24
No
5
O
kbd_row6
No
9
I
gpio3_16
Yes (7)
14
IO
15
I
Driver off
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv6
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
0
1
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AF6
BALL NAME [2]
vin1a_d13
SIGNAL NAME [3]
74x [4]
No
0
I
vin1b_d2
No
1
I
usb3_ulpi_d6
No
2
IO
(9)
No
4
O
gpmc_a25
No
5
O
kbd_row7
No
9
I
14
IO
gpio3_17
Yes
(7)
Driver off
vin1a_d14
15
I
vin1a_d14
No
0
I
vin1b_d1
No
1
I
usb3_ulpi_d5
No
2
IO
vout3_d9 (9)
No
4
O
gpmc_a26
No
5
O
kbd_row8
No
9
I
gpio3_18
Yes (7)
14
IO
Driver off
AF4
vin1a_d15
15
I
vin1a_d15
No
0
I
vin1b_d0
No
1
I
usb3_ulpi_d4
No
2
IO
vout3_d8 (9)
No
4
O
gpmc_a27
No
5
O
kbd_col0
No
9
O
gpio3_19
Yes (7)
14
IO
15
I
Driver off
AF1
vin1a_d16
vin1a_d16
No
0
I
vin1b_d7
No
1
I
usb3_ulpi_d3
No
2
IO
vout3_d7 (9)
No
4
O
vin3a_d0
No
6
I
kbd_col1
No
9
O
gpio3_20
Yes (7)
14
IO
15
I
Driver off
58
TYPE [6]
vin1a_d13
vout3_d10
AF3
MUXMODE
[5]
Terminal Configuration and Functions
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv6
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
0
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AE3
BALL NAME [2]
vin1a_d17
SIGNAL NAME [3]
74x [4]
No
0
I
vin1b_d6
No
1
I
usb3_ulpi_d2
No
2
IO
No
4
O
vin3a_d1
No
6
I
kbd_col2
No
9
O
gpio3_21
Yes (7)
14
IO
15
I
(9)
Driver off
vin1a_d18
vin1a_d18
No
0
I
vin1b_d5
No
1
I
usb3_ulpi_d1
No
2
IO
vout3_d5 (9)
No
4
O
vin3a_d2
No
6
I
kbd_col3
No
9
O
gpio3_22
Yes (7)
14
IO
Driver off
AE1
vin1a_d19
15
I
vin1a_d19
No
0
I
vin1b_d4
No
1
I
usb3_ulpi_d0
No
2
IO
vout3_d4 (9)
No
4
O
vin3a_d3
No
6
I
kbd_col4
No
9
O
gpio3_23
Yes (7)
14
IO
15
I
Driver off
AG7
vin1a_d2
TYPE [6]
vin1a_d17
vout3_d6
AE5
MUXMODE
[5]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv6
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
0
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
vin1a_d2
No
0
I
vout3_d5 (9)
No
3
O
vout3_d21 (9)
No
4
O
uart8_ctsn
No
5
I
1
ehrpwm1_tripzone_input
No
10
IO
0
gpio3_6
Yes (7)
14
IO
15
I
Driver off
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AE2
BALL NAME [2]
vin1a_d20
SIGNAL NAME [3]
74x [4]
No
0
I
vin1b_d3
No
1
I
usb3_ulpi_nxt
No
2
I
No
4
O
vin3a_d4
No
6
I
kbd_col5
No
9
O
gpio3_24
Yes (7)
14
IO
15
I
(9)
Driver off
vin1a_d21
vin1a_d21
No
0
I
vin1b_d2
No
1
I
usb3_ulpi_dir
No
2
I
vout3_d2 (9)
No
4
O
vin3a_d5
No
6
I
kbd_col6
No
9
O
gpio3_25
Yes (7)
14
IO
Driver off
AD2
vin1a_d22
15
I
vin1a_d22
No
0
I
vin1b_d1
No
1
I
usb3_ulpi_stp
No
2
O
vout3_d1 (9)
No
4
O
vin3a_d6
No
6
I
kbd_col7
No
9
O
gpio3_26
Yes (7)
14
IO
15
I
Driver off
AD3
vin1a_d23
vin1a_d23
No
0
I
vin1b_d0
No
1
I
usb3_ulpi_clk
No
2
I
vout3_d0 (9)
No
4
O
vin3a_d7
No
6
I
kbd_col8
No
9
O
gpio3_27
Yes (7)
14
IO
15
I
Driver off
60
TYPE [6]
vin1a_d20
vout3_d3
AE6
MUXMODE
[5]
Terminal Configuration and Functions
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv6
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
0
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AH6
BALL NAME [2]
vin1a_d3
SIGNAL NAME [3]
74x [4]
vin1a_d4
No
0
I
vout3_d4 (9)
No
3
O
vout3_d20 (9)
No
4
O
uart8_rtsn
No
5
O
eCAP1_in_PWM1_out
No
10
IO
gpio3_7
Yes (7)
14
IO
15
I
vin1a_d4
No
0
I
vout3_d3 (9)
No
3
O
vout3_d19 (9)
No
4
O
ehrpwm1_synci
No
10
I
14
IO
gpio3_8
Yes
(7)
Driver off
AH5
vin1a_d5
15
I
vin1a_d5
No
0
I
vout3_d2 (9)
No
3
O
vout3_d18 (9)
No
4
O
ehrpwm1_synco
No
10
O
gpio3_9
Yes (7)
14
IO
Driver off
AG6
vin1a_d6
15
I
No
0
I
No
3
O
vout3_d17 (9)
No
4
O
eQEP2A_in
No
10
I
gpio3_10
Yes (7)
14
IO
vin1a_d6
vout3_d1
(9)
Driver off
AH4
vin1a_d7
TYPE [6]
vin1a_d3
Driver off
AH3
MUXMODE
[5]
15
I
vin1a_d7
No
0
I
vout3_d0 (9)
No
3
O
vout3_d16 (9)
No
4
O
eQEP2B_in
No
10
I
gpio3_11
Yes (7)
14
IO
15
I
Driver off
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv6
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AG4
BALL NAME [2]
vin1a_d8
SIGNAL NAME [3]
74x [4]
vin1a_de0
Yes
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
I
vout3_d15 (9)
No
4
O
kbd_row2
No
9
I
0
eQEP2_index
No
10
IO
0
14
IO
0
0
15
I
vin1a_d9
No
0
I
vin1b_d6
No
1
I
vout3_d14 (9)
No
4
O
kbd_row3
No
9
I
0
eQEP2_strobe
No
10
IO
0
gpio3_13
Yes (7)
14
IO
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
15
I
vin1a_de0
No
0
I
vin1b_hsync1
No
1
I
vout3_d17 (9)
No
3
O
vout3_de (9)
No
4
O
uart7_rxd
No
5
I
timer16
No
7
IO
spi3_sclk
No
8
IO
0
kbd_row0
No
9
I
0
eQEP1A_in
No
10
I
0
14
IO
Yes
(7)
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
15
I
vin1a_fld0
No
0
I
vin1b_vsync1
No
1
I
vout3_clk (9)
No
4
O
uart7_txd
No
5
O
timer15
No
7
IO
spi3_d1
No
8
IO
0
kbd_row1
No
9
I
0
eQEP1B_in
No
10
I
0
14
IO
15
I
gpio3_1
Driver off
62
vddshv6
PULL
UP/DOWN
TYPE [14]
I
Driver off
vin1a_fld0
1.8/3.3
BUFFER
TYPE [13]
1
gpio3_0
AF9
15
HYS [12]
0
Yes
PD
POWER
[11]
No
(7)
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
No
Driver off
AD9
BALL
RESET
STATE [7]
vin1b_d7
Driver off
vin1a_d9
TYPE [6]
vin1a_d8
gpio3_12
AG2
MUXMODE
[5]
Terminal Configuration and Functions
Yes
(7)
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AE9
BALL NAME [2]
vin1a_hsync0
SIGNAL NAME [3]
74x [4]
vin1a_vsync0
E1
vin2a_clk0
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv6
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
No
0
I
No
1
I
vout3_hsync (9)
No
4
O
uart7_ctsn
No
5
I
timer14
No
7
IO
spi3_d0
No
8
IO
0
eQEP1_index
No
10
IO
0
gpio3_2
Yes (7)
14
IO
0
0
1
15
I
vin1a_vsync0
No
0
I
vin1b_de1
No
1
I
vout3_vsync (9)
No
4
O
uart7_rtsn
No
5
O
timer13
No
7
IO
spi3_cs0
No
8
IO
1
eQEP1_strobe
No
10
IO
0
14
IO
Yes
(7)
Driver off
vin1b_clk1
BALL
RESET
STATE [7]
vin1b_fld1
gpio3_3
AH7
TYPE [6]
vin1a_hsync0
Driver off
AF8
MUXMODE
[5]
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
15
I
vin1b_clk1
No
0
I
vin3a_clk0
No
6
I
gpio2_31
Yes (7)
14
IO
Driver off
15
I
vin2a_clk0
0
I
vout2_fld
4
O
emu5
5
O
kbd_row0
9
I
0
eQEP1A_in
10
I
0
gpio3_28
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv6
vddshv1
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
F2
F3
D3
F6
64
BALL NAME [2]
vin2a_d0
vin2a_d1
vin2a_d10
vin2a_d11
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
O
emu10
5
O
uart9_ctsn
7
I
1
spi4_d0
8
IO
0
kbd_row4
9
I
0
ehrpwm1B
10
O
gpio4_1
14
IO
Driver off
15
I
vin2a_d1
0
I
vout2_d22
4
O
emu11
5
O
uart9_rtsn
7
O
spi4_cs0
8
IO
1
kbd_row5
9
I
0
ehrpwm1_tripzone_input
10
IO
0
gpio4_2
14
IO
Driver off
15
I
vin2a_d10
0
I
mdio_mclk
3
O
vout2_d13
4
O
kbd_col7
9
O
ehrpwm2B
10
O
gpio4_11
14
IO
Driver off
15
I
vin2a_d11
0
I
mdio_d
3
IO
vout2_d12
4
O
kbd_row7
9
I
0
ehrpwm2_tripzone_input
10
IO
0
gpio4_12
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
I
1.8/3.3
vddshv1
PULL
UP/DOWN
TYPE [14]
4
15
1.8/3.3
BUFFER
TYPE [13]
0
PD
15
HYS [12]
vout2_d23
PD
PD
POWER
[11]
vin2a_d0
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PU/PD
Dual
Voltage
LVCMOS
PU/PD
Dual
Voltage
LVCMOS
PU/PD
0
0
0
1
0
1
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
D5
C2
C3
C4
BALL NAME [2]
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv1
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
vin2a_d12
0
I
rgmii1_txc
3
O
0
vout2_d11
4
O
mii1_rxclk
8
I
kbd_col8
9
O
eCAP2_in_PWM2_out
10
IO
gpio4_13
14
IO
Driver off
15
I
vin2a_d13
0
I
rgmii1_txctl
3
O
vout2_d10
4
O
mii1_rxdv
8
I
0
kbd_row8
9
I
0
eQEP3A_in
10
I
0
gpio4_14
14
IO
Driver off
15
I
vin2a_d14
0
I
rgmii1_txd3
3
O
vout2_d9
4
O
mii1_txclk
8
I
0
eQEP3B_in
10
I
0
gpio4_15
14
IO
Driver off
15
I
vin2a_d15
0
I
rgmii1_txd2
3
O
vout2_d8
4
O
mii1_txd0
8
O
eQEP3_index
10
IO
gpio4_16
14
IO
Driver off
15
I
0
0
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
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www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
B2
D6
C5
A3
66
BALL NAME [2]
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
15
1.8/3.3
POWER
[11]
vddshv1
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
vin2a_d16
0
I
vin2b_d7
2
I
rgmii1_txd1
3
O
vout2_d7
4
O
vin3a_d8
6
I
mii1_txd1
8
O
eQEP3_strobe
10
IO
gpio4_24
14
IO
Driver off
15
I
vin2a_d17
0
I
vin2b_d6
2
I
rgmii1_txd0
3
O
vout2_d6
4
O
vin3a_d9
6
I
mii1_txd2
8
O
ehrpwm3A
10
O
gpio4_25
14
IO
Driver off
15
I
vin2a_d18
0
I
vin2b_d5
2
I
rgmii1_rxc
3
I
vout2_d5
4
O
vin3a_d10
6
I
mii1_txd3
8
O
ehrpwm3B
10
O
gpio4_26
14
IO
Driver off
15
I
vin2a_d19
0
I
vin2b_d4
2
I
rgmii1_rxctl
3
I
vout2_d4
4
O
vin3a_d11
6
I
0
mii1_txer
8
O
0
ehrpwm3_tripzone_input
10
IO
0
gpio4_27
14
IO
Driver off
15
I
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
0
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
D1
B3
B4
B5
BALL NAME [2]
vin2a_d2
vin2a_d20
vin2a_d21
vin2a_d22
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
I
O
emu12
5
O
uart10_rxd
8
I
1
kbd_row6
9
I
0
eCAP1_in_PWM1_out
10
IO
0
gpio4_3
14
IO
Driver off
15
I
vin2a_d20
0
I
vin2b_d3
2
I
rgmii1_rxd3
3
I
vout2_d3
4
O
vin3a_de0
5
I
0
vin3a_d12
6
I
0
mii1_rxer
8
I
0
eCAP3_in_PWM3_out
10
IO
0
gpio4_28
14
IO
Driver off
15
I
vin2a_d21
0
I
vin2b_d2
2
I
rgmii1_rxd2
3
I
vout2_d2
4
O
vin3a_fld0
5
I
0
vin3a_d13
6
I
0
mii1_col
8
I
0
gpio4_29
14
IO
Driver off
15
I
vin2a_d22
0
I
vin2b_d1
2
I
rgmii1_rxd1
3
I
vout2_d1
4
O
vin3a_hsync0
5
I
0
vin3a_d14
6
I
0
mii1_crs
8
I
0
gpio4_30
14
IO
Driver off
15
I
vddshv1
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
DSIS [15]
4
1.8/3.3
vddshv1
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
vout2_d21
PD
15
HYS [12]
vin2a_d2
PD
PD
POWER
[11]
PU/PD
0
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
A4
E2
D2
F4
68
BALL NAME [2]
vin2a_d23
vin2a_d3
vin2a_d4
vin2a_d5
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
15
1.8/3.3
POWER
[11]
vddshv1
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
vin2a_d23
0
I
vin2b_d0
2
I
rgmii1_rxd0
3
I
vout2_d0
4
O
vin3a_vsync0
5
I
0
vin3a_d15
6
I
0
mii1_txen
8
O
gpio4_31
14
IO
Driver off
15
I
vin2a_d3
0
I
vout2_d20
4
O
emu13
5
O
uart10_txd
8
O
kbd_col0
9
O
ehrpwm1_synci
10
I
gpio4_4
14
IO
Driver off
15
I
vin2a_d4
0
I
vout2_d19
4
O
emu14
5
O
uart10_ctsn
8
I
kbd_col1
9
O
ehrpwm1_synco
10
O
gpio4_5
14
IO
Driver off
15
I
vin2a_d5
0
I
vout2_d18
4
O
emu15
5
O
uart10_rtsn
8
O
kbd_col2
9
O
eQEP2A_in
10
I
gpio4_6
14
IO
Driver off
15
I
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
C1
E4
F5
E6
BALL NAME [2]
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
vin2a_d6
0
I
vout2_d17
4
O
emu16
5
O
mii1_rxd1
8
I
kbd_col3
9
O
eQEP2B_in
10
I
gpio4_7
14
IO
Driver off
15
I
vin2a_d7
0
I
vout2_d16
4
O
emu17
5
O
mii1_rxd2
8
I
kbd_col4
9
O
eQEP2_index
10
IO
gpio4_8
14
IO
Driver off
15
I
vin2a_d8
0
I
vout2_d15
4
O
emu18
5
O
mii1_rxd3
8
I
kbd_col5
9
O
eQEP2_strobe
10
IO
gpio4_9
14
IO
Driver off
15
I
vin2a_d9
0
I
vout2_d14
4
O
emu19
5
O
mii1_rxd0
8
I
kbd_col6
9
O
ehrpwm2A
10
O
gpio4_10
14
IO
Driver off
15
I
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv1
HYS [12]
Yes
BUFFER
TYPE [13]
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
PU/PD
DSIS [15]
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
Terminal Configuration and Functions
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
G2
H7
G1
G6
70
BALL NAME [2]
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
I
vin2b_fld1
2
I
vin2b_de1
3
I
vout2_de
4
O
emu6
5
O
kbd_row1
9
I
0
eQEP1B_in
10
I
0
gpio3_29
14
IO
Driver off
15
I
vin2a_fld0
0
I
vin2b_clk1
2
I
vout2_clk
4
O
emu7
5
O
eQEP1_index
10
IO
gpio3_30
14
IO
Driver off
15
I
vin2a_hsync0
0
I
vin2b_hsync1
3
I
vout2_hsync
4
O
emu8
5
O
uart9_rxd
7
I
1
spi4_sclk
8
IO
0
kbd_row2
9
I
0
eQEP1_strobe
10
IO
0
gpio3_31
14
IO
Driver off
15
I
vin2a_vsync0
0
I
vin2b_vsync1
3
I
vout2_vsync
4
O
emu9
5
O
uart9_txd
7
O
spi4_d1
8
IO
0
kbd_row3
9
I
0
ehrpwm1A
10
O
gpio4_0
14
IO
Driver off
15
I
vddshv1
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
I
1.8/3.3
vddshv1
PULL
UP/DOWN
TYPE [14]
1
15
1.8/3.3
BUFFER
TYPE [13]
0
PD
15
HYS [12]
vin2a_fld0
PD
PD
POWER
[11]
vin2a_de0
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
Dual
Voltage
LVCMOS
PU/PD
PU/PD
0
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv1
vddshv1
Yes
Yes
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
PU/PD
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
D11
F11
G10
D7
D8
BALL NAME [2]
vout1_clk
vout1_d0
vout1_d1
vout1_d10
vout1_d11
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
O
I
vin3a_fld0
4
I
0
spi3_cs0
8
IO
1
gpio4_19
14
IO
Driver off
15
I
vout1_d0
0
O
uart5_rxd
2
I
vin4a_d16
3
I
0
vin3a_d16
4
I
0
spi3_cs2
8
IO
1
gpio8_0
14
IO
Driver off
15
I
vout1_d1
0
O
uart5_txd
2
O
vin4a_d17
3
I
0
vin3a_d17
4
I
0
gpio8_1
14
IO
Driver off
15
I
vout1_d10
0
O
emu3
2
O
vin4a_d10
3
I
0
vin3a_d10
4
I
0
obs5
5
O
obs21
6
O
obs_irq2
7
O
gpio8_10
14
IO
Driver off
15
I
vout1_d11
0
O
emu10
2
O
vin4a_d11
3
I
0
vin3a_d11
4
I
0
obs6
5
O
obs22
6
O
obs_dmarq2
7
O
gpio8_11
14
IO
Driver off
15
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
3
1.8/3.3
vddshv2
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
vin4a_fld0
PD
15
HYS [12]
vout1_clk
PD
PD
POWER
[11]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
0
PU/PD
1
PU/PD
PU/PD
PU/PD
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
A5
C6
C8
C7
72
BALL NAME [2]
vout1_d12
vout1_d13
vout1_d14
vout1_d15
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
O
vin4a_d12
3
I
0
vin3a_d12
4
I
0
obs7
5
O
obs23
6
O
gpio8_12
14
IO
Driver off
15
I
vout1_d13
0
O
emu12
2
O
vin4a_d13
3
I
0
vin3a_d13
4
I
0
obs8
5
O
obs24
6
O
gpio8_13
14
IO
Driver off
15
I
vout1_d14
0
O
emu13
2
O
vin4a_d14
3
I
0
vin3a_d14
4
I
0
obs9
5
O
obs25
6
O
gpio8_14
14
IO
Driver off
15
I
vout1_d15
0
O
emu14
2
O
vin4a_d15
3
I
0
vin3a_d15
4
I
0
obs10
5
O
obs26
6
O
gpio8_15
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
O
1.8/3.3
vddshv2
PULL
UP/DOWN
TYPE [14]
2
15
1.8/3.3
BUFFER
TYPE [13]
0
PD
15
HYS [12]
emu11
PD
PD
POWER
[11]
vout1_d12
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
B7
B8
A7
A8
F10
BALL NAME [2]
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d2
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
O
I
vin4a_d0
3
I
0
vin3a_d0
4
I
0
gpio8_16
14
IO
Driver off
15
I
vout1_d17
0
O
uart7_txd
2
O
vin4a_d1
3
I
0
vin3a_d1
4
I
0
gpio8_17
14
IO
Driver off
15
I
vout1_d18
0
O
emu4
2
O
vin4a_d2
3
I
0
vin3a_d2
4
I
0
obs11
5
O
obs27
6
O
gpio8_18
14
IO
Driver off
15
I
vout1_d19
0
O
emu15
2
O
vin4a_d3
3
I
0
vin3a_d3
4
I
0
obs12
5
O
obs28
6
O
gpio8_19
14
IO
Driver off
15
I
vout1_d2
0
O
emu2
2
O
vin4a_d18
3
I
0
vin3a_d18
4
I
0
obs0
5
O
obs16
6
O
obs_irq1
7
O
gpio8_2
14
IO
Driver off
15
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
2
1.8/3.3
vddshv2
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
uart7_rxd
PD
15
HYS [12]
vout1_d16
PD
PD
POWER
[11]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
1
PU/PD
PU/PD
PU/PD
PU/PD
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
C9
A9
B9
A10
74
BALL NAME [2]
vout1_d20
vout1_d21
vout1_d22
vout1_d23
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
O
vin4a_d4
3
I
0
vin3a_d4
4
I
0
obs13
5
O
obs29
6
O
gpio8_20
14
IO
Driver off
15
I
vout1_d21
0
O
emu17
2
O
vin4a_d5
3
I
0
vin3a_d5
4
I
0
obs14
5
O
obs30
6
O
gpio8_21
14
IO
Driver off
15
I
vout1_d22
0
O
emu18
2
O
vin4a_d6
3
I
0
vin3a_d6
4
I
0
obs15
5
O
obs31
6
O
gpio8_22
14
IO
Driver off
15
I
vout1_d23
0
O
emu19
2
O
vin4a_d7
3
I
0
vin3a_d7
4
I
0
spi3_cs3
8
IO
1
gpio8_23
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
O
1.8/3.3
vddshv2
PULL
UP/DOWN
TYPE [14]
2
15
1.8/3.3
BUFFER
TYPE [13]
0
PD
15
HYS [12]
emu16
PD
PD
POWER
[11]
vout1_d20
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
G11
E9
F9
F8
BALL NAME [2]
vout1_d3
vout1_d4
vout1_d5
vout1_d6
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
O
O
vin4a_d19
3
I
0
vin3a_d19
4
I
0
obs1
5
O
obs17
6
O
obs_dmarq1
7
O
gpio8_3
14
IO
Driver off
15
I
vout1_d4
0
O
emu6
2
O
vin4a_d20
3
I
0
vin3a_d20
4
I
0
obs2
5
O
obs18
6
O
gpio8_4
14
IO
Driver off
15
I
vout1_d5
0
O
emu7
2
O
vin4a_d21
3
I
0
vin3a_d21
4
I
0
obs3
5
O
obs19
6
O
gpio8_5
14
IO
Driver off
15
I
vout1_d6
0
O
emu8
2
O
vin4a_d22
3
I
0
vin3a_d22
4
I
0
obs4
5
O
obs20
6
O
gpio8_6
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
2
1.8/3.3
vddshv2
PULL
UP/DOWN
TYPE [14]
0
15
1.8/3.3
BUFFER
TYPE [13]
emu5
PD
15
HYS [12]
vout1_d3
PD
PD
POWER
[11]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
E7
E8
D9
B10
B11
C11
76
BALL NAME [2]
vout1_d7
vout1_d8
vout1_d9
vout1_de
vout1_fld
vout1_hsync
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
O
vin4a_d23
3
I
0
vin3a_d23
4
I
0
gpio8_7
14
IO
Driver off
15
I
vout1_d8
0
O
uart6_rxd
2
I
vin4a_d8
3
I
0
vin3a_d8
4
I
0
gpio8_8
14
IO
Driver off
15
I
vout1_d9
0
O
uart6_txd
2
O
vin4a_d9
3
I
0
vin3a_d9
4
I
0
gpio8_9
14
IO
Driver off
15
I
vout1_de
0
O
vin4a_de0
3
I
vin3a_de0
4
I
0
spi3_d1
8
IO
0
gpio4_20
14
IO
Driver off
15
I
vout1_fld
0
O
vin4a_clk0
3
I
vin3a_clk0
4
I
0
spi3_cs1
8
IO
1
gpio4_21
14
IO
Driver off
15
I
vout1_hsync
0
O
vin4a_hsync0
3
I
vin3a_hsync0
4
I
0
spi3_d0
8
IO
0
gpio4_22
14
IO
Driver off
15
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
DSIS [15]
O
1.8/3.3
vddshv2
PULL
UP/DOWN
TYPE [14]
2
15
1.8/3.3
BUFFER
TYPE [13]
0
PD
15
HYS [12]
emu9
PD
PD
POWER
[11]
vout1_d7
Terminal Configuration and Functions
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
Dual
Voltage
LVCMOS
PU/PD
PU/PD
1
PU/PD
PU/PD
0
PU/PD
0
PU/PD
0
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
E11
BALL NAME [2]
vout1_vsync
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
vin3a_vsync0
4
I
0
spi3_sclk
8
IO
0
gpio4_23
14
IO
Driver off
15
I
vssa_hdmi
GND
vssa_osc0
vssa_osc0
GND
AC14
vssa_osc1
vssa_osc1
GND
AD13, AE13
vssa_pcie
vssa_pcie
GND
AE10
vssa_sata
vssa_sata
GND
AA11, AB11
vssa_usb
vssa_usb
GND
AD10
vssa_usb3
vssa_usb3
GND
U14
vssa_video
vssa_video
AD17
Wakeup0
Wakeup0
0
I
dcan1_rx
1
I
gpio1_0
14
I
Driver off
15
I
Wakeup1
0
I
dcan2_rx
1
I
gpio1_1
14
I
Driver off
15
I
Wakeup1
Yes
Dual
Voltage
LVCMOS
DSIS [15]
I
vssa_hdmi
vddshv2
PULL
UP/DOWN
TYPE [14]
O
AF15
1.8/3.3
BUFFER
TYPE [13]
3
AD19, AE19
15
HYS [12]
0
GND
PD
POWER
[11]
vin4a_vsync0
vss
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
vout1_vsync
A1, A14, A2, A23, vss
A28, A6, AA10,
AA14, AA15, AA20,
AA8, AA9, AB14,
AB20, AD1, AD24,
AG1, AH1, AH2,
AH20, AH28, AH8,
B1, D13, D19, E13,
E19, F1, F7, G7,
G8, G9, H12, J12,
J15, J28, K1, K15,
K24, K25, K4, K5,
L13, L14, M19,
N14, N15, N19,
N24, N25, P28, R1,
R12, R13, R15,
R21, T10, T11,
T12, T14, T15, T17,
T18, T21, U15,
U17, U20, U21,
V15, V17, W1,
W15, W24, W25,
W28
AC17
BALL
RESET
STATE [7]
PU/PD
0
GND
OFF
OFF
15
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
1
OFF
OFF
15
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
1
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
AB16
AC16
BALL NAME [2]
Wakeup2
Wakeup3
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
Wakeup2
0
I
sys_nirq2
1
I
gpio1_2
14
I
Driver off
15
I
Wakeup3
0
I
sys_nirq1
1
I
gpio1_3
14
I
Driver off
15
I
BALL
RESET
STATE [7]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
OFF
OFF
15
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
OFF
OFF
15
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
DSIS [15]
AE15
xi_osc0
xi_osc0
0
I
1.8
vdda_osc
No
LVCMOS
Analog
NA
AC15
xi_osc1
xi_osc1
0
I
1.8
vdda_osc
No
LVCMOS
Analog
NA
AD15
xo_osc0
xo_osc0
0
O
1.8
vdda_osc
No
LVCMOS
Analog
NA
AC13
xo_osc1
xo_osc1
0
A
1.8
vdda_osc
No
LVCMOS
Analog
NA
D18
xref_clk0
xref_clk0
0
I
1.8/3.3
vddshv3
Yes
1
IO
Dual
Voltage
LVCMOS
PU/PD
mcasp2_axr8
mcasp1_axr4
2
IO
mcasp1_ahclkx
3
O
mcasp5_ahclkx
4
O
atl_clk0
5
O
7
I
0
hdq0
8
IO
1
clkout2
9
O
timer13
10
IO
gpio6_17
14
IO
Driver off
15
I
xref_clk1
0
I
mcasp2_axr9
1
IO
mcasp1_axr5
2
IO
mcasp2_ahclkx
3
O
mcasp6_ahclkx
4
O
atl_clk1
5
O
7
I
timer14
10
IO
gpio6_18
14
IO
Driver off
15
I
vin6a_d0
E17
xref_clk1
vin6a_clk0
78
Terminal Configuration and Functions
No
No
PD
PD
15
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER [1]
B26
C23
BALL NAME [2]
xref_clk2
xref_clk3
SIGNAL NAME [3]
74x [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
PD
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
REL.
MUXMODE VALUE [10]
STATE [8]
[9]
PD
15
1.8/3.3
POWER
[11]
vddshv3
BUFFER
TYPE [13]
HYS [12]
Yes
Dual
Voltage
LVCMOS
PULL
UP/DOWN
TYPE [14]
DSIS [15]
xref_clk2
0
I
mcasp2_axr10
1
IO
PU/PD
mcasp1_axr6
2
IO
mcasp3_ahclkx
3
O
mcasp7_ahclkx
4
O
atl_clk2
5
O
vout2_clk
6
O
vin4a_clk0
8
I
timer15
10
IO
gpio6_19
14
IO
Driver off
15
I
xref_clk3
0
I
mcasp2_axr11
1
IO
mcasp1_axr7
2
IO
mcasp4_ahclkx
3
O
mcasp8_ahclkx
4
O
atl_clk3
5
O
vout2_de
6
O
hdq0
7
IO
1
vin4a_de0
8
I
0
clkout3
9
O
timer16
10
IO
gpio6_20
14
IO
Driver off
15
I
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
(1) NA in this table stands for Not Applicable.
(2) For more information on recommended operating conditions, see Table 5-4, Recommended Operating Conditions.
(3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
(4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the
Device TRM.
(5) IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
(6) Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
(7) This function will not be supported on some pin-compatibleroadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals.
(8) In PUx / PDy, x and y = 60 to 200 μA.
The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.
(9) The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (i.e., VDDSHV6 must be supplied with 1.8V). 3.3V
mode is not supported. This must be considered in the pin mux programming and VDDSHVx supply connections.
Terminal Configuration and Functions
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4.3
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Multiplexing Characteristics
Table 4-3 describes the device multiplexing (no characteristics are available in this table).
NOTE
This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal
Descriptions.
NOTE
For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration
section of the Device TRM.
NOTE
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration. (Hi-Z mode is not an input signal.)
NOTE
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be
avoided.
CAUTION
The I/O timings provided in Section 7 Timing Requirements and Switching Characteristics are valid only if signals within
a single IOSET are used. The IOSETs are defined in the corresponding tables.
Table 4-3. Multiplexing Characteristics
ADDRESS
80
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
P25
ddr2_a6
Y23
ddr1_d26
Y19
ddr1_d21
AE15
xi_osc0
AH24
ddr1_nck
Terminal Configuration and Functions
1
2
3
4
5
6
7
8
9
10
14
15
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
AG15
ljcb_clkp
AF24
ddr1_d4
U25
ddr2_wen
F27
ddr2_d5
V25
ddr1_ecc_d6
M27
ddr2_dqsn3
G26
ddr2_d12
AG19
hdmi1_data2x
AF21
ddr1_a4
E27
ddr2_d6
F24
ddr2_d3
H26
ddr2_d11
W23
ddr1_ecc_d3
Y27
ddr1_dqsn3
AC24
ddr1_d14
J24
ddr2_d15
R26
ddr2_a1
G27
ddr2_dqsn0
AF28
ddr1_d11
AA23
ddr1_d24
AD18
ddr1_a15
H23
ddr2_d8
AH16
hdmi1_clocky
AC20
ddr1_a2
AA24
ddr1_d27
W19
ddr1_ecc_d2
L24
ddr2_d20
AG11
pcie_rxn1
AG21
ddr1_rst
AE28
ddr1_dqsn1
AC11
usb_txn0
L22
ddr2_d16
U28
ddr2_casn
K22
ddr2_d22
AG25
ddr1_dqsn0
W20
ddr1_d17
AF14
rtc_iso
AA27
ddr1_dqm3
AF25
ddr1_d0
1
2
3
4
5
6
7
8
9
10
14
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Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
82
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
AF23
ddr1_d6
AG18
hdmi1_data1x
AG10
sata1_txn0
AF20
ddr1_rasn
V26
ddr1_dqm_ec
c
V20
ddr1_d16
G25
ddr2_d1
AH13
pcie_rxp0
AC18
ddr1_casn
AG9
sata1_rxp0
AH23
ddr1_csn0
AE11
usb2_dp
R25
ddr2_a0
Y24
ddr1_d28
AH15
ljcb_clkn
AD20
ddr1_a0
AA25
ddr1_d30
L23
ddr2_d19
AA1
mlbp_dat_p
AD14
rtc_osc_xo
J25
ddr2_d13
AC25
ddr1_d13
AB23
ddr1_dqm1
U22
ddr2_a15
T22
ddr2_a13
AH19
hdmi1_data2y
M26
ddr2_d31
AB27
ddr1_d22
AG14
pcie_txn0
Y28
ddr1_dqs3
J20
ddr2_d23
AB19
ddr1_a3
AH10
sata1_txp0
G28
ddr2_dqs0
AG24
ddr1_ck
AE24
ddr1_d5
AC15
xi_osc1
AC21
ddr1_a12
Terminal Configuration and Functions
1
2
3
4
5
6
7
8
9
10
14
15
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
K28
ddr2_dqsn2
AB1
mlbp_clk_p
AF12
usb_rxn0
L28
ddr2_d27
M24
ddr2_d29
AH9
sata1_rxn0
AC26
ddr1_dqm2
AA28
ddr1_d31
H28
ddr2_dqsn1
AD23
ddr1_dqm0
E26
1
2
3
4
5
6
7
8
9
10
14
15
ddr2_d0
AE27
ddr1_dqs1
AF27
ddr1_d9
V24
ddr1_ecc_d5
K23
ddr2_dqm2
K20
ddr2_d17
T28
ddr2_ck
H24
ddr2_d10
AG27
ddr1_d10
R23
ddr2_odt0
U27
ddr2_ba1
AF22
ddr1_a8
AA2
mlbp_dat_n
U23
ddr2_ba0
AH21
ddr1_wen
AE21
ddr1_a7
AC12
usb1_dm
AH12
pcie_txp1
Y20
ddr1_d23
AC27
ddr1_d20
AE23
ddr1_d7
T27
ddr2_nck
AG22
ddr1_cke
AD27
ddr1_dqs2
AH14
pcie_txp0
AH26
ddr1_d3
AD21
ddr1_a10
N28
ddr2_a12
Y25
ddr1_ecc_d4
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Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
0
AE17
ddr1_a14
AH18
hdmi1_data1y
AH22
ddr1_a5
J26
ddr2_d14
W22
ddr1_ecc_d0
V23
ddr1_ecc_d1
AE12
usb_rxp0
AE14
rtc_osc_xi_clki
n32
AH11
pcie_rxp1
AB2
mlbp_clk_n
AG23
84
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
1
2
3
4
5
6
7
8
9
10
14
15
ddr1_a6
H27
ddr2_dqs1
AB18
ddr1_ba2
AG17
hdmi1_data0x
AF26
ddr1_d1
H25
ddr2_d9
M25
ddr2_d30
AD11
usb_txp0
AC1
mlbp_sig_p
L27
ddr2_d24
V27
ddr1_dqs_ecc
AF17
ddr1_ba0
AE26
ddr1_d12
G24
ddr2_dqm1
K27
ddr2_dqs2
AC19
ddr1_a1
AG13
pcie_rxn0
L26
ddr2_d25
AB28
ddr1_d18
N23
ddr2_a10
M22
ddr2_dqm3
U26
ddr2_ba2
Y26
ddr1_ecc_d7
P24
ddr2_csn0
R22
ddr2_a14
AD22
ddr1_a11
N20
ddr2_a7
M23
ddr2_d28
Terminal Configuration and Functions
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
AD28
0
ddr2_cke
P22
ddr2_a5
AE18
ddr1_ba1
F26
ddr2_d4
AE20
ddr1_odt0
N22
ddr2_vref0
E28
ddr2_d7
F25
ddr2_d2
AF11
usb2_dm
R24
ddr2_rst
AD15
xo_osc0
R27
ddr2_a3
AE22
ddr1_a9
AC13
3
4
5
6
7
8
9
10
14
15
ddr1_vref0
xo_osc1
F28
ddr2_dqm0
J23
ddr2_d21
P26
ddr2_a11
M28
ddr2_dqs3
AC2
mlbp_sig_n
AD12
usb1_dp
Y22
ddr1_d25
T23
ddr2_rasn
AH17
2
ddr1_dqsn2
U24
Y18
1
hdmi1_data0y
N27
ddr2_a9
P23
ddr2_a4
AG26
ddr1_d2
AH25
ddr1_dqs0
AG12
pcie_txn1
AF18
ddr1_a13
K21
ddr2_d18
AC28
ddr1_d19
V28
ddr1_dqsn_ec
c
P27
ddr2_a8
AC23
ddr1_d8
F22
porz
L25
ddr2_d26
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Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
86
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
AG16
hdmi1_clockx
R28
ddr2_a2
AA26
ddr1_d29
AD25
ddr1_d15
1
2
3
4
5
6
7
8
9
10
14
15
0x1400
CTRL_CORE_PAD_
GPMC_AD0
M6
gpmc_ad0
vin3a_d0
vout3_d0
gpio1_6
sysboot0
0x1404
CTRL_CORE_PAD_
GPMC_AD1
M2
gpmc_ad1
vin3a_d1
vout3_d1
gpio1_7
sysboot1
0x1408
CTRL_CORE_PAD_
GPMC_AD2
L5
gpmc_ad2
vin3a_d2
vout3_d2
gpio1_8
sysboot2
0x140C
CTRL_CORE_PAD_
GPMC_AD3
M1
gpmc_ad3
vin3a_d3
vout3_d3
gpio1_9
sysboot3
0x1410
CTRL_CORE_PAD_
GPMC_AD4
L6
gpmc_ad4
vin3a_d4
vout3_d4
gpio1_10
sysboot4
0x1414
CTRL_CORE_PAD_
GPMC_AD5
L4
gpmc_ad5
vin3a_d5
vout3_d5
gpio1_11
sysboot5
0x1418
CTRL_CORE_PAD_
GPMC_AD6
L3
gpmc_ad6
vin3a_d6
vout3_d6
gpio1_12
sysboot6
0x141C
CTRL_CORE_PAD_
GPMC_AD7
L2
gpmc_ad7
vin3a_d7
vout3_d7
gpio1_13
sysboot7
0x1420
CTRL_CORE_PAD_
GPMC_AD8
L1
gpmc_ad8
vin3a_d8
vout3_d8
gpio7_18
sysboot8
0x1424
CTRL_CORE_PAD_
GPMC_AD9
K2
gpmc_ad9
vin3a_d9
vout3_d9
gpio7_19
sysboot9
0x1428
CTRL_CORE_PAD_
GPMC_AD10
J1
gpmc_ad10
vin3a_d10
vout3_d10
gpio7_28
sysboot10
0x142C
CTRL_CORE_PAD_
GPMC_AD11
J2
gpmc_ad11
vin3a_d11
vout3_d11
gpio7_29
sysboot11
0x1430
CTRL_CORE_PAD_
GPMC_AD12
H1
gpmc_ad12
vin3a_d12
vout3_d12
gpio1_18
sysboot12
0x1434
CTRL_CORE_PAD_
GPMC_AD13
J3
gpmc_ad13
vin3a_d13
vout3_d13
gpio1_19
sysboot13
0x1438
CTRL_CORE_PAD_
GPMC_AD14
H2
gpmc_ad14
vin3a_d14
vout3_d14
gpio1_20
sysboot14
0x143C
CTRL_CORE_PAD_
GPMC_AD15
H3
gpmc_ad15
vin3a_d15
vout3_d15
gpio1_21
sysboot15
0x1440
CTRL_CORE_PAD_
GPMC_A0
R6
gpmc_a0
vin3a_d16
vout3_d16
vin4a_d0
vin4b_d0
i2c4_scl
uart5_rxd
gpio7_3
Driver off
0x1444
CTRL_CORE_PAD_
GPMC_A1
T9
gpmc_a1
vin3a_d17
vout3_d17
vin4a_d1
vin4b_d1
i2c4_sda
uart5_txd
gpio7_4
Driver off
0x1448
CTRL_CORE_PAD_
GPMC_A2
T6
gpmc_a2
vin3a_d18
vout3_d18
vin4a_d2
vin4b_d2
uart7_rxd
uart5_ctsn
gpio7_5
Driver off
0x144C
CTRL_CORE_PAD_
GPMC_A3
T7
gpmc_a3
qspi1_cs2
vin3a_d19
vout3_d19
vin4a_d3
vin4b_d3
uart7_txd
uart5_rtsn
gpio7_6
Driver off
0x1450
CTRL_CORE_PAD_
GPMC_A4
P6
gpmc_a4
qspi1_cs3
vin3a_d20
vout3_d20
vin4a_d4
vin4b_d4
i2c5_scl
uart6_rxd
gpio1_26
Driver off
Terminal Configuration and Functions
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
2
3
4
5
6
7
8
9
10
14
15
0x1454
CTRL_CORE_PAD_
GPMC_A5
R9
gpmc_a5
vin3a_d21
vout3_d21
vin4a_d5
vin4b_d5
i2c5_sda
uart6_txd
gpio1_27
Driver off
0x1458
CTRL_CORE_PAD_
GPMC_A6
R5
gpmc_a6
vin3a_d22
vout3_d22
vin4a_d6
vin4b_d6
uart8_rxd
uart6_ctsn
gpio1_28
Driver off
0x145C
CTRL_CORE_PAD_
GPMC_A7
P5
gpmc_a7
vin3a_d23
vout3_d23
vin4a_d7
vin4b_d7
uart8_txd
uart6_rtsn
gpio1_29
Driver off
0x1460
CTRL_CORE_PAD_
GPMC_A8
N7
gpmc_a8
vin3a_hsync0 vout3_hsync
vin4b_hsync1 timer12
spi4_sclk
gpio1_30
Driver off
0x1464
CTRL_CORE_PAD_
GPMC_A9
R4
gpmc_a9
vin3a_vsync0 vout3_vsync
vin4b_vsync1 timer11
spi4_d1
gpio1_31
Driver off
0x1468
CTRL_CORE_PAD_
GPMC_A10
N9
gpmc_a10
vin3a_de0
vout3_de
vin4b_clk1
timer10
spi4_d0
gpio2_0
Driver off
0x146C
CTRL_CORE_PAD_
GPMC_A11
P9
gpmc_a11
vin3a_fld0
vout3_fld
vin4b_de1
timer9
spi4_cs0
gpio2_1
Driver off
0x1470
CTRL_CORE_PAD_
GPMC_A12
P4
gpmc_a12
vin4b_fld1
timer8
spi4_cs1
dma_evt1
gpio2_2
Driver off
0x1474
CTRL_CORE_PAD_
GPMC_A13
R3
gpmc_a13
qspi1_rtclk
vin4a_hsync0
timer7
spi4_cs2
dma_evt2
gpio2_3
Driver off
0x1478
CTRL_CORE_PAD_
GPMC_A14
T2
gpmc_a14
qspi1_d3
vin4a_vsync0
timer6
spi4_cs3
gpio2_4
Driver off
0x147C
CTRL_CORE_PAD_
GPMC_A15
U2
gpmc_a15
qspi1_d2
vin4a_d8
timer5
gpio2_5
Driver off
0x1480
CTRL_CORE_PAD_
GPMC_A16
U1
gpmc_a16
qspi1_d0
vin4a_d9
gpio2_6
Driver off
0x1484
CTRL_CORE_PAD_
GPMC_A17
P3
gpmc_a17
qspi1_d1
vin4a_d10
gpio2_7
Driver off
0x1488
CTRL_CORE_PAD_
GPMC_A18
R2
gpmc_a18
qspi1_sclk
vin4a_d11
gpio2_8
Driver off
0x148C
CTRL_CORE_PAD_
GPMC_A19
K7
gpmc_a19
mmc2_dat4
gpmc_a13
vin4a_d12
vin3b_d0
gpio2_9
Driver off
0x1490
CTRL_CORE_PAD_
GPMC_A20
M7
gpmc_a20
mmc2_dat5
gpmc_a14
vin4a_d13
vin3b_d1
gpio2_10
Driver off
0x1494
CTRL_CORE_PAD_
GPMC_A21
J5
gpmc_a21
mmc2_dat6
gpmc_a15
vin4a_d14
vin3b_d2
gpio2_11
Driver off
0x1498
CTRL_CORE_PAD_
GPMC_A22
K6
gpmc_a22
mmc2_dat7
gpmc_a16
vin4a_d15
vin3b_d3
gpio2_12
Driver off
0x149C
CTRL_CORE_PAD_
GPMC_A23
J7
gpmc_a23
mmc2_clk
gpmc_a17
vin4a_fld0
vin3b_d4
gpio2_13
Driver off
0x14A0
CTRL_CORE_PAD_
GPMC_A24
J4
gpmc_a24
mmc2_dat0
gpmc_a18
vin4a_d8
vin3b_d5
gpio2_14
Driver off
0x14A4
CTRL_CORE_PAD_
GPMC_A25
J6
gpmc_a25
mmc2_dat1
gpmc_a19
vin4a_d9
vin3b_d6
gpio2_15
Driver off
0x14A8
CTRL_CORE_PAD_
GPMC_A26
H4
gpmc_a26
mmc2_dat2
gpmc_a20
vin4a_d10
vin3b_d7
gpio2_16
Driver off
0x14AC
CTRL_CORE_PAD_
GPMC_A27
H5
gpmc_a27
mmc2_dat3
gpmc_a21
vin4a_d11
vin3b_hsync1
gpio2_17
Driver off
0x14B0
CTRL_CORE_PAD_
GPMC_CS1
H6
gpmc_cs1
mmc2_cmd
gpmc_a22
vin4a_de0
vin3b_vsync1
gpio2_18
Driver off
vin4a_fld0
vin4a_clk0
gpmc_a0
Terminal Configuration and Functions
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Copyright © 2015–2016, Texas Instruments Incorporated
87
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
88
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
1
2
3
4
5
6
7
8
0x14B4
CTRL_CORE_PAD_
GPMC_CS0
T1
gpmc_cs0
0x14B8
CTRL_CORE_PAD_
GPMC_CS2
P2
gpmc_cs2
qspi1_cs0
0x14BC
CTRL_CORE_PAD_
GPMC_CS3
P1
gpmc_cs3
qspi1_cs1
vin3a_clk0
vout3_clk
0x14C0
CTRL_CORE_PAD_
GPMC_CLK
P7
gpmc_clk
gpmc_cs7
clkout1
gpmc_wait1
vin4a_hsync0 vin4a_de0
vin3b_clk1
timer4
i2c3_scl
0x14C4
CTRL_CORE_PAD_
GPMC_ADVN_ALE
N1
gpmc_advn_al gpmc_cs6
e
clkout2
gpmc_wait1
vin4a_vsync0 gpmc_a2
gpmc_a23
timer3
i2c3_sda
0x14C8
CTRL_CORE_PAD_
GPMC_OEN_REN
M5
0x14CC
CTRL_CORE_PAD_
GPMC_WEN
0x14D0
9
10
14
15
gpio2_19
Driver off
gpio2_20
Driver off
gpio2_21
Driver off
dma_evt1
gpio2_22
Driver off
dma_evt2
gpio2_23
Driver off
gpmc_oen_re
n
gpio2_24
Driver off
M3
gpmc_wen
gpio2_25
Driver off
CTRL_CORE_PAD_
GPMC_BEN0
N6
gpmc_ben0
gpmc_cs4
vin1b_hsync1
0x14D4
CTRL_CORE_PAD_
GPMC_BEN1
M4
gpmc_ben1
gpmc_cs5
vin1b_de1
0x14D8
CTRL_CORE_PAD_
GPMC_WAIT0
N2
gpmc_wait0
0x14DC
CTRL_CORE_PAD_V
IN1A_CLK0
AG8
vin1a_clk0
0x14E0
CTRL_CORE_PAD_V
IN1B_CLK1
AH7
vin1b_clk1
0x14E4
CTRL_CORE_PAD_V
IN1A_DE0
AD9
vin1a_de0
vin1b_hsync1
0x14E8
CTRL_CORE_PAD_V
IN1A_FLD0
AF9
vin1a_fld0
vin1b_vsync1
0x14EC
CTRL_CORE_PAD_V
IN1A_HSYNC0
AE9
0x14F0
CTRL_CORE_PAD_V
IN1A_VSYNC0
0x14F4
vout3_d16
gpmc_a1
vin3b_clk1
gpmc_a3
vin3b_de1
timer2
dma_evt3
gpio2_26
Driver off
vin3b_fld1
timer1
dma_evt4
gpio2_27
Driver off
gpio2_28
Driver off
gpio2_30
Driver off
gpio2_31
Driver off
vout3_fld
vin3a_clk0
vout3_de
uart7_rxd
timer16
spi3_sclk
kbd_row0
eQEP1A_in
gpio3_0
Driver off
vout3_clk
uart7_txd
timer15
spi3_d1
kbd_row1
eQEP1B_in
gpio3_1
Driver off
vin1a_hsync0 vin1b_fld1
vout3_hsync
uart7_ctsn
timer14
spi3_d0
eQEP1_index gpio3_2
Driver off
AF8
vin1a_vsync0 vin1b_de1
vout3_vsync
uart7_rtsn
timer13
spi3_cs0
eQEP1_strob gpio3_3
e
Driver off
CTRL_CORE_PAD_V
IN1A_D0
AE8
vin1a_d0
vout3_d7
vout3_d23
uart8_rxd
ehrpwm1A
gpio3_4
Driver off
0x14F8
CTRL_CORE_PAD_V
IN1A_D1
AD8
vin1a_d1
vout3_d6
vout3_d22
uart8_txd
ehrpwm1B
gpio3_5
Driver off
0x14FC
CTRL_CORE_PAD_V
IN1A_D2
AG7
vin1a_d2
vout3_d5
vout3_d21
uart8_ctsn
ehrpwm1_trip gpio3_6
zone_input
Driver off
0x1500
CTRL_CORE_PAD_V
IN1A_D3
AH6
vin1a_d3
vout3_d4
vout3_d20
uart8_rtsn
eCAP1_in_P
WM1_out
gpio3_7
Driver off
0x1504
CTRL_CORE_PAD_V
IN1A_D4
AH3
vin1a_d4
vout3_d3
vout3_d19
ehrpwm1_syn gpio3_8
ci
Driver off
0x1508
CTRL_CORE_PAD_V
IN1A_D5
AH5
vin1a_d5
vout3_d2
vout3_d18
ehrpwm1_syn gpio3_9
co
Driver off
0x150C
CTRL_CORE_PAD_V
IN1A_D6
AG6
vin1a_d6
vout3_d1
vout3_d17
eQEP2A_in
gpio3_10
Driver off
0x1510
CTRL_CORE_PAD_V
IN1A_D7
AH4
vin1a_d7
vout3_d0
vout3_d16
eQEP2B_in
gpio3_11
Driver off
Terminal Configuration and Functions
vout3_d17
Copyright © 2015–2016, Texas Instruments Incorporated
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
2
3
4
5
6
7
8
9
10
14
15
0x1514
CTRL_CORE_PAD_V
IN1A_D8
AG4
vin1a_d8
vin1b_d7
vout3_d15
kbd_row2
eQEP2_index gpio3_12
Driver off
0x1518
CTRL_CORE_PAD_V
IN1A_D9
AG2
vin1a_d9
vin1b_d6
vout3_d14
kbd_row3
eQEP2_strob gpio3_13
e
Driver off
0x151C
CTRL_CORE_PAD_V
IN1A_D10
AG3
vin1a_d10
vin1b_d5
vout3_d13
kbd_row4
gpio3_14
Driver off
0x1520
CTRL_CORE_PAD_V
IN1A_D11
AG5
vin1a_d11
vin1b_d4
vout3_d12
gpmc_a23
kbd_row5
gpio3_15
Driver off
0x1524
CTRL_CORE_PAD_V
IN1A_D12
AF2
vin1a_d12
vin1b_d3
usb3_ulpi_d7
vout3_d11
gpmc_a24
kbd_row6
gpio3_16
Driver off
0x1528
CTRL_CORE_PAD_V
IN1A_D13
AF6
vin1a_d13
vin1b_d2
usb3_ulpi_d6
vout3_d10
gpmc_a25
kbd_row7
gpio3_17
Driver off
0x152C
CTRL_CORE_PAD_V
IN1A_D14
AF3
vin1a_d14
vin1b_d1
usb3_ulpi_d5
vout3_d9
gpmc_a26
kbd_row8
gpio3_18
Driver off
0x1530
CTRL_CORE_PAD_V
IN1A_D15
AF4
vin1a_d15
vin1b_d0
usb3_ulpi_d4
vout3_d8
gpmc_a27
kbd_col0
gpio3_19
Driver off
0x1534
CTRL_CORE_PAD_V
IN1A_D16
AF1
vin1a_d16
vin1b_d7
usb3_ulpi_d3
vout3_d7
vin3a_d0
kbd_col1
gpio3_20
Driver off
0x1538
CTRL_CORE_PAD_V
IN1A_D17
AE3
vin1a_d17
vin1b_d6
usb3_ulpi_d2
vout3_d6
vin3a_d1
kbd_col2
gpio3_21
Driver off
0x153C
CTRL_CORE_PAD_V
IN1A_D18
AE5
vin1a_d18
vin1b_d5
usb3_ulpi_d1
vout3_d5
vin3a_d2
kbd_col3
gpio3_22
Driver off
0x1540
CTRL_CORE_PAD_V
IN1A_D19
AE1
vin1a_d19
vin1b_d4
usb3_ulpi_d0
vout3_d4
vin3a_d3
kbd_col4
gpio3_23
Driver off
0x1544
CTRL_CORE_PAD_V
IN1A_D20
AE2
vin1a_d20
vin1b_d3
usb3_ulpi_nxt
vout3_d3
vin3a_d4
kbd_col5
gpio3_24
Driver off
0x1548
CTRL_CORE_PAD_V
IN1A_D21
AE6
vin1a_d21
vin1b_d2
usb3_ulpi_dir
vout3_d2
vin3a_d5
kbd_col6
gpio3_25
Driver off
0x154C
CTRL_CORE_PAD_V
IN1A_D22
AD2
vin1a_d22
vin1b_d1
usb3_ulpi_stp
vout3_d1
vin3a_d6
kbd_col7
gpio3_26
Driver off
0x1550
CTRL_CORE_PAD_V
IN1A_D23
AD3
vin1a_d23
vin1b_d0
usb3_ulpi_clk
vout3_d0
vin3a_d7
kbd_col8
gpio3_27
Driver off
0x1554
CTRL_CORE_PAD_V
IN2A_CLK0
E1
vin2a_clk0
0x1558
CTRL_CORE_PAD_V
IN2A_DE0
G2
vin2a_de0
0x155C
CTRL_CORE_PAD_V
IN2A_FLD0
H7
vin2a_fld0
0x1560
CTRL_CORE_PAD_V
IN2A_HSYNC0
G1
vin2a_hsync0
vin2b_hsync1 vout2_hsync
emu8
uart9_rxd
spi4_sclk
0x1564
CTRL_CORE_PAD_V
IN2A_VSYNC0
G6
vin2a_vsync0
vin2b_vsync1 vout2_vsync
emu9
uart9_txd
0x1568
CTRL_CORE_PAD_V
IN2A_D0
F2
vin2a_d0
vout2_d23
emu10
0x156C
CTRL_CORE_PAD_V
IN2A_D1
F3
vin2a_d1
vout2_d22
emu11
0x1570
CTRL_CORE_PAD_V
IN2A_D2
D1
vin2a_d2
vout2_d21
emu12
vin2a_fld0
vin2b_fld1
vin2b_clk1
vin2b_de1
vout2_fld
emu5
kbd_row0
eQEP1A_in
gpio3_28
Driver off
vout2_de
emu6
kbd_row1
eQEP1B_in
gpio3_29
Driver off
vout2_clk
emu7
eQEP1_index gpio3_30
Driver off
kbd_row2
eQEP1_strob gpio3_31
e
Driver off
spi4_d1
kbd_row3
ehrpwm1A
gpio4_0
Driver off
uart9_ctsn
spi4_d0
kbd_row4
ehrpwm1B
gpio4_1
Driver off
uart9_rtsn
spi4_cs0
kbd_row5
ehrpwm1_trip gpio4_2
zone_input
Driver off
uart10_rxd
kbd_row6
eCAP1_in_P
WM1_out
Driver off
gpio4_3
Terminal Configuration and Functions
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Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
Copyright © 2015–2016, Texas Instruments Incorporated
89
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
90
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
14
15
0x1574
CTRL_CORE_PAD_V
IN2A_D3
E2
vin2a_d3
vout2_d20
emu13
uart10_txd
kbd_col0
ehrpwm1_syn gpio4_4
ci
Driver off
0x1578
CTRL_CORE_PAD_V
IN2A_D4
D2
vin2a_d4
vout2_d19
emu14
uart10_ctsn
kbd_col1
ehrpwm1_syn gpio4_5
co
Driver off
0x157C
CTRL_CORE_PAD_V
IN2A_D5
F4
vin2a_d5
vout2_d18
emu15
uart10_rtsn
kbd_col2
eQEP2A_in
gpio4_6
Driver off
0x1580
CTRL_CORE_PAD_V
IN2A_D6
C1
vin2a_d6
vout2_d17
emu16
mii1_rxd1
kbd_col3
eQEP2B_in
gpio4_7
Driver off
0x1584
CTRL_CORE_PAD_V
IN2A_D7
E4
vin2a_d7
vout2_d16
emu17
mii1_rxd2
kbd_col4
eQEP2_index gpio4_8
Driver off
0x1588
CTRL_CORE_PAD_V
IN2A_D8
F5
vin2a_d8
vout2_d15
emu18
mii1_rxd3
kbd_col5
eQEP2_strob gpio4_9
e
Driver off
0x158C
CTRL_CORE_PAD_V
IN2A_D9
E6
vin2a_d9
vout2_d14
emu19
mii1_rxd0
kbd_col6
ehrpwm2A
gpio4_10
Driver off
0x1590
CTRL_CORE_PAD_V
IN2A_D10
D3
vin2a_d10
mdio_mclk
vout2_d13
kbd_col7
ehrpwm2B
gpio4_11
Driver off
0x1594
CTRL_CORE_PAD_V
IN2A_D11
F6
vin2a_d11
mdio_d
vout2_d12
kbd_row7
ehrpwm2_trip gpio4_12
zone_input
Driver off
0x1598
CTRL_CORE_PAD_V
IN2A_D12
D5
vin2a_d12
rgmii1_txc
vout2_d11
mii1_rxclk
kbd_col8
eCAP2_in_P
WM2_out
gpio4_13
Driver off
0x159C
CTRL_CORE_PAD_V
IN2A_D13
C2
vin2a_d13
rgmii1_txctl
vout2_d10
mii1_rxdv
kbd_row8
eQEP3A_in
gpio4_14
Driver off
0x15A0
CTRL_CORE_PAD_V
IN2A_D14
C3
vin2a_d14
rgmii1_txd3
vout2_d9
mii1_txclk
eQEP3B_in
gpio4_15
Driver off
0x15A4
CTRL_CORE_PAD_V
IN2A_D15
C4
vin2a_d15
rgmii1_txd2
vout2_d8
mii1_txd0
eQEP3_index gpio4_16
Driver off
0x15A8
CTRL_CORE_PAD_V
IN2A_D16
B2
vin2a_d16
vin2b_d7
rgmii1_txd1
vout2_d7
vin3a_d8
mii1_txd1
eQEP3_strob gpio4_24
e
Driver off
0x15AC
CTRL_CORE_PAD_V
IN2A_D17
D6
vin2a_d17
vin2b_d6
rgmii1_txd0
vout2_d6
vin3a_d9
mii1_txd2
ehrpwm3A
gpio4_25
Driver off
0x15B0
CTRL_CORE_PAD_V
IN2A_D18
C5
vin2a_d18
vin2b_d5
rgmii1_rxc
vout2_d5
vin3a_d10
mii1_txd3
ehrpwm3B
gpio4_26
Driver off
0x15B4
CTRL_CORE_PAD_V
IN2A_D19
A3
vin2a_d19
vin2b_d4
rgmii1_rxctl
vout2_d4
vin3a_d11
mii1_txer
ehrpwm3_trip gpio4_27
zone_input
Driver off
0x15B8
CTRL_CORE_PAD_V
IN2A_D20
B3
vin2a_d20
vin2b_d3
rgmii1_rxd3
vout2_d3
vin3a_de0
vin3a_d12
mii1_rxer
eCAP3_in_P
WM3_out
gpio4_28
Driver off
0x15BC
CTRL_CORE_PAD_V
IN2A_D21
B4
vin2a_d21
vin2b_d2
rgmii1_rxd2
vout2_d2
vin3a_fld0
vin3a_d13
mii1_col
gpio4_29
Driver off
0x15C0
CTRL_CORE_PAD_V
IN2A_D22
B5
vin2a_d22
vin2b_d1
rgmii1_rxd1
vout2_d1
vin3a_hsync0 vin3a_d14
mii1_crs
gpio4_30
Driver off
0x15C4
CTRL_CORE_PAD_V
IN2A_D23
A4
vin2a_d23
vin2b_d0
rgmii1_rxd0
vout2_d0
vin3a_vsync0 vin3a_d15
mii1_txen
gpio4_31
Driver off
0x15C8
CTRL_CORE_PAD_V
OUT1_CLK
D11
vout1_clk
vin4a_fld0
vin3a_fld0
spi3_cs0
gpio4_19
Driver off
0x15CC
CTRL_CORE_PAD_V
OUT1_DE
B10
vout1_de
vin4a_de0
vin3a_de0
spi3_d1
gpio4_20
Driver off
0x15D0
CTRL_CORE_PAD_V
OUT1_FLD
B11
vout1_fld
vin4a_clk0
vin3a_clk0
spi3_cs1
gpio4_21
Driver off
Terminal Configuration and Functions
1
2
3
4
5
6
7
8
9
10
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
2
3
4
5
6
7
8
9
10
14
15
0x15D4
CTRL_CORE_PAD_V
OUT1_HSYNC
C11
vout1_hsync
vin4a_hsync0 vin3a_hsync0
spi3_d0
gpio4_22
Driver off
0x15D8
CTRL_CORE_PAD_V
OUT1_VSYNC
E11
vout1_vsync
vin4a_vsync0 vin3a_vsync0
spi3_sclk
gpio4_23
Driver off
0x15DC
CTRL_CORE_PAD_V
OUT1_D0
F11
vout1_d0
uart5_rxd
vin4a_d16
vin3a_d16
spi3_cs2
gpio8_0
Driver off
0x15E0
CTRL_CORE_PAD_V
OUT1_D1
G10
vout1_d1
uart5_txd
vin4a_d17
vin3a_d17
gpio8_1
Driver off
0x15E4
CTRL_CORE_PAD_V
OUT1_D2
F10
vout1_d2
emu2
vin4a_d18
vin3a_d18
obs0
obs16
obs_irq1
gpio8_2
Driver off
0x15E8
CTRL_CORE_PAD_V
OUT1_D3
G11
vout1_d3
emu5
vin4a_d19
vin3a_d19
obs1
obs17
obs_dmarq1
gpio8_3
Driver off
0x15EC
CTRL_CORE_PAD_V
OUT1_D4
E9
vout1_d4
emu6
vin4a_d20
vin3a_d20
obs2
obs18
gpio8_4
Driver off
0x15F0
CTRL_CORE_PAD_V
OUT1_D5
F9
vout1_d5
emu7
vin4a_d21
vin3a_d21
obs3
obs19
gpio8_5
Driver off
0x15F4
CTRL_CORE_PAD_V
OUT1_D6
F8
vout1_d6
emu8
vin4a_d22
vin3a_d22
obs4
obs20
gpio8_6
Driver off
0x15F8
CTRL_CORE_PAD_V
OUT1_D7
E7
vout1_d7
emu9
vin4a_d23
vin3a_d23
gpio8_7
Driver off
0x15FC
CTRL_CORE_PAD_V
OUT1_D8
E8
vout1_d8
uart6_rxd
vin4a_d8
vin3a_d8
gpio8_8
Driver off
0x1600
CTRL_CORE_PAD_V
OUT1_D9
D9
vout1_d9
uart6_txd
vin4a_d9
vin3a_d9
gpio8_9
Driver off
0x1604
CTRL_CORE_PAD_V
OUT1_D10
D7
vout1_d10
emu3
vin4a_d10
vin3a_d10
obs5
obs21
obs_irq2
gpio8_10
Driver off
0x1608
CTRL_CORE_PAD_V
OUT1_D11
D8
vout1_d11
emu10
vin4a_d11
vin3a_d11
obs6
obs22
obs_dmarq2
gpio8_11
Driver off
0x160C
CTRL_CORE_PAD_V
OUT1_D12
A5
vout1_d12
emu11
vin4a_d12
vin3a_d12
obs7
obs23
gpio8_12
Driver off
0x1610
CTRL_CORE_PAD_V
OUT1_D13
C6
vout1_d13
emu12
vin4a_d13
vin3a_d13
obs8
obs24
gpio8_13
Driver off
0x1614
CTRL_CORE_PAD_V
OUT1_D14
C8
vout1_d14
emu13
vin4a_d14
vin3a_d14
obs9
obs25
gpio8_14
Driver off
0x1618
CTRL_CORE_PAD_V
OUT1_D15
C7
vout1_d15
emu14
vin4a_d15
vin3a_d15
obs10
obs26
gpio8_15
Driver off
0x161C
CTRL_CORE_PAD_V
OUT1_D16
B7
vout1_d16
uart7_rxd
vin4a_d0
vin3a_d0
gpio8_16
Driver off
0x1620
CTRL_CORE_PAD_V
OUT1_D17
B8
vout1_d17
uart7_txd
vin4a_d1
vin3a_d1
gpio8_17
Driver off
0x1624
CTRL_CORE_PAD_V
OUT1_D18
A7
vout1_d18
emu4
vin4a_d2
vin3a_d2
obs11
obs27
gpio8_18
Driver off
0x1628
CTRL_CORE_PAD_V
OUT1_D19
A8
vout1_d19
emu15
vin4a_d3
vin3a_d3
obs12
obs28
gpio8_19
Driver off
0x162C
CTRL_CORE_PAD_V
OUT1_D20
C9
vout1_d20
emu16
vin4a_d4
vin3a_d4
obs13
obs29
gpio8_20
Driver off
0x1630
CTRL_CORE_PAD_V
OUT1_D21
A9
vout1_d21
emu17
vin4a_d5
vin3a_d5
obs14
obs30
gpio8_21
Driver off
Terminal Configuration and Functions
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Copyright © 2015–2016, Texas Instruments Incorporated
91
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
92
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
1
2
3
4
5
7
CTRL_CORE_PAD_V
OUT1_D22
B9
vout1_d22
emu18
vin4a_d6
vin3a_d6
0x1638
CTRL_CORE_PAD_V
OUT1_D23
A10
vout1_d23
emu19
vin4a_d7
vin3a_d7
0x163C
CTRL_CORE_PAD_
MDIO_MCLK
V1
mdio_mclk
uart3_rtsn
mii0_col
vin2a_clk0
0x1640
CTRL_CORE_PAD_
MDIO_D
U4
mdio_d
uart3_ctsn
mii0_txer
vin2a_d0
0x1644
CTRL_CORE_PAD_R
MII_MHZ_50_CLK
U3
RMII_MHZ_50
_CLK
0x1648
CTRL_CORE_PAD_U
ART3_RXD
V2
uart3_rxd
rmii1_crs
mii0_rxdv
vin2a_d1
vin4b_d1
spi3_sclk
0x164C
CTRL_CORE_PAD_U
ART3_TXD
Y1
uart3_txd
rmii1_rxer
mii0_rxclk
vin2a_d2
vin4b_d2
spi3_d1
0x1650
CTRL_CORE_PAD_R
GMII0_TXC
W9
rgmii0_txc
uart3_ctsn
rmii1_rxd1
mii0_rxd3
vin2a_d3
vin4b_d3
0x1654
CTRL_CORE_PAD_R
GMII0_TXCTL
V9
rgmii0_txctl
uart3_rtsn
rmii1_rxd0
mii0_rxd2
vin2a_d4
0x1658
CTRL_CORE_PAD_R
GMII0_TXD3
V7
rgmii0_txd3
rmii0_crs
mii0_crs
vin2a_de0
0x165C
CTRL_CORE_PAD_R
GMII0_TXD2
U7
rgmii0_txd2
rmii0_rxer
mii0_rxer
0x1660
CTRL_CORE_PAD_R
GMII0_TXD1
V6
rgmii0_txd1
rmii0_rxd1
0x1664
CTRL_CORE_PAD_R
GMII0_TXD0
U6
rgmii0_txd0
rmii0_rxd0
0x1668
CTRL_CORE_PAD_R
GMII0_RXC
U5
rgmii0_rxc
0x166C
CTRL_CORE_PAD_R
GMII0_RXCTL
V5
0x1670
CTRL_CORE_PAD_R
GMII0_RXD3
0x1674
8
9
10
obs31
14
15
gpio8_22
Driver off
gpio8_23
Driver off
vin4b_clk1
gpio5_15
Driver off
vin4b_d0
gpio5_16
Driver off
gpio5_17
Driver off
gpio5_18
Driver off
spi4_cs1
gpio5_19
Driver off
usb4_ulpi_clk spi3_d0
spi4_cs2
gpio5_20
Driver off
vin4b_d4
usb4_ulpi_stp spi3_cs0
spi4_cs3
gpio5_21
Driver off
vin4b_de1
usb4_ulpi_dir spi4_sclk
uart4_rxd
gpio5_22
Driver off
vin2a_hsync0 vin4b_hsync1 usb4_ulpi_nxt spi4_d1
uart4_txd
gpio5_23
Driver off
mii0_rxd1
vin2a_vsync0 vin4b_vsync1 usb4_ulpi_d0 spi4_d0
uart4_ctsn
gpio5_24
Driver off
mii0_rxd0
vin2a_d10
uart4_rtsn
gpio5_25
Driver off
rmii1_txen
mii0_txclk
vin2a_d5
vin4b_d5
usb4_ulpi_d2
gpio5_26
Driver off
rgmii0_rxctl
rmii1_txd1
mii0_txd3
vin2a_d6
vin4b_d6
usb4_ulpi_d3
gpio5_27
Driver off
V4
rgmii0_rxd3
rmii1_txd0
mii0_txd2
vin2a_d7
vin4b_d7
usb4_ulpi_d4
gpio5_28
Driver off
CTRL_CORE_PAD_R
GMII0_RXD2
V3
rgmii0_rxd2
rmii0_txen
mii0_txen
vin2a_d8
usb4_ulpi_d5
gpio5_29
Driver off
0x1678
CTRL_CORE_PAD_R
GMII0_RXD1
Y2
rgmii0_rxd1
rmii0_txd1
mii0_txd1
vin2a_d9
usb4_ulpi_d6
gpio5_30
Driver off
0x167C
CTRL_CORE_PAD_R
GMII0_RXD0
W2
rgmii0_rxd0
rmii0_txd0
mii0_txd0
vin2a_fld0
usb4_ulpi_d7
gpio5_31
Driver off
0x1680
CTRL_CORE_PAD_U
SB1_DRVVBUS
AB10
usb1_drvvbus
timer16
gpio6_12
Driver off
0x1684
CTRL_CORE_PAD_U
SB2_DRVVBUS
AC10
usb2_drvvbus
timer15
gpio6_13
Driver off
0x1688
CTRL_CORE_PAD_
GPIO6_14
E21
gpio6_14
mcasp1_axr8 dcan2_tx
uart10_rxd
vout2_hsync
vin4a_hsync0 i2c3_sda
timer1
gpio6_14
Driver off
0x168C
CTRL_CORE_PAD_
GPIO6_15
F20
gpio6_15
mcasp1_axr9 dcan2_rx
uart10_txd
vout2_vsync
vin4a_vsync0 i2c3_scl
timer2
gpio6_15
Driver off
0x1690
CTRL_CORE_PAD_
GPIO6_16
F21
gpio6_16
mcasp1_axr1
0
vout2_fld
vin4a_fld0
timer3
gpio6_16
Driver off
Terminal Configuration and Functions
obs15
6
0x1634
spi3_cs3
vin2a_d11
usb4_ulpi_d1 spi4_cs0
vin4b_fld1
clkout1
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
2
3
4
5
6
7
0x1694
CTRL_CORE_PAD_X
REF_CLK0
D18
xref_clk0
mcasp2_axr8 mcasp1_axr4 mcasp1_ahclk mcasp5_ahclk atl_clk0
x
x
vin6a_d0
0x1698
CTRL_CORE_PAD_X
REF_CLK1
E17
xref_clk1
mcasp2_axr9 mcasp1_axr5 mcasp2_ahclk mcasp6_ahclk atl_clk1
x
x
vin6a_clk0
0x169C
CTRL_CORE_PAD_X
REF_CLK2
B26
xref_clk2
mcasp2_axr1 mcasp1_axr6 mcasp3_ahclk mcasp7_ahclk atl_clk2
0
x
x
vout2_clk
0x16A0
CTRL_CORE_PAD_X
REF_CLK3
C23
xref_clk3
mcasp2_axr1 mcasp1_axr7 mcasp4_ahclk mcasp8_ahclk atl_clk3
1
x
x
vout2_de
0x16A4
CTRL_CORE_PAD_
MCASP1_ACLKX
C14
mcasp1_aclkx
0x16A8
CTRL_CORE_PAD_
MCASP1_FSX
D14
mcasp1_fsx
0x16AC
CTRL_CORE_PAD_
MCASP1_ACLKR
B14
mcasp1_aclkr mcasp7_axr2
vout2_d0
0x16B0
CTRL_CORE_PAD_
MCASP1_FSR
J14
mcasp1_fsr
vout2_d1
0x16B4
CTRL_CORE_PAD_
MCASP1_AXR0
G12
mcasp1_axr0
uart6_rxd
0x16B8
CTRL_CORE_PAD_
MCASP1_AXR1
F12
mcasp1_axr1
uart6_txd
0x16BC
CTRL_CORE_PAD_
MCASP1_AXR2
G13
mcasp1_axr2 mcasp6_axr2
uart6_ctsn
vout2_d2
0x16C0
CTRL_CORE_PAD_
MCASP1_AXR3
J11
mcasp1_axr3 mcasp6_axr3
uart6_rtsn
0x16C4
CTRL_CORE_PAD_
MCASP1_AXR4
E12
0x16C8
CTRL_CORE_PAD_
MCASP1_AXR5
0x16CC
8
9
14
15
gpio6_17
Driver off
timer14
gpio6_18
Driver off
timer15
gpio6_19
Driver off
timer16
gpio6_20
Driver off
vin6a_fld0
i2c3_sda
gpio7_31
Driver off
vin6a_de0
i2c3_scl
gpio7_30
Driver off
vin4a_d0
i2c4_sda
gpio5_0
Driver off
vin4a_d1
i2c4_scl
gpio5_1
Driver off
vin6a_vsync0
i2c5_sda
gpio5_2
Driver off
vin6a_hsync0
i2c5_scl
gpio5_3
Driver off
vin4a_d2
gpio5_4
Driver off
vout2_d3
vin4a_d3
gpio5_5
Driver off
mcasp1_axr4 mcasp4_axr2
vout2_d4
vin4a_d4
gpio5_6
Driver off
F13
mcasp1_axr5 mcasp4_axr3
vout2_d5
vin4a_d5
gpio5_7
Driver off
CTRL_CORE_PAD_
MCASP1_AXR6
C12
mcasp1_axr6 mcasp5_axr2
vout2_d6
vin4a_d6
gpio5_8
Driver off
0x16D0
CTRL_CORE_PAD_
MCASP1_AXR7
D12
mcasp1_axr7 mcasp5_axr3
vout2_d7
vin4a_d7
timer4
gpio5_9
Driver off
0x16D4
CTRL_CORE_PAD_
MCASP1_AXR8
B12
mcasp1_axr8 mcasp6_axr0
spi3_sclk
vin6a_d15
timer5
gpio5_10
Driver off
0x16D8
CTRL_CORE_PAD_
MCASP1_AXR9
A11
mcasp1_axr9 mcasp6_axr1
spi3_d1
vin6a_d14
timer6
gpio5_11
Driver off
0x16DC
CTRL_CORE_PAD_
MCASP1_AXR10
B13
mcasp1_axr1 mcasp6_aclkx mcasp6_aclkr spi3_d0
0
vin6a_d13
timer7
gpio5_12
Driver off
0x16E0
CTRL_CORE_PAD_
MCASP1_AXR11
A12
mcasp1_axr1 mcasp6_fsx
1
spi3_cs0
vin6a_d12
timer8
gpio4_17
Driver off
0x16E4
CTRL_CORE_PAD_
MCASP1_AXR12
E14
mcasp1_axr1 mcasp7_axr0
2
spi3_cs1
vin6a_d11
timer9
gpio4_18
Driver off
0x16E8
CTRL_CORE_PAD_
MCASP1_AXR13
A13
mcasp1_axr1 mcasp7_axr1
3
vin6a_d10
timer10
gpio6_4
Driver off
0x16EC
CTRL_CORE_PAD_
MCASP1_AXR14
G14
mcasp1_axr1 mcasp7_aclkx mcasp7_aclkr
4
vin6a_d9
timer11
gpio6_5
Driver off
0x16F0
CTRL_CORE_PAD_
MCASP1_AXR15
F14
mcasp1_axr1 mcasp7_fsx
5
vin6a_d8
timer12
gpio6_6
Driver off
mcasp6_fsr
mcasp7_fsr
clkout2
10
timer13
mcasp7_axr3
hdq0
vin4a_clk0
hdq0
vin4a_de0
clkout3
Terminal Configuration and Functions
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Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
Copyright © 2015–2016, Texas Instruments Incorporated
93
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
94
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
1
2
3
4
5
6
7
8
9
10
14
15
0x16F4
CTRL_CORE_PAD_
MCASP2_ACLKX
A19
mcasp2_aclkx
vin6a_d7
Driver off
0x16F8
CTRL_CORE_PAD_
MCASP2_FSX
A18
mcasp2_fsx
vin6a_d6
Driver off
0x16FC
CTRL_CORE_PAD_
MCASP2_ACLKR
E15
mcasp2_aclkr mcasp8_axr2
vout2_d8
vin4a_d8
Driver off
0x1700
CTRL_CORE_PAD_
MCASP2_FSR
A20
mcasp2_fsr
vout2_d9
vin4a_d9
Driver off
0x1704
CTRL_CORE_PAD_
MCASP2_AXR0
B15
mcasp2_axr0
vout2_d10
vin4a_d10
Driver off
0x1708
CTRL_CORE_PAD_
MCASP2_AXR1
A15
mcasp2_axr1
vout2_d11
vin4a_d11
Driver off
0x170C
CTRL_CORE_PAD_
MCASP2_AXR2
C15
mcasp2_axr2 mcasp3_axr2
vin6a_d5
gpio6_8
Driver off
0x1710
CTRL_CORE_PAD_
MCASP2_AXR3
A16
mcasp2_axr3 mcasp3_axr3
vin6a_d4
gpio6_9
Driver off
0x1714
CTRL_CORE_PAD_
MCASP2_AXR4
D15
mcasp2_axr4 mcasp8_axr0
vout2_d12
vin4a_d12
gpio1_4
Driver off
0x1718
CTRL_CORE_PAD_
MCASP2_AXR5
B16
mcasp2_axr5 mcasp8_axr1
vout2_d13
vin4a_d13
gpio6_7
Driver off
0x171C
CTRL_CORE_PAD_
MCASP2_AXR6
B17
mcasp2_axr6 mcasp8_aclkx mcasp8_aclkr
vout2_d14
vin4a_d14
gpio2_29
Driver off
0x1720
CTRL_CORE_PAD_
MCASP2_AXR7
A17
mcasp2_axr7 mcasp8_fsx
vout2_d15
vin4a_d15
gpio1_5
Driver off
0x1724
CTRL_CORE_PAD_
MCASP3_ACLKX
B18
mcasp3_aclkx mcasp3_aclkr mcasp2_axr1 uart7_rxd
2
vin6a_d3
gpio5_13
Driver off
0x1728
CTRL_CORE_PAD_
MCASP3_FSX
F15
mcasp3_fsx
vin6a_d2
gpio5_14
Driver off
0x172C
CTRL_CORE_PAD_
MCASP3_AXR0
B19
mcasp3_axr0
mcasp2_axr1 uart7_ctsn
4
uart5_rxd
vin6a_d1
0x1730
CTRL_CORE_PAD_
MCASP3_AXR1
C17
mcasp3_axr1
mcasp2_axr1 uart7_rtsn
5
uart5_txd
vin6a_d0
0x1734
CTRL_CORE_PAD_
MCASP4_ACLKX
C18
mcasp4_aclkx mcasp4_aclkr spi3_sclk
uart8_rxd
i2c4_sda
vout2_d16
0x1738
CTRL_CORE_PAD_
MCASP4_FSX
A21
mcasp4_fsx
spi3_d1
uart8_txd
i2c4_scl
0x173C
CTRL_CORE_PAD_
MCASP4_AXR0
G16
mcasp4_axr0
spi3_d0
uart8_ctsn
0x1740
CTRL_CORE_PAD_
MCASP4_AXR1
D17
mcasp4_axr1
spi3_cs0
0x1744
CTRL_CORE_PAD_
MCASP5_ACLKX
AA3
0x1748
CTRL_CORE_PAD_
MCASP5_FSX
0x174C
0x1750
mcasp8_axr3
mcasp3_fsr
mcasp8_fsr
mcasp2_axr1 uart7_txd
3
Driver off
vin5a_fld0
Driver off
vin4a_d16
vin5a_d15
Driver off
vout2_d17
vin4a_d17
vin5a_d14
Driver off
uart4_rxd
vout2_d18
vin4a_d18
vin5a_d13
Driver off
uart8_rtsn
uart4_txd
vout2_d19
vin4a_d19
vin5a_d12
Driver off
mcasp5_aclkx mcasp5_aclkr spi4_sclk
uart9_rxd
i2c5_sda
vout2_d20
vin4a_d20
vin5a_d11
Driver off
AB9
mcasp5_fsx
spi4_d1
uart9_txd
i2c5_scl
vout2_d21
vin4a_d21
vin5a_d10
Driver off
CTRL_CORE_PAD_
MCASP5_AXR0
AB3
mcasp5_axr0
spi4_d0
uart9_ctsn
uart3_rxd
mlb_sig
vout2_d22
vin4a_d22
vin5a_d9
Driver off
CTRL_CORE_PAD_
MCASP5_AXR1
AA4
mcasp5_axr1
spi4_cs0
uart9_rtsn
uart3_txd
mlb_dat
vout2_d23
vin4a_d23
vin5a_d8
Driver off
Terminal Configuration and Functions
mcasp4_fsr
mcasp5_fsr
mlb_clk
Copyright © 2015–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
2
3
4
5
6
7
8
9
10
14
15
0x1754
CTRL_CORE_PAD_
MMC1_CLK
W6
mmc1_clk
gpio6_21
Driver off
0x1758
CTRL_CORE_PAD_
MMC1_CMD
Y6
mmc1_cmd
gpio6_22
Driver off
0x175C
CTRL_CORE_PAD_
MMC1_DAT0
AA6
mmc1_dat0
gpio6_23
Driver off
0x1760
CTRL_CORE_PAD_
MMC1_DAT1
Y4
mmc1_dat1
gpio6_24
Driver off
0x1764
CTRL_CORE_PAD_
MMC1_DAT2
AA5
mmc1_dat2
gpio6_25
Driver off
0x1768
CTRL_CORE_PAD_
MMC1_DAT3
Y3
mmc1_dat3
gpio6_26
Driver off
0x176C
CTRL_CORE_PAD_
MMC1_SDCD
W7
mmc1_sdcd
uart6_rxd
i2c4_sda
gpio6_27
Driver off
0x1770
CTRL_CORE_PAD_
MMC1_SDWP
Y9
mmc1_sdwp
uart6_txd
i2c4_scl
gpio6_28
Driver off
0x1774
CTRL_CORE_PAD_
GPIO6_10
AC5
gpio6_10
mdio_mclk
i2c3_sda
usb3_ulpi_d7 vin2b_hsync1
vin5a_clk0
ehrpwm2A
gpio6_10
Driver off
0x1778
CTRL_CORE_PAD_
GPIO6_11
AB4
gpio6_11
mdio_d
i2c3_scl
usb3_ulpi_d6 vin2b_vsync1
vin5a_de0
ehrpwm2B
gpio6_11
Driver off
0x177C
CTRL_CORE_PAD_
MMC3_CLK
AD4
mmc3_clk
usb3_ulpi_d5 vin2b_d7
vin5a_d7
ehrpwm2_trip gpio6_29
zone_input
Driver off
0x1780
CTRL_CORE_PAD_
MMC3_CMD
AC4
mmc3_cmd
spi3_sclk
usb3_ulpi_d4 vin2b_d6
vin5a_d6
eCAP2_in_P
WM2_out
gpio6_30
Driver off
0x1784
CTRL_CORE_PAD_
MMC3_DAT0
AC7
mmc3_dat0
spi3_d1
uart5_rxd
usb3_ulpi_d3 vin2b_d5
vin5a_d5
eQEP3A_in
gpio6_31
Driver off
0x1788
CTRL_CORE_PAD_
MMC3_DAT1
AC6
mmc3_dat1
spi3_d0
uart5_txd
usb3_ulpi_d2 vin2b_d4
vin5a_d4
eQEP3B_in
gpio7_0
Driver off
0x178C
CTRL_CORE_PAD_
MMC3_DAT2
AC9
mmc3_dat2
spi3_cs0
uart5_ctsn
usb3_ulpi_d1 vin2b_d3
vin5a_d3
eQEP3_index gpio7_1
Driver off
0x1790
CTRL_CORE_PAD_
MMC3_DAT3
AC3
mmc3_dat3
spi3_cs1
uart5_rtsn
usb3_ulpi_d0 vin2b_d2
vin5a_d2
eQEP3_strob gpio7_2
e
Driver off
0x1794
CTRL_CORE_PAD_
MMC3_DAT4
AC8
mmc3_dat4
spi4_sclk
uart10_rxd
usb3_ulpi_nxt vin2b_d1
vin5a_d1
ehrpwm3A
gpio1_22
Driver off
0x1798
CTRL_CORE_PAD_
MMC3_DAT5
AD6
mmc3_dat5
spi4_d1
uart10_txd
usb3_ulpi_dir vin2b_d0
vin5a_d0
ehrpwm3B
gpio1_23
Driver off
0x179C
CTRL_CORE_PAD_
MMC3_DAT6
AB8
mmc3_dat6
spi4_d0
uart10_ctsn
usb3_ulpi_stp vin2b_de1
vin5a_hsync0 ehrpwm3_trip gpio1_24
zone_input
Driver off
0x17A0
CTRL_CORE_PAD_
MMC3_DAT7
AB5
mmc3_dat7
spi4_cs0
uart10_rtsn
usb3_ulpi_clk vin2b_clk1
vin5a_vsync0 eCAP3_in_P
WM3_out
gpio1_25
Driver off
0x17A4
CTRL_CORE_PAD_S
PI1_SCLK
A25
spi1_sclk
gpio7_7
Driver off
0x17A8
CTRL_CORE_PAD_S
PI1_D1
F16
spi1_d1
gpio7_8
Driver off
0x17AC
CTRL_CORE_PAD_S
PI1_D0
B25
spi1_d0
gpio7_9
Driver off
0x17B0
CTRL_CORE_PAD_S
PI1_CS0
A24
spi1_cs0
gpio7_10
Driver off
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Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
96
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
0x17B4
CTRL_CORE_PAD_S
PI1_CS1
A22
spi1_cs1
0x17B8
CTRL_CORE_PAD_S
PI1_CS2
B21
spi1_cs2
0x17BC
CTRL_CORE_PAD_S
PI1_CS3
B20
0x17C0
CTRL_CORE_PAD_S
PI2_SCLK
0x17C4
1
2
3
4
5
sata1_led
spi2_cs1
uart4_rxd
mmc3_sdcd
spi2_cs2
dcan2_tx
mdio_mclk
spi1_cs3
uart4_txd
mmc3_sdwp
spi2_cs3
dcan2_rx
mdio_d
A26
spi2_sclk
CTRL_CORE_PAD_S
PI2_D1
B22
0x17C8
CTRL_CORE_PAD_S
PI2_D0
0x17CC
6
7
8
9
10
14
15
gpio7_11
Driver off
hdmi1_hpd
gpio7_12
Driver off
hdmi1_cec
gpio7_13
Driver off
uart3_rxd
gpio7_14
Driver off
spi2_d1
uart3_txd
gpio7_15
Driver off
G17
spi2_d0
uart3_ctsn
uart5_rxd
gpio7_16
Driver off
CTRL_CORE_PAD_S
PI2_CS0
B24
spi2_cs0
uart3_rtsn
uart5_txd
gpio7_17
Driver off
0x17D0
CTRL_CORE_PAD_D
CAN1_TX
G20
dcan1_tx
uart8_rxd
mmc2_sdcd
hdmi1_hpd
gpio1_14
Driver off
0x17D4
CTRL_CORE_PAD_D
CAN1_RX
G19
dcan1_rx
uart8_txd
mmc2_sdwp
hdmi1_cec
gpio1_15
Driver off
0x17E0
CTRL_CORE_PAD_U
ART1_RXD
B27
uart1_rxd
mmc4_sdcd
gpio7_22
Driver off
0x17E4
CTRL_CORE_PAD_U
ART1_TXD
C26
uart1_txd
mmc4_sdwp
gpio7_23
Driver off
0x17E8
CTRL_CORE_PAD_U
ART1_CTSN
E25
uart1_ctsn
uart9_rxd
mmc4_clk
gpio7_24
Driver off
0x17EC
CTRL_CORE_PAD_U
ART1_RTSN
C27
uart1_rtsn
uart9_txd
mmc4_cmd
gpio7_25
Driver off
0x17F0
CTRL_CORE_PAD_U
ART2_RXD
D28
uart3_ctsn
uart3_rctx
mmc4_dat0
uart2_rxd
uart1_dcdn
gpio7_26
Driver off
0x17F4
CTRL_CORE_PAD_U
ART2_TXD
D26
uart2_txd
uart3_rtsn
uart3_sd
mmc4_dat1
uart2_txd
uart1_dsrn
gpio7_27
Driver off
0x17F8
CTRL_CORE_PAD_U
ART2_CTSN
D27
uart2_ctsn
uart3_rxd
mmc4_dat2
uart10_rxd
uart1_dtrn
gpio1_16
Driver off
0x17FC
CTRL_CORE_PAD_U
ART2_RTSN
C28
uart2_rtsn
uart3_irtx
mmc4_dat3
uart10_txd
uart1_rin
gpio1_17
Driver off
0x1800
CTRL_CORE_PAD_I
2C1_SDA
C21
i2c1_sda
0x1804
CTRL_CORE_PAD_I
2C1_SCL
C20
i2c1_scl
0x1808
CTRL_CORE_PAD_I
2C2_SDA
C25
i2c2_sda
hdmi1_ddc_sc
l
Driver off
0x180C
CTRL_CORE_PAD_I
2C2_SCL
F17
i2c2_scl
hdmi1_ddc_sd
a
Driver off
0x1818
CTRL_CORE_PAD_
WAKEUP0
AD17
Wakeup0
dcan1_rx
gpio1_0
Driver off
0x181C
CTRL_CORE_PAD_
WAKEUP1
AC17
Wakeup1
dcan2_rx
gpio1_1
Driver off
0x1820
CTRL_CORE_PAD_
WAKEUP2
AB16
Wakeup2
sys_nirq2
gpio1_2
Driver off
Terminal Configuration and Functions
uart3_txd
sata1_led
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
Wakeup3
1
sys_nirq1
2
3
4
5
6
7
8
9
10
14
15
gpio1_3
Driver off
0x1824
CTRL_CORE_PAD_
WAKEUP3
AC16
0x1828
CTRL_CORE_PAD_
ON_OFF
Y11
0x182C
CTRL_CORE_PAD_R
TC_PORZ
AB17
0x1830
CTRL_CORE_PAD_T
MS
F18
tms
0x1834
CTRL_CORE_PAD_T
DI
D23
tdi
gpio8_27
0x1838
CTRL_CORE_PAD_T
DO
F19
tdo
gpio8_28
0x183C
CTRL_CORE_PAD_T
CLK
E20
tclk
0x1840
CTRL_CORE_PAD_T
RSTN
D20
trstn
0x1844
CTRL_CORE_PAD_R
TCK
E18
rtck
gpio8_29
0x1848
CTRL_CORE_PAD_E
MU0
G21
emu0
gpio8_30
0x184C
CTRL_CORE_PAD_E
MU1
D24
emu1
gpio8_31
0x185C
CTRL_CORE_PAD_R
ESETN
E23
resetn
0x1860
CTRL_CORE_PAD_N
MIN_DSP
D21
nmin_dsp
0x1864
CTRL_CORE_PAD_R
STOUTN
F23
rstoutn
on_off
rtc_porz
1. NA in table stands for Not Applicable.
Terminal Configuration and Functions
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4.4
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Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
1. SIGNAL NAME: The name of the signal passing through the pin.
NOTE
The subsystem multiplexing signals are not described in Table 4-2 and Table 4-3.
2. DESCRIPTION: Description of the signal
3. TYPE: Signal direction and type:
– I = Input
– O = Output
– IO = Input or output
– D = Open Drain
– DS = Differential
– A = Analog
– PWR = Power
– GND = Ground
4. BALL: Associated ball(s) bottom
NOTE
For more information, see the Control Module / Control Module Register Manual section of
the device TRM.
4.4.1
Video Input Ports (VIP)
NOTE
For more information, see the Video Input Port (VIP) section of the device TRM.
CAUTION
The I/O timings provided in Section 7 Timing Requirements and Switching
Characteristics are applicable for all combinations of signals for vin1, vin5 and
vin6. However, the timings are only valid for vin2, vin3, and vin4 if signals within
a single IOSET are used. The IOSETs are defined in the Table 7-4, Table 7-5
and Table 7-6.
Table 4-4. VIP Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
I
AG8
I
AD9
Video Input 1
98
vin1a_clk0
Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video
capture. Input data is sampled on the CLK0 edge.
vin1a_de0
Video Input 1 Data Enable input
vin1a_fld0
Video Input 1 Port A Field ID input
(1)
(1)
vin1a_hsync0
Video Input 1 Port A Horizontal Sync input
vin1a_vsync0
Video Input 1 Port A Vertical Sync input
(1)
(1)
I
AF9
I
AE9
I
AF8
I
AE8
vin1a_d0
Video Input 1 Port A Data input
(1)
vin1a_d1
Video Input 1 Port A Data input
(1)
I
AD8
vin1a_d2
Video Input 1 Port A Data input
(1)
I
AG7
Terminal Configuration and Functions
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
Video Input 1 Port A Data input
(1)
I
AH6
vin1a_d4
Video Input 1 Port A Data input
(1)
I
AH3
vin1a_d5
Video Input 1 Port A Data input
(1)
I
AH5
vin1a_d6
Video Input 1 Port A Data input
(1)
I
AG6
vin1a_d7
Video Input 1 Port A Data input
(1)
I
AH4
vin1a_d8
Video Input 1 Port A Data input
(1)
I
AG4
vin1a_d9
Video Input 1 Port A Data input
(1)
I
AG2
vin1a_d10
Video Input 1 Port A Data input
(1)
I
AG3
vin1a_d11
Video Input 1 Port A Data input
(1)
I
AG5
vin1a_d12
Video Input 1 Port A Data input
(1)
I
AF2
vin1a_d13
Video Input 1 Port A Data input
(1)
I
AF6
vin1a_d14
Video Input 1 Port A Data input
(1)
I
AF3
vin1a_d15
Video Input 1 Port A Data input
(1)
I
AF4
vin1a_d16
Video Input 1 Port A Data input
(1)
I
AF1
vin1a_d17
Video Input 1 Port A Data input
(1)
I
AE3
vin1a_d18
Video Input 1 Port A Data input
(1)
I
AE5
vin1a_d19
Video Input 1 Port A Data input
(1)
I
AE1
vin1a_d20
Video Input 1 Port A Data input
(1)
I
AE2
vin1a_d21
Video Input 1 Port A Data input
(1)
I
AE6
vin1a_d22
Video Input 1 Port A Data input
(1)
I
AD2
vin1a_d23
Video Input 1 Port A Data input
(1)
I
AD3
I
N6 / AD9
vin1a_d3
DESCRIPTION
vin1b_hsync1
Video Input 1 Port B Horizontal Sync input
vin1b_vsync1
Video Input 1 Port B Vertical Sync input
(1)
(1)
vin1b_fld1
Video Input 1 Port B Field ID input
vin1b_de1
Video Input 1 Port B Data Enable input(1)
vin1b_clk1
Video Input 1 Port B Clock input
vin1b_d0
Video Input 1 Port B Data input
vin1b_d1
(1)
(1)
I
AF9
I
AE9
I
AF8 / M4
I
AH7
(1)
I
AF4 / AD3
Video Input 1 Port B Data input
(1)
I
AF3 / AD2
vin1b_d2
Video Input 1 Port B Data input
(1)
I
AF6 / AE6
vin1b_d3
Video Input 1 Port B Data input
(1)
I
AF2 / AE2
vin1b_d4
Video Input 1 Port B Data input
(1)
I
AG5 / AE1
vin1b_d5
Video Input 1 Port B Data input
(1)
I
AG3 / AE5
vin1b_d6
Video Input 1 Port B Data input
(1)
I
AG2 / AE3
vin1b_d7
Video Input 1 Port B Data input
(1)
I
AG4 / AF1
Video Input 2
vin2a_clk0
Video Input 2 Port A Clock input.
I
E1 / V1
vin2a_de0
Video Input 2 Port A Data Enable input
I
G2 / V7
vin2a_fld0
Video Input 2 Port A Field ID input
I
H7 / G2 / W2
vin2a_hsync0
Video Input 2 Port A Horizontal Sync input
I
G1 / U7
vin2a_vsync0
Video Input 2 Port A Vertical Sync input
I
G6 / V6
vin2a_d0
Video Input 2 Port A Data input
I
F2 / U4
vin2a_d1
Video Input 2 Port A Data input
I
F3 / V2
vin2a_d2
Video Input 2 Port A Data input
I
D1 / Y1
vin2a_d3
Video Input 2 Port A Data input
I
E2 / W9
vin2a_d4
Video Input 2 Port A Data input
I
D2 / V9
vin2a_d5
Video Input 2 Port A Data input
I
F4 / U5
vin2a_d6
Video Input 2 Port A Data input
I
C1 / V5
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Table 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
vin2a_d7
DESCRIPTION
Video Input 2 Port A Data input
I
E4 / V4
vin2a_d8
Video Input 2 Port A Data input
I
F5 / V3
vin2a_d9
Video Input 2 Port A Data input
I
E6 / Y2
vin2a_d10
Video Input 2 Port A Data input
I
D3 / U6
vin2a_d11
Video Input 2 Port A Data input
I
F6 / U3
vin2a_d12
Video Input 2 Port A Data input
I
D5
vin2a_d13
Video Input 2 Port A Data input
I
C2
vin2a_d14
Video Input 2 Port A Data input
I
C3
vin2a_d15
Video Input 2 Port A Data input
I
C4
vin2a_d16
Video Input 2 Port A Data input
I
B2
vin2a_d17
Video Input 2 Port A Data input
I
D6
vin2a_d18
Video Input 2 Port A Data input
I
C5
vin2a_d19
Video Input 2 Port A Data input
I
A3
vin2a_d20
Video Input 2 Port A Data input
I
B3
vin2a_d21
Video Input 2 Port A Data input
I
B4
vin2a_d22
Video Input 2 Port A Data input
I
B5
vin2a_d23
Video Input 2 Port A Data input
I
A4
vin2b_clk1
Video Input 2 Port B Clock input
I
AB5 / H7
vin2b_de1
Video Input 2 Port B Data Enable input
I
AB8 / G2
vin2b_fld1
Video Input 2 Port B Field ID input
I
G2
vin2b_hsync1
Video Input 2 Port B Horizontal Sync input
I
AC5 / G1
vin2b_vsync1
Video Input 2 Port B Vertical Sync input
I
AB4 / G6
vin2b_d0
Video Input 2 Port B Data input
I
AD6 / A4
vin2b_d1
Video Input 2 Port B Data input
I
AC8 / B5
vin2b_d2
Video Input 2 Port B Data input
I
AC3 / B4
vin2b_d3
Video Input 2 Port B Data input
I
AC9 / B3
vin2b_d4
Video Input 2 Port B Data input
I
AC6 / A3
vin2b_d5
Video Input 2 Port B Data input
I
AC7 / C5
vin2b_d6
Video Input 2 Port B Data input
I
AC4 / D6
vin2b_d7
Video Input 2 Port B Data input
I
AD4 / B2
vin3a_clk0
Video Input 3 Port A Clock input
I
B11 / AH7 / P1
vin3a_de0
Video Input 3 Port A Data Enable input
I
N9 / B3 / B10
vin3a_fld0
Video Input 3 Port A Field ID input
I
P9 / B4 / D11
vin3a_hsync0
Video Input 3 Port A Horizontal Sync input
I
N7 / B5 / C11
vin3a_vsync0
Video Input 3 Port A Vertical Sync input
I
R4 / A4 / E11
vin3a_d0
Video Input 3 Port A Data input
I
M6 / AF1 / B7
vin3a_d1
Video Input 3 Port A Data input
I
M2 / AE3 / B8
vin3a_d2
Video Input 3 Port A Data input
I
L5 / AE5 / A7
vin3a_d3
Video Input 3 Port A Data input
I
M1 / AE1 / A8
vin3a_d4
Video Input 3 Port A Data input
I
L6 / AE2 / C9
vin3a_d5
Video Input 3 Port A Data input
I
L4 / AE6 / A9
vin3a_d6
Video Input 3 Port A Data input
I
L3 / AD2 / B9
vin3a_d7
Video Input 3 Port A Data input
I
L2 / AD3 / A10
vin3a_d8
Video Input 3 Port A Data input
I
L1 / B2 / E8
vin3a_d9
Video Input 3 Port A Data input
I
K2 / D6 / D9
vin3a_d10
Video Input 3 Port A Data input
I
J1 / C5 / D7
Video Input 3
100
Terminal Configuration and Functions
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
vin3a_d11
DESCRIPTION
Video Input 3 Port A Data input
I
J2 / A3 / D8
vin3a_d12
Video Input 3 Port A Data input
I
H1 / B3 / A5
vin3a_d13
Video Input 3 Port A Data input
I
J3 / B4 / C6
vin3a_d14
Video Input 3 Port A Data input
I
H2 / B5 / C8
vin3a_d15
Video Input 3 Port A Data input
I
H3 / A4 / C7
vin3a_d16
Video Input 3 Port A Data input
I
R6 / F11
vin3a_d17
Video Input 3 Port A Data input
I
T9 / G10
vin3a_d18
Video Input 3 Port A Data input
I
T6 / F10
vin3a_d19
Video Input 3 Port A Data input
I
T7 / G11
vin3a_d20
Video Input 3 Port A Data input
I
P6 / E9
vin3a_d21
Video Input 3 Port A Data input
I
R9 / F9
vin3a_d22
Video Input 3 Port A Data input
I
R5 / F8
vin3a_d23
Video Input 3 Port A Data input
I
P5 / E7
vin3b_clk1
Video Input 3 Port B Clock input
I
P7 / M4
vin3b_de1
Video Input 3 Port B Data Enable input
I
N6
vin3b_fld1
Video Input 3 Port A Field ID input
I
M4
vin3b_hsync1
Video Input 3 Port A Horizontal Sync input
I
H5
vin3b_vsync1
H6
Video Input 3 Port A Vertical Sync input
I
vin3b_d0
Video Input 3 Port B Data input
I
K7
vin3b_d1
Video Input 3 Port B Data input
I
M7
vin3b_d2
Video Input 3 Port B Data input
I
J5
vin3b_d3
Video Input 3 Port B Data input
I
K6
vin3b_d4
Video Input 3 Port B Data input
I
J7
vin3b_d5
Video Input 3 Port B Data input
I
J4
vin3b_d6
Video Input 3 Port B Data input
I
J6
vin3b_d7
Video Input 3 Port B Data input
I
H4
vin4a_clk0
Video Input 4 Port A Clock input
I
P4 / B26 / B11
vin4a_de0
Video Input 4 Port A Data Enable input
I
H6 / C23 / B10 / P7
vin4a_fld0
Video Input 4
Video Input 4 Port A Field ID input
I
J7 / F21 / P9 / D11
vin4a_hsync0
Video Input 4 Port A Horizontal Sync input
I
R3 / E21 / C11 / P7
vin4a_vsync0
Video Input 4 Port A Vertical Sync input
I
T2 / F20 / E11 / N1
vin4a_d0
Video Input 4 Port A Data input
I
R6 / B7 / B14
vin4a_d1
Video Input 4 Port A Data input
I
T9 / B8 / J14
vin4a_d2
Video Input 4 Port A Data input
I
T6 / A7 / G13
vin4a_d3
Video Input 4 Port A Data input
I
T7 / A8 / J11
vin4a_d4
Video Input 4 Port A Data input
I
P6 / C9 / E12
vin4a_d5
Video Input 4 Port A Data input
I
R9 / A9 / F13
vin4a_d6
Video Input 4 Port A Data input
I
R5 / B9 / C12
vin4a_d7
Video Input 4 Port A Data input
I
P5 / A10 / D12
vin4a_d8
Video Input 4 Port A Data input
I
E8 / U2 / E15 / J4
vin4a_d9
Video Input 4 Port A Data input
I
D9 / U1 / A20 / J6
vin4a_d10
Video Input 4 Port A Data input
I
D7 / P3 / B15 / H4
vin4a_d11
Video Input 4 Port A Data input
I
D8 / R2 / A15 / H5
vin4a_d12
Video Input 4 Port A Data input
I
A5 / K7 / D15
vin4a_d13
Video Input 4 Port A Data input
I
C6 / M7 / B16
vin4a_d14
Video Input 4 Port A Data input
I
C8 / J5 / B17
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Table 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
vin4a_d15
DESCRIPTION
Video Input 4 Port A Data input
I
C7 / K6 / A17
vin4a_d16
Video Input 4 Port A Data input
I
C18 / F11
vin4a_d17
Video Input 4 Port A Data input
I
A21 / G10
vin4a_d18
Video Input 4 Port A Data input
I
G16 / F10
vin4a_d19
Video Input 4 Port A Data input
I
D17 / G11
vin4a_d20
Video Input 4 Port A Data input
I
AA3 / E9
vin4a_d21
Video Input 4 Port A Data input
I
AB9 / F9
vin4a_d22
Video Input 4 Port A Data input
I
AB3 / F8
vin4a_d23
Video Input 4 Port A Data input
I
AA4 / E7
vin4b_clk1
Video Input 4 Port B Clock input
I
N9 / V1
vin4b_de1
Video Input 4 Port B Data Enable input
I
P9 / V7
vin4b_fld1
Video Input 4 Port B Field ID input
I
P4 / W2
vin4b_hsync1
Video Input 4 Port B Horizontal Sync input
I
N7 / U7
vin4b_vsync1
Video Input 4 Port B Vertical Sync input
I
R4 / V6
vin4b_d0
Video Input 4 Port B Data input
I
R6 / U4
vin4b_d1
Video Input 4 Port B Data input
I
T9 / V2
vin4b_d2
Video Input 4 Port B Data input
I
T6 / Y1
vin4b_d3
Video Input 4 Port B Data input
I
T7 / W9
vin4b_d4
Video Input 4 Port B Data input
I
P6 / V9
vin4b_d5
Video Input 4 Port B Data input
I
R9 / U5
vin4b_d6
Video Input 4 Port B Data input
I
R5 / V5
vin4b_d7
Video Input 4 Port B Data input
I
P5 / V4
I
AC5
I
AB4
Video Input 5
vin5a_clk0
Video Input 5 Port A Clock input
(2)
vin5a_de0
Video Input 5 Port A Data Enable input
vin5a_fld0
Video Input 5 Port A Field ID input
(2)
(2)
vin5a_hsync0
Video Input 5 Port A Horizontal Sync input
vin5a_vsync0
Video Input 5 Port A Vertical Sync input
(2)
(2)
I
C17
I
AB8
I
AB5
I
AD6
vin5a_d0
Video Input 5 Port A Data input
(2)
vin5a_d1
Video Input 5 Port A Data input
(2)
I
AC8
vin5a_d2
Video Input 5 Port A Data input
(2)
I
AC3
vin5a_d3
Video Input 5 Port A Data input
(2)
I
AC9
vin5a_d4
Video Input 5 Port A Data input
(2)
I
AC6
vin5a_d5
Video Input 5 Port A Data input
(2)
I
AC7
vin5a_d6
Video Input 5 Port A Data input
(2)
I
AC4
vin5a_d7
Video Input 5 Port A Data input
(2)
I
AD4
vin5a_d8
Video Input 5 Port A Data input
(2)
I
AA4
vin5a_d9
Video Input 5 Port A Data input
(2)
I
AB3
vin5a_d10
Video Input 5 Port A Data input
(2)
I
AB9
vin5a_d11
Video Input 5 Port A Data input
(2)
I
AA3
vin5a_d12
Video Input 5 Port A Data input
(2)
I
D17
vin5a_d13
Video Input 5 Port A Data input
(2)
I
G16
vin5a_d14
Video Input 5 Port A Data input
(2)
I
A21
vin5a_d15
Video Input 5 Port A Data input
(2)
I
C18
Video Input 6
102
(2)
vin6a_clk0
Video Input 6 Port A Clock input
vin6a_de0
Video Input 6 Port B Data Enable input(2)
Terminal Configuration and Functions
I
E17
I
D14
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Table 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
vin6a_fld0
DESCRIPTION
Video Input 6 Port A Field ID input
(2)
vin6a_hsync0
Video Input 6 Port A Horizontal Sync input
vin6a_vsync0
Video Input 6 Port A Vertical Sync input
(2)
(2)
TYPE
BALL
I
C14
I
F12
I
G12
Video Input 6 Port A Data input
(2)
I
C17 / D18
vin6a_d1
Video Input 6 Port A Data input
(2)
I
B19
vin6a_d2
Video Input 6 Port A Data input
(2)
I
F15
vin6a_d3
Video Input 6 Port A Data input
(2)
I
B18
vin6a_d4
Video Input 6 Port A Data input
(2)
I
A16
vin6a_d5
Video Input 6 Port A Data input
(2)
I
C15
vin6a_d6
Video Input 6 Port A Data input
(2)
I
A18
vin6a_d7
Video Input 6 Port A Data input
(2)
I
A19
vin6a_d8
Video Input 6 Port A Data input
(2)
I
F14
vin6a_d9
Video Input 6 Port A Data input
(2)
I
G14
vin6a_d10
Video Input 6 Port A Data input
(2)
I
A13
vin6a_d11
Video Input 6 Port A Data input
(2)
I
E14
vin6a_d12
Video Input 6 Port A Data input
(2)
I
A12
vin6a_d13
Video Input 6 Port A Data input
(2)
I
B13
vin6a_d14
Video Input 6 Port A Data input
(2)
I
A11
vin6a_d15
Video Input 6 Port A Data input
(2)
I
B12
vin6a_d0
(1) The VIP1 interface (Video Input 1a and Video Input 1b in Table 4-4 ) signal sets are NOT supported in the DRA74x device. For more
details on the device differentiation, refer to the Table 3-1, Device Comparison.
(2) The VIP3 interface (Video Input 5 and Video Input 6 in Table 4-4 ) signal sets are NOT supported in the DRA74x device. For more
details on the device differentiation, refer to the Table 3-1, Device Comparison.
4.4.2
Display Subsystem – Video Output Ports
CAUTION
The I/O timings provided in Section 7 Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in the Table 7-17 and Table 7-18.
Table 4-5. DSS Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
DPI Video Output 1
vout1_clk
Video Output 1 Clock output
O
D11
vout1_de
Video Output 1 Data Enable output
O
B10
vout1_fld
Video Output 1 Field ID output.This signal is not used for embedded sync modes.
O
B11
vout1_hsync
Video Output 1 Horizontal Sync output.This signal is not used for embedded sync
modes.
O
C11
vout1_vsync
Video Output 1 Vertical Sync output.This signal is not used for embedded sync modes.
O
E11
vout1_d0
Video Output 1 Data output
O
F11
vout1_d1
Video Output 1 Data output
O
G10
vout1_d2
Video Output 1 Data output
O
F10
vout1_d3
Video Output 1 Data output
O
G11
vout1_d4
Video Output 1 Data output
O
E9
vout1_d5
Video Output 1 Data output
O
F9
vout1_d6
Video Output 1 Data output
O
F8
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Table 4-5. DSS Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
vout1_d7
DESCRIPTION
Video Output 1 Data output
O
E7
vout1_d8
Video Output 1 Data output
O
E8
vout1_d9
Video Output 1 Data output
O
D9
vout1_d10
Video Output 1 Data output
O
D7
vout1_d11
Video Output 1 Data output
O
D8
vout1_d12
Video Output 1 Data output
O
A5
vout1_d13
Video Output 1 Data output
O
C6
vout1_d14
Video Output 1 Data output
O
C8
vout1_d15
Video Output 1 Data output
O
C7
vout1_d16
Video Output 1 Data output
O
B7
vout1_d17
Video Output 1 Data output
O
B8
vout1_d18
Video Output 1 Data output
O
A7
vout1_d19
Video Output 1 Data output
O
A8
vout1_d20
Video Output 1 Data output
O
C9
vout1_d21
Video Output 1 Data output
O
A9
vout1_d22
Video Output 1 Data output
O
B9
vout1_d23
Video Output 1 Data output
O
A10
vout2_clk
Video Output 2 Clock output
O
H7 / B26
vout2_de
Video Output 2 Data Enable output
O
G2 / C23
vout2_fld
Video Output 2 Field ID output.This signal is not used for embedded sync modes.
O
E1 / F21
vout2_hsync
Video Output 2 Horizontal Sync output.This signal is not used for embedded sync
modes.
O
G1 / E21
vout2_vsync
Video Output 2 Vertical Sync output.This signal is not used for embedded sync modes.
O
G6 / F20
vout2_d0
Video Output 2 Data output
O
A4 / B14
vout2_d1
Video Output 2 Data output
O
B5 / J14
vout2_d2
Video Output 2 Data output
O
B4 / G13
vout2_d3
Video Output 2 Data output
O
B3 / J11
vout2_d4
Video Output 2 Data output
O
A3 / E12
vout2_d5
Video Output 2 Data output
O
C5 / F13
vout2_d6
Video Output 2 Data output
O
D6 / C12
vout2_d7
Video Output 2 Data output
O
B2 / D12
vout2_d8
Video Output 2 Data output
O
C4 / E15
vout2_d9
Video Output 2 Data output
O
C3 / A20
vout2_d10
Video Output 2 Data output
O
C2 / B15
vout2_d11
Video Output 2 Data output
O
D5 / A15
vout2_d12
Video Output 2 Data output
O
F6 / D15
vout2_d13
Video Output 2 Data output
O
D3 / B16
vout2_d14
Video Output 2 Data output
O
E6 / B17
vout2_d15
Video Output 2 Data output
O
F5 / A17
vout2_d16
Video Output 2 Data output
O
E4 / C18
vout2_d17
Video Output 2 Data output
O
C1 / A21
vout2_d18
Video Output 2 Data output
O
F4 / G16
vout2_d19
Video Output 2 Data output
O
D2 / D17
vout2_d20
Video Output 2 Data output
O
E2 / AA3
vout2_d21
Video Output 2 Data output
O
D1 / AB9
vout2_d22
Video Output 2 Data output
O
F3 / AB3
vout2_d23
Video Output 2 Data output
O
F2 / AA4
DPI Video Output 2
104
Terminal Configuration and Functions
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Table 4-5. DSS Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
DPI Video Output 3
(1)
vout3_clk
Video Output 3 Clock output
O
P1 / AF9
vout3_de
Video Output 3 Data Enable output
O
N9 / AD9 (1)
vout3_fld
Video Output 3 Field ID output.This signal is not used for embedded sync modes.
O
P9 / AG8 (1)
vout3_hsync
Video Output 3 Horizontal Sync output.This signal is not used for embedded sync
modes.
O
N7 / AE9 (1)
vout3_vsync
Video Output 3 Vertical Sync output.This signal is not used for embedded sync modes.
O
R4 / AF8 (1)
vout3_d0
Video Output 3 Data output
O
M6/ AH4 (1)/ AD3
vout3_d1
Video Output 3 Data output
O
M2/ AG6 (1)/ AD2
vout3_d2
Video Output 3 Data output
O
vout3_d3
Video Output 3 Data output
O
vout3_d4
Video Output 3 Data output
O
vout3_d5
Video Output 3 Data output
O
(1)
(1)
L5/ AH5
M1/
(1)
/ AE6
AH3 (1)/
(1)
L6/ AH6
(1)
L4/ AG7
(1)
(1)
AE2
/ AE1
(1)
/ AE5 (1)
vout3_d6
Video Output 3 Data output
O
L3/ AD8
(1)
vout3_d7
Video Output 3 Data output
O
L2/ AE8
(1)
/ AE3
/ AF1
(1)
(1)
(1)
vout3_d8
Video Output 3 Data output
O
L1 / AF4
vout3_d9
Video Output 3 Data output
O
K2 / AF3
(1)
vout3_d10
Video Output 3 Data output
O
J1 / AF6
(1)
vout3_d11
Video Output 3 Data output
O
J2 / AF2
(1)
vout3_d12
Video Output 3 Data output
O
H1 / AG5 (1)
vout3_d13
Video Output 3 Data output
O
J3 / AG3 (1)
vout3_d14
Video Output 3 Data output
O
H2 / AG2 (1)
vout3_d15
Video Output 3 Data output
O
H3 / AG4 (1)
vout3_d16
Video Output 3 Data output
O
R6/ AG8 (1)/ AH4
vout3_d17
Video Output 3 Data output
O
T9/ AD9 (1)/ AG6
vout3_d18
Video Output 3 Data output
O
T6 / AH5 (1)
vout3_d19
Video Output 3 Data output
O
T7 / AH3 (1)
vout3_d20
Video Output 3 Data output
O
P6 / AH6
vout3_d21
Video Output 3 Data output
O
R9 / AG7 (1)
vout3_d22
Video Output 3 Data output
O
R5 / AD8 (1)
vout3_d23
Video Output 3 Data output
O
P5 / AE8
(1)
(1)
(1)
(1)
(1) The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (i.e.,
VDDSHV6 must be supplied with 1.8V). 3.3V mode is not supported. This must be considered in the pin mux programming and
VDDSHVx supply connections.
4.4.3
Display Subsystem – High-Definition Multimedia Interface (HDMI)
NOTE
For more information, see the Display Subsystem / Display Subsystem Overview of the
device TRM.
Table 4-6. HDMI Signal Descriptions
SIGNAL NAME
hdmi1_cec
DESCRIPTION
HDMI consumer electronic control
TYPE
BALL
IOD
B20/ G19
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Table 4-6. HDMI Signal Descriptions (continued)
SIGNAL NAME
hdmi1_hpd
DESCRIPTION
HDMI display hot plug detect
TYPE
BALL
I
B21/ G20
C25
hdmi1_ddc_scl
HDMI display data channel clock
IOD
hdmi1_ddc_sda
HDMI display data channel data
IOD
F17
hdmi1_clockx
HDMI clock differential positive or negative
ODS
AG16
hdmi1_clocky
HDMI clock differential positive or negative
ODS
AH16
hdmi1_data2x
HDMI data 2 differential positive or negative
ODS
AG19
hdmi1_data2y
HDMI data 2 differential positive or negative
ODS
AH19
hdmi1_data1x
HDMI data 1 differential positive or negative
ODS
AG18
hdmi1_data1y
HDMI data 1 differential positive or negative
ODS
AH18
hdmi1_data0x
HDMI data 0 differential positive or negative
ODS
AG17
hdmi1_data0y
HDMI data 0 differential positive or negative
ODS
AH17
4.4.4
External Memory Interface (EMIF)
NOTE
For more information, see the Memory Subsystem / EMIF Controller section of the device
TRM.
NOTE
The index numbers 1 and 2 which are part of the EMIF1 and EMIF2 signal prefixes (ddr1_*
and ddr2_*) listed in Table 4-7, EMIF Signal Descriptions, not to be confused with DDR1 and
DDR2 types of SDRAM memories.
Table 4-7. EMIF Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
EMIF Channel 1
106
ddr1_csn0
EMIF1 Chip Select 0
O
AH23
ddr1_cke
EMIF1 Clock Enable
O
AG22
ddr1_ck
EMIF1 Clock
O
AG24
ddr1_nck
EMIF1 Negative Clock
O
AH24
ddr1_odt0
EMIF1 On-Die Termination for Chip Select 0
O
AE20
ddr1_casn
EMIF1 Column Address Strobe
O
AC18
ddr1_rasn
EMIF1 Row Address Strobe
O
AF20
ddr1_wen
EMIF1 Write Enable
O
AH21
AG21
ddr1_rst
EMIF1 Reset output (DDR3-SDRAM only)
O
ddr1_ba0
EMIF1 Bank Address
O
AF17
ddr1_ba1
EMIF1 Bank Address
O
AE18
ddr1_ba2
EMIF1 Bank Address
O
AB18
ddr1_a0
EMIF1 Address Bus
O
AD20
ddr1_a1
EMIF1 Address Bus
O
AC19
ddr1_a2
EMIF1 Address Bus
O
AC20
ddr1_a3
EMIF1 Address Bus
O
AB19
ddr1_a4
EMIF1 Address Bus
O
AF21
ddr1_a5
EMIF1 Address Bus
O
AH22
ddr1_a6
EMIF1 Address Bus
O
AG23
ddr1_a7
EMIF1 Address Bus
O
AE21
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Table 4-7. EMIF Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
ddr1_a8
DESCRIPTION
EMIF1 Address Bus
O
AF22
ddr1_a9
EMIF1 Address Bus
O
AE22
ddr1_a10
EMIF1 Address Bus
O
AD21
ddr1_a11
EMIF1 Address Bus
O
AD22
ddr1_a12
EMIF1 Address Bus
O
AC21
ddr1_a13
EMIF1 Address Bus
O
AF18
ddr1_a14
EMIF1 Address Bus
O
AE17
ddr1_a15
EMIF1 Address Bus
O
AD18
ddr1_d0
EMIF1 Data Bus
IO
AF25
ddr1_d1
EMIF1 Data Bus
IO
AF26
ddr1_d2
EMIF1 Data Bus
IO
AG26
ddr1_d3
EMIF1 Data Bus
IO
AH26
ddr1_d4
EMIF1 Data Bus
IO
AF24
ddr1_d5
EMIF1 Data Bus
IO
AE24
ddr1_d6
EMIF1 Data Bus
IO
AF23
ddr1_d7
EMIF1 Data Bus
IO
AE23
ddr1_d8
EMIF1 Data Bus
IO
AC23
ddr1_d9
EMIF1 Data Bus
IO
AF27
ddr1_d10
EMIF1 Data Bus
IO
AG27
ddr1_d11
EMIF1 Data Bus
IO
AF28
ddr1_d12
EMIF1 Data Bus
IO
AE26
ddr1_d13
EMIF1 Data Bus
IO
AC25
ddr1_d14
EMIF1 Data Bus
IO
AC24
ddr1_d15
EMIF1 Data Bus
IO
AD25
ddr1_d16
EMIF1 Data Bus
IO
V20
ddr1_d17
EMIF1 Data Bus
IO
W20
ddr1_d18
EMIF1 Data Bus
IO
AB28
ddr1_d19
EMIF1 Data Bus
IO
AC28
ddr1_d20
EMIF1 Data Bus
IO
AC27
ddr1_d21
EMIF1 Data Bus
IO
Y19
ddr1_d22
EMIF1 Data Bus
IO
AB27
ddr1_d23
EMIF1 Data Bus
IO
Y20
ddr1_d24
EMIF1 Data Bus
IO
AA23
ddr1_d25
EMIF1 Data Bus
IO
Y22
ddr1_d26
EMIF1 Data Bus
IO
Y23
ddr1_d27
EMIF1 Data Bus
IO
AA24
ddr1_d28
EMIF1 Data Bus
IO
Y24
ddr1_d29
EMIF1 Data Bus
IO
AA26
ddr1_d30
EMIF1 Data Bus
IO
AA25
ddr1_d31
EMIF1 Data Bus
IO
AA28
W22
EMIF1 ECC Data Bus
(1)
IO
ddr1_ecc_d1
EMIF1 ECC Data Bus
(1)
IO
V23
ddr1_ecc_d2
EMIF1 ECC Data Bus
(1)
IO
W19
ddr1_ecc_d3
EMIF1 ECC Data Bus
(1)
IO
W23
ddr1_ecc_d4
EMIF1 ECC Data Bus
(1)
IO
Y25
ddr1_ecc_d5
EMIF1 ECC Data Bus
(1)
IO
V24
ddr1_ecc_d6
EMIF1 ECC Data Bus
(1)
IO
V25
ddr1_ecc_d0
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Table 4-7. EMIF Signal Descriptions (continued)
SIGNAL NAME
ddr1_ecc_d7
DESCRIPTION
EMIF1 ECC Data Bus
(1)
TYPE
BALL
IO
Y26
AD23
ddr1_dqm0
EMIF1 Data Mask
O
ddr1_dqm1
EMIF1 Data Mask
O
AB23
ddr1_dqm2
EMIF1 Data Mask
O
AC26
ddr1_dqm3
EMIF1 Data Mask
O
AA27
EMIF1 ECC Data Mask
O
V26
ddr1_dqs0
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
AH25
ddr1_dqsn0
Data strobe 0 invert
IO
AG25
ddr1_dqs1
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
AE27
ddr1_dqsn1
Data strobe 1 invert
IO
AE28
ddr1_dqs2
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
AD27
ddr1_dqsn2
Data strobe 2 invert
IO
AD28
ddr1_dqs3
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
Y28
ddr1_dqsn3
Data strobe 3 invert
IO
Y27
ddr1_dqs_ecc
EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when
writing and input when reading.
IO
V27
ddr1_dqsn_ecc
EMIF1 ECC Complementary Data strobe
IO
V28
Reference Power Supply EMIF1
A
Y18
ddr2_csn0
EMIF2 Chip Select 0
O
P24
ddr2_cke
EMIF2 Clock Enable
O
U24
T28
ddr1_dqm_ecc
ddr1_vref0
EMIF Channel 2
108
ddr2_ck
EMIF2 Clock
O
ddr2_nck
EMIF2 Negative Clock
O
T27
ddr2_odt0
EMIF2 On-Die Termination for Chip Select 0
O
R23
ddr2_casn
EMIF2 Column Address Strobe
O
U28
ddr2_rasn
EMIF2 Row Address Strobe
O
T23
ddr2_wen
EMIF2 Write Enable
O
U25
ddr2_rst
EMIF2 Reset output (DDR3-SDRAM only)
O
R24
ddr2_ba0
EMIF2 Bank Address
O
U23
ddr2_ba1
EMIF2 Bank Address
O
U27
ddr2_ba2
EMIF2 Bank Address
O
U26
ddr2_a0
EMIF2 Address Bus
O
R25
ddr2_a1
EMIF2 Address Bus
O
R26
ddr2_a2
EMIF2 Address Bus
O
R28
ddr2_a3
EMIF2 Address Bus
O
R27
ddr2_a4
EMIF2 Address Bus
O
P23
ddr2_a5
EMIF2 Address Bus
O
P22
ddr2_a6
EMIF2 Address Bus
O
P25
ddr2_a7
EMIF2 Address Bus
O
N20
ddr2_a8
EMIF2 Address Bus
O
P27
ddr2_a9
EMIF2 Address Bus
O
N27
ddr2_a10
EMIF2 Address Bus
O
N23
ddr2_a11
EMIF2 Address Bus
O
P26
ddr2_a12
EMIF2 Address Bus
O
N28
ddr2_a13
EMIF2 Address Bus
O
T22
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Table 4-7. EMIF Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
O
R22
EMIF2 Address Bus
O
U22
EMIF2 Data Bus
IO
E26
ddr2_d1
EMIF2 Data Bus
IO
G25
ddr2_d2
EMIF2 Data Bus
IO
F25
ddr2_d3
EMIF2 Data Bus
IO
F24
ddr2_d4
EMIF2 Data Bus
IO
F26
ddr2_d5
EMIF2 Data Bus
IO
F27
ddr2_d6
EMIF2 Data Bus
IO
E27
ddr2_d7
EMIF2 Data Bus
IO
E28
ddr2_d8
EMIF2 Data Bus
IO
H23
ddr2_a14
EMIF2 Address Bus
ddr2_a15
ddr2_d0
ddr2_d9
EMIF2 Data Bus
IO
H25
ddr2_d10
EMIF2 Data Bus
IO
H24
ddr2_d11
EMIF2 Data Bus
IO
H26
ddr2_d12
EMIF2 Data Bus
IO
G26
ddr2_d13
EMIF2 Data Bus
IO
J25
ddr2_d14
EMIF2 Data Bus
IO
J26
ddr2_d15
EMIF2 Data Bus
IO
J24
ddr2_d16
EMIF2 Data Bus
IO
L22
ddr2_d17
EMIF2 Data Bus
IO
K20
ddr2_d18
EMIF2 Data Bus
IO
K21
ddr2_d19
EMIF2 Data Bus
IO
L23
ddr2_d20
EMIF2 Data Bus
IO
L24
ddr2_d21
EMIF2 Data Bus
IO
J23
ddr2_d22
EMIF2 Data Bus
IO
K22
ddr2_d23
EMIF2 Data Bus
IO
J20
ddr2_d24
EMIF2 Data Bus
IO
L27
ddr2_d25
EMIF2 Data Bus
IO
L26
ddr2_d26
EMIF2 Data Bus
IO
L25
ddr2_d27
EMIF2 Data Bus
IO
L28
ddr2_d28
EMIF2 Data Bus
IO
M23
ddr2_d29
EMIF2 Data Bus
IO
M24
ddr2_d30
EMIF2 Data Bus
IO
M25
ddr2_d31
EMIF2 Data Bus
IO
M26
ddr2_dqm0
EMIF2 Data Mask
O
F28
ddr2_dqm1
EMIF2 Data Mask
O
G24
ddr2_dqm2
EMIF2 Data Mask
O
K23
ddr2_dqm3
EMIF2 Data Mask
O
M22
ddr2_dqs0
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF2 memory when writing and input when reading.
IO
G28
ddr2_dqsn0
Data strobe 0 invert
IO
G27
ddr2_dqs1
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF2 memory when writing and input when reading.
IO
H27
ddr2_dqsn1
Data strobe 1 invert
IO
H28
ddr2_dqs2
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF2 memory when writing and input when reading.
IO
K27
ddr2_dqsn2
Data strobe 2 invert
IO
K28
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Table 4-7. EMIF Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
ddr2_dqs3
DESCRIPTION
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
EMIF2 memory when writing and input when reading.
IO
M28
ddr2_dqsn3
Data strobe 3 invert
IO
M27
ddr2_vref0
Reference Power Supply EMIF2
A
N22
(1) The ECC module (EMIF1 ECC Data Bus in Table 4-4 ) signal sets are NOT supported in the DRA74x device. For more details on the
device differentiation, refer to the Table 3-1, Device Comparison.
4.4.5
General-Purpose Memory Controller (GPMC)
NOTE
For more information, see the Memory Subsystem / General-Purpose Memory Controller
section of the device TRM.
Table 4-8. GPMC Signal Descriptions
SIGNAL NAME
110
TYPE
BALL
gpmc_ad0
DESCRIPTION
GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1
in A/D multiplexed mode
IO
M6
gpmc_ad1
GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2
in A/D multiplexed mode
IO
M2
gpmc_ad2
GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3
in A/D multiplexed mode
IO
L5
gpmc_ad3
GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4
in A/D multiplexed mode
IO
M1
gpmc_ad4
GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5
in A/D multiplexed mode
IO
L6
gpmc_ad5
GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6
in A/D multiplexed mode
IO
L4
gpmc_ad6
GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7
in A/D multiplexed mode
IO
L3
gpmc_ad7
GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8
in A/D multiplexed mode
IO
L2
gpmc_ad8
GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9
in A/D multiplexed mode
IO
L1
gpmc_ad9
GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10
in A/D multiplexed mode
IO
K2
gpmc_ad10
GPMC Data 10 in A/D nonmultiplexed mode and additionally Address
11 in A/D multiplexed mode
IO
J1
gpmc_ad11
GPMC Data 11 in A/D nonmultiplexed mode and additionally Address
12 in A/D multiplexed mode
IO
J2
gpmc_ad12
GPMC Data 12 in A/D nonmultiplexed mode and additionally Address
13 in A/D multiplexed mode
IO
H1
gpmc_ad13
GPMC Data 13 in A/D nonmultiplexed mode and additionally Address
14 in A/D multiplexed mode
IO
J3
gpmc_ad14
GPMC Data 14 in A/D nonmultiplexed mode and additionally Address
15 in A/D multiplexed mode
IO
H2
gpmc_ad15
GPMC Data 15 in A/D nonmultiplexed mode and additionally Address
16 in A/D multiplexed mode
IO
H3
gpmc_a0
GPMC Address 0. Only used to effectively address 8-bit data
nonmultiplexed memories
O
R6 / P4
gpmc_a1
GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D
multiplexed mode
O
T9 / P1
gpmc_a2
GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D
multiplexed mode
O
T6 / N1
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Table 4-8. GPMC Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpmc_a3
DESCRIPTION
GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D
multiplexed mode
O
T7 / M4
gpmc_a4
GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D
multiplexed mode
O
P6
gpmc_a5
GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D
multiplexed mode
O
R9
gpmc_a6
GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D
multiplexed mode
O
R5
gpmc_a7
GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D
multiplexed mode
O
P5
gpmc_a8
GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D
multiplexed mode
O
N7
gpmc_a9
GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D
multiplexed mode
O
R4
gpmc_a10
GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D
multiplexed mode
O
N9
gpmc_a11
GPMC address 11 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
P9
gpmc_a12
GPMC address 12 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
P4
gpmc_a13
GPMC address 13 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
R3 / K7
gpmc_a14
GPMC address 14 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
T2 / M7
gpmc_a15
GPMC address 15 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
U2 / J5
gpmc_a16
GPMC address 16 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
U1 / K6
gpmc_a17
GPMC address 17 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
P3 / J7
gpmc_a18
GPMC address 18 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
R2 / J4
gpmc_a19
GPMC address 19 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
K7 / J6
gpmc_a20
GPMC address 20 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
M7 / H4
gpmc_a21
GPMC address 21 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
J5 / H5
gpmc_a22
GPMC address 22 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
K6 / H6
gpmc_a23
GPMC address 23 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
J7/ AG5/ N1
gpmc_a24
GPMC address 24 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
J4 / AF2
gpmc_a25
GPMC address 25 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
J6 / AF6
gpmc_a26
GPMC address 26 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
H4 / AF3
gpmc_a27
GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D
multiplexed mode
O
H5 / AF4
gpmc_cs0
GPMC Chip Select 0 (active low)
O
T1
gpmc_cs1
GPMC Chip Select 1 (active low)
O
H6
gpmc_cs2
GPMC Chip Select 2 (active low)
O
P2
gpmc_cs3
GPMC Chip Select 3 (active low)
O
P1
gpmc_cs4
GPMC Chip Select 4 (active low)
O
N6
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Table 4-8. GPMC Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpmc_cs5
GPMC Chip Select 5 (active low)
O
M4
gpmc_cs6
GPMC Chip Select 6 (active low)
O
N1
gpmc_cs7
GPMC Chip Select 7 (active low)
O
P7
GPMC Clock output
IO
P7
gpmc_advn_ale
GPMC address valid active low or address latch enable
O
N1
gpmc_oen_ren
GPMC output enable active low or read enable
O
M5
gpmc_wen
GPMC write enable active low
O
M3
gpmc_ben0
GPMC lower-byte enable active low
O
N6
gpmc_ben1
GPMC upper-byte enable active low
O
M4
gpmc_wait0
GPMC external indication of wait 0
I
N2
gpmc_wait1
GPMC external indication of wait 1
I
P7 / N1
gpmc_clk(1)(2)
DESCRIPTION
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
(2) The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the
associated timing. See Table 7-24 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load and Table 7-26
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads for timing information.
4.4.6
Timers
NOTE
For more information, see the Timers section of the device TRM.
Table 4-9. Timers Signal Descriptions
SIGNAL NAME
TYPE
BALL
timer1
DESCRIPTION
PWM output/event trigger input
IO
M4 / E21
timer2
PWM output/event trigger input
IO
N6 / F20
timer3
PWM output/event trigger input
IO
N1 / F21
timer4
PWM output/event trigger input
IO
P7 / D12
timer5
PWM output/event trigger input
IO
U2 / B12
timer6
PWM output/event trigger input
IO
T2 / A11
timer7
PWM output/event trigger input
IO
R3 / B13
timer8
PWM output/event trigger input
IO
P4 / A12
timer9
PWM output/event trigger input
IO
P9 / E14
timer10
PWM output/event trigger input
IO
N9 / A13
timer11
PWM output/event trigger input
IO
R4 / G14
timer12
PWM output/event trigger input
IO
N7 / F14
timer13
PWM output/event trigger input
IO
D18 / AF8
timer14
PWM output/event trigger input
IO
E17 / AE9
timer15
PWM output/event trigger input
IO
B26/ AF9/ AC10
timer16
PWM output/event trigger input
IO
C23/ AD9/ AB10
4.4.7
Inter-Integrated Circuit Interface (I2C)
NOTE
For more information, see the Serial Communication Interface / Multimaster High-Speed I2C
Controller / HS I2C Environment / HS I2C in I2C Mode section of the device TRM.
112
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NOTE
I2C1 and I2C2 do NOT support HS-mode.
Table 4-10. I2C Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Inter-Integrated Circuit Interface (I2C1)
i2c1_scl
I2C1 Clock
IOD
C20
i2c1_sda
I2C1 Data
IOD
C21
Inter-Integrated Circuit Interface (I2C2)
i2c2_scl
I2C2 Clock
IOD
F17
i2c2_sda
I2C2 Data
IOD
C25
Inter-Integrated Circuit Interface (I2C3)
i2c3_scl
I2C3 Clock
IOD
P7/ D14/ AB4/ F20
i2c3_sda
I2C3 Data
IOD
N1/ C14/ AC5/ E21
Inter-Integrated Circuit Interface (I2C4)
i2c4_scl
I2C4 Clock
IOD
R6/ J14/ A21/ Y9
i2c4_sda
I2C4 Data
IOD
T9/ B14/ C18/ W7
Inter-Integrated Circuit Interface (I2C5)
4.4.8
i2c5_scl
I2C5 Clock
IOD
AB9/ P6/ F12
i2c5_sda
I2C5 Data
IOD
AA3/ R9/ G12
HDQ / 1-Wire Interface (HDQ1W)
NOTE
For more information, see the Serial Communication Interface / HDQ/1-Wire section of the
device TRM.
Table 4-11. HDQ / 1-Wire Signal Descriptions
SIGNAL NAME
hdq0
4.4.9
DESCRIPTION
HDQ or 1-wire protocol single interface pin
TYPE
BALL
IOD
D18/ C23
Universal Asynchronous Receiver Transmitter (UART)
NOTE
For more information see the Serial Communication Interface /UART/IrDA/CIR section of the
device TRM.
Table 4-12. UART Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Universal Asynchronous Receiver/Transmitter (UART1)
uart1_dcdn
UART1 Data Carrier Detect active low
I
D28
uart1_dsrn
UART1 Data Set Ready Active Low
I
D26
uart1_dtrn
UART1 Data Terminal Ready Active Low
O
D27
uart1_rin
UART1 Ring Indicator
I
C28
uart1_rxd
UART1 Receive Data
I
B27
uart1_txd
UART1 Transmit Data
O
C26
uart1_ctsn
UART1 clear to send active low
I
E25
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Table 4-12. UART Signal Descriptions (continued)
SIGNAL NAME
uart1_rtsn
DESCRIPTION
UART1 request to send active low
TYPE
BALL
O
C27
Universal Asynchronous Receiver/Transmitter (UART2)
uart2_rxd
UART2 Receive Data
I
D28
uart2_txd
UART2 Transmit Data
O
D26
uart2_ctsn
UART2 clear to send active low
I
D27
uart2_rtsn
UART2 request to send active low
O
C28
Universal Asynchronous Receiver/Transmitter (UART3)/IrDA
uart3_rxd
UART3 Receive Data for both normal UART mode and IrDA mode
I
V2/ AB3/ A26 / D27
uart3_txd
UART3 Transmit Data
O
Y1/ AA4/ B22/ C28
uart3_ctsn
UART3 clear to send active low
I
U4/ W9/ G17/ D28
uart3_rtsn
UART3 request to send active low
O
V1/ V9/ D28/ B24
uart3_rctx
Remote control data
O
D28
uart3_sd
Infrared transceiver configure/shutdown
O
D26
uart3_irtx
Infrared data output
O
C28
Universal Asynchronous Receiver/Transmitter (UART4)
uart4_rxd
UART4 Receive Data
I
V7/ G16/ B21
uart4_txd
UART4 Transmit Data
O
U7/ D17/ B20
uart4_ctsn
UART4 clear to send active low
I
V6
uart4_rtsn
UART4 request to send active low
O
U6
Universal Asynchronous Receiver/Transmitter (UART5)
uart5_rxd
UART5 Receive Data
I
R6/ F11/ B19/ AC7/
G17
uart5_txd
UART5 Transmit Data
O
T9/ G10/ C17/ AC6/
B24
uart5_ctsn
UART5 clear to send active low
I
T6 / AC9
uart5_rtsn
UART5 request to send active low
O
T7 / AC3
Universal Asynchronous Receiver/Transmitter (UART6)
uart6_rxd
UART6 Receive Data
I
P6/ E8/ G12/ W7
uart6_txd
UART6 Transmit Data
O
R9/ D9/ F12/ Y9
uart6_ctsn
UART6 clear to send active low
I
R5 / G13
uart6_rtsn
UART6 request to send active low
O
P5 / J11
Universal Asynchronous Receiver/Transmitter (UART7)
uart7_rxd
UART7 Receive Data
I
T6/ AD9/ B7/ B18
uart7_txd
UART7 Transmit Data
O
T7/ AF9/ B8/ F15
uart7_ctsn
UART7 clear to send active low
I
AE9 / B19
uart7_rtsn
UART7 request to send active low
O
AF8 / C17
Universal Asynchronous Receiver/Transmitter (UART8)
uart8_rxd
UART8 Receive Data
I
AE8/ R5/ C18/ G20
uart8_txd
UART8 Transmit Data
O
AD8/ P5/ A21/ G19
uart8_ctsn
UART8 clear to send active low
I
AG7 / G16
uart8_rtsn
UART8 request to send active low
O
AH6 / D17
Universal Asynchronous Receiver/Transmitter (UART9)
uart9_rxd
UART9 Receive Data
I
G1/ AA3/ E25
uart9_txd
UART9 Transmit Data
O
G6/ AB9/ C27
uart9_ctsn
UART9 clear to send active low
I
F2 / AB3
uart9_rtsn
UART9 request to send active low
O
F3/ AA4
I
D1/ E21/ AC8/ D27
Universal Asynchronous Receiver/Transmitter (UART10)
uart10_rxd
114
UART10 Receive Data
Terminal Configuration and Functions
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Table 4-12. UART Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
O
E2/ F20/ AD6/ C28
UART10 clear to send active low
I
D2 / AB8
UART10 request to send active low
O
F4 / AB5
uart10_txd
UART10 Transmit Data
uart10_ctsn
uart10_rtsn
4.4.10 Multichannel Serial Peripheral Interface (McSPI)
CAUTION
The I/O timings provided in Section 7 Timing Requirements and Switching
Characteristics are applicable for all combinations of signals for SPI1 and SPI2.
However, the timings are valid only for SPI3 and SPI4 if signals within a single
IOSET are used. The IOSETS are defined in the Table 7-43.
NOTE
For more information, see the Serial Communication Interface / Multichannel Serial
Peripheral Interface (MCSPI) section of the device TRM.
Table 4-13. SPI Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
A25
Serial Peripheral Interface 1
spi1_sclk(1)
SPI1 Clock
IO
spi1_d1
SPI1 Data. Can be configured as either MISO or MOSI.
IO
F16
spi1_d0
SPI1 Data. Can be configured as either MISO or MOSI.
IO
B25
spi1_cs0
SPI1 Chip Select
IO
A24
spi1_cs1
SPI1 Chip Select
IO
A22
spi1_cs2
SPI1 Chip Select
IO
B21
spi1_cs3
SPI1 Chip Select
IO
B20
Serial Peripheral Interface 2
spi2_sclk(1)
SPI2 Clock
IO
A26
spi2_d1
SPI2 Data. Can be configured as either MISO or MOSI.
IO
B22
spi2_d0
SPI2 Data. Can be configured as either MISO or MOSI.
IO
G17
spi2_cs0
SPI2 Chip Select
IO
B24
spi2_cs1
SPI2 Chip Select
IO
A22
spi2_cs2
SPI2 Chip Select
IO
B21
spi2_cs3
SPI2 Chip Select
IO
B20
SPI3 Clock
IO
AD9/ V2/ B12/ E11/
AC4/ C18
spi3_d1
SPI3 Data. Can be configured as either MISO or MOSI.
IO
AF9/ Y1/ B10/ A11/
A21/ AC7
spi3_d0
SPI3 Data. Can be configured as either MISO or MOSI.
IO
AE9/ W9/ C11/ B13/
AC6/ G16
spi3_cs0
SPI3 Chip Select
IO
AF8/ V9/ D11/ A12/
AC9/ D17
spi3_cs1
SPI3 Chip Select
IO
B11/ AC3/ E14
spi3_cs2
SPI3 Chip Select
IO
F11
spi3_cs3
SPI3 Chip Select
IO
A10
Serial Peripheral Interface 3
spi3_sclk(1)
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Table 4-13. SPI Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
SPI4 Clock
IO
N7/ G1/ AA3/ V7/
AC8
spi4_d1
SPI4 Data. Can be configured as either MISO or MOSI.
IO
R4/ G6/ AB9/ U7/
AD6
spi4_d0
SPI4 Data. Can be configured as either MISO or MOSI.
IO
N9/ F2/ AB3/ V6/
AB8
spi4_cs0
SPI4 Chip Select
IO
P9/ F3/ AA4/ U6/
AB5
spi4_cs1
SPI4 Chip Select
IO
P4 / Y1
spi4_cs2
SPI4 Chip Select
IO
R3 / W9
spi4_cs3
SPI4 Chip Select
IO
T2 / V9
Serial Peripheral Interface 4
spi4_sclk(1)
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any non-monotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
4.4.11 Quad Serial Peripheral Interface (QSPI)
NOTE
For more information see the Serial Communication Interface / Quad Serial Peripheral
Interface section of the device TRM.
Table 4-14. QSPI Signal Descriptions
SIGNAL NAME
TYPE
BALL
qspi1_sclk
DESCRIPTION
QSPI1 Serial Clock
O
R2
qspi1_rtclk
QSPI1 Return Clock Input.Must be connected from QSPI1_SCLK on PCB. Refer
to PCB Guidelines for QSPI1
I
R3
qspi1_d0
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read
and quad read modes it becomes input data pin during read phase.
IO
U1
qspi1_d1
QSPI1 Data[1]. Input read data in all modes
I
P3
qspi1_d2
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during
read phase
I
U2
qspi1_d3
QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during
read phase
I
T2
qspi1_cs0
QSPI1 Chip Select[0]. This pin is Used for QSPI1 boot modes
O
P2
qspi1_cs1
QSPI1 Chip Select[1]
O
P1
qspi1_cs2
QSPI1 Chip Select[2]
O
T7
qspi1_cs3
QSPI1 Chip Select[3]
O
P6
4.4.12 Multichannel Audio Serial Port (McASP)
NOTE
For more information, see the Serial Communication Interface / Multichannel Audio Serial
Port (MCASP) section of the device TRM.
Table 4-15. MCASP Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
IO
G12
Multichannel Audio Serial Port 1
mcasp1_axr0
116
MCASP1 Transmit/Receive Data
Terminal Configuration and Functions
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Table 4-15. MCASP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
mcasp1_axr1
MCASP1 Transmit/Receive Data
IO
F12
mcasp1_axr2
MCASP1 Transmit/Receive Data
IO
G13
mcasp1_axr3
MCASP1 Transmit/Receive Data
IO
J11
mcasp1_axr4
MCASP1 Transmit/Receive Data
IO
D18/ E12
mcasp1_axr5
MCASP1 Transmit/Receive Data
IO
E17 / F13
mcasp1_axr6
MCASP1 Transmit/Receive Data
IO
B26 / C12
mcasp1_axr7
MCASP1 Transmit/Receive Data
IO
C23 / D12
mcasp1_axr8
MCASP1 Transmit/Receive Data
IO
E21 / B12
mcasp1_axr9
MCASP1 Transmit/Receive Data
IO
F20/ A11
mcasp1_axr10
MCASP1 Transmit/Receive Data
IO
F21 / B13
mcasp1_axr11
MCASP1 Transmit/Receive Data
IO
A12
mcasp1_axr12
MCASP1 Transmit/Receive Data
IO
E14
mcasp1_axr13
MCASP1 Transmit/Receive Data
IO
A13
mcasp1_axr14
MCASP1 Transmit/Receive Data
IO
G14
mcasp1_axr15
MCASP1 Transmit/Receive Data
IO
F14
mcasp1_fsx
MCASP1 Transmit Frame Sync
IO
D14
MCASP1 Receive Bit Clock
IO
B14
mcasp1_aclkr (1)
mcasp1_fsr
DESCRIPTION
MCASP1 Receive Frame Sync
IO
J14
mcasp1_ahclkx
MCASP1 Transmit High-Frequency Master Clock
O
D18
mcasp1_aclkx(1)
MCASP1 Transmit Bit Clock
IO
C14
B15
Multichannel Audio Serial Port 2
mcasp2_axr0
MCASP2 Transmit/Receive Data
IO
mcasp2_axr1
MCASP2 Transmit/Receive Data
IO
A15
mcasp2_axr2
MCASP2 Transmit/Receive Data
IO
C15
mcasp2_axr3
MCASP2 Transmit/Receive Data
IO
A16
mcasp2_axr4
MCASP2 Transmit/Receive Data
IO
D15
mcasp2_axr5
MCASP2 Transmit/Receive Data
IO
B16
mcasp2_axr6
MCASP2 Transmit/Receive Data
IO
B17
mcasp2_axr7
MCASP2 Transmit/Receive Data
IO
A17
mcasp2_axr8
MCASP2 Transmit/Receive Data
IO
D18
mcasp2_axr9
MCASP2 Transmit/Receive Data
IO
E17
mcasp2_axr10
MCASP2 Transmit/Receive Data
IO
B26
mcasp2_axr11
MCASP2 Transmit/Receive Data
IO
C23
mcasp2_axr12
MCASP2 Transmit/Receive Data
IO
B18
mcasp2_axr13
MCASP2 Transmit/Receive Data
IO
F15
mcasp2_axr14
MCASP2 Transmit/Receive Data
IO
B19
mcasp2_axr15
MCASP2 Transmit/Receive Data
IO
C17
mcasp2_fsx
MCASP2 Transmit Frame Sync
IO
A18
MCASP2 Receive Bit Clock
IO
E15
MCASP2 Receive Frame Sync
IO
A20
MCASP2 Transmit High-Frequency Master Clock
O
E17
MCASP2 Transmit Bit Clock
IO
A19
mcasp2_aclkr(1)
mcasp2_fsr
mcasp2_ahclkx
(1)
mcasp2_aclkx
Multichannel Audio Serial Port 3
mcasp3_axr0
MCASP3 Transmit/Receive Data
IO
B19
mcasp3_axr1
MCASP3 Transmit/Receive Data
IO
C17
mcasp3_axr2
MCASP3 Transmit/Receive Data
IO
C15
mcasp3_axr3
MCASP3 Transmit/Receive Data
IO
A16
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Table 4-15. MCASP Signal Descriptions (continued)
SIGNAL NAME
mcasp3_fsx
DESCRIPTION
MCASP3 Transmit Frame Sync
TYPE
BALL
IO
F15
mcasp3_ahclkx
MCASP3 Transmit High-Frequency Master Clock
O
B26
mcasp3_aclkx(1)
MCASP3 Transmit Bit Clock
IO
B18
mcasp3_aclkr(1)
MCASP3 Receive Bit Clock
IO
B18
MCASP3 Receive Frame Sync
IO
F15
mcasp3_fsr
Multichannel Audio Serial Port 4
mcasp4_axr0
MCASP4 Transmit/Receive Data
IO
G16
mcasp4_axr1
MCASP4 Transmit/Receive Data
IO
D17
mcasp4_axr2
MCASP4 Transmit/Receive Data
IO
E12
mcasp4_axr3
MCASP4 Transmit/Receive Data
IO
F13
mcasp4_fsx
MCASP4 Transmit Frame Sync
IO
A21
mcasp4_ahclkx
MCASP4 Transmit High-Frequency Master Clock
O
C23
mcasp4_aclkx(1)
MCASP4 Transmit Bit Clock
IO
C18
mcasp4_aclkr(1)
MCASP4 Receive Bit Clock
IO
C18
MCASP4 Receive Frame Sync
IO
A21
mcasp4_fsr
Multichannel Audio Serial Port 5
mcasp5_axr0
MCASP5 Transmit/Receive Data
IO
AB3
mcasp5_axr1
MCASP5 Transmit/Receive Data
IO
AA4
mcasp5_axr2
MCASP5 Transmit/Receive Data
IO
C12
mcasp5_axr3
MCASP5 Transmit/Receive Data
IO
D12
mcasp5_fsx
MCASP5 Transmit Frame Sync
IO
AB9
mcasp5_ahclkx
MCASP5 Transmit High-Frequency Master Clock
O
D18
mcasp5_aclkx(1)
MCASP5 Transmit Bit Clock
IO
AA3
mcasp5_aclkr(1)
MCASP5 Receive Bit Clock
IO
AA3
MCASP5 Receive Frame Sync
IO
AB9
B12
mcasp5_fsr
Multichannel Audio Serial Port 6
mcasp6_axr0
MCASP6 Transmit/Receive Data
IO
mcasp6_axr1
MCASP6 Transmit/Receive Data
IO
A11
mcasp6_axr2
MCASP6 Transmit/Receive Data
IO
G13
mcasp6_axr3
MCASP6 Transmit/Receive Data
IO
J11
mcasp6_ahclkx
MCASP6 Transmit High-Frequency Master Clock
O
E17
mcasp6_aclkx(1)
MCASP6 Transmit Bit Clock
IO
B13
MCASP6 Transmit Frame Sync
IO
A12
MCASP6 Receive Bit Clock
IO
B13
MCASP6 Receive Frame Sync
IO
A12
mcasp6_fsx
mcasp6_aclkr(1)
mcasp6_fsr
Multichannel Audio Serial Port 7
mcasp7_axr0
MCASP7 Transmit/Receive Data
IO
E14
mcasp7_axr1
MCASP7 Transmit/Receive Data
IO
A13
mcasp7_axr2
MCASP7 Transmit/Receive Data
IO
B14
mcasp7_axr3
MCASP7 Transmit/Receive Data
IO
J14
mcasp7_ahclkx
MCASP7 Transmit High-Frequency Master Clock
O
B26
mcasp7_aclkx(1)
MCASP7 Transmit Bit Clock
IO
G14
MCASP7 Transmit Frame Sync
IO
F14
MCASP7 Receive Bit Clock
IO
G14
MCASP7 Receive Frame Sync
IO
F14
IO
D15
mcasp7_fsx
mcasp7_aclkr(1)
mcasp7_fsr
Multichannel Audio Serial Port 8
mcasp8_axr0
118
MCASP8 Transmit/Receive Data
Terminal Configuration and Functions
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Table 4-15. MCASP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
mcasp8_axr1
DESCRIPTION
MCASP8 Transmit/Receive Data
IO
B16
mcasp8_axr2
MCASP8 Transmit/Receive Data
IO
E15
mcasp8_axr3
MCASP8 Transmit/Receive Data
IO
A20
mcasp8_ahclkx
MCASP8 Transmit High-Frequency Master Clock
O
C23
mcasp8_aclkx(1)
MCASP8 Transmit Bit Clock
IO
B17
MCASP8 Transmit Frame Sync
IO
A17
MCASP8 Receive Bit Clock
IO
B17
MCASP8 Receive Frame Sync
IO
A17
mcasp8_fsx
mcasp8_aclkr(1)
mcasp8_fsr
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any non-monotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
4.4.13 Universal Serial Bus (USB)
NOTE
For more information, see: Serial Communication Interface / SuperSpeed USB DRD
Subsystem section of the device TRM.
Table 4-16. Universal Serial Bus Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Universal Serial Bus 1
usb1_dp
USB1 USB2.0 differential signal pair (positive)
IO
AD12
usb1_dm
USB1 USB2.0 differential signal pair (negative)
IO
AC12
USB1 Drive VBUS signal
O
AB10
usb_rxn0
USB1 USB3.0 receiver negative lane
I
AF12
usb_rxp0
USB1 USB3.0 receiver positive lane
I
AE12
usb_txn0
USB1 USB3.0 transmitter negative lane
O
AC11
usb_txp0
USB1 USB3.0 transmitter positive lane
O
AD11
usb2_dp
USB2 USB2.0 differential signal pair (positive)
IO
AE11
usb2_dm
USB2 USB2.0 differential signal pair (negative)
IO
AF11
USB2 Drive VBUS signal
O
AC10
usb3_ulpi_d0
USB3 - ULPI 8-bit data bus
IO
AC3 / AE1
usb3_ulpi_d1
USB3 - ULPI 8-bit data bus
IO
AC9 / AE5
usb3_ulpi_d2
USB3 - ULPI 8-bit data bus
IO
AC6 / AE3
usb3_ulpi_d3
USB3 - ULPI 8-bit data bus
IO
AC7 / AF1
usb3_ulpi_d4
USB3 - ULPI 8-bit data bus
IO
AC4 / AF4
usb3_ulpi_d5
USB3 - ULPI 8-bit data bus
IO
AD4 / AF3
usb3_ulpi_d6
USB3 - ULPI 8-bit data bus
IO
AB4 / AF6
usb3_ulpi_d7
USB3 - ULPI 8-bit data bus
IO
AC5 / AF2
usb3_ulpi_nxt
USB3 - ULPI next
I
AC8 / AE2
usb3_ulpi_dir
USB3 - ULPI bus direction
I
AD6 / AE6
usb3_ulpi_stp
USB3 - ULPI stop
O
AB8 / AD2
usb3_ulpi_clk
USB3 - ULPI functional clock
I
AB5 / AD3
usb1_drvvbus
Universal Serial Bus 2
usb2_drvvbus
Universal Serial Bus 3
Universal Serial Bus 4
usb4_ulpi_d0
usb4_ulpi_d1
USB4 - ULPI 8-bit data bus
(1)
IO
V6
USB4 - ULPI 8-bit data bus
(1)
IO
U6
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Table 4-16. Universal Serial Bus Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
USB4 - ULPI 8-bit data bus
(1)
IO
U5
usb4_ulpi_d3
USB4 - ULPI 8-bit data bus
(1)
IO
V5
usb4_ulpi_d4
USB4 - ULPI 8-bit data bus
(1)
IO
V4
usb4_ulpi_d5
USB4 - ULPI 8-bit data bus
(1)
IO
V3
usb4_ulpi_d6
USB4 - ULPI 8-bit data bus
(1)
IO
Y2
usb4_ulpi_d7
USB4 - ULPI 8-bit data bus
(1)
IO
W2
usb4_ulpi_nxt
USB4 - ULPI next (1)
I
U7
I
V7
usb4_ulpi_d2
DESCRIPTION
(1)
usb4_ulpi_dir
USB4 - ULPI bus direction
usb4_ulpi_stp
USB4 - ULPI stop (1)
O
V9
usb4_ulpi_clk
USB4 - ULPI functional clock (1)
I
W9
(1) USB4 will not be supported on some pin-compatible roadmap devices. USB3 will be mapped to these balls instead. Pin compatibility can
be maintained in the future by either not using USB4, or via software change to use USB4 on this device, but USB3 on these balls in the
future.
4.4.14 SATA
NOTE
For more information, see the Serial Communication Interfaces / SATA section of the device
TRM.
Table 4-17. SATA Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
sata1_rxn0
SATA differential negative receiver lane 0
IOS
AH9
sata1_rxp0
SATA differential positive receiver lane 0
IOS
AG9
sata1_txn0
SATA differential negative transmitter lane 0
ODS
AG10
sata1_txp0
SATA differential positive transmitter lane 0
ODS
AH10
sata1_led
SATA channel activity indicator
O
A22 / G19
4.4.15 Peripheral Component Interconnect Express (PCIe)
NOTE
For more information, see the Serial Communication Interfaces / PCIe Controllers and the
Shared PHY Component Subsystems / PCIe Shared PHY Susbsytem sections of the device
TRM.
NOTE
In the DRA74x device, the PCIe_SS2 controller is NOT available, and the PCIe_SS1
controller supports only a single lane. The PCIe2_PHY interface signal set (pcie_rxn1/rxp1,
pcie_txn1/txp1 in Table 4-18) is NOT supported in the DRA74x device. For more details
on the device differentiation, refer to the Table 3-1, Device Comparison.
Table 4-18. PCIe Signal Descriptions
SIGNAL NAME
120
DESCRIPTION
TYPE
BALL
IOS
AG13
pcie_rxn0
PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only.
pcie_rxp0
PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only.
IOS
AH13
pcie_txn0
PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only.
ODS
AG14
pcie_txp0
PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only.
ODS
AH14
Terminal Configuration and Functions
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Table 4-18. PCIe Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
pcie_rxn1(1)
DESCRIPTION
PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
IOS
AG11
pcie_rxp1(1)
PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
IOS
AH11
pcie_txn1(1)
PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
ODS
AG12
pcie_txp1(1)
PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
ODS
AH12
ljcb_clkp
PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair
(positive)
IODS
AG15
ljcb_clkn
PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair
(negative)
IODS
AH15
(1) This is not applicable for DRA74x devices.
4.4.16 Controller Area Network Interface (DCAN)
NOTE
For more information, see the Serial Communication Interface / DCAN section of the device
TRM.
Table 4-19. DCAN Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
DCAN 1
dcan1_tx
DCAN1 transmit data pin
IO
G20
dcan1_rx
DCAN1 receive data pin
IO
G19 / AD17
dcan2_tx
DCAN2 transmit data pin
IO
E21/ B21
dcan2_rx
DCAN2 receive data pin
IO
F20/ AC17/ B20
DCAN 2
4.4.17 Ethernet Interface (GMAC_SW)
CAUTION
The I/O timings provided in Section 7 Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in the Table 7-73, Table 7-76, Table 7-81 and Table 7-88.
NOTE
For more information, see the Serial Communication Interfaces / Ethernet Controller section
of the device TRM.
Table 4-20. GMAC Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
rgmii0_txc
RGMII0 Transmit Clock
O
W9
rgmii0_txctl
RGMII0 Transmit Enable
O
V9
rgmii0_txd3
RGMII0 Transmit Data
O
V7
rgmii0_txd2
RGMII0 Transmit Data
O
U7
rgmii0_txd1
RGMII0 Transmit Data
O
V6
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Table 4-20. GMAC Signal Descriptions (continued)
SIGNAL NAME
122
TYPE
BALL
rgmii0_txd0
DESCRIPTION
RGMII0 Transmit Data
O
U6
rgmii0_rxc
RGMII0 Receive Clock
I
U5
rgmii0_rxctl
RGMII0 Receive Control
I
V5
rgmii0_rxd3
RGMII0 Receive Data
I
V4
rgmii0_rxd2
RGMII0 Receive Data
I
V3
rgmii0_rxd1
RGMII0 Receive Data
I
Y2
rgmii0_rxd0
RGMII0 Receive Data
I
W2
rgmii1_txc
RGMII1 Transmit Clock
O
D5
rgmii1_txctl
RGMII1 Transmit Enable
O
C2
rgmii1_txd3
RGMII1 Transmit Data
O
C3
rgmii1_txd2
RGMII1 Transmit Data
O
C4
rgmii1_txd1
RGMII1 Transmit Data
O
B2
rgmii1_txd0
RGMII1 Transmit Data
O
D6
rgmii1_rxc
RGMII1 Receive Clock
I
C5
rgmii1_rxctl
RGMII1 Receive Control
I
A3
rgmii1_rxd3
RGMII1 Receive Data
I
B3
rgmii1_rxd2
RGMII1 Receive Data
I
B4
rgmii1_rxd1
RGMII1 Receive Data
I
B5
rgmii1_rxd0
RGMII1 Receive Data
I
A4
mii1_rxd1
MII1 Receive Data
I
C1
mii1_rxd2
MII1 Receive Data
I
E4
mii1_rxd3
MII1 Receive Data
I
F5
mii1_rxd0
MII1 Receive Data
I
E6
mii1_rxclk
MII1 Receive Clock
I
D5
mii1_rxdv
MII1 Receive Data Valid
I
C2
mii1_txclk
MII1 Transmit Clock
I
C3
mii1_txd0
MII1 Transmit Data
O
C4
mii1_txd1
MII1 Transmit Data
O
B2
mii1_txd2
MII1 Transmit Data
O
D6
mii1_txd3
MII1 Transmit Data
O
C5
mii1_txer
MII1 Transmit Error
I
A3
mii1_rxer
MII1 Receive Data Error
I
B3
mii1_col
MII1 Collision Detect (Sense)
I
B4
mii1_crs
MII1 Carrier Sense
I
B5
mii1_txen
MII1 Transmit Data Enable
O
A4
mii0_rxd1
MII0 Receive Data
I
V6
mii0_rxd2
MII0 Receive Data
I
V9
mii0_rxd3
MII0 Receive Data
I
W9
mii0_rxd0
MII0 Receive Data
I
U6
mii0_rxclk
MII0 Receive Clock
I
Y1
mii0_rxdv
MII0 Receive Data Valid
I
V2
mii0_txclk
MII0 Transmit Clock
I
U5
mii0_txd0
MII0 Transmit Data
O
W2
mii0_txd1
MII0 Transmit Data
O
Y2
mii0_txd2
MII0 Transmit Data
O
V4
mii0_txd3
MII0 Transmit Data
O
V5
mii0_txer
MII0 Transmit Error
I
U4
Terminal Configuration and Functions
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-20. GMAC Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
mii0_rxer
DESCRIPTION
MII0 Receive Data Error
I
U7
mii0_col
MII0 Collision Detect (Sense)
I
V1
mii0_crs
MII0 Carrier Sense
I
V7
mii0_txen
MII0 Transmit Data Enable
O
V3
V2
rmii1_crs
RMII1 Carrier Sense
I
rmii1_rxer
RMII1 Receive Data Error
I
Y1
rmii1_rxd1
RMII1 Receive Data
I
W9
rmii1_rxd0
RMII1 Receive Data
I
V9
rmii1_txen
RMII1 Transmit Data Enable
O
U5
rmii1_txd1
RMII1 Transmit Data
O
V5
rmii1_txd0
RMII1 Transmit Data
O
V4
rmii0_crs
RMII0 Carrier Sense
I
V7
rmii0_rxer
RMII0 Receive Data Error
I
U7
rmii0_rxd1
RMII0 Receive Data
I
V6
rmii0_rxd0
RMII0 Receive Data
I
U6
rmii0_txen
RMII0 Transmit Data Enable
O
V3
rmii0_txd1
RMII0 Transmit Data
O
Y2
rmii0_txd0
RMII0 Transmit Data
O
W2
mdio_mclk
Management Data Serial Clock
O
AC5 / V1 / B21 / D3
Management Data
IO
AB4 / U4 / B20 / F6
mdio_d
4.4.18 Media Local Bus (MLB) Interface
NOTE
MLB in 6-pin mode may require pullups/ pulldowns on SIG and DAT bus signals.
For additional details, please consult the MLB bus interface specification.
NOTE
For more information, see the Serial Communication Interface / Media Local Bus (MLB)
section of the device TRM.
Table 4-21. MLB Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
mlb_sig
Media Local Bus (MLB) Subsystem signal
IO
AB3
mlb_dat
Media Local Bus (MLB) Subsystem data
IO
AA4
mlb_clk
Media Local Bus (MLB) Subsystem clock
I
AA3
mlbp_sig_p
Media Local Bus (MLB) Subsystem signal differential pair (positive)
IODS
AC1
mlbp_sig_n
Media Local Bus (MLB) Subsystem signal differential pair (negative)
IODS
AC2
mlbp_dat_p
Media Local Bus (MLB) Subsystem data differential pair (positive)
IODS
AA1
mlbp_dat_n
Media Local Bus (MLB) Subsystem data differential pair (negative)
IODS
AA2
mlbp_clk_p
Media Local Bus (MLB) Subsystem clock differential pair (positive)
IOS
AB1
mlbp_clk_n
Media Local Bus (MLB) Subsystem clock differential pair (negative)
IOS
AB2
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4.4.19 eMMC/SD/SDIO
NOTE
For more information, see the HS MMC/SDIO section of the device TRM.
Table 4-22. eMMC/SD/SDIO Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Multi Media Card 1
mmc1_clk(1)
MMC1 clock
IO
W6
mmc1_cmd
MMC1 command
IO
Y6
W7
mmc1_sdcd
MMC1 Card Detect
I
mmc1_sdwp
MMC1 Write Protect
I
Y9
mmc1_dat0
MMC1 data bit 0
IO
AA6
mmc1_dat1
MMC1 data bit 1
IO
Y4
mmc1_dat2
MMC1 data bit 2
IO
AA5
mmc1_dat3
MMC1 data bit 3
IO
Y3
mmc2_clk(1)
MMC2 clock
IO
J7
mmc2_cmd
MMC2 command
IO
H6
mmc2_sdcd
MMC2 Card Detect
I
G20
mmc2_sdwp
MMC2 Write Protect
I
G19
mmc2_dat0
MMC2 data bit 0
IO
J4
mmc2_dat1
MMC2 data bit 1
IO
J6
mmc2_dat2
MMC2 data bit 2
IO
H4
mmc2_dat3
MMC2 data bit 3
IO
H5
mmc2_dat4
MMC2 data bit 4
IO
K7
mmc2_dat5
MMC2 data bit 5
IO
M7
mmc2_dat6
MMC2 data bit 6
IO
J5
mmc2_dat7
MMC2 data bit 7
IO
K6
mmc3_clk(1)
MMC3 clock
IO
AD4
mmc3_cmd
MMC3 command
IO
AC4
mmc3_sdcd
MMC3 Card Detect
I
B21
mmc3_sdwp
MMC3 Write Protect
I
B20
mmc3_dat0
MMC3 data bit 0
IO
AC7
mmc3_dat1
MMC3 data bit 1
IO
AC6
mmc3_dat2
MMC3 data bit 2
IO
AC9
mmc3_dat3
MMC3 data bit 3
IO
AC3
mmc3_dat4
MMC3 data bit 4
IO
AC8
mmc3_dat5
MMC3 data bit 5
IO
AD6
mmc3_dat6
MMC3 data bit 6
IO
AB8
mmc3_dat7
MMC3 data bit 7
IO
AB5
Multi Media Card 2
Multi Media Card 3
Multi Media Card 4
124
mmc4_sdcd
MMC4 Card Detect
I
B27
mmc4_sdwp
MMC4 Write Protect
I
C26
mmc4_clk(1)
MMC4 clock
IO
E25
mmc4_cmd
MMC4 command
IO
C27
mmc4_dat0
MMC4 data bit 0
IO
D28
mmc4_dat1
MMC4 data bit 1
IO
D26
Terminal Configuration and Functions
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-22. eMMC/SD/SDIO Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
mmc4_dat2
MMC4 data bit 2
IO
D27
mmc4_dat3
MMC4 data bit 3
IO
C28
(1) By default, this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer
to serve as the internal reference signal. mmc1_clk and mmc2_clk have an optional software programmable setting to use an 'internal
loopback clock' instead of the default 'pad loopback clock'. If the 'pad loopback clock' is used, series termination is recommended (as
close to device pin as possible) to improve signal integrity of the clock input. Any non-monotonicity in voltage that occurs at the pad
loopback clock pin between VIH and VIL must be less than VHYS.
4.4.20 General-Purpose Interface (GPIO)
NOTE
For more information, see the General-Purpose Interface section of the device TRM.
Table 4-23. GPIOs Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
GPIO 1
gpio1_0
General-Purpose Input
I
AD17
gpio1_1
General-Purpose Input
I
AC17
gpio1_2
General-Purpose Input
I
AB16
gpio1_3
General-Purpose Input
I
AC16
gpio1_4
General-Purpose Input/Output
IO
D15
gpio1_5
General-Purpose Input/Output
IO
A17
gpio1_6
General-Purpose Input/Output
IO
M6
gpio1_7
General-Purpose Input/Output
IO
M2
gpio1_8
General-Purpose Input/Output
IO
L5
gpio1_9
General-Purpose Input/Output
IO
M1
gpio1_10
General-Purpose Input/Output
IO
L6
gpio1_11
General-Purpose Input/Output
IO
L4
gpio1_12
General-Purpose Input/Output
IO
L3
gpio1_13
General-Purpose Input/Output
IO
L2
gpio1_14
General-Purpose Input/Output
IO
G20
gpio1_15
General-Purpose Input/Output
IO
G19
gpio1_16
General-Purpose Input/Output
IO
D27
gpio1_17
General-Purpose Input/Output
IO
C28
gpio1_18
General-Purpose Input/Output
IO
H1
gpio1_19
General-Purpose Input/Output
IO
J3
gpio1_20
General-Purpose Input/Output
IO
H2
gpio1_21
General-Purpose Input/Output
IO
H3
gpio1_22
General-Purpose Input/Output
IO
AC8
gpio1_23
General-Purpose Input/Output
IO
AD6
gpio1_24
General-Purpose Input/Output
IO
AB8
gpio1_25
General-Purpose Input/Output
IO
AB5
gpio1_26
General-Purpose Input/Output
IO
P6
gpio1_27
General-Purpose Input/Output
IO
R9
gpio1_28
General-Purpose Input/Output
IO
R5
gpio1_29
General-Purpose Input/Output
IO
P5
gpio1_30
General-Purpose Input/Output
IO
N7
gpio1_31
General-Purpose Input/Output
IO
R4
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Table 4-23. GPIOs Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
GPIO 2
gpio2_0
General-Purpose Input/Output
IO
N9
gpio2_1
General-Purpose Input/Output
IO
P9
gpio2_2
General-Purpose Input/Output
IO
P4
gpio2_3
General-Purpose Input/Output
IO
R3
gpio2_4
General-Purpose Input/Output
IO
T2
gpio2_5
General-Purpose Input/Output
IO
U2
gpio2_6
General-Purpose Input/Output
IO
U1
gpio2_7
General-Purpose Input/Output
IO
P3
gpio2_8
General-Purpose Input/Output
IO
R2
gpio2_9
General-Purpose Input/Output
IO
K7
gpio2_10
General-Purpose Input/Output
IO
M7
gpio2_11
General-Purpose Input/Output
IO
J5
gpio2_12
General-Purpose Input/Output
IO
K6
gpio2_13
General-Purpose Input/Output
IO
J7
gpio2_14
General-Purpose Input/Output
IO
J4
gpio2_15
General-Purpose Input/Output
IO
J6
gpio2_16
General-Purpose Input/Output
IO
H4
gpio2_17
General-Purpose Input/Output
IO
H5
gpio2_18
General-Purpose Input/Output
IO
H6
gpio2_19
General-Purpose Input/Output
IO
T1
gpio2_20
General-Purpose Input/Output
IO
P2
gpio2_21
General-Purpose Input/Output
IO
P1
gpio2_22
General-Purpose Input/Output
IO
P7
gpio2_23
General-Purpose Input/Output
IO
N1
gpio2_24
General-Purpose Input/Output
IO
M5
gpio2_25
General-Purpose Input/Output
IO
M3
gpio2_26
General-Purpose Input/Output
IO
N6
gpio2_27
General-Purpose Input/Output
IO
M4
gpio2_28
General-Purpose Input/Output
IO
N2
gpio2_29
General-Purpose Input/Output
IO
B17
gpio2_30
General-Purpose Input/Output
IO
AG8
gpio2_31
General-Purpose Input/Output
IO
AH7
gpio3_0
General-Purpose Input/Output
IO
AD9
gpio3_1
General-Purpose Input/Output
IO
AF9
gpio3_2
General-Purpose Input/Output
IO
AE9
gpio3_3
General-Purpose Input/Output
IO
AF8
gpio3_4
General-Purpose Input/Output
IO
AE8
gpio3_5
General-Purpose Input/Output
IO
AD8
gpio3_6
General-Purpose Input/Output
IO
AG7
gpio3_7
General-Purpose Input/Output
IO
AH6
gpio3_8
General-Purpose Input/Output
IO
AH3
gpio3_9
General-Purpose Input/Output
IO
AH5
gpio3_10
General-Purpose Input/Output
IO
AG6
gpio3_11
General-Purpose Input/Output
IO
AH4
gpio3_12
General-Purpose Input/Output
IO
AG4
GPIO 3
126
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-23. GPIOs Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpio3_13
DESCRIPTION
General-Purpose Input/Output
IO
AG2
gpio3_14
General-Purpose Input/Output
IO
AG3
gpio3_15
General-Purpose Input/Output
IO
AG5
gpio3_16
General-Purpose Input/Output
IO
AF2
gpio3_17
General-Purpose Input/Output
IO
AF6
gpio3_18
General-Purpose Input/Output
IO
AF3
gpio3_19
General-Purpose Input/Output
IO
AF4
gpio3_20
General-Purpose Input/Output
IO
AF1
gpio3_21
General-Purpose Input/Output
IO
AE3
gpio3_22
General-Purpose Input/Output
IO
AE5
gpio3_23
General-Purpose Input/Output
IO
AE1
gpio3_24
General-Purpose Input/Output
IO
AE2
gpio3_25
General-Purpose Input/Output
IO
AE6
gpio3_26
General-Purpose Input/Output
IO
AD2
gpio3_27
General-Purpose Input/Output
IO
AD3
gpio3_28
General-Purpose Input/Output
IO
E1
gpio3_29
General-Purpose Input/Output
IO
G2
gpio3_30
General-Purpose Input/Output
IO
H7
gpio3_31
General-Purpose Input/Output
IO
G1
gpio4_0
General-Purpose Input/Output
IO
G6
gpio4_1
General-Purpose Input/Output
IO
F2
gpio4_2
General-Purpose Input/Output
IO
F3
gpio4_3
General-Purpose Input/Output
IO
D1
gpio4_4
General-Purpose Input/Output
IO
E2
gpio4_5
General-Purpose Input/Output
IO
D2
gpio4_6
General-Purpose Input/Output
IO
F4
gpio4_7
General-Purpose Input/Output
IO
C1
gpio4_8
General-Purpose Input/Output
IO
E4
gpio4_9
General-Purpose Input/Output
IO
F5
gpio4_10
General-Purpose Input/Output
IO
E6
gpio4_11
General-Purpose Input/Output
IO
D3
gpio4_12
General-Purpose Input/Output
IO
F6
gpio4_13
General-Purpose Input/Output
IO
D5
gpio4_14
General-Purpose Input/Output
IO
C2
gpio4_15
General-Purpose Input/Output
IO
C3
gpio4_16
General-Purpose Input/Output
IO
C4
gpio4_17
General-Purpose Input/Output
IO
A12
gpio4_18
General-Purpose Input/Output
IO
E14
gpio4_19
General-Purpose Input/Output
IO
D11
gpio4_20
General-Purpose Input/Output
IO
B10
gpio4_21
General-Purpose Input/Output
IO
B11
gpio4_22
General-Purpose Input/Output
IO
C11
gpio4_23
General-Purpose Input/Output
IO
E11
gpio4_24
General-Purpose Input/Output
IO
B2
gpio4_25
General-Purpose Input/Output
IO
D6
gpio4_26
General-Purpose Input/Output
IO
C5
GPIO 4
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Table 4-23. GPIOs Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpio4_27
DESCRIPTION
General-Purpose Input/Output
IO
A3
gpio4_28
General-Purpose Input/Output
IO
B3
gpio4_29
General-Purpose Input/Output
IO
B4
gpio4_30
General-Purpose Input/Output
IO
B5
gpio4_31
General-Purpose Input/Output
IO
A4
gpio5_0
General-Purpose Input/Output
IO
B14
gpio5_1
General-Purpose Input/Output
IO
J14
gpio5_2
General-Purpose Input/Output
IO
G12
gpio5_3
General-Purpose Input/Output
IO
F12
gpio5_4
General-Purpose Input/Output
IO
G13
gpio5_5
General-Purpose Input/Output
IO
J11
gpio5_6
General-Purpose Input/Output
IO
E12
gpio5_7
General-Purpose Input/Output
IO
F13
gpio5_8
General-Purpose Input/Output
IO
C12
gpio5_9
General-Purpose Input/Output
IO
D12
gpio5_10
General-Purpose Input/Output
IO
B12
gpio5_11
General-Purpose Input/Output
IO
A11
gpio5_12
General-Purpose Input/Output
IO
B13
gpio5_13
General-Purpose Input/Output
IO
B18
gpio5_14
General-Purpose Input/Output
IO
F15
gpio5_15
General-Purpose Input/Output
IO
V1
gpio5_16
General-Purpose Input/Output
IO
U4
gpio5_17
General-Purpose Input/Output
IO
U3
gpio5_18
General-Purpose Input/Output
IO
V2
gpio5_19
General-Purpose Input/Output
IO
Y1
gpio5_20
General-Purpose Input/Output
IO
W9
gpio5_21
General-Purpose Input/Output
IO
V9
gpio5_22
General-Purpose Input/Output
IO
V7
gpio5_23
General-Purpose Input/Output
IO
U7
gpio5_24
General-Purpose Input/Output
IO
V6
gpio5_25
General-Purpose Input/Output
IO
U6
gpio5_26
General-Purpose Input/Output
IO
U5
gpio5_27
General-Purpose Input/Output
IO
V5
gpio5_28
General-Purpose Input/Output
IO
V4
gpio5_29
General-Purpose Input/Output
IO
V3
gpio5_30
General-Purpose Input/Output
IO
Y2
gpio5_31
General-Purpose Input/Output
IO
W2
gpio6_4
General-Purpose Input/Output
IO
A13
gpio6_5
General-Purpose Input/Output
IO
G14
gpio6_6
General-Purpose Input/Output
IO
F14
gpio6_7
General-Purpose Input/Output
IO
B16
gpio6_8
General-Purpose Input/Output
IO
C15
GPIO 5
GPIO 6
128
gpio6_9
General-Purpose Input/Output
IO
A16
gpio6_10
General-Purpose Input/Output
IO
AC5
gpio6_11
General-Purpose Input/Output
IO
AB4
Terminal Configuration and Functions
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-23. GPIOs Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpio6_12
DESCRIPTION
General-Purpose Input/Output
IO
AB10
gpio6_13
General-Purpose Input/Output
IO
AC10
gpio6_14
General-Purpose Input/Output
IO
E21
gpio6_15
General-Purpose Input/Output
IO
F20
gpio6_16
General-Purpose Input/Output
IO
F21
gpio6_17
General-Purpose Input/Output
IO
D18
gpio6_18
General-Purpose Input/Output
IO
E17
gpio6_19
General-Purpose Input/Output
IO
B26
gpio6_20
General-Purpose Input/Output
IO
C23
gpio6_21
General-Purpose Input/Output
IO
W6
gpio6_22
General-Purpose Input/Output
IO
Y6
gpio6_23
General-Purpose Input/Output
IO
AA6
gpio6_24
General-Purpose Input/Output
IO
Y4
gpio6_25
General-Purpose Input/Output
IO
AA5
gpio6_26
General-Purpose Input/Output
IO
Y3
gpio6_27
General-Purpose Input/Output
IO
W7
gpio6_28
General-Purpose Input/Output
IO
Y9
gpio6_29
General-Purpose Input/Output
IO
AD4
gpio6_30
General-Purpose Input/Output
IO
AC4
gpio6_31
General-Purpose Input/Output
IO
AC7
gpio7_0
General-Purpose Input/Output
IO
AC6
gpio7_1
General-Purpose Input/Output
IO
AC9
gpio7_2
General-Purpose Input/Output
IO
AC3
gpio7_3
General-Purpose Input/Output
IO
R6
gpio7_4
General-Purpose Input/Output
IO
T9
gpio7_5
General-Purpose Input/Output
IO
T6
gpio7_6
General-Purpose Input/Output
IO
T7
gpio7_7
General-Purpose Input/Output
IO
A25
gpio7_8
General-Purpose Input/Output
IO
F16
gpio7_9
General-Purpose Input/Output
IO
B25
gpio7_10
General-Purpose Input/Output
IO
A24
gpio7_11
General-Purpose Input/Output
IO
A22
gpio7_12
General-Purpose Input/Output
IO
B21
gpio7_13
General-Purpose Input/Output
IO
B20
gpio7_14
General-Purpose Input/Output
IO
A26
gpio7_15
General-Purpose Input/Output
IO
B22
gpio7_16
General-Purpose Input/Output
IO
G17
gpio7_17
General-Purpose Input/Output
IO
B24
gpio7_18
General-Purpose Input/Output
IO
L1
gpio7_19
General-Purpose Input/Output
IO
K2
gpio7_22
General-Purpose Input/Output
IO
B27
gpio7_23
General-Purpose Input/Output
IO
C26
gpio7_24
General-Purpose Input/Output
IO
E25
gpio7_25
General-Purpose Input/Output
IO
C27
gpio7_26
General-Purpose Input/Output
IO
D28
gpio7_27
General-Purpose Input/Output
IO
D26
GPIO 7
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Table 4-23. GPIOs Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpio7_28
DESCRIPTION
General-Purpose Input/Output
IO
J1
gpio7_29
General-Purpose Input/Output
IO
J2
gpio7_30
General-Purpose Input/Output
IO
D14
gpio7_31
General-Purpose Input/Output
IO
C14
gpio8_0
General-Purpose Input/Output
IO
F11
gpio8_1
General-Purpose Input/Output
IO
G10
gpio8_2
General-Purpose Input/Output
IO
F10
gpio8_3
General-Purpose Input/Output
IO
G11
gpio8_4
General-Purpose Input/Output
IO
E9
gpio8_5
General-Purpose Input/Output
IO
F9
gpio8_6
General-Purpose Input/Output
IO
F8
gpio8_7
General-Purpose Input/Output
IO
E7
gpio8_8
General-Purpose Input/Output
IO
E8
GPIO 8
gpio8_9
General-Purpose Input/Output
IO
D9
gpio8_10
General-Purpose Input/Output
IO
D7
gpio8_11
General-Purpose Input/Output
IO
D8
gpio8_12
General-Purpose Input/Output
IO
A5
gpio8_13
General-Purpose Input/Output
IO
C6
gpio8_14
General-Purpose Input/Output
IO
C8
gpio8_15
General-Purpose Input/Output
IO
C7
gpio8_16
General-Purpose Input/Output
IO
B7
gpio8_17
General-Purpose Input/Output
IO
B8
gpio8_18
General-Purpose Input/Output
IO
A7
gpio8_19
General-Purpose Input/Output
IO
A8
gpio8_20
General-Purpose Input/Output
IO
C9
gpio8_21
General-Purpose Input/Output
IO
A9
gpio8_22
General-Purpose Input/Output
IO
B9
gpio8_23
General-Purpose Input/Output
IO
A10
gpio8_27
General-Purpose Input
I
D23
gpio8_28
General-Purpose Input/Output
IO
F19
gpio8_29
General-Purpose Input/Output
IO
E18
gpio8_30
General-Purpose Input/Output
IO
G21
gpio8_31
General-Purpose Input/Output
IO
D24
4.4.21 Keyboard controller (KBD)
NOTE
For more information, see Keyboard Controller section of the device TRM.
Table 4-24. Keyboard Signal Descriptions
SIGNAL NAME
130
TYPE
BALL
kbd_row0
DESCRIPTION
Keypad row 0
I
AD9/ E1
kbd_row1
Keypad row 1
I
AF9/ G2
kbd_row2
Keypad row 2
I
AG4/ G1
kbd_row3
Keypad row 3
I
AG2/ G6
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Table 4-24. Keyboard Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
kbd_row4
DESCRIPTION
Keypad row 4
I
AG3/ F2
kbd_row5
Keypad row 5
I
AG5/ F3
kbd_row6
Keypad row 6
I
AF2/ D1
kbd_row7
Keypad row 7
I
AF6/ F6
kbd_row8
Keypad row 8
I
AF3/ C2
kbd_col0
Keypad column 0
O
AF4/ E2
kbd_col1
Keypad column 1
O
AF1/ D2
kbd_col2
Keypad column 2
O
AE3/ F4
kbd_col3
Keypad column 3
O
AE5/ C1
kbd_col4
Keypad column 4
O
AE1/ E4
kbd_col5
Keypad column 5
O
AE2/ F5
kbd_col6
Keypad column 6
O
AE6/ E6
kbd_col7
Keypad column 7
O
AD2/ D3
kbd_col8
Keypad column 8
O
AD3/ D5
4.4.22 Pulse Width Modulation (PWM) Interface
NOTE
For more information, see the Pulse-Width Modulation (PWM) SS section of the device TRM.
Table 4-25. PWM Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
PWMSS1
eQEP1A_in
EQEP1 Quadrature Input A
I
E1 / AD9
eQEP1B_in
EQEP1 Quadrature Input B
I
G2 / AF9
AE9 / H7
eQEP1_index
EQEP1 Index Input
IO
eQEP1_strobe
EQEP1 Strobe Input
IO
G1 / AF8
ehrpwm1A
EHRPWM1 Output A
O
AE8 / G6
ehrpwm1B
EHRPWM1 Output B
O
AD8 / F2
EHRPWM1 Trip Zone Input
IO
AG7 / F3
ehrpwm1_tripzone_in
put
eCAP1_in_PWM1_out ECAP1 Capture Iniput / PWM Output
IO
AH6 / D1
ehrpwm1_synci
EHRPWM1 Sync Input
I
AH3 / E2
ehrpwm1_synco
EHRPWM1 Sync Output
O
AH5 / D2
eQEP2A_in
EQEP2 Quadrature Input A
I
AG6 / F4
eQEP2B_in
EQEP2 Quadrature Input B
PWMSS2
I
AH4 / C1
eQEP2_index
EQEP2 Index Input
IO
AG4 / E4
eQEP2_strobe
EQEP2 Strobe Input
IO
AG2 / F5
ehrpwm2A
EHRPWM2 Output A
O
AC5 / E6
ehrpwm2B
EHRPWM2 Output B
O
AB4 / D3
EHRPWM2 Trip Zone Input
IO
AD4 / F6
IO
AC4 / D5
ehrpwm2_tripzone_in
put
eCAP2_in_PWM2_out ECAP2 Capture Iniput / PWM Output
PWMSS3
eQEP3A_in
EQEP3 Quadrature Input A
I
AC7 / C2
eQEP3B_in
EQEP3 Quadrature Input B
I
AC6 / C3
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Table 4-25. PWM Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
eQEP3_index
DESCRIPTION
EQEP3 Index Input
IO
AC9 / C4
eQEP3_strobe
EQEP3 Strobe Input
IO
AC3 / B2
ehrpwm3A
EHRPWM3 Output A
O
AC8 / D6
ehrpwm3B
EHRPWM3 Output B
O
AD6 / C5
EHRPWM3 Trip Zone Input
IO
AB8 / A3
IO
AB5 / B3
ehrpwm3_tripzone_in
put
eCAP3_in_PWM3_out ECAP3 Capture Iniput / PWM Output
4.4.23 Audio Tracking Logic (ATL)
NOTE
For more information, see the Audio Tracking Logic (ATL) section of the device TRM.
Table 4-26. ATL Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
atl_clk0
Audio Tracking Logic Clock 0
O
D18
atl_clk1
Audio Tracking Logic Clock 1
O
E17
atl_clk2
Audio Tracking Logic Clock 2
O
B26
atl_clk3
Audio Tracking Logic Clock 3
O
C23
4.4.24 Test Interfaces
CAUTION
The I/O timings provided in Section 7 Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in the Table 7-152.
NOTE
For more information, see the On-Chip Debug Support / Debug Ports section of the device
TRM.
Table 4-27. Debug Signal Descriptions
SIGNAL NAME
132
DESCRIPTION
tms
JTAG test port mode select. An external pullup resistor should be used on this
ball.
TYPE
BALL
IO
F18
tdi
JTAG test data
I
D23
tdo
JTAG test port data
O
F19
tclk
JTAG test clock
I
E20
trstn
JTAG test reset
I
D20
rtck
JTAG return clock
O
E18
emu0
Emulator pin 0
IO
G21
emu1
Emulator pin 1
IO
D24
emu2
Emulator pin 2
O
F10
emu3
Emulator pin 3
O
D7
emu4
Emulator pin 4
O
A7
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Table 4-27. Debug Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
emu5
Emulator pin 5
O
E1 / G11
emu6
Emulator pin 6
O
G2 / E9
emu7
Emulator pin 7
O
H7 / F9
emu8
Emulator pin 8
O
G1 / F8
emu9
Emulator pin 9
O
G6 / E7
emu10
Emulator pin 10
O
F2 / D8
emu11
Emulator pin 11
O
F3 / A5
emu12
Emulator pin 12
O
D1 / C6
emu13
Emulator pin 13
O
E2 / C8
emu14
Emulator pin 14
O
D2 / C7
emu15
Emulator pin 15
O
F4 / A8
emu16
Emulator pin 16
O
C1 / C9
emu17
Emulator pin 17
O
E4 / A9
emu18
Emulator pin 18
O
F5 / B9
emu19
Emulator pin 19
O
E6 / A10
4.4.25 System and Miscellaneous
4.4.25.1 Sysboot
NOTE
For more information, see the Initialization (ROM Code) section of the device TRM.
Table 4-28. Sysboot Signal Descriptions
SIGNAL NAME
TYPE
BALL
sysboot0
DESCRIPTION
Boot Mode Configuration 0. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M6
sysboot1
Boot Mode Configuration 1. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M2
sysboot2
Boot Mode Configuration 2. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L5
sysboot3
Boot Mode Configuration 3. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M1
sysboot4
Boot Mode Configuration 4. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L6
sysboot5
Boot Mode Configuration 5. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L4
sysboot6
Boot Mode Configuration 6. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L3
sysboot7
Boot Mode Configuration 7. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L2
sysboot8
Boot Mode Configuration 8. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L1
sysboot9
Boot Mode Configuration 9. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
K2
sysboot10
Boot Mode Configuration 10. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
J1
sysboot11
Boot Mode Configuration 11. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
J2
sysboot12
Boot Mode Configuration 12. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
H1
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Table 4-28. Sysboot Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
sysboot13
DESCRIPTION
Boot Mode Configuration 13. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
J3
sysboot14
Boot Mode Configuration 14. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
H2
sysboot15
Boot Mode Configuration 15. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
H3
4.4.25.2 Power, Reset, and Clock Management (PRCM)
NOTE
For more information, see PRCM section of the device TRM.
Table 4-29. PRCM Signal Descriptions
SIGNAL NAME
TYPE
BALL
clkout1
Device Clock output 1. Can be used externally for devices with non-critical timing
requirements, or for debug, or as a reference clock on GPMC as described in
Table 7-24 GPMC/NOR Flash Interface Switching Characteristics - Synchronous
Mode - 1 Load and Table 7-26 GPMC/NOR Flash Interface Switching
Characteristics - Synchronous Mode - 5 Loads.
O
F21 / P7
clkout2
Device Clock output 2. Can be used externally for devices with non-critical timing
requirements, or for debug.
O
D18 / N1
clkout3
Device Clock output 3. Can be used externally for devices with non-critical timing
requirements, or for debug.
O
C23
rstoutn
Reset out (Active low). This pin asserts low in response to any global reset condition
on the device.
O
F23
resetn
Device Reset Input
I
E23
Power on Reset (active low). This pin must be asserted low until all device supplies
are valid (see reset sequence/requirements)
I
F22
xref_clk0
External Reference Clock 0. For Audio and other Peripherals.
I
D18
xref_clk1
External Reference Clock 1. For Audio and other Peripherals.
I
E17
xref_clk2
External Reference Clock 2. For Audio and other Peripherals.
I
B26
xref_clk3
External Reference Clock 3. For Audio and other Peripherals.
I
C23
xi_osc0
System Oscillator OSC0 Crystal input / LVCMOS clock input. Functions as the input
connection to a crystal when the internal oscillator OSC0 is used. Functions as an
LVCMOS-compatible input clock when an external oscillator is used.
I
AE15
xo_osc0
System Oscillator OSC0 Crystal output
O
AD15
xi_osc1
Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input. Functions as the
input connection to a crystal when the internal oscillator OSC1 is used. Functions as
an LVCMOS-compatible input clock when an external oscillator is used
I
AC15
xo_osc1
Auxiliary Oscillator OSC1 Crystal output
O
AC13
IO
U3
porz
DESCRIPTION
RMII_MHZ_50_C RMII Reference Clock (50MHz). This pin is an input when external reference is used
LK(1)
or output when internal reference is used.
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any non-monotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
4.4.25.3 Real Time Clock (RTC) Interface
NOTE
For more information, see the Real Time Clock (RTC) SS section of the device TRM.
134
Terminal Configuration and Functions
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Table 4-30. RTC Signal Descriptions
SIGNAL NAME
TYPE
BALL
Wakeup0
RTC External Wakeup Input 0
I
AD17
Wakeup1
RTC External Wakeup Input 1
I
AC17
Wakeup2
RTC External Wakeup Input 2
I
AB16
Wakeup3
RTC External Wakeup Input 3
I
AC16
RTC Power Domain Power-On Reset Input
I
AB17
I
AE14
rtc_porz
DESCRIPTION
rtc_osc_xi_clkin3 RTC Oscillator Input. Crystal connection to internal RTC oscillator. Functions as an
2
RTC clock input when an external oscillator is used.
rtc_osc_xo
RTC Oscillator Output
O
AD14
rtc_iso(1)
RTC domain isolation signal.
I
AF14
on_off
RTC Power Enable output pin
O
Y11
(1) This signal must be kept 0 if device power supplies are not valid during RTC mode and 1 during normal operation. This can typically be
achieved by connecting rtc_iso to the same signal driving porz (not rtc_porz) with appropriate voltage level translation if necessary.
4.4.25.4 System Direct Memory Access (SDMA)
NOTE
For more information, see the DMA Controllers / System DMA section of the device TRM.
Table 4-31. SDMA Signal Descriptions
SIGNAL NAME
TYPE
BALL
dma_evt1
DESCRIPTION
System DMA Event Input 1
I
P7 / P4
dma_evt2
System DMA Event Input 2
I
N1 / R3
dma_evt3
System DMA Event Input 3
I
N6
dma_evt4
System DMA Event Input 4
I
M4
4.4.25.5 Interrupt Controllers (INTC)
NOTE
For more information, see the Interrupt Controllers section of the device TRM.
Table 4-32. INTC Signal Descriptions
SIGNAL NAME
TYPE
BALL
nmin_dsp
DESCRIPTION
Non maskable interrupt input, active-low. This pin can be optionally routed to the
DSP NMI input or as generic input to the ARM cores. Note that by default this pin
has an internal pulldown resistor enabled. This internal pulldown should be disabled
or countered by a stronger external pullup resistor before routing to the DSP or
ARM processors.
I
D21
sys_nirq2
External interrupt event to any device INTC
I
AB16
sys_nirq1
External interrupt event to any device INTC
I
AC16
4.4.25.6 Observability
NOTE
For more information, see the Control Module section of the device TRM.
Terminal Configuration and Functions
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Table 4-33. Observability Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
obs0
Observation Output 0
O
F10
obs1
Observation Output 1
O
G11
obs2
Observation Output 2
O
E9
obs3
Observation Output 3
O
F9
obs4
Observation Output 4
O
F8
obs5
Observation Output 5
O
D7
obs6
Observation Output 6
O
D8
obs7
Observation Output 7
O
A5
obs8
Observation Output 8
O
C6
obs9
Observation Output 9
O
C8
obs10
Observation Output 10
O
C7
obs11
Observation Output 11
O
A7
obs12
Observation Output 12
O
A8
obs13
Observation Output 13
O
C9
obs14
Observation Output 14
O
A9
obs15
Observation Output 15
O
B9
obs16
Observation Output 16
O
F10
obs17
Observation Output 17
O
G11
obs18
Observation Output 18
O
E9
obs19
Observation Output 19
O
F9
obs20
Observation Output 20
O
F8
obs21
Observation Output 21
O
D7
obs22
Observation Output 22
O
D8
obs23
Observation Output 23
O
A5
obs24
Observation Output 24
O
C6
obs25
Observation Output 25
O
C8
obs26
Observation Output 26
O
C7
obs27
Observation Output 27
O
A7
obs28
Observation Output 28
O
A8
obs29
Observation Output 29
O
C9
obs30
Observation Output 30
O
A9
obs31
Observation Output 31
O
B9
obs_dmarq1
DMA Request External Observation Output 1
O
G11
obs_dmarq2
DMA Request External Observation Output 2
O
D8
obs_irq1
IRQ External Observation Output 1
O
F10
obs_irq2
IRQ External Observation Output 2
O
D7
4.4.26 Power Supplies
NOTE
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs section of the device TRM.
136
Terminal Configuration and Functions
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Table 4-34. Power Supply Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
vdd
Core voltage domain supply
PWR
H13/ H14/ J17/ J18/
L7/ L8/ N10/ N13/
P11/ P12/ P13/ R11/
R16/ R19/ T13/ T16/
T19/ U8/ U9/ U13/
U16/ V8/ V16
vss
Ground
GND
A1/ A2/ A6/ A14/ A23/
A28/ B1/ D13/ D19/
E13/ E19/ F1/ F7/ G7/
G8/ G9/ H12/ J12/
J15/ J28/ K1/ K4/ K5/
K15/ K24/ K25/ L13/
L14/ M19/ N14/ N15/
N19/ N24/ N25/ P28/
R1/ R12/ R13/ R15/
R21/ T10/ T11/ T12/
T14/ T15/ T17/ T18/
T21/ U15/ U17/ U20/
U21/ V15/ V17/ W1/
W15/ W24/ W25/
W28/ AA8/ AA9/
AA10/ AA14/ AA15/
AA20/ AB14/ AB20/
AD1/ AD24/ AG1/
AH1/ AH2/ AH8/
AH20/ AH28
DSP-EVE voltage domain supply
PWR
J13/ K10/ K11/ K12/
K13/ L10/ L11/ L12/
M10/ M11/ M12/ M13
vdd_iva
IVA voltage domain supply
PWR
U18/ U19/ V18/ V19
vdd_gpu
GPU voltage domain supply
PWR
U11/ U12/ V10/ V11/
V14/ W10/ W11/ W13
vdd_mpu
MPU voltage domain supply
PWR
K17/ K18/ L15/ L16/
L17/ L18/ L19/ M15/
M16/ M17/ M18/ N17/
N18/ P17/ P18/ R18
vdd_rtc
RTC voltage domain supply
PWR
AB15
DPLL_USB and HS USB1 1.8V analog power supply
PWR
AA13
HS USB1 and HS USB2 analog ground
GND
AB11/ AA11
HS USB2 1.8V analog power supply
PWR
AB12
vdda33v_usb1
HS USB1 3.3V analog power supply. If USB1 is not used, this pin can
alternatively be connected to VSS if the following requirements are met:
- The usb1_dm/usb1_dp pins are left unconnected
- The USB1 PHY is kept powered down
PWR
AA12
vdda33v_usb2
HS USB2 3.3V analog power supply. If USB2 is not used, this pin can
alternatively be connected to VSS if the following requirements are met:
- The usb2_dm/usb2_dp pins are left unconnected
- The USB2 PHY is kept powered down
PWR
Y12
vdda_abe_per
DPLL_ABE, DPLL_PER, and PER HSDIVIDER analog power supply
PWR
M14
DPLL_DDR and DDR HSDIVIDER analog power supply
PWR
P16
DPLL_DEBUG analog power supply
PWR
N11
DPLL_DSP and DPLL_EVE analog power supply
PWR
N12
vdd_dspeve
vdda_usb1
vssa_usb
vdda_usb2
vdda_ddr
vdda_debug
vdda_dsp_eve
vdda_gmac_core
DPLL_CORE and CORE HSDIVIDER analog power supply
PWR
P15
vdda_gpu
DPLL_GPU analog power supply
PWR
R14
vdda_hdmi
PLL_HDMI and HDMI analog power supply
PWR
Y17
vssa_hdmi
AE19 / AD19
DPLL_HDMI and HDMI PHY analog ground
GND
vdda_iva
DPLL_IVA analog power supply
PWR
R17
vdda_pcie
DPLL_PCIe_REF and PCIe analog power supply
PWR
W14
vssa_pcie
PCIe analog ground
GND
AE13 / AD13
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Table 4-34. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
vdda_pcie0
PCIe ch0 RX/TX analog power supply
PWR
AA17
vdda_pcie1
PCIe ch1 RX/TX analog power supply
PWR
AA16
vdda_sata
DPLL_SATA and SATA RX/TX analog power supply
PWR
V13
vssa_sata
SATA analog ground
GND
AE10
vdda_usb3
DPLL_USB_OTG_SS and USB3.0 RX/TX analog power supply
PWR
W12
vssa_usb3
DPLL_USB and USB3.0 RX/TX analog ground
GND
AD10
vdda_video
DPLL_VIDEO1 and DPLL_VIDEO2 analog power supply
PWR
P14
vssa_video
DPLL_VIDEO1 and DPLL_VIDEO2 analog ground
GND
U14
vdds_mlbp
MLBP IO power supply
PWR
AA7 / Y7
vdda_mpu
DPLL_MPU analog power supply
PWR
N16
vdda_osc
HFOSC analog power supply
PWR
AE16 / AD16
vssa_osc0
OSC0 analog ground
GND
AF15
vssa_osc1
OSC1 analog ground
GND
AC14
vdda_rtc
RTC bias and RTC LFOSC analog power supply
PWR
AB13
vdds18v
1.8V power supply
PWR
W17/ W18/ V21/ V22/
T8/ R8/ P8/ N8/ M8/
M9/ H17/ G18
vdds18v_ddr1
DDR1 bias power supply
PWR
AA18/ AA19/ Y21/
W21
vdds18v_ddr2
DDR2 bias power supply
PWR
P20/ P21/ N21/ J21/
J22
vdds_ddr2
DDR2 power supply (1.8V for DDR2 mode / 1.5V for DDR3 mode /
1.35V DDR3L mode)
PWR
T24/ T25/ M20/ M21/
L20/ L21/ J27/ H20/
H21/ H22/ G22/ G23/
E24
vdds_ddr1
DDR1 power supply (1.8V for DDR2 mode / 1.5V for DDR3 mode /
1.35V DDR3L mode)
PWR
AH27/ AG20/ AG28/
AD26/ AC22/ AB21/
AB22/ AB24/ AB25/
AA21/ AA22/ W16/
W27
vddshv5
Dual Voltage (1.8V or 3.3V) power supply for the RTC Power Group
pins
PWR
V12
vddshv1
Dual Voltage (1.8V or 3.3V) power supply for the VIN2 Power Group
pins
PWR
H8/ H9/ G4/ G5/ E3/
E5
vddshv10
Dual Voltage (1.8V or 3.3V) power supply for the GPMC Power Group
pins
PWR
T4/ T5/ R7/ R10/ P10/
N4/ N5
vddshv11
Dual Voltage (1.8V or 3.3V) power supply for the MMC2 Power Group
pins
PWR
K8/ J8
vddshv2
Dual Voltage (1.8V or 3.3V) power supply for the VOUT Power Group
pins
PWR
H10/ H11/ E10/ D10/
B6
vddshv3
Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power
Group pins
PWR
H15/ H16/ H18/ H19/
G15/ E16/ E22/ D16/
D22/ B23
vddshv4
Dual Voltage (1.8V or 3.3V) power supply for the MMC4 Power Group
pins
PWR
C24
vddshv6
Dual Voltage (1.8V or 3.3V) power supply for the VIN1 Power Group
pins
PWR
AF5/ AE7/ AD5/ AD7
vddshv7
Dual Voltage (1.8V or 3.3V) power supply for the WIFI Power Group
pins
PWR
AB6 / AB7
vddshv8
Dual Voltage (1.8V or 3.3V) power supply for the MMC1 Power Group
pins
PWR
Y8 / W8
vddshv9
Dual Voltage (1.8V or 3.3V) power supply for the RGMII Power Group
pins
PWR
W4/ W5/ U10
External capacitor connection for the DSP-EVE SRAM array ldo2
output
CAP
J9
cap_vddram_dspeve2(1)
138
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 4-34. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
External capacitor connection for the DSP-EVE SRAM array ldo1
output
CAP
J10
External capacitor connection for the MPU vbb ldo output
CAP
J16
External capacitor connection for the Core SRAM array ldo2 output
CAP
J19
cap_vbbldo_dspeve
External capacitor connection for the DSP-EVE vbb ldo output
CAP
K9
cap_vddram_mpu1(1)
External capacitor connection for the MPU SRAM array ldo1 output
CAP
K16
cap_vddram_mpu2(1)
External capacitor connection for the MPU SRAM array ldo2 output
CAP
K19
cap_vddram_core1(1)
External capacitor connection for the Core SRAM array ldo1 output
CAP
L9
(1)
cap_vddram_dspeve1(1)
cap_vbbldo_mpu(1)
cap_vddram_core2(1)
(1)
cap_vddram_core4
External capacitor connection for the Core SRAM array ldo4 output
CAP
P19
cap_vbbldo_iva(1)
External capacitor connection for the IVA vbb ldo output
CAP
R20
cap_vddram_iva(1)
External capacitor connection for the IVA SRAM array ldo output
CAP
T20
External capacitor connection for the GPU SRAM array ldo output
CAP
Y13
External capacitor connection for the GPU vbb ldo output
CAP
Y14
cap_vddram_core3(1)
External capacitor connection for the Core SRAM array ldo3 output
CAP
Y15
(1)
External capacitor connection for the Core SRAM array ldo5 output
CAP
Y16
cap_vddram_gpu
(1)
cap_vbbldo_gpu(1)
cap_vddram_core5
(1) This pin must always be connected via a 1-uF capacitor to vss.
Terminal Configuration and Functions
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5 Specifications
NOTE
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements
section of the Device TRM.
NOTE
The index numbers 1 and 2 which are part of the EMIF1 and EMIF2 signal prefixes (ddr1_*
and ddr2_*) listed in Table 4-7, EMIF Signal Descriptions, not to be confused with DDR1 and
DDR2 types of SDRAM memories.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
CAUTION
All IO Cells are NOT Fail-safe compliant and should not be externally driven in
absence of their IO supply.
5.1
Absolute Maximum Ratings
Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those listed under Section 5.4, Recommended Operating Conditions, is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Table 5-1. Absolute Maximum Rating Over Junction Temperature Range
PARAMETER(1)
VSUPPLY (Steady-State)
140
Specifications
Supply Voltage Ranges (SteadyState)
MIN
MAX
UNIT
Core (vdd, vdd_mpu, vdd_gpu,
vdd_dspeve, vdd_iva, vdd_rtc)
-0.3
1.5
V
Analog (vdda_usb1, vdda_usb2,
vdda_abe_per, vdda_ddr,
vdda_debug, vdda_dsp_eve,
vdda_gmac_core, vdda_gpu,
vdda_hdmi, vdda_iva, vdda_pcie,
vdda_pcie0, vdda_pcie1,
vdda_sata, vdda_usb3, vdda_video,
vdda_mpu, vdda_osc, vdda_rtc)
-0.3
2.0
V
Analog 3.3V (vdda33v_usb1,
vdda33v_usb2)
-0.3
3.8
V
vdds18v, vdds18v_ddr1,
vdds18v_ddr2, vdds_mlbp,
vdds_ddr1, vdds_ddr2
-0.3
2.1
V
vddshv1-11 (1.8V mode)
-0.3
2.1
V
vddshv1-7 (3.3V mode), vddshv9-11
(3.3V mode)
-0.3
3.8
V
vddshv8 (3.3V mode)
-0.3
3.6
V
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-1. Absolute Maximum Rating Over Junction Temperature Range (continued)
PARAMETER(1)
VIO (Steady-State)
Input and Output Voltage Ranges
(Steady-State)
MIN
MAX
UNIT
Core I/Os
-0.3
1.5
V
Analog I/Os (except HDMI)
-0.3
2.0
V
HDMI I/Os
-0.3
3.5
V
I/O 1.35V
-0.3
1.65
V
I/O 1.5V
-0.3
1.8
V
1.8V I/Os
-0.3
2.1
V
3.3V I/Os (except those powered by
vddshv8)
-0.3
3.8
V
3.3V I/Os (powered by vddshv8)
-0.3
SR
Maximum slew rate, all supplies
VIO (Transient Overshoot /
Undershoot)
Input and Output Voltage Ranges (Transient Overshoot/Undershoot)
Note: valid for up to 20% of the signal period.
TJ
Operating junction temperature
range
TSTG
Storage temperature range after soldered onto PC Board
Automotive
(3)
3.6
V
105
V/s
0.2*VDD
V
-40
125
°C
-55
+150
°C
(2)
Latch-up I-Test
I-test , All I/Os (if different levels then one line per level)
-100
100
mA
Latch-up OV-Test
Over-voltage Test(4), All supplies (if different levels then one line per level)
N/A
1.5*Vsup
ply max
V
(1) See I/Os supplied by this power pin in Table 4-2 Ball Characteristics.
(2) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(3) Per JEDEC JESD78 at 125°C with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O
voltage and negative 0.5 times maximum recommended I/O voltage.
(4) Per JEDEC JESD78 at 125°C.
5.2
ESD Ratings
Table 5-2 presents the Device ESD Ratings requirements.
Table 5-2. ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-Body model (HBM), per AEC Q100-002(1)
±1000
All pins
Charged-device model (CDM), per AEC
Corner pins (A1,
Q100-011
AH1, A28, AH28)
±250
UNIT
V
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3
Power on Hour (POH) Limits
The information in the section below is provided solely for your convenience and does not extend or
modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.
NOTE
POH is a functional of voltage, temperature and time. Usage at higher voltages and
temperatures will result in a reduction in POH to achieve the same reliability performance.
For assessment of alternate use cases, contact your local TI representative.
Specifications
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Table 5-3. Power on Hour (POH) Limits
IP
Duty Cycle
Voltage Domain
Voltage (V) (max)
Frequency (MHz)
(max)
Tj(°C)
POH
ARM
70%
vdd_mpu
OPP_HIGH
1500
Automotive Profile(1)
20000
30%
vdd_mpu
Retention
0
40%
vdd_mpu
OPP_HIGH
1500
Automotive Profile(1)
20000
60%
vdd_mpu
OPP_HIGH
1000
55%
vdd_mpu
OPP_HIGH
1500
Automotive Profile(1)
20000
Others(2)
45%
vdd_mpu
OPP_NOM
1000
100%
vdd_mpu
OPP_HIGH
1176
Automotive Profile(1)
20000
100%
vdd_mpu
OPP_NOM
1000
Automotive Profile(1)
20000
100%
All
Automotive Profile(1)
20000
All Support OPPs
(1) Automotive profile is defined as 20000 power on hours with junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
10%@125°C.
(2) Others covers all other IP's voltage and temperature combinations that are not specified in the table, and are constrained by other
sections of this data manual.
142
Specifications
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5.4
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Recommended Operating Conditions
The device is used under the recommended operating conditions described in Table 5-4.
NOTE
Logic functions and parameter values are not assured out of the range specified in the
recommended operating conditions.
Table 5-4. Recommended Operating Conditions
PARAMETER
DESCRIPTION
MIN (2)
NOM
MAX DC (3)
MAX (2)
UNIT
Input Power Supply Voltage Range
vdd
Core voltage domain supply
See Section 5.5
V
vdd_mpu
Supply voltage range for MPU domain
See Section 5.5
V
vdd_gpu
GPU voltage domain supply
See Section 5.5
V
vdd_dspeve
DSP-EVE voltage domain supply
See Section 5.5
V
vdd_iva
IVA voltage domain supply
See Section 5.5
V
vdd_rtc
RTC voltage domain supply
See Section 5.5
vdda_usb1
DPLL_USB and HS USB1 1.8V
analog power supply
1.71
1.80
1.71
1.80
Maximum noise (peak-peak)
vdda_usb2
HS USB2 1.8V analog power supply
HS USB1 3.3V analog power supply.If
USB1 is not used, this pin can
alternatively be connected to VSS if
the following requirements are met:
- The usb1_dm/usb1_dp pins are left
unconnected
- The USB1 PHY is kept powered
down
HS USB2 3.3V analog power supply. If
USB2 is not used, this pin can
alternatively be connected to VSS if
the following requirements are met:
- The usb2_dm/usb2_dp pins are left
unconnected
- The USB2 PHY is kept powered
down
3.135
3.3
3.135
3.3
DPLL_ABE, DPLL_PER, and PER
HSDIVIDER analog power supply
1.71
1.80
DPLL_DDR and DDR HSDIVIDER
analog power supply
1.71
1.80
DPLL_DEBUG analog power supply
1.71
1.80
vdda_dsp_eve
DPLL_DSP and DPLL_EVE analog
power supply
DPLL_CORE and CORE HSDIVIDER
analog power supply
1.71
1.80
1.71
1.80
DPLL_GPU analog power supply
Maximum noise (peak-peak)
3.366
3.465
1.836
1.89
1.836
1.89
1.836
1.89
1.71
1.80
V
mVPPmax
V
mVPPmax
V
mVPPmax
V
mVPPmax
1.836
1.89
1.836
1.89
1.836
1.89
V
mVPPmax
50
50
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_gpu
3.465
50
Maximum noise (peak-peak)
vdda_gmac_core
3.366
50
Maximum noise (peak-peak)
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_debug
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_ddr
1.89
50
Maximum noise (peak-peak)
vdda_abe_per
1.836
50
Maximum noise (peak-peak)
vdda33v_usb2
1.89
50
Maximum noise (peak-peak)
vdda33v_usb1
V
1.836
V
mVPPmax
V
mVPPmax
Specifications
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Table 5-4. Recommended Operating Conditions (continued)
PARAMETER
vdda_hdmi
DESCRIPTION
PLL_HDMI and HDMI analog power
supply
MIN (2)
NOM
MAX DC (3)
MAX (2)
UNIT
1.71
1.80
1.836
1.89
V
1.71
1.80
1.836
1.89
1.71
1.80
1.836
1.89
Maximum noise (peak-peak)
vdda_iva
DPLL_IVA analog power supply
50
Maximum noise (peak-peak)
vdda_pcie
DPLL_PCIe_REF and PCIe analog
power supply
50
Maximum noise (peak-peak)
vdda_pcie0
PCIe ch0 RX/TX analog power supply
1.71
PCIe ch1 RX/TX analog power supply
DPLL_SATA and SATA RX/TX analog
power supply
vdda_usb3
DPLL_USB_OTG_SS and USB3.0
RX/TX analog power supply
DPLL_VIDEO1 and DPLL_VIDEO2
analog power supply
1.71
1.80
MLBP IO power supply
1.71
DPLL_MPU analog power supply
vdda_osc
HFOSC analog power supply
RTC bias and RTC LFOSC analog
power supply
1.8V power supply
1.80
vdds18v_ddr1
(4)
DDR1 bias power supply
1.71
1.80
DDR1 power supply
(1.8V for DDR2 mode /
1.5V for DDR3 mode /
1.35V DDR3L mode)
Maximum noise (peakpeak)
V
V
mVPPmax
1.89
V
mVPPmax
1.836
1.89
V
mVPPmax
1.80
1.89
V
mVPPmax
1.71
1.80
1.71
1.80
1.89
50
V
mVPPmax
1.836
1.89
50
V
mVPPmax
1.80
1.836
1.89
50
V
mVPPmax
1.71
1.80
1.35-V
Mode
1.28
1.5-V Mode
1.8-V Mode
1.35-V
Mode
1.89
50
1.836
1.89
1.35
1.377
1.42
1.43
1.50
1.53
1.57
1.71
1.80
1.836
1.89
Maximum noise (peak-peak)
vdds_ddr1 (4)
1.836
50
1.71
DDR2 bias power supply
1.89
50
Maximum noise (peak-peak)
vdds18v_ddr2 (4)
1.836
50
Maximum noise (peak-peak)
V
mVPPmax
1.71
Maximum noise (peak-peak)
vdds18v
1.80
1.80
1.71
V
mVPPmax
1.71
Maximum noise (peak-peak)
vdda_rtc
1.89
50
Maximum noise (peak-peak)
V
mVPPmax
1.836
50
Maximum noise (peak-peak)
vdda_mpu
1.89
50
Maximum noise (peak-peak)
vdds_mlbp
1.89
mVPPmax
1.80
Maximum noise (peak-peak)
vdda_video
1.80
1.71
Maximum noise (peak-peak)
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_sata
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_pcie1
mVPPmax
50
V
mVPPmax
50
V
mVPPmax
1.5-V Mode
1.8-V Mode
144
Specifications
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-4. Recommended Operating Conditions (continued)
PARAMETER
vdds_ddr2 (4)
MIN (2)
NOM
MAX DC (3)
MAX (2)
UNIT
1.35-V
Mode
1.28
1.35
1.377
1.42
V
1.5-V Mode
1.43
1.50
1.53
1.57
1.8-V Mode
1.71
1.80
1.836
1.89
DESCRIPTION
DDR2 power supply
(1.8V for DDR2 mode/
1.5V for DDR3 mode /
1.35V DDR3L mode)
Maximum noise (peakpeak)
1.35-V
Mode
50
mVPPmax
1.5-V Mode
1.8-V Mode
vddshv5
vddshv1
vddshv10
vddshv11
vddshv2
vddshv3
vddshv4
Dual Voltage (1.8V or
3.3V) power supply for
the RTC Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the VIN2 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
Dual Voltage (1.8V or
1.8-V Mode
3.3V) power supply for
3.3-V Mode
the GPMC Power Group
pins
1.71
1.80
1.836
1.89
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
50
Dual Voltage (1.8V or
3.3V) power supply for
the MMC2 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the VOUT Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the GENERAL Power
Group pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the MMC4 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
Specifications
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Table 5-4. Recommended Operating Conditions (continued)
PARAMETER
vddshv6
vddshv7
vddshv8
vddshv9
DESCRIPTION
MIN (2)
NOM
MAX DC (3)
MAX (2)
UNIT
V
Dual Voltage (1.8V or
3.3V) power supply for
the VIN1 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the WIFI Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the MMC1 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the RGMII Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
50
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
vss
Ground supply
0
V
vssa_hdmi
DPLL_HDMI and HDMI PHY analog
ground
0
V
vssa_pcie
PCIe analog ground
0
V
vssa_usb
HS USB1 and HS USB2 analog
ground
0
V
vssa_usb3
DPLL_USB and USB3.0 RX/TX
analog ground
0
V
vssa_video
DPLL_VIDEO1 and DPLL_VIDEO2
analog ground
0
V
vssa_osc0
OSC0 analog ground
0
V
vssa_osc1
OSC1 analog ground
0
TJ(1)
Operating junction
temperature range
Automotive
-40
V
125
°C
Output Power Supply Voltage Range
ddr1_vref0
Reference Power Supply DDR1
0.5*vdds_ddr1
V
ddr2_vref0
Reference Power Supply DDR2
0.5*vdds_ddr2
V
(1) Refer to Power on Hours table Table 5-3 for limitations.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(4) If DDR2 type of memories are used, the EMIF power supply (vdds_ddrx) and the corresponding bias power supply (vdds18v_ddrx) must
be sourced from single power source.
5.5
Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of
each OPP (operating performance point) for processor clocks and device core clocks.
Table 5-5 describes the maximum supported frequency per speed grade for DRA75x/DRA74x devices.
146
Specifications
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-5. Speed Grade Maximum Frequency
Device Speed
Maximum frequency (MHz)
MPU
DSP
EVE
IVA
GPU
IPU
L3
DDR3/DDR3L
DDR2
DRA7xxxP
1500
700
650 (1)
532
532
212.8
266
532 (DDR3-1066)
400 (DDR2-800)
DRA7xxxL
1176
700
650 (1)
532
532
212.8
266
532 (DDR3-1066)
400 (DDR2-800)
700
(1)
532
532
212.8
266
532 (DDR3-1066)
400 (DDR2-800)
DRA7xxxJ
1000
650
(1) Applicable for DRA754, DRA755, and DRA756. Not Applicable for all other devices!
5.5.1
AVS and ABB Requirements
Adaptive Voltage Scaling (AVS) and Adaptive Body Biasing (ABB) are required on most of the vdd_*
supplies as defined in Table 5-6.
Table 5-6. AVS and ABB Requirements per vdd_* Supply
Supply
AVS Required?
vdd
Yes, for all OPPs
No
vdd_mpu
Yes, for all OPPs
Yes, for all OPPs
vdd_iva
Yes, for all OPPs
Yes, for all OPPs
vdd_dspeve
Yes, for all OPPs
Yes, for all OPPs
vdd_gpu
Yes, for all OPPs
Yes, for all OPPs
vdd_rtc
No
No
5.5.2
ABB Required?
Voltage And Core Clock Specifications
Table 5-7 shows the recommended OPP per voltage domain.
Table 5-7. Voltage Domains Operating Performance Points
DOMAIN
CONDITION
OPP_NOM
MIN
(2)
VD_CORE (V)
BOOT (Before AVS is
enabled) (4)
After AVS is enabled (4)
VD_MPU (V)
BOOT (Before AVS is
enabled) (4)
After AVS is enabled (4)
VD_RTC (V)
Others (V)
(6)
1.11
1.15
AVS
AVS
Voltag Voltage
(5)
e (5) –
3.5%
1.11
OPP_OD
NOM (1) MAX (2)
1.15
AVS
AVS
Voltag Voltage
(5)
e (5) –
3.5%
MIN (2)
NOM (1) MAX (2)
OPP_HIGH
MIN (2)
NOM (1) MAX DC
(3)
1.2
Not Applicable
Not Applicable
1.16
Not Applicable
Not Applicable
1.2
Not Applicable
Not Applicable
1.16
AVS
AVS
AVS
AVS
AVS
AVS
Voltage Voltage Voltage Voltage Voltage Voltage
(5)
(5)
(5) –
(5) +
(5) –
(5) +2%
3.5%
5%
3.5%
-
0.84
0.88 to
1.06
1.16
Not Applicable
Not Applicable
BOOT (Before AVS is
enabled) (4)
1.02
1.06
1.16
Not Applicable
Not Applicable
After AVS is enabled (4)
AVS
AVS
Voltag Voltage
(5)
e (5) –
3.5%
1.16
AVS
AVS
AVS
AVS
AVS
AVS
Voltage Voltage Voltage Voltage Voltage Voltage
(5)
(5)
(5) –
(5) +
(5) –
(5) +2%
3.5%
5%
3.5%
MAX (2)
AVS
Voltage
(5) +
5%
AVS
Voltage
(5) +
5%
(1) In a typical implementation, the power supply should target the NOM voltage.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(4) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
Specifications
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(5) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the TRM. The
power supply should be adjustable over the following ranges for each required OPP:
– OPP_NOM for MPU: 0.85V – 1.15V
– OPP_NOM for CORE and Others: 0.85V - 1.15V
– OPP_OD: 0.885V - 1.15V
– OPP_HIGH: 0.95V - 1.25V
The AVS Voltages will be within the above specified ranges.
(6) VD_RTC can optionally be tied to VD_CORE and operate at the VD_CORE AVS voltages.
(7) The power supply must be programmed with the AVS voltages for the MPU and the CORE voltage domain, either just after the ROM
boot or at the earliest possible time in the secondary boot loader before there is significant activity seen on these domains.
Table 5-8 describes the standard processor clocks speed characteristics vs OPP of the device.
Table 5-8. Supported OPP vs Max Frequency (2)
DESCRIPTION
OPP_NOM
OPP_OD
OPP_HIGH
Max Freq. (MHz)
Max Freq. (MHz)
Max Freq. (MHz)
1000
1176
1500
DSP_CLK
600
700
700
EVE_FCLK
535
650
650
IVA_GCLK
388.3
430
532
GPU_CLK
425.6
500
532
CORE_IPUx_CLK
212.8
N/A
N/A
L3_CLK
266
N/A
N/A
DDR2
400 (DDR2-800)
N/A
N/A
DDR3 / DDR3L
532 (DDR3-1066)
N/A
N/A
RTC_FCLK
0.034
N/A
N/A
VD_MPU
MPU_CLK
VD_DSPEVE
VD_IVA
VD_GPU
VD_CORE
VD_RTC
(1) N/A in this table stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Device Speed Grade (see Table 5-5).
5.5.3
Maximum Supported Frequency
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM. Table 5-9 lists the clock source options for each module on this device, along with the maximum
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers
must be programmed not to exceed the maximum frequencies listed in this table.
Table 5-9. Maximum Supported Frequency
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
AES1
AES1_L3_CLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
AES2
AES2_L3_CLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
148
Specifications
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
ATL
ATL_ICLK_L3
Int
266
ATL_L3_GICLK
CORE_X2_CLK
DPLL_CORE
ATLPCLK
Func
266
ATL_GFCLK
CORE_X2_CLK
DPLL_CORE
PER_ABE_X1_GF
CLK
DPLL_ABE
FUNC_32K_CLK
OSC1
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
RTC Oscillator
HDMI_CLK
DPLL_HDMI
BB2D_GFCLK
DPLL_CORE
266
DSS_L3_GICLK
CORE_X2_CLK
DPLL_CORE
0.032
FUNC_32K_CLK
SYS_32K
RTC Oscillator
BB2D_FCLK
BB2D_ICLK
Int
COUNTER_32K
COUNTER_32K_F
CLK
Func
COUNTER_32K_IC
LK
Int
38.4
WKUPAON_GICLK
CTRL_MODULE_B
ANDGAP
L3INSTR_TS_GCL
K
Int
CTRL_MODULE_C
ORE
L4CFG_L4_GICLK
Int
133
CTRL_MODULE_
WKUP
WKUPAON_GICLK
Int
38.4
DCAN1
DCAN1_FCLK
DCAN1_ICLK
DCAN2
Func
BB2D_GFCLK
BB2D
Func
Int
354.6
4.8
38.4
266
L3INSTR_TS_GCLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
L4CFG_L4_GICLK
CORE_X2_CLK
DPLL_CORE
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
SYS_CLK2
OSC2
DCAN1_SYS_CLK
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
DCAN2_FCLK
Func
38.4
DCAN2_SYS_CLK
SYS_CLK1
OSC1
DCAN2_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DES3DES
DES_CLK_L3
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DLL
EMIF_DLL_FCLK
Func
EMIF_DLL_FC
LK
EMIF_DLL_GCLK
EMIF_DLL_GCLK
DPLL_DDR
DLL_AGING
FCLK
Int
38.4
L3INSTR_DLL_AGING
_GCLK
DMA_CRYPTO
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
DMA_CRYPTO_FC
LK
Int &
Func
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DMA_CRYPTO_IC
LK
Int
133
L4SEC_L4_GICLK
CORE_X2_CLK
DPLL_CORE
DMM
DMM_CLK
Int
266
EMIF_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DPLL_DEBUG
SYSCLK
Int
38.4
EMU_SYS_CLK
SYS_CLK1
OSC1
DSP1
DSP1_FICLK
Int &
Func
DSP_CLK
DSP1_GFCLK
DSP_GFCLK
DPLL_DSP
DSP2
DSP2_FICLK
Int &
Func
DSP_CLK
DSP2_GFCLK
DSP_GFCLK
DPLL_DSP
Specifications
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Table 5-9. Maximum Supported Frequency (continued)
Module
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
DSS_HDMI_CEC_
CLK
Func
0.032
HDMI_CEC_GFCLK
SYS_32K
RTC Oscillator
DSS_HDMI_PHY_
CLK
Func
48
HDMI_PHY_GFCLK
FUNC_192M_CLK
DPLL_PER
DSS_CLK
Func
192
DSS_GFCLK
DSS_CLK
DPLL_PER
HDMI_CLKINP
Func
38.4
HDMI_DPLL_CLK
SYS_CLK1
OSC1
Instance Name
Input Clock Name
DSS
SYS_CLK2
OSC2
DSS_L3_ICLK
Int
266
DSS_L3_GICLK
CORE_X2_CLK
DPLL_CORE
VIDEO1_CLKINP
Func
38.4
VIDEO1_DPLL_CLK
SYS_CLK1
OSC1
SYS_CLK2
OSC2
SYS_CLK1
OSC1
SYS_CLK2
OSC2
VIDEO2_CLKINP
Func
DPLL_DSI1_A_CL
K1
Func
DPLL_DSI1_B_CL
K1
Func
DPLL_DSI1_C_CL
K1
DSS DISPC
Clock Sources
Func
38.4
209.3
209.3
209.3
VIDEO2_DPLL_CLK
N/A
N/A
N/A
HDMI_CLK
DPLL_HDMI
VIDEO1_CLKOUT1
DPLL_VIDEO1
VIDEO1_CLKOUT3
DPLL_VIDEO1
VIDEO2_CLKOUT3
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
DPLL_ABE_X2_CL
K
DPLL_ABE
HDMI_CLK
DPLL_HDMI
VIDEO1_CLKOUT3
DPLL_VIDEO1
VIDEO2_CLKOUT1
DPLL_VIDEO2
DPLL_HDMI_CLK1
Func
185.6
N/A
HDMI_CLK
DPLL_HDMI
LCD1_CLK
Func
209.3
N/A
DPLL_DSI1_A_CL
K1
See DSS data in
the rows above
LCD2_CLK
Func
209.3
N/A
DPLL_DSI1_B_CL
K1
DSS_CLK
DSS_CLK
LCD3_CLK
Func
209.3
N/A
DPLL_DSI1_C_CL
K1
DSS_CLK
F_CLK
Func
209.3
N/A
DPLL_DSI1_A_CL
K1
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_HDMI_CLK1
EFUSE_CTRL_CU
ST
ocp_clk
Int
133
CUSTEFUSE_L4_GICL
K
CORE_X2_CLK
DPLL_CORE
sys_clk
Func
38.4
CUSTEFUSE_SYS_GF
CLK
SYS_CLK1
OSC1
ELM
ELM_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
EMIF_OCP_FW
L3_CLK
Int
266
EMIF_L3_GICLK
CORE_X2_CLK
DPLL_CORE
EMIF_PHY1
EMIF_PHY1_FCLK
Func
DDR
EMIF_PHY_GCLK
EMIF_PHY_GCLK
DPLL_DDR
EMIF_PHY2
EMIF_PHY2_FCLK
Func
DDR
EMIF_PHY_GCLK
EMIF_PHY_GCLK
DPLL_DDR
150
Specifications
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
EMIF1
EMIF1_ICLK
Int
266
EMIF_L3_GICLK
CORE_X2_CLK
DPLL_CORE
EMIF2
EMIF2_ICLK
Int
266
EMIF_L3_GICLK
CORE_X2_CLK
DPLL_CORE
EVE1
EVE1_FCLK
Func
EVE_FCLK
EVE1_GFCLK
-
DPLL_DSP
EVE_GFCLK
DPLL_EVE
DPLL_DSP
EVE2
EVE2_FCLK
Func
EVE_FCLK
EVE2_GFCLK
EVE_GFCLK
DPLL_EVE
FPKA
PKA_CLK
Int &
Func
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GMAC_SW
CPTS_RFT_CLK
Func
266
GMAC_RFT_CLK
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
GPIO1
GPIO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
MAIN_CLK
Int
125
GMAC_MAIN_CLK
GMAC_250M_CLK
DPLL_GMAC
MHZ_250_CLK
Func
250
GMII_250MHZ_CLK
GMII_250MHZ_CL
K
DPLL_GMAC
MHZ_5_CLK
Func
5
RGMII_5MHZ_CLK
GMAC_RMII_HS_C
LK
DPLL_GMAC
MHZ_50_CLK
Func
50
RMII_50MHZ_CLK
GMAC_RMII_HS_C
LK
DPLL_GMAC
RMII1_MHZ_50_CL
K
Func
50
RMII_50MHZ_CLK
GMAC_RMII_HS_C
LK
DPLL_GMAC
RMII2_MHZ_50_CL
K
Func
50
RMII_50MHZ_CLK
GMAC_RMII_HS_C
LK
DPLL_GMAC
GPIO1_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
OSC1
GPIO1_DBCLK
Func
0.032
WKUPAON_SYS_GFC
LK
WKUPAON_32K_G
FCLK
GPIO2_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
GPIO2_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
RTC Oscillator
DPLL_CORE
OSC1
RTC Oscillator
GPIO3
GPIO3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
GPIO3_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
DPLL_CORE
OSC1
RTC Oscillator
GPIO4
GPIO5
GPIO6
GPIO4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
GPIO4_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
PIDBCLK
Func
0.032
GPIO_GFCLK
DPLL_CORE
OSC1
RTC Oscillator
GPIO5_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
GPIO5_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
PIDBCLK
Func
0.032
GPIO_GFCLK
GPIO6_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
GPIO6_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
PIDBCLK
Func
0.032
GPIO_GFCLK
DPLL_CORE
OSC1
RTC Oscillator
DPLL_CORE
OSC1
RTC Oscillator
Specifications
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
GPIO7
GPIO7_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GPIO7_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
PIDBCLK
Func
0.032
GPIO_GFCLK
GPIO8
OSC1
RTC Oscillator
GPIO8_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GPIO8_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
OSC1
PIDBCLK
Func
0.032
GPIO_GFCLK
GPMC
GPMC_FCLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GPU
GPU_FCLK1
Func
GPU_CLK
GPU_CORE_GCLK
CORE_GPU_CLK
DPLL_CORE
GPU_FCLK2
Func
GPU_CLK
GPU_HYD_GCLK
RTC Oscillator
PER_GPU_CLK
DPLL_PER
GPU_GCLK
DPLL_GPU
CORE_GPU_CLK
DPLL_CORE
PER_GPU_CLK
DPLL_PER
GPU_GCLK
DPLL_GPU
GPU_ICLK
Int
266
GPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
HDMI PHY
DSS_HDMI_PHY_
CLK
Func
38.4
HDMI_PHY_GFCLK
FUNC_192M_CLK
DPLL_PER
HDQ1W
HDQ1W_ICLK
Int &
Func
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
HDQ1W_FCLK
Func
12
PER_12M_GFCLK
FUNC_192M_CLK
DPLL_PER
I2C1_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
I2C1_FCLK
Func
96
PER_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
I2C2_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
I2C2_FCLK
Func
96
PER_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
I2C3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
I2C3_FCLK
Func
96
PER_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
DPLL_CORE
I2C1
I2C2
I2C3
I2C4
I2C5
I2C4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
I2C4_FCLK
Func
96
PER_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
I2C5_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
I2C5_FCLK
Func
96
IPU_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
IEEE1500_2_OCP
PI_L3CLK
Int &
Func
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
IPU1
IPU1_GFCLK
Int &
Func
425.6
IPU1_GFCLK
DPLL_ABE_X2_CL
K
DPLL_ABE
CORE_IPU_ISS_B
OOST_CLK
DPLL_CORE
CORE_IPU_ISS_B
OOST_CLK
DPLL_CORE
IPU2
152
IPU2_GFCLK
Int &
Func
425.6
IPU2_GFCLK
IVA
IVA_GCLK
Int
IVA_GCLK
IVA_GCLK
IVA_GFCLK
DPLL_IVA
KBD
KBD_FCLK
Func
0.032
WKUPAON_SYS_GFC
LK
WKUPAON_32K_G
FCLK
OSC1
PICLKKBD
Func
0.032
WKUPAON_SYS_GFC
LK
KBD_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
PICLKOCP
Int
38.4
WKUPAON_GICLK
DPLL_ABE_X2_CL
K
DPLL_ABE
L3_INSTR
L3_CLK
Int
L3_CLK
L3INSTR_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L3_MAIN
L3_CLK1
Int
L3_CLK
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L3_CLK2
Int
L3_CLK
L3INSTR_L3_GICLK
CORE_X2_CLK
DPLL_CORE
Specifications
RTC Oscillator
Copyright © 2015–2016, Texas Instruments Incorporated
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
L4_CFG
L4_CFG_CLK
Int
133
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L4_PER1
L4_PER1_CLK
Int
133
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L4_PER2
L4_PER2_CLK
Int
133
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L4_PER3
L4_PER3_CLK
Int
133
L4PER3_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L4_WKUP
L4_WKUP_CLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
MAILBOX1
MAILBOX1_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX2
MAILBOX2_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX3
MAILBOX3_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX4
MAILBOX4_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX5
MAILBOX5_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX6
MAILBOX6_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX7
MAILBOX7_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX8
MAILBOX8_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX9
MAILBOX9_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX10
MAILBOX10_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX11
MAILBOX11_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX12
MAILBOX12_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX13
MAILBOX13_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
Specifications
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
MCASP1
MCASP1_AHCLKR
Func
100
MCASP1_AHCLKR
MCASP1_AHCLKX
MCASP1_FCLK
MCASP1_ICLK
154
Specifications
Func
Func
Int
100
192
266
MCASP1_AHCLKX
MCASP1_AUX_GFCLK
IPU_L3_GICLK
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATLCLK0
Module ATL
ATLCLK1
Module ATL
ATLCLK2
Module ATL
ATLCLK3
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATLCLK0
Module ATL
ATLCLK1
Module ATL
ATLCLK2
Module ATL
ATLCLK3
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
Copyright © 2015–2016, Texas Instruments Incorporated
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Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
MCASP2
MCASP2_AHCLKR
Func
100
MCASP2_AHCLKR
MCASP2_AHCLKX
MCASP2_FCLK
MCASP2_ICLK
Func
Func
Int
100
192
266
MCASP2_AHCLKX
MCASP2_AUX_GFCLK
L4PER2_L3_GICLK
PLL / OSC /
Source Clock
Name
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
Specifications
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Copyright © 2015–2016, Texas Instruments Incorporated
155
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
MCASP3
MCASP3_AHCLKX
Func
100
MCASP3_AHCLKX
MCASP3_FCLK
MCASP4
MCASP3_AUX_GFCLK
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_ABE
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MCASP4_AHCLKX
Func
100
MCASP4_AHCLKX
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MCASP4_ICLK
Specifications
192
PLL / OSC /
Source Name
MCASP3_ICLK
MCASP4_FCLK
156
Func
PLL / OSC /
Source Clock
Name
Func
Int
192
266
MCASP4_AUX_GFCLK
L4PER2_L3_GICLK
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_ABE
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
Copyright © 2015–2016, Texas Instruments Incorporated
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Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
MCASP5
MCASP5_AHCLKX
Func
100
MCASP5_AHCLKX
MCASP5_FCLK
MCASP6
Func
192
MCASP5_AUX_GFCLK
PLL / OSC /
Source Clock
Name
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_ABE
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
MCASP5_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MCASP6_AHCLKX
Func
100
MCASP6_AHCLKX
DPLL_ABE_X2_CL
K
DPLL_ABE
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
MCASP6_FCLK
MCASP6_ICLK
Func
Int
192
266
MCASP6_AUX_GFCLK
L4PER2_L3_GICLK
ATL_CLK0
Module ATL
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
SYS_CLK1
OSC1
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_ABE
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
Specifications
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Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
Copyright © 2015–2016, Texas Instruments Incorporated
157
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
MCASP7
MCASP7_AHCLKX
Func
100
MCASP7_AHCLKX
MCASP7_FCLK
MCASP8
Specifications
MCASP7_AUX_GFCLK
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_ABE
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MCASP8_AHCLKX
Func
100
MCASP8_AHCLKX
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MCASP8_ICLK
158
192
PLL / OSC /
Source Name
MCASP7_ICLK
MCASP8_FCLK
MCSPI1
Func
PLL / OSC /
Source Clock
Name
Func
192
Int
266
SPI1_ICLK
Int
266
SPI1_FCLK
Func
48
MCASP8_AUX_GFCLK
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_ABE
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
PER_48M_GFCLK
PER_48M_GFCLK
DPLL_PER
L4PER2_L3_GICLK
Copyright © 2015–2016, Texas Instruments Incorporated
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Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
MCSPI2
SPI2_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SPI2_FCLK
Func
48
PER_48M_GFCLK
PER_48M_GFCLK
DPLL_PER
SPI3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MCSPI3
SPI3_FCLK
Func
48
PER_48M_GFCLK
PER_48M_GFCLK
DPLL_PER
MCSPI4
SPI4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SPI4_FCLK
Func
48
PER_48M_GFCLK
PER_48M_GFCLK
DPLL_PER
MLB_SS
MLB_L3_ICLK
Int
266
MLB_SHB_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MLB_L4_ICLK
Int
133
MLB_SPB_L4_GICLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
MMC1
MLB_FCLK
Func
266
MLB_SYS_L3_GFCLK
CORE_X2_CLK
MMC1_CLK_32K
Func
0.032
L3INIT_32K_GFCLK
FUNC_32K_CLK
OSC1
MMC1_FCLK
Func
192
MMC1_GFCLK
FUNC_192M_CLK
DPLL_PER
MMC1_ICLK1
Int
128
MMC2
266
L3INIT_L3_GICLK
DPLL_PER
CORE_X2_CLK
DPLL_CORE
MMC1_ICLK2
Int
133
L3INIT_L4_GICLK
CORE_X2_CLK
DPLL_CORE
MMC2_CLK_32K
Func
0.032
L3INIT_32K_GFCLK
FUNC_32K_CLK
OSC1
MMC2_FCLK
Func
192
MMC2_GFCLK
FUNC_192M_CLK
DPLL_PER
128
MMC3
FUNC_256M_CLK
FUNC_256M_CLK
DPLL_PER
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MMC2_ICLK1
Int
266
MMC2_ICLK2
Int
133
L3INIT_L4_GICLK
CORE_X2_CLK
DPLL_CORE
MMC3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MMC3_CLK_32K
Func
0.032
L4PER_32K_GFCLK
FUNC_32K_CLK
OSC1
MMC3_FCLK
Func
48
MMC3_GFCLK
FUNC_192M_CLK
DPLL_PER
192
MMC4
MMC4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MMC4_CLK_32K
Func
0.032
L4PER_32K_GFCLK
FUNC_32K_CLK
OSC1
MMC4_FCLK
Func
48
MMC4_GFCLK
FUNC_192M_CLK
DPLL_PER
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
192
MMU_EDMA
MMU1_CLK
Int
MMU_PCIESS
MMU2_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MPU
MPU_CLK
Int &
Func
MPU_CLK
MPU_GCLK
MPU_GCLK
DPLL_MPU
MPU_EMU_DBG
FCLK
Int
38.4
EMU_SYS_CLK
SYS_CLK1
OSC1
MPU_GCLK
DPLL_MPU
OCMC_RAM1
OCMC1_L3_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
OCMC_RAM2
OCMC2_L3_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
OCMC_RAM3
OCMC3_L3_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
OCMC_ROM
OCMC_L3_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
OCP_WP_NOC
PICLKOCPL3
Int
266
L3INSTR_L3_GICLK
CORE_X2_CLK
DPLL_CORE
OCP2SCP1
L4CFG1_ADAPTE
R_CLKIN
Int
133
L3INIT_L4_GICLK
CORE_X2_CLK
DPLL_CORE
OCP2SCP2
L4CFG2_ADAPTE
R_CLKIN
Int
133
L4CFG_L4_GICLK
CORE_X2_CLK
DPLL_CORE
OCP2SCP3
L4CFG3_ADAPTE
R_CLKIN
Int
133
L3INIT_L4_GICLK
CORE_X2_CLK
DPLL_CORE
Specifications
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
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Table 5-9. Maximum Supported Frequency (continued)
Module
Instance Name
Input Clock Name
PCIESS1
PCIE1_PHY_WKU
P_CLK
PCIESS2
PRCM_MPU
Clock Sources
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
Func
0.032
PCIE_32K_GFCLK
FUNC_32K_CLK
RTC Oscillator
PCIe_SS1_FICLK
Int
266
PCIE_L3_GICLK
CORE_X2_CLK
DPLL_CORE
PCIEPHY_CLK
Func
2500
PCIE_PHY_GCLK
PCIE_PHY_GCLK
APLL_PCIE
PCIEPHY_CLK_DI
V
Func
1250
PCIE_PHY_DIV_GCLK
PCIE_PHY_DIV_G
CLK
APLL_PCIE
PCIE1_REF_CLKI
N
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
PCIE1_PWR_CLK
Func
38.4
PCIE_SYS_GFCLK
SYS_CLK1
OSC1
PCIE2_PHY_WKU
P_CLK
Func
0.032
PCIE_32K_GFCLK
FUNC_32K_CLK
RTC Oscillator
PCIe_SS2_FICLK
Func
266
PCIE_L3_GICLK
CORE_X2_CLK
DPLL_CORE
PCIEPHY_CLK
Func
2500
PCIE_PHY_GCLK
PCIE_PHY_GCLK
APLL_PCIE
PCIEPHY_CLK_DI
V
Func
1250
PCIE_PHY_DIV_GCLK
PCIE_PHY_DIV_G
CLK
APLL_PCIE
PCIE2_REF_CLKI
N
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
PCIE2_PWR_CLK
Func
38.4
PCIE_SYS_GFCLK
SYS_CLK1
OSC1
32K_CLK
Func
0.032
FUNC_32K_CLK
SYS_32K
RTC Oscillator
SYS_CLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
PWMSS1
PWMSS1_GICLK
Int &
Func
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
PWMSS2
PWMSS2_GICLK
Int &
Func
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
PWMSS3
PWMSS3_GICLK
Int &
Func
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
QSPI
QSPI_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
QSPI_FCLK
Func
128
QSPI_GFCLK
FUNC_256M_CLK
DPLL_PER
PER_QSPI_CLK
DPLL_PER
RNG
RNG_ICLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
RTC_SS
RTC_ICLK
Int
133
RTC_L4_GICLK
CORE_X2_CLK
DPLL_CORE
RTC_FCLK
Func
RTC_FCLK
RTC_AUX_CLK
FUNC_32K_CLK
RTC Oscillator
SAR_ROM
PRCM_ROM_CLO
CK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SATA
SATA_FICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SATA_PMALIVE_F
CLK
Func
48
L3INIT_48M_GFCLK
FUNC_192M_CLK
DPLL_PER
REF_CLK
Func
38
SATA_REF_GFCLK
SYS_CLK1
OSC1
SDMA
SDMA_FCLK
Int &
Func
266
DMA_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SHA2MD51
SHAM_1_CLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SHA2MD52
SHAM_2_CLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SL2
IVA_GCLK
Int
IVA_GCLK
IVA_GCLK
IVA_GFCLK
DPLL_IVA
SMARTREFLEX_C
ORE
MCLK
Int
133
COREAON_L4_GICLK
CORE_X2_CLK
DPLL_CORE
SYSCLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
160
Specifications
Copyright © 2015–2016, Texas Instruments Incorporated
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DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
SMARTREFLEX_D
SPEVE
MCLK
Int
133
COREAON_L4_GICLK
CORE_X2_CLK
DPLL_CORE
SYSCLK
Func
38.4
WKUPAON_ICLK
SMARTREFLEX_G
PU
SMARTREFLEX_IV
AHD
SMARTREFLEX_M
PU
MCLK
Int
133
COREAON_L4_GICLK
SYSCLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
DPLL_CORE
MCLK
Int
133
COREAON_L4_GICLK
CORE_X2_CLK
SYSCLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
DPLL_CORE
MCLK
Int
133
COREAON_L4_GICLK
CORE_X2_CLK
SYSCLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
DPLL_CORE
SPINLOCK
SPINLOCK_ICLK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
TIMER1
TIMER1_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
TIMER1_FCLK
Func
100
TIMER1_GFCLK
RTC Oscillator
TIMER2
TIMER2_ICLK
Int
266
L4PER_L3_GICLK
TIMER2_FCLK
Func
100
TIMER2_GFCLK
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
Specifications
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Copyright © 2015–2016, Texas Instruments Incorporated
161
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER3
TIMER3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER3_FCLK
Func
100
TIMER3_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER4
TIMER4_ICLK
Int
266
L4PER_L3_GICLK
TIMER4_FCLK
Func
100
TIMER4_GFCLK
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER5
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
TIMER5_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER5_FCLK
Func
100
TIMER5_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
162
Specifications
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
Copyright © 2015–2016, Texas Instruments Incorporated
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Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER6
TIMER6_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER6_FCLK
Func
100
TIMER6_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER7
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
TIMER7_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER7_FCLK
Func
100
TIMER7_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER8
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
TIMER8_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER8_FCLK
Func
100
TIMER8_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
Specifications
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Copyright © 2015–2016, Texas Instruments Incorporated
163
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER9
TIMER9_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER9_FCLK
Func
100
TIMER9_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER10
TIMER10_ICLK
Int
266
L4PER_L3_GICLK
TIMER10_FCLK
Func
100
TIMER10_GFCLK
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER11
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
TIMER11_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER11_FCLK
Func
100
TIMER11_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER12
TIMER12_ICLK
TIMER12_FCLK
164
Specifications
Int
Func
38.4
0.032
WKUPAON_GICLK
OSC_32K_CLK
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
RC_CLK
RC oscillator
Copyright © 2015–2016, Texas Instruments Incorporated
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Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER13
TIMER13_ICLK
Int
266
L4PER3_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER13_FCLK
Func
100
TIMER13_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER14
TIMER14_ICLK
Int
266
L4PER3_L3_GICLK
TIMER14_FCLK
Func
100
TIMER14_GFCLK
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER15
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
TIMER15_ICLK
Int
266
L4PER3_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER15_FCLK
Func
100
TIMER15_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
Specifications
Submit Documentation Feedback
Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
Copyright © 2015–2016, Texas Instruments Incorporated
165
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
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Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER16
TIMER16_ICLK
Int
266
L4PER3_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER16_FCLK
Func
100
TIMER16_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
VIDEO2_CLK
DPLL_VIDEO2
HDMI_CLK
DPLL_HDMI
TPCC
TPCC_GCLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TPTC1
TPTC0_GCLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TPTC2
TPTC1_GCLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART1
UART1_FCLK
Func
48
UART1_GFCLK
FUNC_192M_CLK
DPLL_PER
UART1_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART2
UART2_FCLK
Func
48
UART2_GFCLK
FUNC_192M_CLK
DPLL_PER
UART2_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART3
UART3_FCLK
Func
48
UART3_GFCLK
FUNC_192M_CLK
DPLL_PER
UART3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART4
UART4_FCLK
Func
48
UART4_GFCLK
FUNC_192M_CLK
DPLL_PER
UART4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART5_FCLK
Func
48
UART5_GFCLK
FUNC_192M_CLK
DPLL_PER
UART5_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART6
UART6_FCLK
Func
48
UART6_GFCLK
FUNC_192M_CLK
DPLL_PER
UART6_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART7
UART7_FCLK
Func
48
UART7_GFCLK
FUNC_192M_CLK
DPLL_PER
UART7_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART8
UART8_FCLK
Func
48
UART8_GFCLK
FUNC_192M_CLK
DPLL_PER
UART8_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART9
UART9_FCLK
Func
48
UART9_GFCLK
FUNC_192M_CLK
DPLL_PER
UART9_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART10_FCLK
Func
48
UART10_GFCLK
FUNC_192M_CLK
DPLL_PER
UART10_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
UART5
UART10
USB1
166
SYS_CLK2
Specifications
USB1_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
USB3PHY_REF_C
LK
Func
34.3
USB_LFPS_TX_GFCL
K
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
USB2PHY1_TREF
_CLK
Func
38.4
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC1
USB2PHY1_REF_
CLK
Func
960
L3INIT_960M_GFCLK
L3INIT_960_GFCL
K
DPLL_USB
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Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
USB2
USB2_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
USB2PHY2_TREF
_CLK
Func
38.4
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC1
USB2PHY2_REF_
CLK
Func
960
L3INIT_960M_GFCLK
L3INIT_960_GFCL
K
DPLL_USB
USB3
USB3_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
USB3PHY_PWRS_
CLK
Func
38.4
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC1
USB4_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DPLL_USBSS_RE
F_CLK
Func
38.4
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC1
USB_PHY1_CORE USB2PHY1_WKUP
_CLK
Func
0.032
COREAON_32K_GFCL
K
SYS_32K
RTC Oscillator
USB_PHY2_CORE USB2PHY2_WKUP
_CLK
Func
0.032
COREAON_32K_GFCL
K
SYS_32K
RTC Oscillator
USB_PHY3_CORE USB3PHY_WKUP_
CLK
Func
0.032
COREAON_32K_GFCL
K
SYS_32K
RTC Oscillator
USB4
VCP1
VCP1_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
VCP2
VCP2_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
VIP1
L3_CLK_PROC_CL
K
Int &
Func
266
VIP1_GCLK
L3_CLK_PROC_CL
K
Int &
Func
266
L3_CLK_PROC_CL
K
Int &
Func
266
VPE
L3_CLK_PROC_CL
K
Int &
Func
300
VPE_GCLK
WD_TIMER1
PIOCPCLK
Int
38.4
WKUPAON_GICLK
VIP2
VIP3
WD_TIMER2
VIP3_GCLK
DPLL_CORE
DPLL_CORE
CORE_X2_CLK
DPLL_CORE
CORE_ISS_MAIN_
CLK
DPLL_CORE
CORE_X2_CLK
DPLL_CORE
CORE_ISS_MAIN_
CLK
DPLL_CORE
CORE_ISS_MAIN_
CLK
DPLL_CORE
VIDEO1_CLKOUT4
DPLL_VIDEO1
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
RC oscillator
PITIMERCLK
Func
0.032
OSC_32K_CLK
RC_CLK
WD_TIMER2_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
WKUPAON_32K_G
FCLK
RTC Oscillator
WD_TIMER2_FCL
K
5.6
VIP2_GCLK
CORE_X2_CLK
CORE_ISS_MAIN_
CLK
Func
0.032
WKUPAON_SYS_GFC
LK
Power Consumption Summary
NOTE
Maximum power consumption for this SoC depends on the specific use conditions for the
end system. Contact your TI representative for assistance in estimating maximum power
consumption for the end system use case.
5.7
Electrical Characteristics
Specifications
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NOTE
The data specified in Section 5.7.1 through Section 5.7.14 are subject to change.
NOTE
The interfaces or signals described in Section 5.7.1 through Section 5.7.14 correspond to the
interfaces or signals available in multiplexing mode 0 (Function 1).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which
case different DC electrical characteristics are specified for the different multiplexing modes
(Functions).
5.7.1
LVCMOS DDR DC Electrical Characteristics
Table 5-10 summarizes the DC electrical characteristics for LVCMOS DDR Buffers.
NOTE
For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control
Module of the Device TRM.
168
Specifications
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Table 5-10. LVCMOS DDR DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[0], ddr1_cke,
ddr1_odt[0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc, ddr2_d[31:0], ddr2_a[15:0], ddr2_dqm[3:0],
ddr2_ba[2:0], ddr2_csn[0], ddr2_cke, ddr2_odt[0], ddr2_casn, ddr2_rasn, ddr2_wen, ddr2_rst;
Balls: AA28 / AA25 / AA26 / Y24 / AA24 / Y23 / Y22 / AA23 / Y20 / AB27 / Y19 / AC27 / AC28 / AB28 / W20 / V20 / AD25 / AC24 / AC25 /
AE26 / AF28 / AG27 / AF27 / AC23 / AE23 / AF23 / AE24 / AF24 / AH26 / AG26 / AF26 / AF25 / AD18 / AE17 / AF18 / AC21 / AD22 /
AD21 / AE22 / AF22 / AE21 / AE21 / AH22 / AF21 / AB19 / AC20 / AC19 / AD20 / AA27 / AC26 / AB23 / AD23 / AB18 / AE18 / AF17 /
AH23 / AG22 / AE20 / AC18 / AF20 / AH21 / AG21 / Y26 / V25 / V24 / Y25 / W23 / W19 / V23 / W22 / V26 / M26 / M25 / M24 / M23 / L28 /
L25 / L26 / L27 / J20 / K22 / J23 / L24 / L23 / K21 / K20 / L22 / J24 / J26 / J25 / G26 / H26 / H24 / H25 / H23 / E28 / E27 / F27 / F26 / F24 /
F25 / G25 / E26 / U22 / R22 / T22 / N28 / P26 / N23 / N27 / P27 / N20 / P25 / P22 / P23 / R27 / R28 / R26 / R25 / M22 / K23 / G24 / F28 /
U26 / U27 / U23 / P24 / U24 / R23 / U28 / T23 / U25 / R24;
Driver Mode
VOH
High-level output threshold (IOH = 0.1 mA)
VOL
Low-level output threshold (IOL = 0.1 mA)
CPAD
Pad capacitance (including package capacitance)
ZO
Output impedance (drive
strength)
0.9*VDDS
V
l[2:0] = 000
(Imp80)
80
l[2:0] = 001
(Imp60)
60
l[2:0] = 010
(Imp48)
48
l[2:0] = 011
(Imp40)
40
l[2:0] = 100
(Imp34)
34
0.1*VDDS
V
3
pF
Ω
Single-Ended Receiver Mode
VIH
High-level input threshold
DDR3/DDR3L
VREF+0.1
VDDS+0.2
DDR2
VREF+0.125
VDDS+0.3
DDR3/DDR3L
-0.2
VREF-0.1
-0.3
VREF-0.125
VREF 10%vdds
VREF+
10%vdds
V
3
pF
VIL
Low-level input threshold
VCM
Input common-mode voltage
CPAD
Pad capacitance (including package capacitance)
DDR2
V
V
Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr2_dqs[3:0], ddr2_dqsn[3:0],
ddr2_ck, ddr2_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc
Bottom Balls: Y28 / AD27 / AE27 / AH25 / Y27 / AD28 / AE28 / AG25 / AG24 / AH24 / M28 / K27 / H27 / G28 / M27 / K28 / H28 / G27 /
T28 / T27 / V27 / V28
Driver Mode
VOH
High-level output threshold (IOH = 0.1 mA)
VOL
Low-level output threshold (IOL = 0.1 mA)
CPAD
Pad capacitance (including package capacitance)
ZO
Output impedance (drive
strength)
0.9*VDDS
V
l[2:0] = 000
(Imp80)
80
l[2:0] = 001
(Imp60)
60
l[2:0] = 010
(Imp48)
48
l[2:0] = 011
(Imp40)
40
l[2:0] = 100
(Imp34)
34
0.1*VDDS
V
3
pF
Ω
Single-Ended Receiver Mode
VIH
High-level input threshold
DDR3/DDR3L
VREF+0.1
VDDS+0.2
DDR2
VREF+0.125
VDDS+0.3
V
Specifications
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Table 5-10. LVCMOS DDR DC Electrical Characteristics (continued)
PARAMETER
MIN
VIL
Low-level input threshold
DDR3/DDR3L
VCM
Input common-mode voltage
CPAD
Pad capacitance (including package capacitance)
DDR2
MAX
UNIT
-0.2
NOM
VREF-0.1
V
-0.3
VREF-0.125
VREF 10%vdds
VREF+
10%vdds
V
3
pF
V
Differential Receiver Mode
VSWING
Input voltage swing
DDR3/DDR3L
0.2
vdds+0.4
DDR2
0.25
vdds+0.6
VREF 10%vdds
VREF+
10%vdds
VCM
Input common-mode voltage
CPAD
Pad capacitance (including package capacitance)
3
pF
1. VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1 or vdds_ddr2). For more
information on the power supply name and the corresponding ball, see Table 4-2, POWER [11]
column.
2. VREF in this table stands for corresponding Reference Power Supply (i.e. ddr1_vref0 or ddr2_vref0).
For more information on the power supply name and the corresponding ball, see Table 4-2, POWER
[11] column.
5.7.2
HDMIPHY DC Electrical Characteristics
The HDMIPHY DC Electrical Characteristics are compliant with the HDMI 1.4a specification and are not
reproduced here.
5.7.3
Dual Voltage LVCMOS I2C DC Electrical Characteristics
Table 5-11 summarizes the DC electrical characteristics for Dual Voltage LVCMOS I2C Buffers.
NOTE
For more information on the I/O cell configurations, see the Control Module section of the
Device TRM.
Table 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda;
Balls: F17 / C20 / C21 / C25
I2C Standard Mode – 1.8 V
170
VIH
Input high-level threshold
VIL
Input low-level threshold
Vhys
Hysteresis
0.7*VDDS
V
0.3*VDDS
V
0.1*VDDS
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
12
µA
CIN
Input capacitance
10
pF
0.2*VDDS
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
IOLmin
Low-level output current @VOL=0.2*VDDS
Specifications
3
mA
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Table 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
PARAMETER
tOF
MIN
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
NOM
MAX
UNIT
250
ns
I2C Fast Mode – 1.8 V
VIH
Input high-level threshold
VIL
Input low-level threshold
Vhys
Hysteresis
0.7*VDDS
V
0.3*VDDS
V
0.1*VDDS
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
12
µA
CIN
Input capacitance
10
pF
0.2*VDDS
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
IOLmin
Low-level output current @VOL=0.2*VDDS
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 400 pF
3
20+0.1*Cb
mA
250
ns
I2C Standard Mode – 3.3 V
VIH
Input high-level threshold
VIL
Input low-level threshold
Vhys
Hysteresis
0.7*VDDS
V
0.3*VDDS
V
0.05*VDDS
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
31
80
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
31
80
µA
CIN
Input capacitance
10
pF
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
V
IOLmin
Low-level output current @VOL=0.4V
3
mA
IOLmin
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
6
mA
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
250
ns
I2C Fast Mode – 3.3 V
VIH
Input high-level threshold
VIL
Input low-level threshold
Vhys
Hysteresis
0.7*VDDS
V
0.3*VDDS
V
0.05*VDDS
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDSS
31
80
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
31
80
µA
CIN
Input capacitance
10
pF
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
V
IOLmin
Low-level output current @VOL=0.4V
3
mA
IOLmin
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
6
mA
Specifications
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Table 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
PARAMETER
tOF
MAX
UNIT
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 200 pF (Proper
External Resistor Value should be used as per
I2C spec)
20+0.1*Cb
MIN
NOM
250
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 300 pF to 400 pF (Proper
External Resistor Value should be used as per
I2C spec)
40
290
1. VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the
power supply name and the corresponding ball, see Table 4-2, POWER [11] column.
5.7.4
IQ1833 Buffers DC Electrical Characteristics
Table 5-12 summarizes the DC electrical characteristics for IQ1833 Buffers.
Table 5-12. IQ1833 Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: tclk;
Balls: E20;
1.8-V Mode
VIH
Input high-level threshold (Does not meet JEDEC VIH)
VIL
Input low-level threshold (Does not meet JEDEC VIL)
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
CPAD
Pad capacitance (including package capacitance)
0.75 *
VDDS
V
0.25 *
VDDS
100
V
mV
2
11
µA
1
pF
3.3-V Mode
VIH
Input high-level threshold (Does not meet JEDEC VIH)
VIL
Input low-level threshold (Does not meet JEDEC VIL)
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
CPAD
Pad capacitance (including package capacitance)
5.7.5
2.0
V
0.6
400
V
mV
5
11
µA
1
pF
MAX
UNIT
IHHV1833 Buffers DC Electrical Characteristics
Table 5-13 summarizes the DC electrical characteristics for IHHV1833 Buffers.
Table 5-13. IHHV1833 Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
Signal Names in MUXMODE 0: porz / rtc_iso / rtc_porz / wakeup [3:0];
Balls: F22 / AF14 / AB17 / AD17 / AC17 / AB16 / AC16;
1.8-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
CPAD
Pad capacitance (including package capacitance)
1.2
V
0.4
40
0.02
V
mV
1
µA
1
pF
3.3-V Mode
172
Specifications
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Table 5-13. IHHV1833 Buffers DC Electrical Characteristics (continued)
PARAMETER
MIN
VIH
Input high-level threshold
1.2
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
40
IIN
Input current at each I/O pin
5
CPAD
Pad capacitance (including package capacitance)
5.7.6
NOM
MAX
UNIT
V
0.4
V
mV
8
µA
1
pF
MAX
UNIT
LVCMOS OSC Buffers DC Electrical Characteristics
Table 5-14 summarizes the DC electrical characteristics for LVCMOS OSC Buffers.
Table 5-14. LVCMOS OSC Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
Signal Names in MUXMODE 0: rtc_osc_xi_clkin32 / rtc_osc_xo;
Balls: AE14 / AD14;
1.8-V Mode
5.7.7
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
CPAD
Pad capacitance (including package capacitance)
0.65 *
VDDS
V
0.35 *
VDDS
V
150
mV
3
pF
MAX
UNIT
ILVDS18 Buffers DC Electrical Characteristics
Table 5-15 summarizes the DC electrical characteristics for ILVDS18 Buffers.
Table 5-15. ILVDS18 Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
Signal Names in MUXMODE 0: mlbp_clk_n / mlbp_clk_p;
Balls: AB2 / AB1;
1.8-V Mode
VIN (DC) single ended
input voltage
Input voltage
VIH/VIL (DC)
Input high-level threshold
VHYS
Input hysteresis voltage
CPAD
Pad capacitance (including package capacitance)
5.7.8
0.5
VDDSVSWING
VCM ±
50mV
V
NONE
mV
4
pF
MAX
UNIT
BMLB18 Buffers DC Electrical Characteristics
Table 5-16 summarizes the DC electrical characteristics for BMLB18 Buffers.
Table 5-16. BMLB18 Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
Signal Names in MUXMODE 0: mlbp_dat_n / mlbp_dat_p / mlbp_sig_n / mlbp_sig_p;
Balls: AA2 / AA1 / AC2 / AC1;
1.8-V Mode
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Table 5-16. BMLB18 Buffers DC Electrical Characteristics (continued)
PARAMETER
MIN
VIH/VIL
Input high-level threshold
VHYS
Input hysteresis voltage
VOD
Differential output voltage (measured with 50ohm resistor
between PAD and PADN)
VCM
Common mode output voltage
CPAD
Pad capacitance (including package capacitance)
5.7.9
NOM
MAX
VCM ±
50mV
UNIT
V
NONE
mV
300
500
mV
1
1.5
V
4
pF
MAX
UNIT
BC1833IHHV Buffers DC Electrical Characteristics
Table 5-17 summarizes the DC electrical characteristics for BC1833IHHV Buffers.
Table 5-17. BC1833IHHV Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
Signal Names in MUXMODE 0: on_off;
Balls: Y11;
1.8-V Mode
VOH
Output high-level threshold (IOH = 2 mA)
VDDS0.45
V
VOL
Output low-level threshold (IOL = 2 mA)
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V
6
IIN
Input current at each I/O pin
6
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by
the tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and
the Max(I(PAD)) is measured and is reported as IOZ
6
µA
CPAD
Pad capacitance (including package capacitance)
4
pF
0.45
V
mA
3.3-V Mode
VOH
Output high-level threshold (IOH =100µA)
VOL
Output low-level threshold (IOL = 100µA)
VDDS-0.2
V
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V
IIN
Input current at each I/O pin
60
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by
the tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and
the Max(I(PAD)) is measured and is reported as IOZ
60
µA
CPAD
Pad capacitance (including package capacitance)
4
pF
0.2
6
V
mA
5.7.10 USBPHY DC Electrical Characteristics
NOTE
USB1 instance is compliant with the USB3.0 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the USB3.0 Specification Rev 1.0 dated Jun 6,
2011.
NOTE
USB1 and USB2 Electrical Characteristics are compliant with USB2.0 Specification Rev 2.0
dated April 27, 2000 including ECNs and Errata as applicable.
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5.7.11
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Dual Voltage SDIO1833 DC Electrical Characteristics
Table 5-18 summarizes the DC electrical characteristics for Dual Voltage SDIO1833 Buffers.
Table 5-18. Dual Voltage SDIO1833 DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in Mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0]
Bottom Balls: W6 / Y6 / AA6 / Y4 / AA5 / Y3
1.8-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
30
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
30
µA
IIN with
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
50
120
210
µA
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
60
120
200
µA
5
pF
pulldown
enabled
IIN with
pullup
enabled
CPAD
Pad capacitance (including package capacitance)
VOH
Output high-level threshold (IOH = 2 mA)
VOL
Output low-level threshold (IOL = 2 mA)
1.27
V
0.58
50
V
mV
(2)
1.4
V
0.45
V
3.3-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
110
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
110
µA
IIN with
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
40
100
290
µA
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
10
100
290
µA
5
pF
pulldown
enabled
IIN with
pullup
enabled
CPAD
Pad capacitance (including package capacitance)
VOH
Output high-level threshold (IOH = 2 mA)
VOL
Output low-level threshold (IOL = 2 mA)
0.625 ×
VDDS
V
0.25 × VDDS
40(2)
V
mV
0.75 × VDDS
V
0.125 ×
VDDS
V
(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,
see Table 4-2, POWER [11] column.
(2) Hysteresis is enabled/disabled with CTRL_CORE_CONTROL_HYST_1.SDCARD_HYST register.
5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
Table 5-19 summarizes the DC electrical characteristics for Dual Voltage LVCMOS Buffers.
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Table 5-19. Dual Voltage LVCMOS DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
1.8-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
VOH
Output high-level threshold (IOH = 2 mA)
VOL
Output low-level threshold (IOL = 2 mA)
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
IIN
Input current at each I/O pin
16
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
16
µA
IIN with pulldown
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
50
120
210
µA
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
60
120
200
µA
enabled
CPAD
Pad capacitance (including package capacitance)
4
pF
ZO
Output impedance (drive strength)
enabled
IIN with pullup
0.65*VDDS
V
0.35*VDDS
100
V
mV
VDDS-0.45
V
0.45
6
V
mA
Ω
40
3.3-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
VOH
Output high-level threshold (IOH =100 µA)
VOL
Output low-level threshold (IOL = 100 µA)
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
IIN
Input current at each I/O pin
65
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
65
µA
IIN with pulldown
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
40
100
200
µA
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
10
100
290
µA
enabled
CPAD
Pad capacitance (including package capacitance)
4
pF
ZO
Output impedance (drive strength)
enabled
IIN with pullup
2
V
0.8
200
V
mV
VDDS-0.2
V
0.2
6
V
mA
40
Ω
1. VDDS in this table stands for corresponding power supply. For more information on the power supply
name and the corresponding ball, see Table 4-2, POWER [11] column.
5.7.13 SATAPHY DC Electrical Characteristics
NOTE
The SATA module is compliant with the electrical parameters specified in the SATA-IO SATA
Specification, Revision 3.2, August 7, 2013.
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5.7.14 PCIEPHY DC Electrical Characteristics
NOTE
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express®
Base Specification Revision 2.0.
5.8
Thermal Resistance Characteristics
For reliability and operability concerns, the maximum junction temperature of the Device has to be at or
below the TJ value identified in Table 5-4, Recommended Operating Conditions.
A BCI compact thermal model for this Device is available and recommended for use when modeling
thermal performance in a system.
Therefore, it is recommended to perform thermal simulations at the system level with the worst case
device power consumption.
5.8.1
Package Thermal Characteristics
Table 5-20 provides the thermal resistance characteristics for the package used on this device.
NOTE
Power dissipation of 1.5 W and an ambient temperature of 85ºC is assumed for ABC
package.
Table 5-20. Thermal Resistance Characteristics
PARAMET
ER
DESCRIPTION
°C/W(1)
AIR FLOW (m/s)(2)
T1
RΘJC
Junction-to-case
0.82
N/A
T2
RΘJB
Junction-to-board
3.78
N/A
Junction-to-free air
11.1
0
8.8
1
8.0
2
T6
7.5
3
T7
0.62
0
T8
0.66
1
NO.
T3
T4
T5
T9
RΘJA
ΨJT
Junction-to-moving air
Junction-to-package top
0.66
2
T10
0.66
3
T11
3.43
0
3.22
1
3.12
2
3.04
3
T12
T13
ΨJB
Junction-to-board
T14
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
– JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
– JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
– JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
– JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
– JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second
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5.9
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Power Supply Sequences
This section describes the power-up and power-down sequence required to ensure proper device
operation. The power supply names described in this section comprise a superset of a family of
compatible devices. Some members of this family will not include a subset of these power supplies and
their associated device modules. Refer to the Section 4.2, Ball Characteristics of the Section 4, Terminal
Configuration and Functions to determine which power supplies are applicable.
Figure 5-1 and Figure 5-2, describes the device Power Sequencing when RTC-mode is used.
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Note 4
vdda_rtc
Note 5
(3)
vdds18v, vdds_mlbp, vdds18v_ddr1,
)
vdds18v_ddr2
vdda_abe_per, vdda_ddr, vdda_debug,
vdda_dsp_eve, vdda_gmac_core, vdda_gpu,
vdda_iva, vdda_video, vdda_mpu, vdda_osc
vdd_rtc
(3)
vdds_ddr2, vdds_ddr1, ddr1_vref0,
ddr2_vref0
VD_CORE BOOT voltage
vdd
VD_MPU BOOT voltage
vdd_mpu
VD_IVA BOOT voltage
vdd_iva
VD_GPU BOOT voltage
vdd_gpu
VD_DSPEVE BOOT voltage
vdd_dspeve
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_pcie1,
vdda_sata, vdda_usb3
vddshv5
(3)
Note 6
vddshv1, vddshv2, vddshv3, vddshv4,
vddshv6, vddshv7, vddshv9,
vddshv10, vddshv11
vdda33v_usb1, vdda33v_usb2
Note 7
vddshv8
xi_osc0
Note 9
rtc_porz
Note 11
resetn/porz
Note 12
sysboot[15:0]
Note 13
Valid Config
Note 14
rstoutn
SPRS85v_ELCH_01
Figure 5-1. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
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(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) If RTC-mode is used then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be
combined with other rails.
(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
(5) vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: resetn/porz must remain low a minimum of 12P(15) after xi_osc0 is stable and at a valid frequency.
(12) Setup time: sysboot[15:0] pins must be valid 2P(15) before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P(15) after porz is de-asserted high.
(14) resetn to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
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Note 5
Note 6
porz
Note 8
vddshv8
vdda33v_usb1, vdda33v_usb2
Note 7
vddshv1, vddshv2, vddshv3, vddshv4,
vddshv6, vddshv7, vddshv9, vddshv10,
vddshv11
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_pcie1,
vdda_sata, vdda_usb3
vddshv5
(4)
vdd_dspeve
vdd_gpu
vdd_iva
vdd_mpu
vdd
vdds_ddr2, vdds_ddr1, ddr1_vref0,
ddr2_vref0
vdda_abe_per, vdda_ddr, vdda_debug,
vdda_dsp_eve, vdda_gmac_core, vdda_gpu,
vdda_iva, vdda_video, vdda_mpu, vdda_osc
vdd_rtc
(4)
vdds18v, vdds_mlbp, vdds18v_ddr1,
vdds18v_ddr2
vdda_rtc
(4)
xi_osc0
SPRS85v_ELCH_02
Figure 5-2. Power-Down Sequencing
(1) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(2) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(3) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(4) If RTC-mode is supported then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot
be combined with other rails.
(5) vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
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(6) vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
(7) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is
never higher than 2.0 V above the vdds18v rail.
(8) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
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Figure 5-3 describes the RTC-mode Power Sequencing.
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Figure 5-3. RTC Mode Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
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(3) vdd must ramp down after or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
(4) vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
(5) vdd must ramp up before or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp down before vdd and must ramp up after vdd.
(8) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshvn rail is never higher
than 2.0 V above the vdds18v rail.
(9) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
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Figure 5-4 and Figure 5-5, describe the device Power Sequencing when RTC-mode is NOT used.
Note 4
Note 5
vdds18v, vdds_mlbp, vdds18v_ddr1,
(3)
vdds18v_ddr2, vdda_rtc
vdda_abe_per, vdda_ddr, vdda_debug,
vdda_dsp_eve, vdda_gmac_core, vdda_gpu,
vdda_iva, vdda_video, vdda_mpu, vdda_osc
vdds_ddr2, vdds_ddr1, ddr1_vref0,
ddr2_vref0
VD_CORE BOOT voltage
vdd, vdd_rtc
(3)
VD_MPU BOOT voltage
vdd_mpu
VD_IVA BOOT voltage
vdd_iva
VD_GPU BOOT voltage
vdd_gpu
VD_DSPEVE BOOT voltage
vdd_dspeve
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_pcie1,
vdda_sata, vdda_usb3
vddshv1, vddshv2, vddshv3, vddshv4,
(3)
vddshv5 , vddshv6, vddshv7, vddshv9,
vddshv10, vddshv11
Note 6
vdda33v_usb1, vdda33v_usb2
Note 7
vddshv8
xi_osc0
Note 9
rtc_porz
Note 11
resetn/porz
Note 12
sysboot[15:0]
Note 13
Valid Config
Note 14
rstoutn
SPRS85v_ELCH_04
Figure 5-4. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) If RTC-mode is not supported then the following combinations are approved:
- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
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- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails.
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
(5) vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: resetn/porz must remain low a minimum of 12P(15) after xi_osc0 is stable and at a valid frequency.
(12) Setup time: sysboot[15:0] pins must be valid 2P(15) before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P(15) after porz is de-asserted high.
(14) resetn to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
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Note 5
Note 6
porz
Note 8
vddshv8
vdda33v_usb1, vdda33v_usb2
Note 7
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_pcie1,
vdda_sata, vdda_usb3
vdd_dspeve
vdd_gpu
vdd_iva
vdd_mpu
vdd, vdd_rtc
(4)
vdds_ddr2, vdds_ddr1, ddr1_vref0,
ddr2_vref0
vdda_abe_per, vdda_ddr, vdda_debug,
vdda_dsp_eve, vdda_gmac_core, vdda_gpu,
vdda_iva, vdda_video, vdda_mpu, vdda_osc
xi_osc0
SPRS85v_ELCH_05
Figure 5-5. Power-Down Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(4) If RTC-mode is not used then the following combinations are approved:
- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
(5) vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
(6) vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
(7) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18h.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is
never higher than 2.0 V above the vdds18v rail.
(8) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
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vddshv[1-7,9-11] rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
Figure 5-6 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.
Figure 5-6. vddshv* Supplies Falling After vdds18v Supplies Delta
(1) Vdelta MAX = 2V
(2) If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.
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6 Clock Specifications
NOTE
For more information, see Power, Reset, and Clock Management / PRCM Environment /
External Clock Signal and Power Reset / PRCM Functional Description / PRCM Clock
Manager Functional Description section of the Device TRM.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
The device operation requires the following clocks:
• The 32 kHz frequency is used for low frequency operation. It supplies the wake-up domain for
operation in lowest power mode. This is an optional clock and will be supplied by on chip divider + mux
(FUNC_32K_CLK) incase it is not available on external pin.
• The system clocks, SYS_CLKIN1(Mandatory) and SYS_CLKIN2(Optional) are the main clock sources
of the device. They supply the reference clock to the DPLLs as well as functional clock to several
modules.
The Device also embeds an internal free-running 32-kHz oscillator that is always active as long as the the
wake-up (WKUP) domain is supplied.
Figure 6-1 shows the external input clock sources and the output clocks to peripherals.
190
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DEVICE
rtc_osc_xi_clkin32
rtc_osc_xo
From quartz (32 kHz) or from CMOS square clock source (32 kHz).
To quartz (from oscillator output).
rstoutn
Warm reset output.
resetn
Device reset input.
porz
xi_osc0
Power ON Reset.
From quartz (19.2, 20 or 27 MHz)
or from CMOS square clock source (19.2, 20 or 27MHz).
xo_osc0
To quartz (from oscillator output).
xi_osc1
From quartz (range from 19.2 to 32 MHz)
or from CMOS square clock source(range from 12 to 38.4 MHz).
xo_osc1
To quartz (from oscillator output).
clkout1
clkout2
Output clkout[3:1] clocks come from:
• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)
• Or a CORE clock (from CORE output)
• Or a 192-MHz clock (from PER DPLL output).
clkout3
xref_clk0
xref_clk1
External Reference Clock [3:0].
For Audio and other Peripherals
xref_clk2
xref_clk3
sysboot[15:0]
Boot Mode Configuration
Figure 6-1. Clock Interface
6.1
Input Clock Specifications
6.1.1
Input Clock Requirements
•
•
•
The source of the internal system clock (SYS_CLK1) could be either:
– A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock
case).
– A crystal oscillator clock managed by xi_osc0 and xo_osc0.
The source of the internal system clock (SYS_CLK2) could be either:
– A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock
case).
– A crystal oscillator clock managed by xi_osc1 and xo_osc1.
The source of the internal system clock (SYS_32K) could be either:
– A CMOS clock that enters on the rtc_osc_xi_clkin32 ball and supports external LVCMOS clock
generators
– A crystal oscillator clock managed by rtc_osc_xi_clkin32 and rtc_osc_xo.
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6.1.2
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System Oscillator OSC0 Input Clock
SYS_CLKIN1 is received directly from oscillator OSC0. For more information about SYS_CLKIN1 see
Device TRM, Chapter: Power, Reset, and Clock Management.
6.1.2.1
OSC0 External Crystal
An external crystal is connected to the device pins. Figure 6-2 describes the crystal implementation.
Device
xo_osc0
xi_osc0
vssa_osc0
Rd
(Optional)
Crystal
Cf2
Cf1
Figure 6-2. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 6-2, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc0, xo_osc0, and vssa_osc0 pins.
CL=
Cf1Cf2
(Cf1+Cf2)
Figure 6-3. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-1 summarizes
the required electrical constraints.
Table 6-1. OSC0 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
TYP
MAX
19.2, 20, 27
UNIT
MHz
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
100
Ω
19.2 MHz, 20 MHz, 27 MHz
7
pF
19.2 MHz, 20 MHz
7
pF
27 MHz
5
pF
19.2 MHz, 20 MHz
7
pF
5
pF
3
pF
ESR(Cf1,Cf2)
Crystal ESR
ESR = 30 Ω
ESR = 40 Ω
ESR = 50 Ω
CO
Crystal shunt capacitance
ESR = 60 Ω
ESR = 80 Ω
ESR = 100 Ω
192
MIN
Clock Specifications
27 MHz
Not Supported
19.2 MHz, 20 MHz
27 MHz
Not Supported
19.2 MHz, 20 MHz
27 MHz
-
Not Supported
-
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Table 6-1. OSC0 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
LM
Crystal motional inductance for fp = 20 MHz
CM
Crystal motional capacitance
tj(xiosc0)
MIN
TYP
MAX
UNIT
10.16
mH
3.42
(1)
Frequency accuracy , xi_osc0
fF
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
Ethernet MII using derived
clock
±100
MLB using derived clock
±50
ppm
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 6-2 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 6-2. Oscillator Switching Characteristics—Crystal Mode
NAME
DESCRIPTION
fp
Oscillation frequency
tsX
Start-up time
6.1.2.2
MIN
TYP
MAX
19.2, 20, 27 MHz
UNIT
MHz
4
ms
OSC0 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLKIN1 clock input to the system. The external connections to support this are shown in Figure 6-4.
The xi_osc0 pin is connected to the 1.8-V LVCMOS-Compatible clock source. The xi_osc0 pin is left
unconnected. The vssa_osc0 pin is connected to board ground (VSS).
Device
xi_osc0
xo_osc0
vssa_osc0
NC
SPRS85v_CLK_09
Figure 6-4. 1.8-V LVCMOS-Compatible Clock Input
Table 6-3 summarizes the OSC0 input clock electrical characteristics.
Table 6-3. OSC0 Input Clock Electrical Characteristics—Bypass Mode
NAME
f
DESCRIPTION
MIN
Frequency
CIN
Input capacitance
IIN
Input current (3.3V mode)
TYP
MAX
19.2, 20, 27
UNIT
MHz
2.184
2.384
2.584
pF
4
6
10
µA
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Table 6-4 details the OSC0 input clock timing requirements.
Table 6-4. OSC0 Input Clock Timing Requirements
NAME
DESCRIPTION
1/
CK0
tc(xiosc0)
CK1
Frequency, xi_osc0
TYP
MAX
19.2, 20, 27
UNIT
MHz
0.55 *
tc(xiosc0)
ns
0.01 ×
tc(xiosc0)
ns
Rise time, xi_osc0
5
ns
Fall time, xi_osc0
5
ns
tw(xiosc0)
Pulse duration, xi_osc0 low or high
tj(xiosc0)
Period jitter(1), xi_osc0
tR(xiosc0)
tF(xiosc0)
tj(xiosc0)
MIN
Frequency accuracy(2), xi_osc0
0.45
*
tc(xiosc0)
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
Ethernet MII using derived
clock
±100
MLB using derived clock
±50
ppm
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
CK0
CK1
CK1
xi_osc0
Figure 6-5. xi_osc0 Input Clock
6.1.3
Auxiliary Oscillator OSC1 Input Clock
SYS_CLKIN2 is received directly from oscillator OSC1. For more information about SYS_CLKIN2 see
Device TRM, Chapter: Power, Reset, and Clock Management.
6.1.3.1
OSC1 External Crystal
An external crystal is connected to the device pins. Figure 6-6 describes the crystal implementation.
Device
xo_osc1
xi_osc1
Rd
(Optional)
Crystal
Cf1
vssa_osc1
Cf2
Figure 6-6. Crystal Implementation
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NOTE
The load capacitors, Cf1 and Cf2 in Figure 6-6, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins.
CL=
Cf1Cf2
(Cf1+Cf2)
Figure 6-7. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-5 summarizes
the required electrical constraints.
Table 6-5. OSC1 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
MIN
Parallel resonance crystal frequency
TYP
MAX
Range from 19.2 to 32
UNIT
MHz
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
100
Ω
ESR(Cf1,Cf2)
Crystal ESR
ESR = 30 Ω
19.2 MHz≤fp≤32 MHz
7
pF
ESR = 40 Ω
19.2 MHz≤fp≤32 MHz
5
pF
19.2 MHz≤fp≤25 MHz
7
pF
5
pF
7
pF
5
pF
19.2 MHz≤fp≤23 MHz
5
pF
23 MHz≤fp≤25 MHz
3
pF
3
pF
ESR = 50 Ω
25 MHz<fp≤27 MHz
27 MHz<fp≤32 MHz
Not Supported
19.2 MHz≤fp≤23 MHz
CO
Crystal shunt capacitance
ESR = 60 Ω
23 MHz<fp≤25 MHz
25 MHz<fp≤32 MHz
ESR = 80 Ω
25 MHz<fp≤32 MHz
ESR = 100 Ω
Not Supported
-
Not Supported
19.2 MHz≤fp≤20 MHz
20 MHz<fp≤32 MHz
-
-
Not Supported
-
LM
Crystal motional inductance for fp = 20 MHz
10.16
mH
CM
Crystal motional capacitance
3.42
fF
tj(xiosc1)
Frequency accuracy(1), xi_osc1
Ethernet and MLB not
used
±200
Ethernet RGMII and
RMII using derived
clock
±50
Ethernet MII using
derived clock
±100
MLB using derived
clock
±50
ppm
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 6-6 details the switching characteristics of the oscillator and the requirements of the input clock.
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Table 6-6. Oscillator Switching Characteristics—Crystal Mode
NAME
DESCRIPTION
fp
Oscillation frequency
tsX
Start-up time
6.1.3.2
MIN
TYP
MAX
UNIT
Range from 19.2 to 32
MHz
4
ms
OSC1 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLKIN2 clock input to the system. The external connections to support this are shown in, Figure 6-8.
The xi_osc1 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The xo_osc1 pin is left
unconnected. The vssa_osc1 pin is connected to board ground (vss).
Device
xi_osc1
xo_osc1
vssa_osc1
NC
SPRS85v_CLK_10
Figure 6-8. 1.8-V LVCMOS-Compatible Clock Input
Table 6-7 summarizes the OSC1 input clock electrical characteristics.
Table 6-7. OSC1 Input Clock Electrical Characteristics—Bypass Mode
NAME
f
DESCRIPTION
MIN
Frequency
MAX
UNIT
Range from 12 to 38.4
CI
Input capacitance
II
Input current (3.3V mode)
tsX
TYP
Start-up time(1)
MHz
2.819
3.019
3.219
pF
4
6
10
µA
See(2)
ms
(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip
comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 6-6, tsX parameter.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in
application mode and receives a wave. The switching time in this case is about 100 μs.
Table 6-8 details the OSC1 input clock timing requirements.
Table 6-8. OSC1 Input Clock Timing Requirements
NAME
DESCRIPTION
CK0
1/
tc(xiosc1)
Frequency, xi_osc1
CK1
tw(xiosc1)
Pulse duration, xi_osc1 low or high
tj(xiosc1)
Period jitter(1), xi_osc1
tR(xiosc1)
tF(xiosc1)
196
MIN
TYP
MAX
Range from 12 to 38.4
MHz
0.55 *
tc(xiosc1)
ns
0.01 ×
tc(xiosc1)
ns
Rise time, xi_osc1
5
ns
Fall time, xi_osc1
5
ns
Clock Specifications
0.45 *
tc(xiosc1)
UNIT
(3)
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Table 6-8. OSC1 Input Clock Timing Requirements (continued)
NAME
DESCRIPTION
tj(xiosc1)
MIN
(2)
Frequency accuracy , xi_osc1
TYP
MAX
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
Ethernet MII using derived
clock
±100
MLB using derived clock
±50
UNIT
ppm
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02*tc(xiosc1) under the following constraints:
a.The osc1/SYS_CLK2 clock bypasses all device PLLs
b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
CK0
CK1
CK1
xi_osc1
Figure 6-9. xi_osc1 Input Clock
6.1.4
RTC Oscillator Input Clock
SYS_32K is received directly from RTC Oscillator. For more information about SYS_32K see Device TRM,
Chapter: Power, Reset, and Clock Management.
6.1.4.1
RTC Oscillator External Crystal
An external crystal is connected to the device pins. Figure 6-2 describes the crystal implementation.
Device
rtc_osc_xo
rtc_osc_xi_clkin32
Rd
(Optional)
Crystal
Cf2
Cf1
Figure 6-10. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 6-10, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator rtc_osc_xi_clkin32 and rtc_osc_xo pins.
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CL=
Cf1Cf2
(Cf1+Cf2)
Figure 6-11. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-9 summarizes
the required electrical constraints.
Table 6-9. RTC Crystal Electrical Characteristics
NAME
DESCRIPTION
fp
MIN
TYP
Parallel resonance crystal frequency
MAX
32.768
UNIT
kHz
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
80
kΩ
ESR(Cf1,Cf2)
Crystal ESR
CO
Crystal shunt capacitance
LM
Crystal motional inductance for fp = 32,768 kHz
10.7
CM
Crystal motional capacitance
2.2
tj(rtc_osc_xi_clkin32)
5
pF
pF
mH
fF
Frequency accuracy, rtc_osc_xi_clkin32
±200
ppm
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 6-10 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 6-10. Oscillator Switching Characteristics—Crystal Mode
NAME
DESCRIPTION
fp
Oscillation frequency
tsX
Start-up time
6.1.4.2
MIN
TYP
MAX
32.768
UNIT
kHz
4
ms
RTC Oscillator Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_32K clock input to the system. The external connections to support this are shown in Figure 6-12.
The rtc_osc_xi_clkin32 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The rtc_osc_xo
pin is left unconnected.
Device
rtc_osc_xi_clkin32
rtc_osc_xo
NC
SPRS85v_CLK_11
Figure 6-12. LVCMOS-Compatible Clock Input
Table 6-11 summarizes the RTC Oscillator input clock electrical characteristics.
198
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Table 6-11. RTC Oscillator Input Clock Electrical Characteristics—Bypass Mode
NAME
CK0
CK1
DESCRIPTION
1/tc(rtc_osc_xi_clkin32)
tw(rtc_osc_xi_clkin32)
MIN
Frequency, rtc_osc_xi_clkin32
Pulse duration, rtc_osc_xi_clkin32 low or
high
CIN
Input capacitance
IIN
Input current (3.3V mode)
tsX
Start-up time
TYP
MAX
UNIT
32.768
kHz
0.45 *
0.55 *
tc(rtc_osc_xi_clkin32)
tc(rtc_osc_xi_clkin32)
ns
2.178
2.378
2.578
pF
4
6
10
µA
See (1)
ms
(1) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is
inapplication mode and receives a wave. The switching time in this case is about 100 μs.
CK0
CK1
CK1
rtc_osc_xi_clkin32
Figure 6-13. rtc_osc_xi_clkin32 Input Clock
6.2
DPLLs, DLLs Specifications
NOTE
For more information, see:
• Power, Reset and Clock Management / Clock Management Functional / Internal Clock
Sources / Generators / Generic DPLL Overview Section
and
• Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the
PRCM module. They are of two types: type A and type B DPLLs.
•
They have their own independent power domain (each one embeds its own switch and can be
controlled as an independent functional power domain)
• They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
• DPLL_MPU: It supplies the MPU subsystem clocking internally.
• DPLL_IVA: It feeds the IVA subsystem clocking.
• DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
• DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a
96-MHz functional clock to subsystems and peripherals.
• DPLL_ABE: It provides clocks to various modules within the device.
• DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).
• DPLL_GMAC: It supplies several clocks for the Gigabit Ethernet Switch (GMAC_SW).
• DPLL_EVE: It provides the Embedded Vision Engine Subsystem (EVE1/2/3/4) clocking.
• DPLL_DSP: It feeds the DSP Subsystem clocking.
• DPLL_GPU: It supplies clock for the GPU Subsystem.
• DPLL_DDR: It generates clocks for the two External Memory Interface (EMIF) controllers and their
associated EMIF PHYs.
• DPLL_PCIE_REF: It provides reference clock for the APLL_PCIE in PCIE Subsystem.
• APLL_PCIE: It feeds clocks for the device Peripheral Component Interconnect Express (PCIe)
controllers.
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NOTE
The following DPLLs are controlled by the clock manager located in the always-on Core
power domain (CM_CORE_AON):
• DPLL_MPU, DPLL_IVA, DPLL_CORE, DPLL_ABE, DPLL_DDR, DPLL_GMAC,
DPLL_PCIE_REF, DPLL_PER, DPLL_USB, DPLL_EVE, DPLL_DSP, DPLL_GPU,
APLL_PCIE_REF.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and
Clock Management (PRCM) chapter of the Device TRM.
The following DPLLs are not managed by the PRCM:
•
•
•
•
•
•
DPLL_VIDEO1; (It is controlled from DSS)
DPLL_VIDEO2; (It is controlled from DSS)
DPLL_HDMI; (It is controlled from DSS)
DPLL_SATA; (It is controlled from SATA)
DPLL_DEBUG; (It is controlled from DEBUGSS)
DPLL_USB_OTG_SS; (It is controlled from OCP2SCP1)
NOTE
For more information for not controlled from PRCM DPLL’s see the related chapters in TRM.
6.2.1
DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power Reset Controller Management chapter of the Device TRM.
Table 6-12 summarizes DPLL type described in Section 6.2, DPLLs, DLLs Specifications introduction.
Table 6-12. DPLL Control Type
200
DPLL NAME
TYPE
CONTROLLED BY PRCM
DPLL_ABE
Table 6-13 (Type A)
Yes(1)
DPLL_CORE
Table 6-13 (Type A)
Yes(1)
DPLL_DEBUGSS
Table 6-13 (Type A)
No(2)
DPLL_DSP
Table 6-13 (Type A)
Yes(1)
DPLL_EVE
Table 6-13 (Type A)
Yes(1)
DPLL_GMAC
Table 6-13 (Type A)
Yes(1)
DPLL_HDMI
Table 6-14 (Type B)
No(2)
DPLL_IVA
Table 6-13 (Type A)
Yes(1)
DPLL_MPU
Table 6-13 (Type A)
Yes(1)
DPLL_PER
Table 6-13 (Type A)
Yes(1)
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Table 6-12. DPLL Control Type (continued)
DPLL NAME
TYPE
CONTROLLED BY PRCM
APLL_PCIE
Table 6-13 (Type A)
Yes(1)
DPLL_PCIE_REF
Table 6-14 (Type B)
Yes(1)
DPLL_SATA
Table 6-14 (Type B)
No(2)
DPLL_USB
Table 6-14 (Type B)
Yes(1)
DPLL_USB_OTG_SS
Table 6-14 (Type B)
No(2)
DPLL_VIDEO1
Table 6-13 (Type A)
No(2)
DPLL_VIDEO2
Table 6-13 (Type A)
No(2)
DPLL_DDR
Table 6-13 (Type A)
Yes(1)
DPLL_GPU
Table 6-13 (Type A)
Yes(1)
(1) DPLL is in the always-on domain.
(2) DPLL is not controlled by the PRCM.
Table 6-13 and Table 6-14 summarize the DPLL characteristics and assume testing over recommended
operating conditions.
Table 6-13. DPLL Type A Characteristics
NAME
DESCRIPTION
finput
MIN
MAX
UNIT
52
MHz
FINP
0.15
52
MHz
REFCLK
10
1400
MHz
FINPHIF
0.001
600
MHz
Bypass mode: fCLKOUT =
fCLKINPULOW / (M1 + 1) if
ulowclken = 1(6)
CLKOUT output frequency
20(1)
1400(2)
MHz
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
CLKOUTx2 output frequency
40(1)
2200(2)
MHz
2 × [M / (N + 1)] × FINP × [1 /
M2] (in locked condition)
20(3)
1400(4)
MHz
FINPHIF / M3 if clkinphifsel = 1
40(3)
2200(4)
MHz
2 × [M / (N + 1)] × FINP × [1 /
M3] if clkinphifsel = 0
40
2800
MHz
2 × [M / (N + 1)] × FINP (in
locked condition)
CLKINP input frequency
0.032
finternal
Internal reference frequency
fCLKINPHIF
CLKINPHIF input frequency
fCLKINPULOW
fCLKOUT
fCLKOUTx2
CLKINPULOW input frequency
TYP
COMMENTS
fCLKOUTHIF
CLKOUTHIF output frequency
fCLKDCOLDO
DCOCLKLDO output
frequency
tlock
Frequency lock time
6 + 350 ×
REFCLK
µs
plock
Phase lock time
6 + 500 ×
REFCLK
µs
trelock-L
Relock time—Frequency
lock(5) (LP relock time from
bypass)
6 + 70 ×
REFCLK
µs
DPLL in LP relock time:
lowcurrstdby = 1
prelock-L
Relock time—Phase lock(5)
(LP relock time from bypass)
6 + 120 ×
REFCLK
µs
DPLL in LP relock time:
lowcurrstdby = 1
trelock-F
Relock time—Frequency
lock(5) (fast relock time from
bypass)
3.55 + 70 ×
REFCLK
µs
DPLL in fast relock time:
lowcurrstdby = 0
prelock-F
Relock time—Phase lock(5)
(fast relock time from bypass)
3.55 + 120 ×
REFCLK
µs
DPLL in fast relock time:
lowcurrstdby = 0
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
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(6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM.
Table 6-14. DPLL Type B Characteristics
NAME
MAX
UNIT
CLKINP input clock frequency
DESCRIPTION
0.62
60
MHz
FINP
finternal
REFCLK internal reference
clock frequency
0.62
2.5
MHz
[1 / (N + 1)] × FINP
fCLKINPULOW
CLKINPULOW bypass input
clock frequency
0.001
600
MHz
Bypass mode: fCLKOUT =
fCLKINPULOW / (M1 + 1) If
ulowclken = 1(4)
fCLKLDOOUT
CLKOUTLDO output clock
frequency
20(1)(5)
2500(2)(5)
MHz
M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
CLKOUT output clock
frequency
20(1)(5)
1450(2)(5)
MHz
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
750(5)
1500(5)
MHz
1250(5)
2500(5)
MHz
–2.5%
2.5%
finput
fCLKOUT
fCLKDCOLDO
MIN
Internal oscillator (DCO) output
clock frequency
TYP
COMMENTS
[M / (N + 1)] × FINP (in locked
condition)
CLKOUTLDO period jitter
tJ
CLKOUT period jitter
The period jitter at the output
clocks is ± 2.5% peak to peak
CLKDCOLDO period jitter
tlock
Frequency lock time
350 ×
REFCLKs
µs
plock
Phase lock time
500 ×
REFCLKs
µs
Relock time—Frequency lock(3)
(LP relock time from bypass)
9 + 30 ×
REFCLKs
µs
9 + 125 ×
REFCLKs
µs
trelock-L
(3)
prelock-L
Relock time—Phase lock
relock time from bypass)
(LP
(1) The minimum frequency on CLKOUT is assuming M2 = 1.
For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.
(2) The maximum frequency on CLKOUT is assuming M2 = 1.
(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(4) Bypass mode: fCLKOUT = FINP if ULOWCLKEN = 0. For more information, see the Device TRM.
(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.
6.2.2
DLL Characteristics
Table 6-15 summarizes the DLL characteristics and assumes testing over recommended operating
conditions.
Table 6-15. DLL Characteristics
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
finput
Input clock frequency (EMIF_DLL_FCLK)
266
MHz
tlock
Lock time
50k
cycles
Relock time (a change of the DLL frequency implies that DLL must relock)
50k
cycles
trelock
6.2.3
DPLL and DLL Noise Isolation
NOTE
For more information on DPLL and DLL decoupling capacitor requirements, see the External
Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA
Power Domain section.
202
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7 Timing Requirements and Switching Characteristics
7.1
Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
unless otherwise specified.
7.2
7.2.1
Interface Clock Specifications
Interface Clock Terminology
The interface clock is used at the system level to sequence the data and/or to control transfers accordingly
with the interface protocol.
7.2.2
Interface Clock Frequency
The two interface clock characteristics are:
• The maximum clock frequency
• The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the Device IC and does not take into account any system consideration
(PCB, peripherals).
The system designer will have to consider these system considerations and the Device IC timing
characteristics as well to define properly the maximum operating frequency that corresponds to the
maximum frequency supported to transfer the data on this interface.
7.3
Timing Parameters and Information
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other
related terminologies have been abbreviated as follows:
Table 7-1. Timing Parameters
SUBSCRIPTS
SYMBOL
PARAMETER
c
Cycle time (period)
d
Delay time
dis
Disable time
en
Enable time
h
Hold time
su
Setup time
START
Start bit
t
Transition time
v
Valid time
w
Pulse duration (width)
X
Unknown, changing, or don't care level
F
Fall time
H
High
L
Low
R
Rise time
V
Valid
IV
Invalid
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Table 7-1. Timing Parameters (continued)
SUBSCRIPTS
7.3.1
SYMBOL
PARAMETER
AE
Active Edge
FE
First Edge
LE
Last Edge
Z
High impedance
Parameter Information
Tester Pin Electronics
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see Note)
4.0 pF
1.85 pF
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see Note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
pm_tstcirc_prs403
Figure 7-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
7.3.1.1
1.8V and 3.3V Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD
I/O)/2.
Vref
pm_io_volt_prs403
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
204
Timing Requirements and Switching Characteristics
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Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
pm_transvolt_prs403
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
7.3.1.2
1.8V and 3.3V Signal Transition Rates
The default SLEWCONTROL settings in each pad configuration register must be used to guarantee
timings, unless specific instructions otherwise are given in the individual timing sub-sections of the
datasheet.
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
7.3.1.3
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routes. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information
specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to
attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis
application report (literature number SPRA839). If needed, external logic hardware such as buffers may be
used to compensate any timing differences.
7.4
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner. Monotonic transitions are more easily guaranteed with faster switching signals. Slower input
transitions are more susceptible to glitches due to noise and special care should be taken for slow input
clocks.
7.5
Virtual and Manual I/O Timing Modes
Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing
Modes. Table 7-2 provides a summary of the Virtual and Manual I/O Timing Modes across all device
interfaces. The individual interface timing sections found later in this document provide the full description
of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the
TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system.
Table 7-2. Modes Summary
Virtual or Manual IO Mode Name
Data Manual Timing Mode
VIP
VIP1_MANUAL1
VIN1A/1B/2A Rise-Edge Capture Mode Timings
VIP1_2B_MANUAL1
VIN2B Rise-Edge Capture Mode Timings
VIP1_MANUAL2
VIN1A/1B/2A Fall-Edge Capture Mode Timings
VIP1_2B_MANUAL2
VIN2B Fall-Edge Capture Mode Timings
VIP2_MANUAL1
VIN3A and VIN3B IOSET1 Rise-Edge Capture Mode Timings
VIP2_4A_MANUAL1
VIN4A IOSET1/2 Rise-Edge Capture Mode Timings
VIP2_4A_IOSET3_MANUAL1
VIN4A IOSET3 Rise-Edge Capture Mode Timings
VIP2_4B_MANUAL1
VIN4B Rise-Edge Capture Mode Timings
VIP2_3B_IOSET2_MANUAL1
VIN3B IOSET2 Rise-Edge Capture Mode Timings
VIP2_3B_IOSET2_MANUAL2
VIN3B IOSET2 Fall-Edge Capture Mode Timings
VIP2_MANUAL2
VIN3A, VIN3B IOSET1, VIN4A IOSET1/2 Fall-Edge Capture Mode Timings
VIP2_4A_MANUAL2
VIN4A IOSET1/2 Fall-Edge Capture Mode Timings
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Table 7-2. Modes Summary (continued)
Virtual or Manual IO Mode Name
Data Manual Timing Mode
VIP2_4A_IOSET3_MANUAL2
VIN4A IOSET3 Fall-Edge Capture Mode Timings
VIP2_4B_MANUAL2
VIN4B Fall-Edge Capture Mode Timings
VIP3_MANUAL1
VIN5A and VIN6A Rise-Edge Capture Mode Timings
VIP3_MANUAL2
VIN5A and VIN6A Fall-Edge Capture Mode Timings
DPI Video Output
VOUT1_MANUAL1
DPI1 Video Output Alternate Timings
VOUT1_MANUAL2
DPI1 Video Output Default Timings - Rising-edge Clock Reference
VOUT1_MANUAL3
DPI1 Video Output Default Timings - Falling-edge Clock Reference
VOUT2_IOSET1_MANUAL1
DPI2 Video Output IOSET1 Alternate Timings
VOUT2_IOSET1_MANUAL2
DPI2 Video Output IOSET1 Default Timings - Rising-edge Clock Reference
VOUT2_IOSET1_MANUAL3
DPI2 Video Output IOSET1 Default Timings - Falling-edge Clock Reference
VOUT2_IOSET2_MANUAL1
DPI2 Video Output IOSET2 Alternate Timings
VOUT2_IOSET2_MANUAL2
DPI2 Video Output IOSET2 Default Timings - Rising-edge Clock Reference
VOUT2_IOSET2_MANUAL3
DPI2 Video Output IOSET2 Default Timings - Falling-edge Clock Reference
VOUT3_MANUAL1
DPI3 Video Output Alternate Timings
VOUT3_MANUAL2
DPI3 Video Output Default Timings - Rising-edge Clock Reference
VOUT3_MANUAL3
DPI3 Video Output Default Timings - Falling-edge Clock Reference
HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, SATA, PCIe, DCAN, GPIO, KBD, PWM, ATL, JTAG, TPIU, RTC, SDMA,
INTC
No Virtual or Manual IO Timing
Mode Required
All Modes
GPMC
No Virtual or Manual IO Timing
Mode Required
GPMC Asyncronous Mode (1/5 Load) Timings and Synchronous Mode - (1 Load) Timings
GPMC_VIRTUAL1
GPMC Synchronous Mode - (5 Load) Timings
QSPI
No Virtual or Manual IO Timing
Mode Required
QSPI Mode 3 Default Timing Mode
QSPI_MODE0_MANUAL1
QSPI Mode 0 Default Timing Mode
McASP
No Virtual or Manual IO Timing
Mode Required
McASP1 Synchronous Transmit Timings
MCASP1_VIRTUAL1_ASYNC_TX
See Table 7-53
MCASP1_VIRTUAL2_SYNC_RX
See Table 7-53
MCASP1_VIRTUAL3_ASYNC_RX
See Table 7-53
No Virtual or Manual IO Timing
Mode Required
McASP2 Synchronous Transmit Timings
MCASP2_VIRTUAL1_ASYNC_RX_
80M
See Table 7-54
MCASP2_VIRTUAL2_ASYNC_RX
See Table 7-54
MCASP2_VIRTUAL3_ASYNC_TX
See Table 7-54
MCASP2_VIRTUAL4_SYNC_RX
See Table 7-54
MCASP2_VIRTUAL5_SYNC_RX_8
0M
See Table 7-54
No Virtual or Manual IO Timing
Mode Required
McASP3 Synchronous Transmit Timings
MCASP3_VIRTUAL2_SYNC_RX
See Table 7-55
No Virtual or Manual IO Timing
Mode Required
McASP4 Synchronous Transmit Timings
MCASP4_VIRTUAL1_SYNC_RX
See Table 7-56
206
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Table 7-2. Modes Summary (continued)
Virtual or Manual IO Mode Name
Data Manual Timing Mode
No Virtual or Manual IO Timing
Mode Required
McASP5 Synchronous Transmit Timings
MCASP5_VIRTUAL1_SYNC_RX
See Table 7-57
No Virtual or Manual IO Timing
Mode Required
McASP6 Synchronous Transmit Timings
MCASP6_VIRTUAL1_SYNC_RX
See Table 7-58
No Virtual or Manual IO Timing
Mode Required
McASP7 Synchronous Transmit Timings
MCASP7_VIRTUAL2_SYNC_RX
See Table 7-59
No Virtual or Manual IO Timing
Mode Required
McASP8 Synchronous Transmit Timings
MCASP8_VIRTUAL1_SYNC_RX
See Table 7-60
GMAC
No Virtual or Manual IO Timing
Mode Required
GMAC MII1/2 Timings
GMAC_RMII0_MANUAL1
GMAC RMII0 Timings
GMAC_RMII1_MANUAL1
GMAC RMII1 Timings
GMAC_RGMII0_MANUAL1
GMAC RGMII0 Internal Delay Enabled Timings Mode
GMAC_RGMII1_MANUAL1
GMAC RGMII1 Internal Delay Enabled Timings Mode
MLB
MLB_MANUAL1
MLB 3-Pin and 6-Pin Timings
eMMC/SD/SDIO
No Virtual or Manual IO Timing
Mode Required
MMC1 DS (Pad Loopback) and SDR12 (Pad Loopback) Timings
MMC1_VIRTUAL1
MMC1 HS (Internal Loopback and Pad Loopback), SDR12 (Internal Loopback), SDR25 Timings
(Internal Loopback and Pad Loopback)
MMC1_VIRTUAL2
SDR50 (Pad Loopback) Timings
MMC1_VIRTUAL5
MMC1 DS (Internal Loopback) Timings
MMC1_VIRTUAL6
MMC1 SDR50 (Internal Loopback) Timings
MMC1_VIRTUAL7
MMC1 DDR50 (Internal Loopback) Timings
MMC1_DDR_MANUAL1
MMC1 DDR50 (Pad Loopback) Timings
MMC1_SDR104_MANUAL1
MMC1 SDR104 Timings
No Virtual or Manual IO Timing
Mode Required
MMC2 Standard (Pad Loopback) and High Speed (Pad Loopback) Timings
MMC2_DDR_LB_MANUAL1
MMC2 DDR (Internal Loopback) Timings
MMC2_DDR_MANUAL1
MMC2 DDR (Pad Loopback) 1.8V and 3.3V Mode Timings
MMC2_HS200_MANUAL1
MMC2 HS200 Timings
MMC2_STD_HS_LB_MANUAL1
MMC2 Standard (Internal Loopback), High Speed (Internal Loopback) Timings
MMC3_MANUAL1
MMC3 DS, SDR12, HS, SDR25 Timings, SDR50 Timings
MMC4_MANUAL1
MMC4 SDR12, HS, SDR25 Timings
MMC4_DS_MANUAL1
MMC4 DS Timings
Timing Requirements and Switching Characteristics
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Video Input Ports (VIP)
The Device includes 3 Video Input Ports (VIP).
Table 7-3, Figure 7-4 and Figure 7-5 present timings and switching characteristics of the VIPs.
CAUTION
The IO timings provided in this section are applicable for all combinations of
signals for vin1, vin5 and vin6. However, the timings are only valid for vin2,
vin3, and vin4 if signals within a single IOSET are used. The IOSETs are
defined in the Table 7-4, Table 7-5 and Table 7-6.
Table 7-3. Timing Requirements for VIP (1)(2)
NO.
PARAMETER
DESCRIPTION
V1
tc(CLK)
Cycle time, vinx_clki (3) (5)
MODE
V2
tw(CLKH)
Pulse duration, vinx_clki high (3) (5)
0.45*P
(2)
ns
V3
tw(CLKL)
Pulse duration, vinx_clki low (3) (5)
0.45*P
(2)
ns
V4
tsu(CTL/DATA-CLK)
Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3)
(4) (5)
V5
th(CLK-CTL/DATA)
MIN
6.06
Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
vinx_hsynci) and Data (vinx_dn) valid from vinx_clki transition
MAX
(1)
UNIT
ns
vin1x,
vin2x
2.93
ns
vin5x,
vin6x
3.11
ns
vin3x,
vin4x
3.11
ns
-0.05
ns
(3) (4) (5)
(1) For maximum frequency of 165 MHZ.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a, 2b, 3a, 3b, 4a, 4b, 5a and 6a.
(4) n in dn = 0 to 7 when x = 1b, 2b, 3b and 4b;
n = 0 to 15 when x = 5a and 6a;
n = 0 to 23 when x = 1a, 2a, 3a and 4a;
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
V3
V2
V1
vinx_clki
SPRS8xx_VIP_01
Figure 7-4. Video Input Ports clock signal
208
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vinx_clki
(positive-edge clocking)
vinx_clki
(negative-edge clocking)
V5
V4
vinx_d[23:0]/sig
SPRS8xx_VIP_02
Figure 7-5. Video Input Ports timings
In Table 7-4, Table 7-5 and Table 7-6 are presented the specific groupings of signals (IOSET) for use with
vin2, vin3, and vin4.
Table 7-4. VIN2 IOSETs
Signals
IOSET1
BALL
IOSET2
MUX
IOSET3
BALL
MUX
BALL
MUX
F2
0
U4
4
vin2a
vin2a_d0
F2
0
vin2a_d1
F3
0
F3
0
V2
4
vin2a_d2
D1
0
D1
0
Y1
4
vin2a_d3
E2
0
E2
0
W9
4
vin2a_d4
D2
0
D2
0
V9
4
vin2a_d5
F4
0
F4
0
U5
4
vin2a_d6
C1
0
C1
0
V5
4
vin2a_d7
E4
0
E4
0
V4
4
vin2a_d8
F5
0
F5
0
V3
4
vin2a_d9
E6
0
E6
0
Y2
4
vin2a_d10
D3
0
D3
0
U6
4
vin2a_d11
F6
0
F6
0
U3
4
vin2a_d12
D5
0
D5
0
-
-
vin2a_d13
C2
0
C2
0
-
-
vin2a_d14
C3
0
C3
0
-
-
vin2a_d15
C4
0
C4
0
-
-
vin2a_d16
B2
0
B2
0
-
-
vin2a_d17
D6
0
D6
0
-
-
vin2a_d18
C5
0
C5
0
-
-
vin2a_d19
A3
0
A3
0
-
-
vin2a_d20
B3
0
B3
0
-
-
vin2a_d21
B4
0
B4
0
-
-
vin2a_d22
B5
0
B5
0
-
-
vin2a_d23
A4
0
A4
0
-
-
vin2a_hsync0
G1
0
G1
0
U7
4
vin2a_vsync0
G6
0
G6
0
V6
4
vin2a_de0
G2
0
-
-
V7
4
vin2a_fld0
H7
0
G2
1
W2
4
vin2a_clk0
E1
0
E1
0
V1
4
vin2b
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Table 7-4. VIN2 IOSETs (continued)
Signals
IOSET1
IOSET2
BALL
MUX
vin2b_clk1
H7
vin2b_de1
-
vin2b_fld1
IOSET3
BALL
MUX
BALL
MUX
2
H7
2
AB5
4
-
G2
3
AB8
4
G2
2
-
-
-
-
vin2b_d0
A4
2
A4
2
AD6
4
vin2b_d1
B5
2
B5
2
AC8
4
vin2b_d2
B4
2
B4
2
AC3
4
vin2b_d3
B3
2
B3
2
AC9
4
vin2b_d4
A3
2
A3
2
AC6
4
vin2b_d5
C5
2
C5
2
AC7
4
vin2b_d6
D6
2
D6
2
AC4
4
vin2b_d7
B2
2
B2
2
AD4
4
vin2b_hsync1
G1
3
G1
3
AC5
4
vin2b_vsync1
G6
3
G6
3
AB4
4
Table 7-5. VIN3 IOSETs
Signals
IOSET1
BALL
IOSET2
MUX
BALL
IOSET3
MUX
IOSET4
BALL
MUX
BALL
MUX
vin3a
210
vin3a_d0
M6
2
AF1
6
AF1
6
B7
4
vin3a_d1
M2
2
AE3
6
AE3
6
B8
4
vin3a_d2
L5
2
AE5
6
AE5
6
A7
4
vin3a_d3
M1
2
AE1
6
AE1
6
A8
4
vin3a_d4
L6
2
AE2
6
AE2
6
C9
4
vin3a_d5
L4
2
AE6
6
AE6
6
A9
4
vin3a_d6
L3
2
AD2
6
AD2
6
B9
4
vin3a_d7
L2
2
AD3
6
AD3
6
A10
4
vin3a_d8
L1
2
B2
6
B2
6
E8
4
vin3a_d9
K2
2
D6
6
D6
6
D9
4
vin3a_d10
J1
2
C5
6
C5
6
D7
4
vin3a_d11
J2
2
A3
6
A3
6
D8
4
vin3a_d12
H1
2
B3
6
-
-
A5
4
vin3a_d13
J3
2
B4
6
-
-
C6
4
vin3a_d14
H2
2
B5
6
-
-
C8
4
vin3a_d15
H3
2
A4
6
-
-
C7
4
vin3a_d16
R6
2
-
-
-
-
F11
4
vin3a_d17
T9
2
-
-
-
-
G10
4
vin3a_d18
T6
2
-
-
-
-
F10
4
vin3a_d19
T7
2
-
-
-
-
G11
4
vin3a_d20
P6
2
-
-
-
-
E9
4
vin3a_d21
R9
2
-
-
-
-
F9
4
vin3a_d22
R5
2
-
-
-
-
F8
4
vin3a_d23
P5
2
-
-
-
-
E7
4
vin3a_hsync0
N7
2
N7
2
B5
5
C11
4
vin3a_vsync0
R4
2
R4
2
A4
5
E11
4
vin3a_de0
N9
2
N9
2
B3
5
B10
4
vin3a_fld0
P9
2
P9
2
B4
5
D11
4
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Table 7-5. VIN3 IOSETs (continued)
Signals
vin3a_clk0
IOSET1
IOSET2
BALL
MUX
BALL
P1
2
AH7
IOSET3
IOSET4
MUX
BALL
MUX
BALL
MUX
6
AH7
6
B11
4
vin3b
vin3b_clk1
P7
6
M4
4
-
-
-
-
vin3b_de1
N6
6
N6
6
-
-
-
-
vin3b_fld1
M4
6
-
-
-
-
-
-
vin3b_d0
K7
6
K7
6
-
-
-
-
vin3b_d1
M7
6
M7
6
-
-
-
-
vin3b_d2
J5
6
J5
6
-
-
-
-
vin3b_d3
K6
6
K6
6
-
-
-
-
vin3b_d4
J7
6
J7
6
-
-
-
-
vin3b_d5
J4
6
J4
6
-
-
-
-
vin3b_d6
J6
6
J6
6
-
-
-
-
vin3b_d7
H4
6
H4
6
-
-
-
-
vin3b_hsync1
H5
6
H5
6
-
-
-
-
vin3b_vsync1
H6
6
H6
6
-
-
-
-
Table 7-6. VIN4 IOSETs
Signals
IOSET1
BALL
IOSET2
MUX
IOSET3
BALL
MUX
BALL
MUX
vin4a
vin4a_d0
R6
4
B7
3
B14
8
vin4a_d1
T9
4
B8
3
J14
8
vin4a_d2
T6
4
A7
3
G13
8
vin4a_d3
T7
4
A8
3
J11
8
vin4a_d4
P6
4
C9
3
E12
8
vin4a_d5
R9
4
A9
3
F13
8
vin4a_d6
R5
4
B9
3
C12
8
vin4a_d7
P5
4
A10
3
D12
8
vin4a_d8
U2
4
E8
3
E15
8
vin4a_d9
U1
4
D9
3
A20
8
vin4a_d10
P3
4
D7
3
B15
8
vin4a_d11
R2
4
D8
3
A15
8
vin4a_d12
K7
4
A5
3
D15
8
vin4a_d13
M7
4
C6
3
B16
8
vin4a_d14
J5
4
C8
3
B17
8
vin4a_d15
K6
4
C7
3
A17
8
vin4a_d16
-
-
F11
3
C18
8
vin4a_d17
-
-
G10
3
A21
8
vin4a_d18
-
-
F10
3
G16
8
vin4a_d19
-
-
G11
3
D17
8
vin4a_d20
-
-
E9
3
AA3
8
vin4a_d21
-
-
F9
3
AB9
8
vin4a_d22
-
-
F8
3
AB3
8
vin4a_d23
-
-
E7
3
AA4
8
vin4a_hsync0
R3/ P7
4/4
C11
3
E21
8
vin4a_vsync0
T2/ N1
4/4
E11
3
F20
8
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Table 7-6. VIN4 IOSETs (continued)
Signals
IOSET1
IOSET2
BALL
MUX
vin4a_de0
H6/ P7
vin4a_fld0
P9/ J7
vin4a_clk0
IOSET3
BALL
MUX
BALL
MUX
4/5
B10
3
C23
8
4/4
D11
3
F21
8
P4
4
B11
3
B26
8
vin4b_clk1
N9
6
V1
5
-
-
vin4b_de1
P9
6
V7
5
-
-
vin4b_fld1
P4
6
W2
5
-
-
vin4b_d0
R6
6
U4
5
-
-
vin4b_d1
T9
6
V2
5
-
-
vin4b_d2
T6
6
Y1
5
-
-
vin4b_d3
T7
6
W9
5
-
-
vin4b_d4
P6
6
V9
5
-
-
vin4b_d5
R9
6
U5
5
-
-
vin4b_d6
R5
6
V5
5
-
-
vin4b_d7
P5
6
V4
5
-
-
vin4b_hsync1
N7
6
U7
5
-
-
vin4b_vsync1
R4
6
V6
5
-
-
vin4b
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for VIP1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-7 Manual
Functions Mapping for VIP1 for a definition of the Manual modes.
Table 7-7 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
212
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Table 7-7. Manual Functions Mapping for VIP1
BALL BALL NAME
VIP1_MANUAL1
VIP1_MANUAL2
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
0
1
2
3
4
U3
RMII_MHZ_5
0_CLK
1621
614
2018
279
CFG_RMII_MHZ_50_CLK
_IN
-
-
-
-
vin2a_d11
N6
gpmc_ben0
1756
1019
2235
494
CFG_GPMC_BEN0_IN
-
-
-
vin1b_hsync1
-
M4
gpmc_ben1
1684
1107
2198
568
CFG_GPMC_BEN1_IN
-
-
-
vin1b_de1
-
U4
mdio_d
1594
417
2007
36
CFG_MDIO_D_IN
-
-
-
-
vin2a_d0
V1
mdio_mclk
0
0
0
0
CFG_MDIO_MCLK_IN
-
-
-
-
vin2a_clk0
U5
rgmii0_rxc
1005
935
1932
0
CFG_RGMII0_RXC_IN
-
-
-
-
vin2a_d5
V5
rgmii0_rxctl
1579
836
1982
485
CFG_RGMII0_RXCTL_IN
-
-
-
-
vin2a_d6
W2
rgmii0_rxd0
1032
1033
1995
0
CFG_RGMII0_RXD0_IN
-
-
-
-
vin2a_fld0
Y2
rgmii0_rxd1
950
1625
1993
673
CFG_RGMII0_RXD1_IN
-
-
-
-
vin2a_d9
V3
rgmii0_rxd2
1578
832
1973
535
CFG_RGMII0_RXD2_IN
-
-
-
-
vin2a_d8
V4
rgmii0_rxd3
1022
1648
2017
740
CFG_RGMII0_RXD3_IN
-
-
-
-
vin2a_d7
W9
rgmii0_txc
1604
769
2020
393
CFG_RGMII0_TXC_IN
-
-
-
-
vin2a_d3
V9
rgmii0_txctl
1060
1389
2074
396
CFG_RGMII0_TXCTL_IN
-
-
-
-
vin2a_d4
U6
rgmii0_txd0
938
1242
2021
194
CFG_RGMII0_TXD0_IN
-
-
-
-
vin2a_d10
V6
rgmii0_txd1
1013
1679
2036
730
CFG_RGMII0_TXD1_IN
-
-
-
-
vin2a_vsync0
U7
rgmii0_txd2
1524
886
1933
526
CFG_RGMII0_TXD2_IN
-
-
-
-
vin2a_hsync0
V7
rgmii0_txd3
1079
1504
2090
490
CFG_RGMII0_TXD3_IN
-
-
-
-
vin2a_de0
V2
uart3_rxd
1530
125
1586
0
CFG_UART3_RXD_IN
-
-
-
-
vin2a_d1
Y1
uart3_txd
1572
487
1980
16
CFG_UART3_TXD_IN
-
-
-
-
vin2a_d2
AG8
vin1a_clk0
0
0
0
0
CFG_VIN1A_CLK0_IN
vin1a_clk0
-
-
-
-
AE8
vin1a_d0
1697
1087
2105
619
CFG_VIN1A_D0_IN
vin1a_d0
-
-
-
-
AD8
vin1a_d1
1589
1164
2017
757
CFG_VIN1A_D1_IN
vin1a_d1
-
-
-
-
AG3
vin1a_d10
1733
1119
2107
739
CFG_VIN1A_D10_IN
vin1a_d10
vin1b_d5
-
-
-
AG5
vin1a_d11
1563
1210
2005
788
CFG_VIN1A_D11_IN
vin1a_d11
vin1b_d4
-
-
-
AF2
vin1a_d12
1705
1647
2059
1297
CFG_VIN1A_D12_IN
vin1a_d12
vin1b_d3
-
-
-
AF6
vin1a_d13
1624
1525
2027
1141
CFG_VIN1A_D13_IN
vin1a_d13
vin1b_d2
-
-
-
AF3
vin1a_d14
1730
1655
2071
1332
CFG_VIN1A_D14_IN
vin1a_d14
vin1b_d1
-
-
-
AF4
vin1a_d15
1681
2004
1995
1764
CFG_VIN1A_D15_IN
vin1a_d15
vin1b_d0
-
-
-
AF1
vin1a_d16
1659
1813
1999
1542
CFG_VIN1A_D16_IN
vin1a_d16
vin1b_d7
-
-
-
AE3
vin1a_d17
1715
1887
2072
1540
CFG_VIN1A_D17_IN
vin1a_d17
vin1b_d6
-
-
-
AE5
vin1a_d18
1728
1898
2034
1629
CFG_VIN1A_D18_IN
vin1a_d18
vin1b_d5
-
-
-
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Table 7-7. Manual Functions Mapping for VIP1 (continued)
BALL BALL NAME
VIP1_MANUAL1
VIP1_MANUAL2
CFG REGISTER
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
vin1a_d19
1707
2006
2026
1761
AG7
vin1a_d2
1557
1414
1996
962
CFG_VIN1A_D2_IN
AE2
vin1a_d20
1695
1814
2037
1469
CFG_VIN1A_D20_IN
AE6
vin1a_d21
1757
1682
2077
1349
CFG_VIN1A_D21_IN
AD2
vin1a_d22
1683
1813
2022
1545
AD3
vin1a_d23
1833
1187
2168
AH6
vin1a_d3
1588
1289
1993
AH3
vin1a_d4
1687
949
AE1
MUXMODE
0
1
2
3
4
vin1a_d19
vin1b_d4
-
-
-
vin1a_d2
-
-
-
-
vin1a_d20
vin1b_d3
-
-
-
vin1a_d21
vin1b_d2
-
-
-
CFG_VIN1A_D22_IN
vin1a_d22
vin1b_d1
-
-
-
784
CFG_VIN1A_D23_IN
vin1a_d23
vin1b_d0
-
-
-
901
CFG_VIN1A_D3_IN
vin1a_d3
-
-
-
-
2098
499
CFG_VIN1A_D4_IN
vin1a_d4
-
-
-
-
CFG_VIN1A_D19_IN
AH5
vin1a_d5
1616
1257
2038
844
CFG_VIN1A_D5_IN
vin1a_d5
-
-
-
-
AG6
vin1a_d6
1582
1265
2002
863
CFG_VIN1A_D6_IN
vin1a_d6
-
-
-
-
AH4
vin1a_d7
1659
1255
2063
873
CFG_VIN1A_D7_IN
vin1a_d7
-
-
-
-
AG4
vin1a_d8
1681
1205
2088
759
CFG_VIN1A_D8_IN
vin1a_d8
vin1b_d7
-
-
-
AG2
vin1a_d9
1778
1168
2152
701
CFG_VIN1A_D9_IN
vin1a_d9
vin1b_d6
-
-
-
AD9
vin1a_de0
1468
1290
1926
728
CFG_VIN1A_DE0_IN
vin1a_de0
vin1b_hsync1
-
-
-
AF9
vin1a_fld0
1633
1425
2043
937
CFG_VIN1A_FLD0_IN
vin1a_fld0
vin1b_vsync1
-
-
-
AE9
vin1a_hsync0
1561
1424
1978
909
CFG_VIN1A_HSYNC0_IN
vin1a_hsync0
vin1b_fld1
-
-
-
AF8
vin1a_vsync0
1470
1369
1926
987
CFG_VIN1A_VSYNC0_IN
vin1a_vsync0
vin1b_de1
-
-
-
AH7
vin1b_clk1
69
150
242
0
CFG_VIN1B_CLK1_IN
vin1b_clk1
-
-
-
-
E1
vin2a_clk0
0
0
0
0
CFG_VIN2A_CLK0_IN
vin2a_clk0
-
-
-
-
F2
vin2a_d0
1597
561
2009
147
CFG_VIN2A_D0_IN
vin2a_d0
-
-
-
-
F3
vin2a_d1
1598
801
2015
561
CFG_VIN2A_D1_IN
vin2a_d1
-
-
-
-
D3
vin2a_d10
1576
655
2021
377
CFG_VIN2A_D10_IN
vin2a_d10
-
-
-
-
F6
vin2a_d11
1488
340
1940
19
CFG_VIN2A_D11_IN
vin2a_d11
-
-
-
-
D5
vin2a_d12
1399
612
1895
181
CFG_VIN2A_D12_IN
vin2a_d12
-
-
-
-
C2
vin2a_d13
1595
439
2063
15
CFG_VIN2A_D13_IN
vin2a_d13
-
-
-
-
C3
vin2a_d14
1480
243
1709
0
CFG_VIN2A_D14_IN
vin2a_d14
-
-
-
-
C4
vin2a_d15
1415
755
1899
369
CFG_VIN2A_D15_IN
vin2a_d15
-
-
-
-
B2
vin2a_d16
1341
653
1821
317
CFG_VIN2A_D16_IN
vin2a_d16
-
vin2b_d7
-
-
D6
vin2a_d17
1396
724
1880
349
CFG_VIN2A_D17_IN
vin2a_d17
-
vin2b_d6
-
-
C5
vin2a_d18
1582
364
1963
0
CFG_VIN2A_D18_IN
vin2a_d18
-
vin2b_d5
-
-
A3
vin2a_d19
1308
289
1681
0
CFG_VIN2A_D19_IN
vin2a_d19
-
vin2b_d4
-
-
D1
vin2a_d2
1600
323
2021
0
CFG_VIN2A_D2_IN
vin2a_d2
-
-
-
-
214
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-7. Manual Functions Mapping for VIP1 (continued)
BALL BALL NAME
VIP1_MANUAL1
VIP1_MANUAL2
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
0
1
2
3
4
B3
vin2a_d20
1307
586
1772
299
CFG_VIN2A_D20_IN
vin2a_d20
-
vin2b_d3
-
-
B4
vin2a_d21
1301
640
1787
282
CFG_VIN2A_D21_IN
vin2a_d21
-
vin2b_d2
-
-
B5
vin2a_d22
1316
534
1789
223
CFG_VIN2A_D22_IN
vin2a_d22
-
vin2b_d1
-
-
A4
vin2a_d23
1311
613
1788
286
CFG_VIN2A_D23_IN
vin2a_d23
-
vin2b_d0
-
-
E2
vin2a_d3
1765
720
2142
492
CFG_VIN2A_D3_IN
vin2a_d3
-
-
-
-
D2
vin2a_d4
1680
282
2071
0
CFG_VIN2A_D4_IN
vin2a_d4
-
-
-
-
F4
vin2a_d5
1791
696
2155
461
CFG_VIN2A_D5_IN
vin2a_d5
-
-
-
-
C1
vin2a_d6
1538
175
1849
0
CFG_VIN2A_D6_IN
vin2a_d6
-
-
-
-
E4
vin2a_d7
1546
451
1977
192
CFG_VIN2A_D7_IN
vin2a_d7
-
-
-
-
F5
vin2a_d8
1522
650
1966
391
CFG_VIN2A_D8_IN
vin2a_d8
-
-
-
-
E6
vin2a_d9
1546
578
1996
270
CFG_VIN2A_D9_IN
vin2a_d9
-
-
-
-
G2
vin2a_de0
1548
623
2036
213
CFG_VIN2A_DE0_IN
vin2a_de0
vin2a_fld0
vin2b_fld1
vin2b_de1
-
H7
vin2a_fld0
1771
815
2162
566
CFG_VIN2A_FLD0_IN
vin2a_fld0
-
vin2b_clk1
-
-
G1
vin2a_hsync0
1703
587
2071
225
CFG_VIN2A_HSYNC0_IN
vin2a_hsync0
-
-
vin2b_hsync1
-
G6
vin2a_vsync0
1486
464
1895
53
CFG_VIN2A_VSYNC0_IN
vin2a_vsync0
-
-
vin2b_vsync1
-
Manual IO Timings Modes must be used to guarantee some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-8 Manual Functions Mapping for VIP1 2B for a definition of the Manual modes.
Table 7-8 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-8. Manual Functions Mapping for VIP1 2B
BALL
BALL NAME
VIP1_2B_MANUAL1
VIP1_2B_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
2
3
4
AC5
gpio6_10
1830
911
2136
593
CFG_GPIO6_10_IN
-
-
vin2b_hsync1
AB4
gpio6_11
1797
1159
2088
926
CFG_GPIO6_11_IN
-
-
vin2b_vsync1
AC4
mmc3_cmd
1769
980
2092
650
CFG_MMC3_CMD_IN
-
-
vin2b_d6
AC7
mmc3_dat0
1678
984
2027
691
CFG_MMC3_DAT0_IN
-
-
vin2b_d5
AC6
mmc3_dat1
1664
883
2031
491
CFG_MMC3_DAT1_IN
-
-
vin2b_d4
AC9
mmc3_dat2
1672
439
2065
0
CFG_MMC3_DAT2_IN
-
-
vin2b_d3
AC3
mmc3_dat3
1762
1078
2089
799
CFG_MMC3_DAT3_IN
-
-
vin2b_d2
AC8
mmc3_dat4
1766
583
2125
135
CFG_MMC3_DAT4_IN
-
-
vin2b_d1
AD6
mmc3_dat5
1777
577
2072
362
CFG_MMC3_DAT5_IN
-
-
vin2b_d0
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Table 7-8. Manual Functions Mapping for VIP1 2B (continued)
BALL
BALL NAME
VIP1_2B_MANUAL1
VIP1_2B_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
2
3
4
AB8
mmc3_dat6
1675
808
2035
431
CFG_MMC3_DAT6_IN
-
-
vin2b_de1
AB5
mmc3_dat7
0
0
0
0
CFG_MMC3_DAT7_IN
-
-
vin2b_clk1
B2
vin2a_d16
1181
0
1424
0
CFG_VIN2A_D16_IN
vin2b_d7
-
-
D6
vin2a_d17
1317
0
1545
0
CFG_VIN2A_D17_IN
vin2b_d6
-
-
C5
vin2a_d18
1132
0
1240
0
CFG_VIN2A_D18_IN
vin2b_d5
-
-
A3
vin2a_d19
749
0
919
0
CFG_VIN2A_D19_IN
vin2b_d4
-
-
B3
vin2a_d20
1078
0
1320
0
CFG_VIN2A_D20_IN
vin2b_d3
-
-
B4
vin2a_d21
1119
0
1357
0
CFG_VIN2A_D21_IN
vin2b_d2
-
-
B5
vin2a_d22
1089
0
1306
0
CFG_VIN2A_D22_IN
vin2b_d1
-
-
A4
vin2a_d23
1118
0
1362
0
CFG_VIN2A_D23_IN
vin2b_d0
-
-
G2
vin2a_de0
1371
420
1813
86
CFG_VIN2A_DE0_IN
vin2b_fld1
vin2b_de1
-
H7
vin2a_fld0
0
0
0
0
CFG_VIN2A_FLD0_IN
vin2b_clk1
-
-
G1
vin2a_hsync0
1605
0
1674
0
CFG_VIN2A_HSYNC0_IN
-
vin2b_hsync1
-
G6
vin2a_vsync0
1231
0
1300
0
CFG_VIN2A_VSYNC0_IN
-
vin2b_vsync1
-
Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-9 Manual Functions Mapping for VIP2 for a definition of the Manual modes.
Table 7-9 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-9. Manual Functions Mapping for VIP2
BALL
BALL NAME
VIP2_MANUAL 1
A_DELAY
(ps)
VIP2_MANUAL2
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
2
3
4
5
6
R6
gpmc_a0
2216
947
2519
702
CFG_GPMC_A0_IN
vin3a_d16
-
vin4a_d0
-
-
T9
gpmc_a1
2078
1022
2384
778
CFG_GPMC_A1_IN
vin3a_d17
-
vin4a_d1
-
-
N9
gpmc_a10
2108
823
2435
411
CFG_GPMC_A10_IN
vin3a_de0
-
-
-
-
P9
gpmc_a11
2068
977
2379
755
CFG_GPMC_A11_IN
vin3a_fld0
-
vin4a_fld0
-
-
K7
gpmc_a19
1740
123
1743
0
CFG_GPMC_A19_IN
-
-
vin4a_d12
-
vin3b_d0
T6
gpmc_a2
2280
1298
2499
1127
CFG_GPMC_A2_IN
vin3a_d18
-
vin4a_d2
-
-
M7
gpmc_a20
1628
30
1529
0
CFG_GPMC_A20_IN
-
-
vin4a_d13
-
vin3b_d1
J5
gpmc_a21
1687
217
1779
0
CFG_GPMC_A21_IN
-
-
vin4a_d14
-
vin3b_d2
K6
gpmc_a22
1595
151
1620
0
CFG_GPMC_A22_IN
-
-
vin4a_d15
-
vin3b_d3
216
Timing Requirements and Switching Characteristics
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DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-9. Manual Functions Mapping for VIP2 (continued)
BALL
BALL NAME
VIP2_MANUAL 1
VIP2_MANUAL2
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
2
3
4
5
6
J7
gpmc_a23
1366
0
1363
0
CFG_GPMC_A23_IN
-
-
vin4a_fld0
-
vin3b_d4
J4
gpmc_a24
1554
343
1765
0
CFG_GPMC_A24_IN
-
-
vin4a_d8
-
vin3b_d5
J6
gpmc_a25
1652
268
1808
0
CFG_GPMC_A25_IN
-
-
vin4a_d9
-
vin3b_d6
H4
gpmc_a26
1546
281
1669
0
CFG_GPMC_A26_IN
-
-
vin4a_d10
-
vin3b_d7
H5
gpmc_a27
1534
198
1611
0
CFG_GPMC_A27_IN
-
-
vin4a_d11
-
vin3b_hsync
1
T7
gpmc_a3
2246
1318
2455
1181
CFG_GPMC_A3_IN
vin3a_d19
-
vin4a_d3
-
-
P6
gpmc_a4
2266
1216
2486
1039
CFG_GPMC_A4_IN
vin3a_d20
-
vin4a_d4
-
-
R9
gpmc_a5
2185
1122
2456
938
CFG_GPMC_A5_IN
vin3a_d21
-
vin4a_d5
-
-
R5
gpmc_a6
2206
782
2463
573
CFG_GPMC_A6_IN
vin3a_d22
-
vin4a_d6
-
-
P5
gpmc_a7
2369
1025
2608
783
CFG_GPMC_A7_IN
vin3a_d23
-
vin4a_d7
-
-
N7
gpmc_a8
2154
978
2430
656
CFG_GPMC_A8_IN
vin3a_hsync
0
-
-
-
-
R4
gpmc_a9
2185
1152
2465
850
CFG_GPMC_A9_IN
vin3a_vsync0
-
-
-
-
M6
gpmc_ad0
1908
620
2316
301
CFG_GPMC_AD0_IN
vin3a_d0
-
-
-
-
M2
gpmc_ad1
2117
382
2440
70
CFG_GPMC_AD1_IN
vin3a_d1
-
-
-
-
J1
gpmc_ad10
1968
686
2324
406
CFG_GPMC_AD10_IN
vin3a_d10
-
-
-
-
J2
gpmc_ad11
1853
689
2278
352
CFG_GPMC_AD11_IN
vin3a_d11
-
-
-
-
H1
gpmc_ad12
1910
497
2297
160
CFG_GPMC_AD12_IN
vin3a_d12
-
-
-
-
J3
gpmc_ad13
1869
436
2278
108
CFG_GPMC_AD13_IN
vin3a_d13
-
-
-
-
H2
gpmc_ad14
1895
147
2035
0
CFG_GPMC_AD14_IN
vin3a_d14
-
-
-
-
H3
gpmc_ad15
1917
655
2279
378
CFG_GPMC_AD15_IN
vin3a_d15
-
-
-
-
L5
gpmc_ad2
2097
666
2404
446
CFG_GPMC_AD2_IN
vin3a_d2
-
-
-
-
M1
gpmc_ad3
1954
581
2343
212
CFG_GPMC_AD3_IN
vin3a_d3
-
-
-
-
L6
gpmc_ad4
2034
610
2355
322
CFG_GPMC_AD4_IN
vin3a_d4
-
-
-
-
L4
gpmc_ad5
1965
484
2337
192
CFG_GPMC_AD5_IN
vin3a_d5
-
-
-
-
L3
gpmc_ad6
1861
635
2270
314
CFG_GPMC_AD6_IN
vin3a_d6
-
-
-
-
L2
gpmc_ad7
2004
507
2339
259
CFG_GPMC_AD7_IN
vin3a_d7
-
-
-
-
L1
gpmc_ad8
1945
853
2308
577
CFG_GPMC_AD8_IN
vin3a_d8
-
-
-
K2
gpmc_ad9
1914
539
2334
166
CFG_GPMC_AD9_IN
vin3a_d9
-
-
-
-
N6
gpmc_ben0
1806
0
1722
0
CFG_GPMC_BEN0_IN
-
-
-
-
vin3b_de1
M4
gpmc_ben1
1879
20
1840
0
CFG_GPMC_BEN1_IN
-
-
vin3b_clk1
-
vin3b_fld1
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Table 7-9. Manual Functions Mapping for VIP2 (continued)
BALL
BALL NAME
VIP2_MANUAL 1
VIP2_MANUAL2
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
2
3
4
5
6
-
-
vin4a_hsync
0
vin4a_de0
vin3b_clk1
vin3b_vsync1
P7
gpmc_clk
0
0
0
0
CFG_GPMC_CLK_IN
H6
gpmc_cs1
1505
41
1388
0
CFG_GPMC_CS1_IN
-
-
vin4a_de0
-
P1
gpmc_cs3
0
0
0
0
CFG_GPMC_CS3_IN
vin3a_clk0
-
-
-
-
AF1
vin1a_d16
1803
1679
2244
1202
CFG_VIN1A_D16_IN
-
-
-
-
vin3a_d0
AE3
vin1a_d17
1871
1654
2321
1116
CFG_VIN1A_D17_IN
-
-
-
-
vin3a_d1
AE5
vin1a_d18
1875
1742
2280
1288
CFG_VIN1A_D18_IN
-
-
-
-
vin3a_d2
AE1
vin1a_d19
1844
1759
2282
1281
CFG_VIN1A_D19_IN
-
-
-
-
vin3a_d3
AE2
vin1a_d20
1845
1624
2284
1090
CFG_VIN1A_D20_IN
-
-
-
-
vin3a_d4
AE6
vin1a_d21
1906
1520
2324
1000
CFG_VIN1A_D21_IN
-
-
-
-
vin3a_d5
AD2
vin1a_d22
1807
1437
2278
915
CFG_VIN1A_D22_IN
-
-
-
-
vin3a_d6
AD3
vin1a_d23
1996
997
2423
398
CFG_VIN1A_D23_IN
-
-
-
-
vin3a_d7
AH7
vin1b_clk1
0
0
0
0
CFG_VIN1B_CLK1_IN
-
-
-
-
vin3a_clk0
B2
vin2a_d16
1329
528
1779
0
CFG_VIN2A_D16_IN
-
-
-
-
vin3a_d8
D6
vin2a_d17
1270
677
1844
0
CFG_VIN2A_D17_IN
-
-
-
-
vin3a_d9
C5
vin2a_d18
1494
411
1767
0
CFG_VIN2A_D18_IN
-
-
-
-
vin3a_d10
A3
vin2a_d19
1225
154
1254
0
CFG_VIN2A_D19_IN
-
-
-
-
vin3a_d11
B3
vin2a_d20
1212
450
1597
0
CFG_VIN2A_D20_IN
-
-
-
vin3a_de0
vin3a_d12
B4
vin2a_d21
1232
494
1662
0
CFG_VIN2A_D21_IN
-
-
-
vin3a_fld0
vin3a_d13
B5
vin2a_d22
1203
503
1641
0
CFG_VIN2A_D22_IN
-
-
-
vin3a_hsync
0
vin3a_d14
A4
vin2a_d23
1214
599
1748
0
CFG_VIN2A_D23_IN
-
-
-
vin3a_vsync0
vin3a_d15
D11
vout1_clk
2047
735
2391
637
CFG_VOUT1_CLK_IN
-
vin4a_fld0
vin3a_fld0
-
-
F11
vout1_d0
2135
987
2403
965
CFG_VOUT1_D0_IN
-
vin4a_d16
vin3a_d16
-
-
G10
vout1_d1
2048
955
2368
880
CFG_VOUT1_D1_IN
-
vin4a_d17
vin3a_d17
-
-
D7
vout1_d10
1970
855
2347
724
CFG_VOUT1_D10_IN
-
vin4a_d10
vin3a_d10
-
-
D8
vout1_d11
2111
893
2389
861
CFG_VOUT1_D11_IN
-
vin4a_d11
vin3a_d11
-
-
A5
vout1_d12
2018
841
2356
748
CFG_VOUT1_D12_IN
-
vin4a_d12
vin3a_d12
-
-
C6
vout1_d13
2073
805
2382
731
CFG_VOUT1_D13_IN
-
vin4a_d13
vin3a_d13
-
-
C8
vout1_d14
2112
770
2401
703
CFG_VOUT1_D14_IN
-
vin4a_d14
vin3a_d14
-
-
C7
vout1_d15
2132
831
2434
771
CFG_VOUT1_D15_IN
-
vin4a_d15
vin3a_d15
-
-
B7
vout1_d16
1996
632
2338
536
CFG_VOUT1_D16_IN
-
vin4a_d0
vin3a_d0
-
-
218
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-9. Manual Functions Mapping for VIP2 (continued)
BALL
BALL NAME
VIP2_MANUAL 1
VIP2_MANUAL2
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
2
3
4
5
6
B8
vout1_d17
2190
790
2442
775
CFG_VOUT1_D17_IN
-
vin4a_d1
vin3a_d1
-
-
A7
vout1_d18
2100
604
2385
565
CFG_VOUT1_D18_IN
-
vin4a_d2
vin3a_d2
-
-
A8
vout1_d19
2108
286
2424
168
CFG_VOUT1_D19_IN
-
vin4a_d3
vin3a_d3
-
-
F10
vout1_d2
1979
1020
2335
909
CFG_VOUT1_D2_IN
-
vin4a_d18
vin3a_d18
-
-
C9
vout1_d20
2031
967
2362
881
CFG_VOUT1_D20_IN
-
vin4a_d4
vin3a_d4
-
-
A9
vout1_d21
2039
450
2350
384
CFG_VOUT1_D21_IN
-
vin4a_d5
vin3a_d5
-
-
B9
vout1_d22
2037
583
2369
497
CFG_VOUT1_D22_IN
-
vin4a_d6
vin3a_d6
-
-
A10
vout1_d23
1768
740
2246
508
CFG_VOUT1_D23_IN
-
vin4a_d7
vin3a_d7
-
-
G11
vout1_d3
2099
881
2382
844
CFG_VOUT1_D3_IN
-
vin4a_d19
vin3a_d19
-
-
E9
vout1_d4
2120
786
2387
756
CFG_VOUT1_D4_IN
-
vin4a_d20
vin3a_d20
-
-
F9
vout1_d5
1965
857
2299
769
CFG_VOUT1_D5_IN
-
vin4a_d21
vin3a_d21
-
-
F8
vout1_d6
2139
680
2366
699
CFG_VOUT1_D6_IN
-
vin4a_d22
vin3a_d22
-
-
E7
vout1_d7
2122
912
2360
920
CFG_VOUT1_D7_IN
-
vin4a_d23
vin3a_d23
-
-
E8
vout1_d8
2073
906
2372
853
CFG_VOUT1_D8_IN
-
vin4a_d8
vin3a_d8
-
-
D9
vout1_d9
2097
934
2386
879
CFG_VOUT1_D9_IN
-
vin4a_d9
vin3a_d9
-
-
B10
vout1_de
2021
527
2366
428
CFG_VOUT1_DE_IN
-
vin4a_de0
vin3a_de0
-
-
B11
vout1_fld
0
0
0
0
CFG_VOUT1_FLD_IN
-
vin4a_clk0
vin3a_clk0
-
-
C11
vout1_hsync
1775
486
2272
164
CFG_VOUT1_HSYNC_IN
-
vin4a_hsync
0
vin3a_hsync
0
-
-
E11
vout1_vsync
1917
314
2301
0
CFG_VOUT1_VSYNC_IN
-
vin4a_vsync0 vin3a_vsync0
-
-
Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-10 Manual Functions Mapping for VIP2 4A for a definition of the Manual modes.
Table 7-10 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-10. Manual Functions Mapping for VIP2 4A
BALL
BALL NAME
VIP2_4A_MANUAL1
VIP2_4A_MANUAL2
CFG REGISTER
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
R6
gpmc_a0
1801
521
2268
0
MUXMODE
3
4
5
CFG_GPMC_A0_IN
-
vin4a_d0
-
T9
gpmc_a1
1668
488
2135
0
CFG_GPMC_A1_IN
-
vin4a_d1
-
P9
gpmc_a11
1694
308
2026
0
CFG_GPMC_A11_IN
-
vin4a_fld0
-
P4
gpmc_a12
0
0
0
0
CFG_GPMC_A12_IN
-
vin4a_clk0
-
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Table 7-10. Manual Functions Mapping for VIP2 4A (continued)
BALL
BALL NAME
VIP2_4A_MANUAL1
VIP2_4A_MANUAL2
CFG REGISTER
3
4
5
R3
gpmc_a13
1529
570
2029
38
CFG_GPMC_A13_IN
-
vin4a_hsync0
-
T2
gpmc_a14
1747
753
2266
261
CFG_GPMC_A14_IN
-
vin4a_vsync0
-
U2
gpmc_a15
1536
336
1882
0
CFG_GPMC_A15_IN
-
vin4a_d8
-
U1
gpmc_a16
1662
293
1936
0
CFG_GPMC_A16_IN
-
vin4a_d9
-
P3
gpmc_a17
1637
247
1851
0
CFG_GPMC_A17_IN
-
vin4a_d10
-
R2
gpmc_a18
1454
0
1369
0
CFG_GPMC_A18_IN
-
vin4a_d11
-
K7
gpmc_a19
1577
205
1634
0
CFG_GPMC_A19_IN
-
vin4a_d12
-
T6
gpmc_a2
1891
747
2369
238
CFG_GPMC_A2_IN
-
vin4a_d2
-
M7
gpmc_a20
1398
220
1450
0
CFG_GPMC_A20_IN
-
vin4a_d13
-
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
MUXMODE
J5
gpmc_a21
1521
329
1691
0
CFG_GPMC_A21_IN
-
vin4a_d14
-
K6
gpmc_a22
1383
273
1488
0
CFG_GPMC_A22_IN
-
vin4a_d15
-
J7
gpmc_a23
1163
0
1147
0
CFG_GPMC_A23_IN
-
vin4a_fld0
-
T7
gpmc_a3
1820
786
2325
271
CFG_GPMC_A3_IN
-
vin4a_d3
-
P6
gpmc_a4
1865
662
2359
126
CFG_GPMC_A4_IN
-
vin4a_d4
-
R9
gpmc_a5
1722
629
2260
53
CFG_GPMC_A5_IN
-
vin4a_d5
-
R5
gpmc_a6
1755
279
1990
0
CFG_GPMC_A6_IN
-
vin4a_d6
-
P5
gpmc_a7
1979
506
2410
0
CFG_GPMC_A7_IN
-
vin4a_d7
-
N1
gpmc_advn_ale
1793
267
2045
0
CFG_GPMC_ADVN_ALE_IN
-
vin4a_vsync0
-
P7
gpmc_clk
1738
309
2040
0
CFG_GPMC_CLK_IN
-
vin4a_hsync0
vin4a_de0
H6
gpmc_cs1
1379
95
1361
0
CFG_GPMC_CS1_IN
-
vin4a_de0
-
D11
vout1_clk
2090
401
2409
357
CFG_VOUT1_CLK_IN
vin4a_fld0
-
-
F11
vout1_d0
2139
961
2394
981
CFG_VOUT1_D0_IN
vin4a_d16
-
-
G10
vout1_d1
1993
878
2347
799
CFG_VOUT1_D1_IN
vin4a_d17
-
-
D7
vout1_d10
1976
678
2346
583
CFG_VOUT1_D10_IN
vin4a_d10
-
-
D8
vout1_d11
2135
749
2393
767
CFG_VOUT1_D11_IN
vin4a_d11
-
-
A5
vout1_d12
2014
696
2351
634
CFG_VOUT1_D12_IN
vin4a_d12
-
-
C6
vout1_d13
2035
590
2370
531
CFG_VOUT1_D13_IN
vin4a_d13
-
-
C8
vout1_d14
2108
861
2385
860
CFG_VOUT1_D14_IN
vin4a_d14
-
-
C7
vout1_d15
2074
682
2423
609
CFG_VOUT1_D15_IN
vin4a_d15
-
-
B7
vout1_d16
1976
579
2331
500
CFG_VOUT1_D16_IN
vin4a_d0
-
-
B8
vout1_d17
2203
505
2464
509
CFG_VOUT1_D17_IN
vin4a_d1
-
-
A7
vout1_d18
2096
412
2394
390
CFG_VOUT1_D18_IN
vin4a_d2
-
-
220
Timing Requirements and Switching Characteristics
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DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-10. Manual Functions Mapping for VIP2 4A (continued)
BALL
BALL NAME
VIP2_4A_MANUAL1
VIP2_4A_MANUAL2
CFG REGISTER
MUXMODE
3
4
5
A8
vout1_d19
2106
72
2423
21
CFG_VOUT1_D19_IN
vin4a_d3
-
-
F10
vout1_d2
2023
648
2374
572
CFG_VOUT1_D2_IN
vin4a_d18
-
-
C9
vout1_d20
2027
767
2370
700
CFG_VOUT1_D20_IN
vin4a_d4
-
-
A9
vout1_d21
2026
184
2354
128
CFG_VOUT1_D21_IN
vin4a_d5
-
-
B9
vout1_d22
2061
195
2397
135
CFG_VOUT1_D22_IN
vin4a_d6
-
-
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
A10
vout1_d23
1764
607
2251
396
CFG_VOUT1_D23_IN
vin4a_d7
-
-
G11
vout1_d3
2053
757
2377
707
CFG_VOUT1_D3_IN
vin4a_d19
-
-
E9
vout1_d4
2119
617
2392
619
CFG_VOUT1_D4_IN
vin4a_d20
-
-
F9
vout1_d5
1951
712
2305
633
CFG_VOUT1_D5_IN
vin4a_d21
-
-
F8
vout1_d6
2119
515
2365
543
CFG_VOUT1_D6_IN
vin4a_d22
-
-
E7
vout1_d7
2119
779
2363
810
CFG_VOUT1_D7_IN
vin4a_d23
-
-
E8
vout1_d8
2043
807
2357
768
CFG_VOUT1_D8_IN
vin4a_d8
-
-
D9
vout1_d9
2166
643
2412
671
CFG_VOUT1_D9_IN
vin4a_d9
-
-
B10
vout1_de
1982
410
2353
314
CFG_VOUT1_DE_IN
vin4a_de0
-
-
B11
vout1_fld
0
0
0
0
CFG_VOUT1_FLD_IN
vin4a_clk0
-
-
C11
vout1_hsync
1755
305
2269
4
CFG_VOUT1_HSYNC_IN
vin4a_hsync0
-
-
E11
vout1_vsync
1924
8
2066
0
CFG_VOUT1_VSYNC_IN
vin4a_vsync0
-
-
Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-11 Manual Functions Mapping for VIP2 4A IOSET3 for a definition of the Manual modes.
Table 7-11 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-11. Manual Functions Mapping for VIP2 4A IOSET3
BALL
BALL NAME
VIP2_4A_IOSET3_MANUAL1
VIP2_4A_IOSET3_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
CFG REGISTER
MUXMODE
8
E21
gpio6_14
683
0
939
0
CFG_GPIO6_14_IN
vin4a_hsync0
F20
gpio6_15
1065
0
1321
0
CFG_GPIO6_15_IN
vin4a_vsync0
F21
gpio6_16
858
0
1114
0
CFG_GPIO6_16_IN
vin4a_fld0
B14
mcasp1_aclkr
1711
23
1990
0
CFG_MCASP1_ACLKR_IN
vin4a_d0
G13
mcasp1_axr2
2131
1054
2423
1073
CFG_MCASP1_AXR2_IN
vin4a_d2
J11
mcasp1_axr3
2267
691
2573
696
CFG_MCASP1_AXR3_IN
vin4a_d3
E12
mcasp1_axr4
2089
813
2441
773
CFG_MCASP1_AXR4_IN
vin4a_d4
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Table 7-11. Manual Functions Mapping for VIP2 4A IOSET3 (continued)
BALL
BALL NAME
VIP2_4A_IOSET3_MANUAL1
VIP2_4A_IOSET3_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
F13
mcasp1_axr5
2061
858
2430
799
CFG_MCASP1_AXR5_IN
vin4a_d5
C12
mcasp1_axr6
2151
595
2539
480
CFG_MCASP1_AXR6_IN
vin4a_d6
D12
mcasp1_axr7
2112
J14
mcasp1_fsr
1714
931
2421
932
CFG_MCASP1_AXR7_IN
vin4a_d7
323
2248
44
CFG_MCASP1_FSR_IN
E15
mcasp2_aclkr
vin4a_d1
1462
76
1795
0
CFG_MCASP2_ACLKR_IN
vin4a_d8
B15
A15
mcasp2_axr0
1578
833
2113
554
CFG_MCASP2_AXR0_IN
vin4a_d10
mcasp2_axr1
1785
396
2279
212
CFG_MCASP2_AXR1_IN
vin4a_d11
D15
mcasp2_axr4
1765
485
2299
206
CFG_MCASP2_AXR4_IN
vin4a_d12
B16
mcasp2_axr5
1644
509
2179
230
CFG_MCASP2_AXR5_IN
vin4a_d13
B17
mcasp2_axr6
1098
0
1354
0
CFG_MCASP2_AXR6_IN
vin4a_d14
A17
mcasp2_axr7
1242
521
1777
243
CFG_MCASP2_AXR7_IN
vin4a_d15
A20
mcasp2_fsr
1328
130
1713
0
CFG_MCASP2_FSR_IN
vin4a_d9
8
C18
mcasp4_aclkx
1033
0
1166
0
CFG_MCASP4_ACLKX_IN
vin4a_d16
G16
mcasp4_axr0
2147
358
2529
221
CFG_MCASP4_AXR0_IN
vin4a_d18
D17
mcasp4_axr1
2140
676
2482
645
CFG_MCASP4_AXR1_IN
vin4a_d19
A21
mcasp4_fsx
2140
339
2554
165
CFG_MCASP4_FSX_IN
vin4a_d17
AA3
mcasp5_aclkx
2846
2620
3059
2547
CFG_MCASP5_ACLKX_IN
vin4a_d20
AB3
mcasp5_axr0
2880
3301
3040
3417
CFG_MCASP5_AXR0_IN
vin4a_d22
AA4
mcasp5_axr1
2851
3586
3042
3593
CFG_MCASP5_AXR1_IN
vin4a_d23
AB9
mcasp5_fsx
2847
2856
3031
2890
CFG_MCASP5_FSX_IN
vin4a_d21
B26
xref_clk2
0
0
0
0
CFG_XREF_CLK2_IN
vin4a_clk0
C23
xref_clk3
927
0
1183
0
CFG_XREF_CLK3_IN
vin4a_de0
Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-12 Manual Functions Mapping for VIP2 4B for a definition of the Manual modes.
Table 7-12 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-12. Manual Functions Mapping for VIP2 4B
BALL
BALL NAME
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
5
6
R6
gpmc_a0
1861
901
2102
660
CFG_GPMC_A0_IN
-
vin4b_d0
T9
gpmc_a1
1652
891
1955
583
CFG_GPMC_A1_IN
-
vin4b_d1
222
VIP2_4B_MANUAL1
Timing Requirements and Switching Characteristics
VIP2_4B_MANUAL2
CFG REGISTER
MUXMODE
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Table 7-12. Manual Functions Mapping for VIP2 4B (continued)
BALL
BALL NAME
VIP2_4B_MANUAL1
VIP2_4B_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
5
6
N9
gpmc_a10
0
0
0
0
CFG_GPMC_A10_IN
-
vin4b_clk1
P9
gpmc_a11
1783
1178
1975
1021
CFG_GPMC_A11_IN
-
vin4b_de1
P4
gpmc_a12
1903
853
2076
664
CFG_GPMC_A12_IN
-
vin4b_fld1
T6
gpmc_a2
1888
1212
2065
994
CFG_GPMC_A2_IN
-
vin4b_d2
T7
gpmc_a3
1839
1274
2025
1075
CFG_GPMC_A3_IN
-
vin4b_d3
P6
gpmc_a4
1868
1113
2058
869
CFG_GPMC_A4_IN
-
vin4b_d4
R9
gpmc_a5
1757
1079
2028
802
CFG_GPMC_A5_IN
-
vin4b_d5
R5
gpmc_a6
1800
670
2032
421
CFG_GPMC_A6_IN
-
vin4b_d6
P5
gpmc_a7
1967
898
2179
597
CFG_GPMC_A7_IN
-
vin4b_d7
N7
gpmc_a8
1731
959
1993
559
CFG_GPMC_A8_IN
-
vin4b_hsync1
R4
gpmc_a9
1766
1150
2022
834
CFG_GPMC_A9_IN
-
vin4b_vsync1
U4
mdio_d
1602
506
1931
283
CFG_MDIO_D_IN
vin4b_d0
-
V1
mdio_mclk
0
0
0
0
CFG_MDIO_MCLK_IN
vin4b_clk1
-
U5
rgmii0_rxc
1678
887
1987
663
CFG_RGMII0_RXC_IN
vin4b_d5
-
V5
rgmii0_rxctl
1595
932
1903
748
CFG_RGMII0_RXCTL_IN
vin4b_d6
-
W2
rgmii0_rxd0
1707
464
2010
160
CFG_RGMII0_RXD0_IN
vin4b_fld1
-
V4
rgmii0_rxd3
1662
1146
1943
996
CFG_RGMII0_RXD3_IN
vin4b_d7
-
W9
rgmii0_txc
1639
1195
1970
1006
CFG_RGMII0_TXC_IN
vin4b_d3
-
V9
rgmii0_txctl
1695
1226
1952
1113
CFG_RGMII0_TXCTL_IN
vin4b_d4
-
V6
rgmii0_txd1
1693
1118
1951
1003
CFG_RGMII0_TXD1_IN
vin4b_vsync1
-
U7
rgmii0_txd2
1522
1004
1895
685
CFG_RGMII0_TXD2_IN
vin4b_hsync1
-
V7
rgmii0_txd3
1777
957
2018
787
CFG_RGMII0_TXD3_IN
vin4b_de1
-
V2
uart3_rxd
1537
236
1762
0
CFG_UART3_RXD_IN
vin4b_d1
-
Y1
uart3_txd
1575
645
1933
276
CFG_UART3_TXD_IN
vin4b_d2
-
Manual IO Timings Modes must be used to guarantee some IO timings for VIP2. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-13 Manual Functions Mapping for VIP2 3B IOSET2 for a definition of the Manual modes.
Table 7-13 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Timing Requirements and Switching Characteristics
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Table 7-13. Manual Functions Mapping for VIP2 3B IOSET2
BALL
BALL NAME
VIP2_3B_IOSET2_MANUAL1
VIP2_3B_IOSET2_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
CFG REGISTER
MUXMODE
4
6
K7
gpmc_a19
1505
1172
1854
799
CFG_GPMC_A19_IN
-
vin3b_d0
M7
gpmc_a20
1394
1074
1723
716
CFG_GPMC_A20_IN
-
vin3b_d1
J5
gpmc_a21
1452
1266
1789
900
CFG_GPMC_A21_IN
-
vin3b_d2
K6
gpmc_a22
1360
1200
1684
847
CFG_GPMC_A22_IN
-
vin3b_d3
J7
gpmc_a23
1446
735
1831
443
CFG_GPMC_A23_IN
-
vin3b_d4
J4
gpmc_a24
1329
1360
1686
970
CFG_GPMC_A24_IN
-
vin3b_d5
J6
gpmc_a25
1417
1318
1757
962
CFG_GPMC_A25_IN
-
vin3b_d6
H4
gpmc_a26
1321
1298
1680
880
CFG_GPMC_A26_IN
-
vin3b_d7
H5
gpmc_a27
1309
1215
1669
834
CFG_GPMC_A27_IN
-
vin3b_hsync1
N6
gpmc_ben0
1677
944
1994
638
CFG_GPMC_BEN0_IN
-
vin3b_de1
M4
gpmc_ben1
0
0
0
0
CFG_GPMC_BEN1_IN
vin3b_clk1
vin3b_fld1
H6
gpmc_cs1
1280
1058
1620
664
CFG_GPMC_CS1_IN
-
vin3b_vsync1
224
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Manual IO Timings Modes must be used to guarantee some IO timings for VIP3. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-14 Manual
Functions Mapping for VIP3 for a definition of the Manual modes.
Table 7-14 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-14. Manual Functions Mapping for VIP3
BAL
L
BALL NAME
AC5
AB4
VIP3_MANUAL1
A_DELAY
(ps)
G_DELAY
(ps)
gpio6_10
774
gpio6_11
2453
C14
mcasp1_aclkx
G12
VIP3_MANUAL2
A_DELAY
(ps)
G_DELAY
(ps)
2462
765
2551
3000
2863
2719
1400
154
1698
mcasp1_axr0
2055
612
F12
mcasp1_axr1
1623
B13
mcasp1_axr10
A12
mcasp1_axr11
E14
CFG REGISTER
MUXMODE
7
9
CFG_GPIO6_10_IN
-
vin5a_clk0
CFG_GPIO6_11_IN
-
vin5a_de0
0
CFG_MCASP1_ACLKX_IN
vin6a_fld0
-
2459
381
CFG_MCASP1_AXR0_IN
vin6a_vsyn
c0
-
338
2098
0
CFG_MCASP1_AXR1_IN
vin6a_hsyn
c0
-
1625
92
1681
0
CFG_MCASP1_AXR10_IN
vin6a_d13
-
1509
714
2048
317
CFG_MCASP1_AXR11_IN
vin6a_d12
-
mcasp1_axr12
1189
619
1729
222
CFG_MCASP1_AXR12_IN
vin6a_d11
-
A13
mcasp1_axr13
1546
265
1954
0
CFG_MCASP1_AXR13_IN
vin6a_d10
-
G14
mcasp1_axr14
1305
0
1448
0
CFG_MCASP1_AXR14_IN
vin6a_d9
-
F14
mcasp1_axr15
1342
313
1798
0
CFG_MCASP1_AXR15_IN
vin6a_d8
-
B12
mcasp1_axr8
1833
466
2264
0
CFG_MCASP1_AXR8_IN
vin6a_d15
-
A11
mcasp1_axr9
1555
777
2029
352
CFG_MCASP1_AXR9_IN
vin6a_d14
-
D14
mcasp1_fsx
1549
281
1972
0
CFG_MCASP1_FSX_IN
vin6a_de0
-
A19
mcasp2_aclkx
1063
0
1206
0
CFG_MCASP2_ACLKX_IN
vin6a_d7
-
C15
mcasp2_axr2
1134
0
1277
0
CFG_MCASP2_AXR2_IN
vin6a_d5
-
A16
mcasp2_axr3
1348
487
1888
90
CFG_MCASP2_AXR3_IN
vin6a_d4
-
A18
mcasp2_fsx
1030
250
1424
0
CFG_MCASP2_FSX_IN
vin6a_d6
-
B18
mcasp3_aclkx
0
0
0
0
CFG_MCASP3_ACLKX_IN
vin6a_d3
-
B19
mcasp3_axr0
888
485
1428
88
CFG_MCASP3_AXR0_IN
vin6a_d1
-
C17
mcasp3_axr1
861
582
1331
254
CFG_MCASP3_AXR1_IN
vin6a_d0
vin5a_fld0
F15
mcasp3_fsx
1093
451
1633
54
CFG_MCASP3_FSX_IN
vin6a_d2
-
C18
mcasp4_aclkx
557
0
541
0
CFG_MCASP4_ACLKX_IN
-
vin5a_d15
G16
mcasp4_axr0
1027
989
1441
644
CFG_MCASP4_AXR0_IN
-
vin5a_d13
D17
mcasp4_axr1
1140
1038
1601
740
CFG_MCASP4_AXR1_IN
-
vin5a_d12
A21
mcasp4_fsx
1140
885
700
1377
CFG_MCASP4_FSX_IN
-
vin5a_d14
AA3
mcasp5_aclkx
1633
3030
1658
2999
CFG_MCASP5_ACLKX_IN
-
vin5a_d11
AB3
mcasp5_axr0
2392
3028
2816
2711
CFG_MCASP5_AXR0_IN
-
vin5a_d9
AA4
mcasp5_axr1
2435
3026
2856
2723
CFG_MCASP5_AXR1_IN
-
vin5a_d8
AB9
mcasp5_fsx
2285
2660
2713
2288
CFG_MCASP5_FSX_IN
-
vin5a_d10
AD4
mmc3_clk
2501
2822
2915
2475
CFG_MMC3_CLK_IN
-
vin5a_d7
AC4
mmc3_cmd
2423
2826
2832
2485
CFG_MMC3_CMD_IN
-
vin5a_d6
AC7
mmc3_dat0
2336
2820
2743
2526
CFG_MMC3_DAT0_IN
-
vin5a_d5
AC6
mmc3_dat1
2332
2710
2749
2346
CFG_MMC3_DAT1_IN
-
vin5a_d4
AC9
mmc3_dat2
1732
3048
1811
3012
CFG_MMC3_DAT2_IN
-
vin5a_d3
AC3
mmc3_dat3
2459
2969
2872
2683
CFG_MMC3_DAT3_IN
-
vin5a_d2
AC8
mmc3_dat4
2436
2662
2836
2271
CFG_MMC3_DAT4_IN
-
vin5a_d1
AD6
mmc3_dat5
2450
2431
1771
3271
CFG_MMC3_DAT5_IN
-
vin5a_d0
Timing Requirements and Switching Characteristics
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Table 7-14. Manual Functions Mapping for VIP3 (continued)
BAL
L
BALL NAME
AB8
VIP3_MANUAL1
VIP3_MANUAL2
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
mmc3_dat6
2332
2640
2752
2255
AB5
mmc3_dat7
1799
2927
1881
D18
xref_clk0
681
0
E17
xref_clk1
21
0
7.7
CFG REGISTER
MUXMODE
7
9
CFG_MMC3_DAT6_IN
-
vin5a_hsyn
c0
2844
CFG_MMC3_DAT7_IN
-
vin5a_vsyn
c0
824
0
CFG_XREF_CLK0_IN
vin6a_d0
-
0
0
CFG_XREF_CLK1_IN
vin6a_clk0
-
Display Subsystem – Video Output Ports
Three Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1, DPI
Video Output 2 and DPI Video Output 3.
NOTE
The DPI Video Output i (i = 1 to 3) interface is also referred to as VOUTi.
Every VOUT interface consists of:
• 24-bit data bus (data[23:0])
• Horizontal synchronization signal (HSYNC)
• Vertical synchronization signal (VSYNC)
• Data enable (DE)
• Field ID (FID)
• Pixel clock (CLK)
NOTE
For more information, see the Display Subsystem chapter of the Device TRM.
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in the Table 7-17 and Table 7-18.
CAUTION
The IO Timings provided in this section are only valid for some DSS usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
CAUTION
All pads/balls configured as vouti_* signals are recommended to use slow slew
rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1). FAST slew setting is allowed, but results in faster
edge rates on the VOUTn bus, higher power/ground noise, and higher EMI
emissions compared to SLOW slew rate.
226
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www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-15, Table 7-16 and Figure 7-6 assume testing over the recommended operating conditions and
electrical characteristic conditions.
Table 7-15. DPI Video Output i (i = 1..3) Default Switching Characteristics
NO.
PARAMETER
DESCRIPTION
D1
tc(clk)
Cycle time, output pixel clock vouti_clk
D2
tw(clkL)
Pulse duration, output pixel clock vouti_clk low
D3
D5
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
MODE
MIN
MAX
ns
DPI1, DPI2 (IOSET1),
DPI3 (1)
P*0.5-1
ns
DPI2 (IOSET2) (1)
P*0.51.35
ns
DPI1, DPI2 (IOSET1),
DPI3 (1)
P*0.5-1
ns
DPI2 (IOSET2)
P*0.51.35 (1)
ns
DPI1
-2.5
2.6
DPI2 (IOSET1)
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
ns
ns
DPI2 (IOSET2)
D6
UNIT
11.76
ns
DPI3 (IOSET1)
-2.5
2.5
ns
DPI3 (IOSET2/3)
DPI1
-2.5
3
ns
-2.5
2.6
ns
DPI2 (IOSET1)
ns
DPI2 (IOSET2)
ns
DPI3 (IOSET1)
-2.5
2.5
ns
DPI3 (IOSET2/3)
-2.5
3
ns
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals are recommended to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1). FAST slew setting is allowed, but results in faster edge rates on
the VOUTn bus, higher power/ground noise, and higher EMI emissions compared to SLOW slew rate.
Table 7-16. DPI Video Output i (i = 1..3) Alternate Switching Characteristics
NO.
PARAMETER
DESCRIPTION
D1
tc(clk)
Cycle time, output pixel clock vouti_clk
D2
tw(clkL)
D3
D5
MODE
MIN
MAX
ns
Pulse duration, output pixel clock vouti_clk low
P*0.5-1
(1)
ns
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
(1)
ns
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI1
1.51
4.55
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
ns
DPI2 (IOSET2)
ns
DPI1
ns
1.51
4.55
ns
DPI2 (IOSET1)
ns
DPI2 (IOSET2)
ns
DPI3
ns
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ns
DPI2 (IOSET1)
DPI3
D6
UNIT
6.06
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(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals are recommended to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1). FAST slew setting is allowed, but results in faster edge rates on
the VOUTn bus, higher power/ground noise, and higher EMI emissions compared to SLOW slew rate.
D2
D1
D3
D4
Falling-edge Clock Reference
vouti_clk
D6
Rising-edge Clock Reference
vouti_clk
vouti_vsync
D6
vouti_hsync
D5
vouti_d[23:0]
data_1 data_2
data_n
D6
vouti_de
D6
vouti_fld
even
odd
SWPS049-018
(1) (2)(3)
Figure 7-6. DPI Video Output
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Chapter
18 - Control Module.
In Table 7-17 are presented the specific groupings of signals (IOSET) for use with VOUT2.
Table 7-17. VOUT2 IOSETs
SIGNALS
IOSET2
MUX
BALL
MUX
F2
4
AA4
6
vout2_d22
F3
4
AB3
6
vout2_d21
D1
4
AB9
6
vout2_d20
E2
4
AA3
6
vout2_d19
D2
4
D17
6
vout2_d18
F4
4
G16
6
vout2_d17
C1
4
A21
6
vout2_d16
E4
4
C18
6
vout2_d23
228
IOSET1
BALL
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Table 7-17. VOUT2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
vout2_d15
F5
4
A17
6
vout2_d14
E6
4
B17
6
vout2_d13
D3
4
B16
6
vout2_d12
F6
4
D15
6
vout2_d11
D5
4
A15
6
vout2_d10
C2
4
B15
6
vout2_d9
C3
4
A20
6
vout2_d8
C4
4
E15
6
vout2_d7
B2
4
D12
6
vout2_d6
D6
4
C12
6
vout2_d5
C5
4
F13
6
vout2_d4
A3
4
E12
6
vout2_d3
B3
4
J11
6
vout2_d2
B4
4
G13
6
vout2_d1
B5
4
J14
6
vout2_d0
A4
4
B14
6
vout2_vsync
G6
4
F20
6
vout2_hsync
G1
4
E21
6
vout2_clk
H7
4
B26
6
vout2_fld
E1
4
F21
6
vout2_de
G2
4
C23
6
In Table 7-18 are presented the specific groupings of signals (IOSET) for use with VOUT3.
Table 7-18. VOUT3 IOSETs
SIGNALS
IOSET2 (1)
IOSET1
BALL
MUX
vout3_d23
P5
vout3_d22
R5
vout3_d21
IOSET3 (1)
BALL
MUX
BALL
MUX
3
AE8
4
3
AD8
4
R9
3
AG7
4
vout3_d20
P6
3
AH6
4
vout3_d19
T7
3
AH3
4
vout3_d18
T6
3
AH5
4
vout3_d17
T9
3
AG6
vout3_d16
R6
3
AH4
4
AD9
3
4
AG8
vout3_d15
H3
3
3
AG4
4
AG4
vout3_d14
H2
4
3
AG2
4
AG2
4
vout3_d13
vout3_d12
J3
3
AG3
4
AG3
4
H1
3
AG5
4
AG5
vout3_d11
4
J2
3
AF2
4
AF2
4
vout3_d10
J1
3
AF6
4
AF6
4
vout3_d9
K2
3
AF3
4
AF3
4
vout3_d8
L1
3
AF4
4
AF4
4
vout3_d7
L2
3
AF1
4
AE8
3
vout3_d6
L3
3
AE3
4
AD8
3
vout3_d5
L4
3
AE5
4
AG7
3
vout3_d4
L6
3
AE1
4
AH6
3
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Table 7-18. VOUT3 IOSETs (continued)
SIGNALS
IOSET2 (1)
IOSET1
IOSET3 (1)
BALL
MUX
BALL
MUX
BALL
MUX
vout3_d3
M1
3
AE2
4
AH3
3
vout3_d2
L5
3
AE6
4
AH5
3
vout3_d1
M2
3
AD2
4
AG6
3
vout3_d0
M6
3
AD3
4
AH4
3
vout3_de
N9
3
AD9
4
vout3_vsync
R4
3
AF8
4
AF8
4
vout3_clk
P1
3
AF9
4
AF9
4
vout3_hsync
N7
3
AE9
4
AE9
4
vout3_fld
P9
3
AG8
4
(1) The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (i.e.,
VDDSHV6 must be supplied with 1.8V). 3.3V mode is not supported. This must be considered in the pin mux programming and
VDDSHVx supply connections.
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for VOUT1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-19 Manual
Functions Mapping for DSS VOUT1 for a definition of the Manual modes.
Table 7-19 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
230
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Table 7-19. Manual Functions Mapping for DSS VOUT1
BALL
BALL NAME
VOUT1_MANUAL1
VOUT1_MANUAL2
VOUT1_MANUAL3
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
0
D11
vout1_clk
0
706
1126
751
1067
829
CFG_VOUT1_CLK_OUT
vout1_clk
vout1_d0
F11
vout1_d0
2313
0
395
0
391
0
CFG_VOUT1_D0_OUT
G10
vout1_d1
2439
0
521
0
517
0
CFG_VOUT1_D1_OUT
vout1_d1
D7
vout1_d10
2199
0
282
0
278
0
CFG_VOUT1_D10_OUT
vout1_d10
D8
vout1_d11
2266
0
348
0
345
0
CFG_VOUT1_D11_OUT
vout1_d11
A5
vout1_d12
3159
0
1240
0
1236
0
CFG_VOUT1_D12_OUT
vout1_d12
C6
vout1_d13
2100
0
182
0
178
0
CFG_VOUT1_D13_OUT
vout1_d13
C8
vout1_d14
2229
0
311
0
308
0
CFG_VOUT1_D14_OUT
vout1_d14
C7
vout1_d15
2202
0
285
0
281
0
CFG_VOUT1_D15_OUT
vout1_d15
B7
vout1_d16
2084
0
166
0
0
162
CFG_VOUT1_D16_OUT
vout1_d16
B8
vout1_d17
2195
0
278
0
274
0
CFG_VOUT1_D17_OUT
vout1_d17
A7
vout1_d18
2342
0
425
0
421
0
CFG_VOUT1_D18_OUT
vout1_d18
A8
vout1_d19
2463
0
516
0
512
0
CFG_VOUT1_D19_OUT
vout1_d19
F10
vout1_d2
2200
0
282
0
279
0
CFG_VOUT1_D2_OUT
vout1_d2
C9
vout1_d20
2304
0
386
0
383
0
CFG_VOUT1_D20_OUT
vout1_d20
A9
vout1_d21
2103
0
111
0
107
0
CFG_VOUT1_D21_OUT
vout1_d21
B9
vout1_d22
2145
0
227
0
223
0
CFG_VOUT1_D22_OUT
vout1_d22
A10
vout1_d23
1932
0
0
0
0
0
CFG_VOUT1_D23_OUT
vout1_d23
G11
vout1_d3
2355
0
438
0
434
0
CFG_VOUT1_D3_OUT
vout1_d3
E9
vout1_d4
3215
0
1298
0
1294
0
CFG_VOUT1_D4_OUT
vout1_d4
F9
vout1_d5
2314
0
397
0
393
0
CFG_VOUT1_D5_OUT
vout1_d5
F8
vout1_d6
2238
0
321
0
317
0
CFG_VOUT1_D6_OUT
vout1_d6
E7
vout1_d7
2381
0
155
309
135
325
CFG_VOUT1_D7_OUT
vout1_d7
E8
vout1_d8
2138
0
212
0
208
0
CFG_VOUT1_D8_OUT
vout1_d8
D9
vout1_d9
2383
0
466
0
462
0
CFG_VOUT1_D9_OUT
vout1_d9
B10
vout1_de
1984
0
0
0
0
0
CFG_VOUT1_DE_OUT
vout1_de
B11
vout1_fld
2265
0
236
0
215
0
CFG_VOUT1_FLD_OUT
vout1_fld
C11
vout1_hsync
1947
0
0
0
0
0
CFG_VOUT1_HSYNC_OUT
vout1_hsync
E11
vout1_vsync
2739
0
139
701
118
701
CFG_VOUT1_VSYNC_OUT
vout1_vsync
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Manual IO Timings Modes must be used to guarantee some IO timings for VOUT2. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Manual IO Timings Modes. See Table 7-20 Manual Functions Mapping for DSS VOUT2 for a definition of the Manual modes.
Table 7-20 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-20. Manual Functions Mapping for DSS VOUT2
BALL
BALL NAME
VOUT2_IOSET1_MANUAL1
VOUT2_IOSET1_MANUAL2
VOUT2_IOSET1_MANUAL3
CFG REGISTER
MUXMODE
E1
vin2a_clk0
2718
0
473
378
819
0
CFG_VIN2A_CLK0_OUT
vout2_fld
F2
vin2a_d0
2680
0
435
356
485
296
CFG_VIN2A_D0_OUT
vout2_d23
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
4
F3
vin2a_d1
2633
0
744
0
733
0
CFG_VIN2A_D1_OUT
vout2_d22
D3
vin2a_d10
1867
0
0
0
0
0
CFG_VIN2A_D10_OUT
vout2_d13
F6
vin2a_d11
2457
0
401
167
431
127
CFG_VIN2A_D11_OUT
vout2_d12
D5
vin2a_d12
2683
1016
1319
491
1286
514
CFG_VIN2A_D12_OUT
vout2_d11
C2
vin2a_d13
2629
985
1263
463
1229
486
CFG_VIN2A_D13_OUT
vout2_d10
C3
vin2a_d14
2531
804
1159
286
1126
309
CFG_VIN2A_D14_OUT
vout2_d9
C4
vin2a_d15
2624
818
1260
292
1227
315
CFG_VIN2A_D15_OUT
vout2_d8
B2
vin2a_d16
2747
767
1390
233
1357
256
CFG_VIN2A_D16_OUT
vout2_d7
D6
vin2a_d17
2622
841
1260
314
1226
337
CFG_VIN2A_D17_OUT
vout2_d6
C5
vin2a_d18
2328
0
375
65
430
0
CFG_VIN2A_D18_OUT
vout2_d5
A3
vin2a_d19
2300
0
411
0
401
0
CFG_VIN2A_D19_OUT
vout2_d4
D1
vin2a_d2
2452
0
397
165
446
106
CFG_VIN2A_D2_OUT
vout2_d21
B3
vin2a_d20
1998
0
109
0
98
0
CFG_VIN2A_D20_OUT
vout2_d3
B4
vin2a_d21
1953
0
64
0
54
0
CFG_VIN2A_D21_OUT
vout2_d2
B5
vin2a_d22
1893
0
0
0
0
0
CFG_VIN2A_D22_OUT
vout2_d1
A4
vin2a_d23
1936
0
47
0
36
0
CFG_VIN2A_D23_OUT
vout2_d0
E2
vin2a_d3
2494
0
605
0
595
0
CFG_VIN2A_D3_OUT
vout2_d20
D2
vin2a_d4
3001
153
1265
0
1254
0
CFG_VIN2A_D4_OUT
vout2_d19
F4
vin2a_d5
2463
0
476
97
563
0
CFG_VIN2A_D5_OUT
vout2_d18
C1
vin2a_d6
2456
0
568
0
558
0
CFG_VIN2A_D6_OUT
vout2_d17
E4
vin2a_d7
2431
0
542
0
532
0
CFG_VIN2A_D7_OUT
vout2_d16
F5
vin2a_d8
2262
0
373
0
363
0
CFG_VIN2A_D8_OUT
vout2_d15
E6
vin2a_d9
2145
0
256
0
246
0
CFG_VIN2A_D9_OUT
vout2_d14
G2
vin2a_de0
2597
0
500
208
550
149
CFG_VIN2A_DE0_OUT
vout2_de
H7
vin2a_fld0
0
957
1225
948
1208
969
CFG_VIN2A_FLD0_OUT
vout2_clk
G1
vin2a_hsync0
2958
0
1091
0
1059
0
CFG_VIN2A_HSYNC0_OUT
vout2_hsync
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Table 7-20. Manual Functions Mapping for DSS VOUT2 (continued)
BALL
BALL NAME
G6
vin2a_vsync0
VOUT2_IOSET1_MANUAL1
VOUT2_IOSET1_MANUAL2
VOUT2_IOSET1_MANUAL3
CFG REGISTER
MUXMODE
CFG_VIN2A_VSYNC0_OUT
vout2_vsync
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
2752
0
391
495
853
4
0
Manual IO Timings Modes must be used to guarantee some IO timings for VOUT2. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Manual IO Timings Modes. See Table 7-21 Manual Functions Mapping for DSS VOUT2 IOSET2 for a definition of the Manual
modes.
Table 7-21 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-21. Manual Functions Mapping for DSS VOUT2 IOSET2
BAL
L
BALL NAME
VOUT2_IOSET2_MANUAL1
VOUT2_IOSET2_MANUAL2
VOUT2_IOSET2_MANUAL3
CFG REGISTER
E21
gpio6_14
854
0
0
0
0
0
CFG_GPIO6_14_OUT
vout2_hsync
F20
gpio6_15
1062
0
214
0
209
0
CFG_GPIO6_15_OUT
vout2_vsync
F21
gpio6_16
907
0
39
0
33
0
CFG_GPIO6_16_OUT
vout2_fld
B14
mcasp1_aclkr
3500
0
2641
0
2636
0
CFG_MCASP1_ACLKR_OUT
vout2_d0
G13
mcasp1_axr2
2579
0
1713
0
1730
0
CFG_MCASP1_AXR2_OUT
vout2_d2
J11
mcasp1_axr3
2346
0
1481
0
1498
0
CFG_MCASP1_AXR3_OUT
vout2_d3
E12
mcasp1_axr4
2727
0
1862
0
1879
0
CFG_MCASP1_AXR4_OUT
vout2_d4
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
MUXMODE
6
F13
mcasp1_axr5
2650
0
1785
0
1802
0
CFG_MCASP1_AXR5_OUT
vout2_d5
C12
mcasp1_axr6
2641
0
1776
0
1792
0
CFG_MCASP1_AXR6_OUT
vout2_d6
D12
mcasp1_axr7
2566
0
1701
0
1717
0
CFG_MCASP1_AXR7_OUT
vout2_d7
vout2_d1
J14
mcasp1_fsr
2315
0
1450
0
1466
0
CFG_MCASP1_FSR_OUT
E15
mcasp2_aclkr
3336
0
2471
0
2488
0
CFG_MCASP2_ACLKR_OUT
vout2_d8
B15
mcasp2_axr0
1870
0
1005
0
1022
0
CFG_MCASP2_AXR0_OUT
vout2_d10
A15
mcasp2_axr1
2028
0
1163
0
1179
0
CFG_MCASP2_AXR1_OUT
vout2_d11
D15
mcasp2_axr4
2223
0
1357
0
1374
0
CFG_MCASP2_AXR4_OUT
vout2_d12
B16
mcasp2_axr5
2012
0
1148
0
1164
0
CFG_MCASP2_AXR5_OUT
vout2_d13
B17
mcasp2_axr6
3176
0
2310
0
2339
0
CFG_MCASP2_AXR6_OUT
vout2_d14
A17
mcasp2_axr7
1779
0
914
0
931
0
CFG_MCASP2_AXR7_OUT
vout2_d15
A20
mcasp2_fsr
1564
0
698
0
715
0
CFG_MCASP2_FSR_OUT
vout2_d9
C18
mcasp4_aclkx
2900
0
2034
0
2051
0
CFG_MCASP4_ACLKX_OUT
vout2_d16
G16
mcasp4_axr0
1666
0
801
0
830
0
CFG_MCASP4_AXR0_OUT
vout2_d18
D17
mcasp4_axr1
1341
0
0
476
505
0
CFG_MCASP4_AXR1_OUT
vout2_d19
A21
mcasp4_fsx
1380
0
512
0
541
0
CFG_MCASP4_FSX_OUT
vout2_d17
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Table 7-21. Manual Functions Mapping for DSS VOUT2 IOSET2 (continued)
BAL
L
BALL NAME
VOUT2_IOSET2_MANUAL1
VOUT2_IOSET2_MANUAL2
VOUT2_IOSET2_MANUAL3
CFG REGISTER
MUXMODE
AA3
mcasp5_aclkx
4184
2166
3497
1993
3499
1978
CFG_MCASP5_ACLKX_OUT
vout2_d20
AB3
mcasp5_axr0
4189
1590
3503
1417
3505
1402
CFG_MCASP5_AXR0_OUT
vout2_d22
AA4
mcasp5_axr1
4155
1213
3468
AB9
mcasp5_fsx
4131
1464
3441
1035
3457
1063
CFG_MCASP5_AXR1_OUT
vout2_d23
1295
3443
1280
CFG_MCASP5_FSX_OUT
B26
xref_clk2
0
873
vout2_d21
1900
1100
1900
1150
CFG_XREF_CLK2_OUT
vout2_clk
C23
xref_clk3
2588
0
1723
0
1752
0
CFG_XREF_CLK3_OUT
vout2_de
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
6
Manual IO Timings Modes must be used to guarantee some IO timings for VOUT3. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Manual IO Timings Modes. See Table 7-22 Manual Functions Mapping for DSS VOUT3 for a definition of the Manual modes.
Table 7-22 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-22. Manual Functions Mapping for DSS VOUT3
BALL
R6
BALL NAME
VOUT3_MANUAL1
VOUT3_MANUAL2
VOUT3_MANUAL3
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
gpmc_a0
2284
0
831
0
565
267
CFG REGISTER
MUXMODE
3
4
CFG_GPMC_A0_OUT
vout3_d16
-
T9
gpmc_a1
2102
0
649
0
650
0
CFG_GPMC_A1_OUT
vout3_d17
-
N9
gpmc_a10
2609
0
1156
0
1157
0
CFG_GPMC_A10_OUT
vout3_de
-
P9
gpmc_a11
3054
35
559
1097
669
970
CFG_GPMC_A11_OUT
vout3_fld
-
T6
gpmc_a2
2155
0
704
0
705
0
CFG_GPMC_A2_OUT
vout3_d18
-
T7
gpmc_a3
2973
0
1520
0
1521
0
CFG_GPMC_A3_OUT
vout3_d19
-
P6
gpmc_a4
3158
131
1836
0
1837
0
CFG_GPMC_A4_OUT
vout3_d20
-
R9
gpmc_a5
2191
0
739
0
739
0
CFG_GPMC_A5_OUT
vout3_d21
-
R5
gpmc_a6
2390
0
937
0
937
0
CFG_GPMC_A6_OUT
vout3_d22
-
P5
gpmc_a7
2396
0
943
0
944
0
CFG_GPMC_A7_OUT
vout3_d23
-
N7
gpmc_a8
3275
18
1859
0
1843
0
CFG_GPMC_A8_OUT
vout3_hsync
-
R4
gpmc_a9
2448
0
1015
0
998
0
CFG_GPMC_A9_OUT
vout3_vsync
-
M6
gpmc_ad0
2603
0
1150
0
1151
0
CFG_GPMC_AD0_OUT
vout3_d0
-
M2
gpmc_ad1
2407
0
955
0
956
0
CFG_GPMC_AD1_OUT
vout3_d1
-
J1
gpmc_ad10
2516
0
1063
0
1064
0
CFG_GPMC_AD10_OUT
vout3_d10
-
J2
gpmc_ad11
2262
0
810
0
809
0
CFG_GPMC_AD11_OUT
vout3_d11
-
H1
gpmc_ad12
2583
30
1160
0
1161
0
CFG_GPMC_AD12_OUT
vout3_d12
-
J3
gpmc_ad13
1976
0
523
0
524
0
CFG_GPMC_AD13_OUT
vout3_d13
-
234
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Table 7-22. Manual Functions Mapping for DSS VOUT3 (continued)
BALL
BALL NAME
VOUT3_MANUAL1
VOUT3_MANUAL2
VOUT3_MANUAL3
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
0
96
534
632
0
CFG REGISTER
MUXMODE
3
4
CFG_GPMC_AD14_OUT
vout3_d14
-
H2
gpmc_ad14
2083
H3
gpmc_ad15
2465
0
1011
0
1012
0
CFG_GPMC_AD15_OUT
vout3_d15
-
L5
gpmc_ad2
2658
16
1221
0
1222
0
CFG_GPMC_AD2_OUT
vout3_d2
-
M1
gpmc_ad3
2328
0
224
650
875
0
CFG_GPMC_AD3_OUT
vout3_d3
-
L6
gpmc_ad4
2622
0
1169
0
1170
0
CFG_GPMC_AD4_OUT
vout3_d4
-
L4
gpmc_ad5
1837
0
290
0
358
0
CFG_GPMC_AD5_OUT
vout3_d5
-
L3
gpmc_ad6
2613
22
1183
0
1184
0
CFG_GPMC_AD6_OUT
vout3_d6
-
L2
gpmc_ad7
2359
0
907
0
908
0
CFG_GPMC_AD7_OUT
vout3_d7
-
L1
gpmc_ad8
1242
0
0
0
0
0
CFG_GPMC_AD8_OUT
vout3_d8
-
K2
gpmc_ad9
1312
0
0
0
0
0
CFG_GPMC_AD9_OUT
vout3_d9
-
P1
gpmc_cs3
0
1214
1472
1390
1505
1379
CFG_GPMC_CS3_OUT
vout3_clk
-
AG8
vin1a_clk0
2730
0
1296
0
1280
0
CFG_VIN1A_CLK0_OUT
vout3_d16
vout3_fld
AE8
vin1a_d0
2738
0
1141
144
1286
0
CFG_VIN1A_D0_OUT
vout3_d7
vout3_d23
AD8
vin1a_d1
2734
0
1281
0
1282
0
CFG_VIN1A_D1_OUT
vout3_d6
vout3_d22
AG3
vin1a_d10
3160
0
1182
516
1078
622
CFG_VIN1A_D10_OUT
-
vout3_d13
AG5
vin1a_d11
2800
0
1338
0
1339
0
CFG_VIN1A_D11_OUT
-
vout3_d12
AF2
vin1a_d12
3338
16
1893
0
1894
0
CFG_VIN1A_D12_OUT
-
vout3_d11
AF6
vin1a_d13
2748
0
1254
32
1287
0
CFG_VIN1A_D13_OUT
-
vout3_d10
AF3
vin1a_d14
3337
154
2029
0
2030
0
CFG_VIN1A_D14_OUT
-
vout3_d9
AF4
vin1a_d15
2688
0
1226
0
1138
89
CFG_VIN1A_D15_OUT
-
vout3_d8
AF1
vin1a_d16
2805
0
1344
0
1345
0
CFG_VIN1A_D16_OUT
-
vout3_d7
AE3
vin1a_d17
2793
0
1331
0
1332
0
CFG_VIN1A_D17_OUT
-
vout3_d6
AE5
vin1a_d18
2790
0
1328
0
1329
0
CFG_VIN1A_D18_OUT
-
vout3_d5
AE1
vin1a_d19
2862
0
1400
0
1221
180
CFG_VIN1A_D19_OUT
-
vout3_d4
AG7
vin1a_d2
2725
0
1272
0
1273
0
CFG_VIN1A_D2_OUT
vout3_d5
vout3_d21
AE2
vin1a_d20
2985
0
1523
0
1524
0
CFG_VIN1A_D20_OUT
-
vout3_d3
AE6
vin1a_d21
2954
0
1492
0
1493
0
CFG_VIN1A_D21_OUT
-
vout3_d2
AD2
vin1a_d22
2891
0
1430
0
1431
0
CFG_VIN1A_D22_OUT
-
vout3_d1
AD3
vin1a_d23
3008
0
1546
0
1547
0
CFG_VIN1A_D23_OUT
-
vout3_d0
AH6
vin1a_d3
2782
26
1356
0
1357
0
CFG_VIN1A_D3_OUT
vout3_d4
vout3_d20
AH3
vin1a_d4
3149
354
2033
17
2033
19
CFG_VIN1A_D4_OUT
vout3_d3
vout3_d19
AH5
vin1a_d5
2490
0
1038
0
1039
0
CFG_VIN1A_D5_OUT
vout3_d2
vout3_d18
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Table 7-22. Manual Functions Mapping for DSS VOUT3 (continued)
BALL
BALL NAME
VOUT3_MANUAL1
VOUT3_MANUAL2
VOUT3_MANUAL3
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
3
4
AG6
vin1a_d6
2682
0
1229
0
1230
0
CFG_VIN1A_D6_OUT
vout3_d1
vout3_d17
AH4
vin1a_d7
2687
0
1234
0
1235
0
CFG_VIN1A_D7_OUT
vout3_d0
vout3_d16
AG4
vin1a_d8
2783
0
1321
0
1322
0
CFG_VIN1A_D8_OUT
-
vout3_d15
AG2
vin1a_d9
2833
0
1371
0
1116
256
CFG_VIN1A_D9_OUT
-
vout3_d14
AD9
vin1a_de0
2946
0
1494
0
1494
0
CFG_VIN1A_DE0_OUT
vout3_d17
vout3_de
AF9
vin1a_fld0
178
747
1813
752
1718
869
CFG_VIN1A_FLD0_OUT
-
vout3_clk
AE9
vin1a_hsync0
2731
0
1288
0
1272
0
CFG_VIN1A_HSYNC0_OUT
-
vout3_hsync
AF8
vin1a_vsync0
2543
0
1100
0
995
88
CFG_VIN1A_VSYNC0_OUT
-
vout3_vsync
236
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7.8
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Display Subsystem – High-Definition Multimedia Interface (HDMI)
The High-Definition Multimedia Interface is provided for transmitting digital television audiovisual signals
from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other
video displays. The HDMI interface is aligned with the HDMI TMDS single stream standard v1.4a (720p
@60Hz to 1080p @24Hz) and the HDMI v1.3 (1080p @60Hz): 3 data channels, plus 1 clock channel is
supported (differential).
NOTE
For more information, see the High-Definition Multimedia Interface chapter of the device
TRM.
7.9
External Memory Interface (EMIF)
The device has a dedicated interface to DDR3 and DDR2 SDRAM. It supports JEDEC standard compliant
DDR2 and DDR3 SDRAM devices with the following features:
• 16-bit or 32-bit data path to external SDRAM memory
• Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices (Single die only)
• One interface with associated DDR2/DDR3 PHYs
NOTE
For more information, see the EMIF Controller section of the Device TRM.
7.10 General-Purpose Memory Controller (GPMC)
The GPMC is the unified memory controller that interfaces external memory devices such as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
NOTE
For more information, see the General-Purpose Memory Controller section of the Device
TRM.
7.10.1 GPMC/NOR Flash Interface Synchronous Timing
CAUTION
The IO Timings provided in this section are only valid for some GPMC usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-23 and Table 7-24 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-7, Figure 7-8, Figure 7-9, Figure 7-10, Figure 7-11, and
Figure 7-12).
Table 7-23. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 1 Load
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
F12
tsu(dV-clkH)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
2.69
ns
F13
th(clkH-dV)
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
1.53
ns
Timing Requirements and Switching Characteristics
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Table 7-23. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 1 Load (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
F21
tsu(waitV-clkH)
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
2.23
ns
F22
th(clkH-waitV)
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
1.52
ns
NOTE
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of
wait monitoring feature, see General-Purpose Memory Controller section in the Device TRM.
Table 7-24. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
F0
tc(clk)
Cycle time, output clock gpmc_clk period
F2
td(clkH-nCSV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
F-1.48(6)
11.3
F+3.84(6)
ns
ns
F3
td(clkH-nCSIV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
E-1.48(5) E +3.84(5)
ns
F4
td(ADDV-clk)
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
B-1.69(2)
ns
F5
td(clkH-ADDIV)
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
F6
td(nBEV-clk)
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
B-3.8(2)
B+2.37(2)
ns
F7
td(clkH-nBEIV)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
D-0.4(4)
D+1.1(4)
ns
F8
td(clkH-nADV)
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
G-1.48 G+3.84 (7)
(7)
ns
F9
td(clkH-nADVIV)
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
D-1.48 G+3.84 (7)
(4)
ns
F10
td(clkH-nOE)
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
H-1.41 H+2.45 (8)
(8)
ns
F11
td(clkH-nOEIV)
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
E-1.41
(5)
E+2.1 (5)
ns
F14
td(clkH-nWE)
Delay time, gpmc_clk rising edge to gpmc_wen transition
I-1.18 (9)
I+3.68 (9)
ns
F15
td(clkH-Data)
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
J-1.89
(10)
J+4.89
(10)
ns
F17
td(clkH-nBE)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
J-1.3
(10)
J+3.8 (10)
ns
F18
tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
A (1)
ns
F19
tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C (3)
ns
F20
tw(nADVV)
Pulse duration, gpmc_advn_ale low
K (11)
F23
td(CLK-GPIO)
Delay time, gpmc_clk transition to gpio6_16.clkout1 transition
B+3.76(2)
-1.69
1.2
ns
ns
6.1
ns
Table 7-25. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 5 Loads
NO.
PARAMETER
DESCRIPTION
F12
tsu(dV-clkH)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
F13
th(clkH-dV)
F21
tsu(waitV-clkH)
F22
th(clkH-waitV)
MIN
MAX
UNIT
3.56
ns
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
1.9
ns
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
3.1
ns
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
1.9
ns
Table 7-26. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads
NO.
PARAMETER
DESCRIPTION
F0
tc(clk)
Cycle time, output clock gpmc_clk period (12)
F2
td(clkH-nCSV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
238
MIN
MAX
15.04
F-0.84 (6)
UNIT
ns
F+6.73
(6)
ns
Timing Requirements and Switching Characteristics
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-26. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5
Loads (continued)
NO.
MIN
MAX
F3
td(clkH-nCSIV)
PARAMETER
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
DESCRIPTION
E-0.84 (5)
E+6.73
(5)
ns
F4
td(ADDV-clk)
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
B-1.36 (2)
B+6.73
(2)
ns
F5
td(clkH-ADDIV)
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
F6
td(nBEV-clk)
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
F7
td(clkH-nBEIV)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
F8
td(clkH-nADV)
F9
-1.36
UNIT
ns
B-6.34 (2) B+0.6 (2)
ns
D-0.4 (4) D+4.9 (4)
ns
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
G-0.67 (7) G+6.1 (7)
ns
td(clkH-nADVIV)
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
D-0.67 (4) D+6.1 (4)
ns
F10
td(clkH-nOE)
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
H-0.67 (8)
H+5.65
(8)
ns
F11
td(clkH-nOEIV)
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
E-0.67 (5)
E+5.65
(5)
ns
F14
td(clkH-nWE)
Delay time, gpmc_clk rising edge to gpmc_wen transition
F15
td(clkH-Data)
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
F17
td(clkH-nBE)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
F18
tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
F19
tw(nBEV)
F20
tw(nADVV)
F23
td(CLK-GPIO)
Delay time, gpmc_clk transition to gpio6_16.clkout1 transition
I-0.6 (9)
I+6.1 (9)
ns
J-1.76 (10)
J+6.39
(10)
ns
J-0.6 (10)
J+6.34
(10)
ns
A (10)
ns
Pulse duration, gpmc_ben[1:0] low
C (3)
ns
Pulse duration, gpmc_advn_ale low
K (11)
(13)
0.96
ns
6.1
ns
(1) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
with n the page burst access number.
(2) B = ClkActivationTime * GPMC_FCLK
(3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For Burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n the page burst
access number.
(4) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(5) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(6) For nCS falling edge (CS activated):
Case GpmcFCLKDivider = 0 :
F = 0.5 * CSExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1:
F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 4)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 4)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 4)
F = (3 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 3) is a multiple of 4)
(7) For ADV falling edge (ADV activated):
Case GpmcFCLKDivider = 0 :
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are
even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
Timing Requirements and Switching Characteristics
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Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime
are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 4)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 4)
G = (3 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 3) is a multiple of 4)
For ADV rising edge (ADV deactivated) in Writing mode:
Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime
are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 4)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 4)
G = (3 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 3) is a multiple of 4)
(8) For OE falling edge (OE activated):
Case GpmcFCLKDivider = 0:
- H = 0.5 * OEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 4)
- H = (3 + 0.5 * OEExtraDelay)) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 3) is a multiple of 4)
For OE rising edge (OE deactivated):
Case GpmcFCLKDivider = 0:
- H = 0.5 * OEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 4)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 4)
- H = (3 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 3) is a multiple of 4)
(9) For WE falling edge (WE activated):
Case GpmcFCLKDivider = 0:
- I = 0.5 * WEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are
even)
240
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- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 3) is a multiple of 4)
For WE rising edge (WE deactivated):
Case GpmcFCLKDivider = 0:
- I = 0.5 * WEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are
even)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 3) is a multiple of 4)
(10) J = GPMC_FCLK period, where GPMC_FCLK is the General Purpose Memory Controller internal functional clock
(11) For read:
K = (ADVRdOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For write: K = (ADVWrOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(12) The gpmc_clk output clock maximum and minimum frequency is programmable in the I/F module by setting the GPMC_CONFIG1_CSx
configuration register bit fields GpmcFCLKDivider
(13) gpio6_16 programmed to MUXMODE=9 (clkout1), CM_CLKSEL_CLKOUTMUX1 programmed to 7 (CORE_DPLL_OUT_DCLK),
CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX programmed to 1.
(14) CSEXTRADELAY = 0, ADVEXTRADELAY = 0, WEEXTRADELAY = 0, OEEXTRADELAY = 0. Extra half-GPMC_FCLK cycle delay
mode is not timed.
Timing Requirements and Switching Characteristics
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
Address (MSB)
gpmc_a[10:1]
gpmc_a[27]
F6
F7
F19
gpmc_ben1
F6
F7
F19
gpmc_ben0
F8
F8
F20
F9
gpmc_advn_ale
F10
F11
gpmc_oen_ren
F13
F4
gpmc_ad[15:0]
F5
F12
Address (LSB)
D0
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_01
Figure 7-7. GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
242
Timing Requirements and Switching Characteristics
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
Address
F6
F7
F19
gpmc_ben1
F6
F7
F19
gpmc_ben0
F8
F8
F9
F20
gpmc_advn_ale
F10
F11
gpmc_oen_ren
F13
F12
D0
gpmc_ad[15:0]
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_02
Figure 7-8. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Single Read (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
Timing Requirements and Switching Characteristics
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F7
F6
F19
Valid
gpmc_ben1
F7
F6
F19
Valid
gpmc_ben0
F8
F8
F9
F20
gpmc_advn_ale
F10
F11
gpmc_oen_ren
F12
F4
gpmc_ad[15:0]
F5
F13
D0
Address (LSB)
F22
D1
F12
D2
D3
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_03
Figure 7-9. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i= 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
244
Timing Requirements and Switching Characteristics
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DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
Address
F7
F6
F19
Valid
gpmc_ben1
F7
F6
F19
Valid
gpmc_ben0
F8
F8
F20
F9
gpmc_advn_ale
F10
F11
gpmc_oen_ren
F12
F13
gpmc_ad[15:0]
D0
D1
F12
D2
D3
F21
F22
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_04
Figure 7-10. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
Timing Requirements and Switching Characteristics
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245
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F17
F6
F17
F6
F17
F17
gpmc_ben1
F17
F17
gpmc_ben0
F8
F8
F20
F9
gpmc_advn_ale
F14
F14
gpmc_wen
F15
gpmc_ad[15:0]
Address (LSB)
D0
F22
D1
F15
D2
F15
D3
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_05
Figure 7-11. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
246
Timing Requirements and Switching Characteristics
Copyright © 2015–2016, Texas Instruments Incorporated
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DRA744, DRA745, DRA746
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DRA754, DRA755, DRA756
www.ti.com
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
Address
gpmc_a[27:1]
F17
F6
F17
F17
gpmc_ben1
F17
F6
F17
F17
gpmc_ben0
F8
F8
F20
F9
gpmc_advn_ale
F14
F14
gpmc_wen
F15
gpmc_ad[15:0]
D0
D1
F15
F15
D2
D3
F21
F22
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_06
Figure 7-12. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 1 to 7.
(2) In gpmc_waitj, j = 0 to 1.
7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
CAUTION
The IO Timings provided in this section are only valid for some GPMC usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-27 and Table 7-28 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-13, Figure 7-14, Figure 7-15, Figure 7-16, Figure 7-17, and
Figure 7-18).
Table 7-27. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode
NO.
FA5
PARAMETER
tacc(DAT)
DESCRIPTION
Data Maximum Access Time (GPMC_FCLK cycles)
MIN
MAX
UNIT
(1)
cycles
H
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Table 7-27. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode (continued)
NO.
PARAMETER
DESCRIPTION
FA20
tacc1-pgmode(DAT)
Page Mode Successive Data Maximum Access Time (GPMC_FCLK
cycles)
FA21
tacc2-pgmode(DAT)
Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)
-
tsu(DV-OEH)
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high
-
th(OEH-DV)
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high
MIN
MAX
UNIT
P
(2)
cycles
H
(1)
cycles
1.9
ns
1
ns
(1) H = Access Time * (TimeParaGranularity + 1)
(2) P = PageBurstAccessTime * (TimeParaGranularity + 1)
Table 7-28. GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
-
tr(DO)
Rising time, gpmc_ad[15:0] output data
0.447
4.067
ns
-
tf(DO)
Fallling time, gpmc_ad[15:0] output data
0.43
4.463
ns
FA0
tw(nBEV)
Pulse duration, gpmc_ben[1:0] valid time
N
(1)
ns
FA1
tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
A
(2)
ns
FA3
td(nCSV-nADVIV)
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid
B-2
(3)
B+4
(3)
ns
FA4
td(nCSV-nOEIV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read)
C-2
(4)
C+4
(4)
ns
FA9
td(AV-nCSV)
Delay time, address bus valid to gpmc_cs[7:0] valid
J-2
(5)
J+4
(5)
ns
FA10 td(nBEV-nCSV)
Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid
J-2
(5)
J+4
(5)
ns
FA12 td(nCSV-nADVV)
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid
K-2
(6)
K+4
(6)
ns
FA13 td(nCSV-nOEV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
L-2
(7)
L+4
(7)
ns
FA16 tw(AIV)
Pulse duration, address invalid between 2 successive R/W accesses
G
(8)
FA18 td(nCSV-nOEIV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read)
I-2
(9)
I+4
(9)
FA20 tw(AV)
Pulse duration, address valid : 2nd, 3rd and 4th accesses
FA25 td(nCSV-nWEV)
ns
ns
D
(10)
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
E-2
(11)
E+4
(11)
ns
FA27 td(nCSV-nWEIV)
Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid
F-2
(12)
F+4
(12)
ns
FA28 td(nWEV-DV)
Delay time, gpmc_ wen valid to data bus valid
2
ns
FA29 td(DV-nCSV)
Delay time, data bus valid to gpmc_cs[7:0] valid
(5)
ns
FA37 td(nOEV-AIV)
Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed address bus
phase end
2
ns
J-2
ns
(5)
J+4
(1) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: N = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: N = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: A = (CSWrOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(3) For reading: B = ((ADVRdOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
For writing: B = ((ADVWrOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(4) C = ((OEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(5) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
(6) K = ((ADVOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(7) L = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(8) G = Cycle2CycleDelay * GPMC_FCLK * (TimeParaGranularity +1)
(9) I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK
(10) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(11) E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(12) F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
248
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GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_csi
FA9
Valid Address
gpmc_a[27:1]
FA0
FA10
gpmc_ben0
Valid
gpmc_ben1
Valid
FA0
FA10
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data IN 0
Data IN 0
gpmc_waitj
FA15
FA14
DIR
OUT
IN
OUT
GPMC_07
Figure 7-13. GPMC / NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)(4)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
Timing Requirements and Switching Characteristics
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GPMC_FCLK
gpmc_clk
FA5
FA5
FA1
FA1
gpmc_csi
FA16
FA9
FA9
gpmc_a[27:1]
Address 0
Address 1
FA0
FA0
FA10
FA10
gpmc_ben0
Valid
FA0
FA0
gpmc_ben1
Valid
Valid
Valid
FA10
FA10
FA3
FA3
FA12
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data Upper
gpmc_waitj
FA15
FA15
FA14
DIR
OUT
FA14
IN
OUT
IN
GPMC_08
(1)(2)(3)(4)
Figure 7-14. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
250
Timing Requirements and Switching Characteristics
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GPMC_FCLK
gpmc_clk
FA21
FA20
FA20
FA20
FA1
gpmc_csi
FA9
Add0
gpmc_a[27:1]
Add1
Add2
Add3
D0
D1
D2
Add4
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen_ren
gpmc_ad[15:0]
D3
D3
gpmc_waitj
FA15
FA14
DIR
OUT
IN
OUT
SPRS91v_GPMC_09
Figure 7-15. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4)(5)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled
by active functional clock edge. FA21 calculation is detailled in a separated application note and should be stored inside AccessTime
register bits field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC
functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first
input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(5) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
Timing Requirements and Switching Characteristics
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gpmc_fclk
gpmc_clk
FA1
gpmc_csi
FA9
Valid Address
gpmc_a[27:1]
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
FA29
Data OUT
gpmc_ad[15:0]
gpmc_waitj
DIR
OUT
GPMC_10
Figure 7-16. GPMC / NOR Flash - Asynchronous Write - Single Word Timing(1)(2)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
252
Timing Requirements and Switching Characteristics
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csi
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
gpmc_ben0
Valid
FA0
FA10
Valid
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
FA29
gpmc_ad[15:0]
FA37
Address (LSB)
Data IN
Data IN
FA15
FA14
DIR
OUT
IN
OUT
gpmc_waitj
GPMC_11
Figure 7-17. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)(4)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
Timing Requirements and Switching Characteristics
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gpmc_fclk
gpmc_clk
FA1
gpmc_csi
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
FA29
FA28
Valid Address (LSB)
gpmc_ad[15:0]
Data OUT
gpmc_waitj
OUT
DIR
GPMC_12
Figure 7-18. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1)(2)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
CAUTION
The IO Timings provided in this section are only valid for some GPMC usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-29 and Table 7-30 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-19, Figure 7-20, Figure 7-21, and Figure 7-22).
Table 7-29. GPMC/NAND Flash Interface Timing Requirements
NO.
GNF12
254
PARAMETER
DESCRIPTION
tacc(DAT)
Data maximum access time (GPMC_FCLK Cycles)
-
tsu(DV-OEH)
Setup time, read gpmc_ad[15:0] valid before
gpmc_oen_ren high
-
th(OEH-DV)
Hold time, read gpmc_ad[15:0] valid after
gpmc_oen_ren high
MIN
MAX
UNIT
(1)
cycles
J
1.9
ns
1
ns
Timing Requirements and Switching Characteristics
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(1) J = AccessTime * (TimeParaGranularity + 1)
Table 7-30. GPMC/NAND Flash Interface Switching Characteristics
NO.
MIN
MAX
UNIT
-
tr(DO)
PARAMETER
Rising time, gpmc_ad[15:0] output data
DESCRIPTION
0.447
4.067
ns
-
0.43
4.463
ns
A
(1)
ns
B+4
(2)
ns
ns
tf(DO)
Fallling time, gpmc_ad[15:0] output data
GNF0
tw(nWEV)
Pulse duration, gpmc_wen valid time
GNF1
td(nCSV-nWEV)
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
B-2
(2)
GNF2
td(CLEH-nWEV)
Delay time, gpmc_ben[1:0] high to gpmc_wen valid
C-2
(3)
C+4
(3)
GNF3
td(nWEV-DV)
Delay time, gpmc_ad[15:0] valid to gpmc_wen valid
D-2
(4)
D+4
(4)
ns
GNF4
td(nWEIV-DIV)
Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid
E-2
(5)
E+4
(5)
ns
GNF5
td(nWEIV-CLEIV)
Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid
F-2
(6)
F+4
(6)
ns
ns
GNF6
td(nWEIV-nCSIV)
Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid
G-2
(7)
G+4
(7)
GNF7
td(ALEH-nWEV)
Delay time, gpmc_advn_ale high to gpmc_wen valid
C-2
(3)
C+4
(3)
ns
GNF8
td(nWEIV-ALEIV)
Delay time, gpmc_wen invalid to gpmc_advn_ale invalid
F-2
(6)
F+4
(6)
ns
H
(8)
ns
I+4
(9)
ns
K
(10)
ns
L
(11)
ns
M+4
(12)
ns
GNF9
tc(nWE)
Cycle time, write cycle time
GNF10 td(nCSV-nOEV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
GNF13 tw(nOEV)
Pulse duration, gpmc_oen_ren valid time
GNF14 tc(nOE)
Cycle time, read cycle time
GNF15 td(nOEIV-nCSIV)
Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid
I-2
M-2
(9)
(12)
(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
(5) E = (WrCycleTime – WEOffTime * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK
(6) F = (ADVWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay) * GPMC_FCLK
(7) G = (CSWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay) * GPMC_FCLK
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(9) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *
GPMC_FCLK
(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(12) M = (CSRdOffTime – OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay) * GPMC_FCLK
Timing Requirements and Switching Characteristics
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GPMC_FCLK
GNF1
GNF6
GNF2
GNF5
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF0
gpmc_wen
GNF3
GNF4
Command
gpmc_ad[15:0]
GPMC_13
(1)
Figure 7-19. GPMC / NAND Flash - Command Latch Cycle Timing
(1) In gpmc_csi, i = 0 to 7.
GPMC_FCLK
GNF1
GNF6
GNF7
GNF8
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
gpmc_ad[15:0]
GNF4
Address
GPMC_14
Figure 7-20. GPMC / NAND Flash - Address Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
256
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GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_csi
gpmc_ben0
gpmc_advn_ale
GNF14
GNF13
gpmc_oen_ren
gpmc_ad[15:0]
DATA
gpmc_waitj
GPMC_15
Figure 7-21. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)
(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
GPMC_FCLK
GNF1
GNF6
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
DATA
GPMC_16
(1)
Figure 7-22. GPMC / NAND Flash - Data Write Cycle Timing
(1) In gpmc_csi, i = 0 to 7.
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Chapter
18 - Control Module.
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Virtual IO Timings Modes must be used to guarantee some IO timings for GPMC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-31 Virtual
Functions Mapping for GPMC for a definition of the Virtual modes.
Table 7-31 presents the values for DELAYMODE bitfield.
Table 7-31. Virtual Functions Mapping for GPMC
BALL
BALL NAME
Delay Mode Value
MUXMODE[15:0]
GPMC_VIRTUAL1
0
M6
gpmc_ad0
11
gpmc_ad0
M2
gpmc_ad1
11
gpmc_ad1
L5
gpmc_ad2
11
gpmc_ad2
M1
gpmc_ad3
11
gpmc_ad3
L6
gpmc_ad4
11
gpmc_ad4
L4
gpmc_ad5
11
gpmc_ad5
L3
gpmc_ad6
11
gpmc_ad6
L2
gpmc_ad7
11
gpmc_ad7
L1
gpmc_ad8
11
gpmc_ad8
K2
gpmc_ad9
11
gpmc_ad9
J1
gpmc_ad10
11
gpmc_ad10
J2
gpmc_ad11
11
gpmc_ad11
H1
gpmc_ad12
11
gpmc_ad12
J3
gpmc_ad13
11
gpmc_ad13
H2
gpmc_ad14
11
gpmc_ad14
H3
gpmc_ad15
11
gpmc_ad15
R6
gpmc_a0
11
gpmc_a0
T9
gpmc_a1
11
gpmc_a1
T6
gpmc_a2
11
gpmc_a2
T7
gpmc_a3
10
gpmc_a3
P6
gpmc_a4
10
gpmc_a4
R9
gpmc_a5
11
gpmc_a5
R5
gpmc_a6
11
gpmc_a6
P5
gpmc_a7
11
gpmc_a7
N7
gpmc_a8
12
gpmc_a8
R4
gpmc_a9
12
gpmc_a9
N9
gpmc_a10
12
gpmc_a10
P9
gpmc_a11
11
gpmc_a11
P4
gpmc_a12
13
gpmc_a12
R3
gpmc_a13
12
gpmc_a13
T2
gpmc_a14
12
gpmc_a14
U2
gpmc_a15
12
gpmc_a15
U1
gpmc_a16
12
gpmc_a16
1
2
5
6
gpmc_a0
P3
gpmc_a17
12
gpmc_a17
R2
gpmc_a18
12
gpmc_a18
K7
gpmc_a19
11
gpmc_a19
gpmc_a13
M7
gpmc_a20
11
gpmc_a20
gpmc_a14
J5
gpmc_a21
11
gpmc_a21
gpmc_a15
K6
gpmc_a22
11
gpmc_a22
gpmc_a16
J7
gpmc_a23
11
gpmc_a23
gpmc_a17
J4
gpmc_a24
11
gpmc_a24
gpmc_a18
258
3
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Table 7-31. Virtual Functions Mapping for GPMC (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE[15:0]
GPMC_VIRTUAL1
0
1
2
3
J6
gpmc_a25
11
gpmc_a25
gpmc_a19
H4
gpmc_a26
11
gpmc_a26
gpmc_a20
H5
gpmc_a27
11
gpmc_a27
gpmc_a21
H6
gpmc_cs1
11
gpmc_cs1
gpmc_a22
T1
gpmc_cs0
14
gpmc_cs0
P2
gpmc_cs2
12
gpmc_cs2
P1
gpmc_cs3
10
gpmc_cs3
P7
gpmc_clk
12
gpmc_clk
gpmc_cs7
gpmc_wait1
N1
gpmc_advn_
ale
13
gpmc_advn_
ale
gpmc_cs6
gpmc_wait1
M5
gpmc_oen_re
n
14
gpmc_oen_re
n
M3
gpmc_wen
14
gpmc_wen
5
6
gpmc_a1
gpmc_a2
N6
gpmc_ben0
11
gpmc_ben0
gpmc_cs4
M4
gpmc_ben1
11
gpmc_ben1
gpmc_cs5
N2
gpmc_wait0
14
gpmc_wait0
AG5
vin1a_d11
9
gpmc_a23
AF2
vin1a_d12
9
gpmc_a24
AF6
vin1a_d13
9
gpmc_a25
AF3
vin1a_d14
9
gpmc_a26
AF4
vin1a_d15
9
gpmc_a27
gpmc_a23
gpmc_a3
7.11 Timers
The device has 16 general-purpose (GP) timers (TIMER1 - TIMER16), two watchdog timers, and a 32-kHz
synchronized timer (COUNTER_32K) that have the following features:
• Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)
signal
• Interrupts generated on overflow, compare, and capture
• Free-running 32-bit upward counter
• Supported modes:
– Compare and capture modes
– Auto-reload mode
– Start-stop mode
• On-the-fly read/write register (while counting)
The device has two system watchdog timer (WD_TIMER1 and WD_TIMER2) that have the following
features:
• Free-running 32-bit upward counter
• On-the-fly read/write register (while counting)
• Reset upon occurrence of a timer overflow condition
The device includes one instance of the 32-bit watchdog timer: WD_TIMER2, also called the MPU
watchdog timer.
The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
Timing Requirements and Switching Characteristics
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NOTE
For additional information on the Timer Module, see the Device TRM.
7.12 Inter-Integrated Circuit Interface (I2C)
The device includes 5 inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module.
NOTE
Note that, on I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is
not supported
NOTE
Inter-integrated circuit i ( i=1 to 5) module is also referred to as I2Ci
NOTE
For more information, see the Multimaster High-Speed I2C Controller section of the Device
TRM.
Table 7-32, Table 7-33 and Figure 7-23 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
Table 7-32. Timing Requirements for I2C Input Timings(1)
NO.
PARAMETER
DESCRIPTION
STANDARD MODE
MIN
MAX
FAST MODE
MIN
MAX
UNIT
1
tc(SCL)
Cycle time, SCL
10
2.5
µs
2
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7
0.6
µs
3
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START
and a repeated START condition)
4
0.6
µs
4
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
5
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
6
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
100(2)
7
(3)
ns
(4)
Hold time, SDA valid after SCL low
0
8
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions
4.7
9
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
300(3)
ns
10
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
300(3)
ns
11
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
300(3)
ns
12
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb
300(3)
ns
13
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for
STOP condition)
14
tw(SP)
Pulse duration, spike (must be suppressed)
15
(5)
260
Capacitive load for each bus line
0
(3)
th(SCLL-SDAV)
Cb
3.45
(4)
0.9
1.3
4
(5)
(5)
(5)
(5)
µs
0.6
0
400
µs
µs
50
ns
400
pF
Timing Requirements and Switching Characteristics
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(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Table 7-33. Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)(1)
NO.
PARAMETER
DESCRIPTION
1
tc(SCL)
Cycle time, SCL
2
tsu(SCLH-SDAL)
3
Cb = 400 pF (2)
Cb = 100 pF MAX
MIN
MAX
MIN
UNIT
MAX
0.294
0.588
us
Set-up time, SCL high before
SDA low (for a repeated START
condition)
160
160
ns
th(SDAL-SCLL)
Hold time, SCL low after SDA
low (for a repeated START
condition)
160
160
ns
4
tw(SCLL)
LOW period of the SCLH clock
160
320
ns
5
tw(SCLH)
HIGH period of the SCLH clock
60
120
ns
6
tsu(SDAV-SCLH)
Setup time, SDA valid vefore
SCL high
10
10
ns
7
th(SCLL-SDAV)
Hold time, SDA valid after SCL
low
0
13
tsu(SCLH-SDAH)
Setup time, SCL high before
SDA high (for a STOP condition)
160
14
tw(SP)
Pulse duration, spike (must be
suppressed)
15
Cb (2)
Capacitive load for SDAH and
SCLH lines
16
Cb
Capacitive load for SDAH + SDA
line and SCLH + SCL line
(3)
70
0
(3)
150
ns
160
0
10
ns
0
10
ns
100
400
pF
400
400
pF
(1) I2C HS-Mode is only supported on I2C3/4/5. I2C HS-Mode is not supported on I2C1/2.
(2) For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
9
11
I2Ci_SDA
6
8
14
4
13
5
10
I2Ci_SCL
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
Figure 7-23. I2C Receive Timing
Timing Requirements and Switching Characteristics
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Table 7-34 and Figure 7-24 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 7-34. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)
NO.
16
PARAMETER
STANDARD MODE
DESCRIPTION
MIN
FAST MODE
MAX
MIN
MAX
UNIT
tc(SCL)
Cycle time, SCL
10
2.5
µs
17
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7
0.6
µs
18
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
4
0.6
µs
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
21
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
100
ns
22
th(SCLL-SDAV)
Hold time, SDA valid after SCL low (for I2C
bus devices)
23
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions
24
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
300(3)
ns
25
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
300(3)
ns
26
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
300(3)
ns
27
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb
300(3)
ns
28
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for
STOP condition)
29
Cp
Capacitance for each I2C pin
0
3.45
0
4.7
0.9
µs
1.3
(1) (3)
(1) (3)
(1) (3)
(1) (3)
4
µs
0.6
µs
10
10
pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.
(3) These timings apply only to I2C1 and I2C2. I2C3, I2C4, and I2C5 use standard LVCMOS buffers to emulate open-drain buffers and their
rise/fall times should be referenced in the device IBIS model.
NOTE
I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of
driving high when transmitting logic-1.
24
26
I2Ci_SDA
21
23
19
28
20
25
I2Ci_SCL
27
16
18
22
17
18
Stop
Start
Repeated
Start
Stop
Figure 7-24. I2C Transmit Timing
262
Timing Requirements and Switching Characteristics
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7.13 HDQ / 1-Wire Interface (HDQ1W)
The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to
communicate between the master and the slave. The protocols employ an asynchronous return to one
mechanism where, after any command, the line is pulled high.
NOTE
For more information, see the HDQ / 1-Wire section of the Device TRM.
7.13.1 HDQ / 1-Wire — HDQ Mode
Table 7-35 and Table 7-36 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-25, Figure 7-26, Figure 7-27 and Figure 7-28).
Table 7-35. HDQ/1-Wire Timing Requirements—HDQ Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
1
tCYCH
Read bit window timing
190
250
µs
2
tHW1
Read one data valid after HDQ low
32(2)
66(2)
µs
3
tHW0
Read zero data hold after HDQ low
70(2)
145(2)
µs
4
tRSPS
Response time from HDQ slave device(1)
190
320
µs
(1) Defined by software.
(2) If the HDQ slave device drives a logic-low state after tHW0 maximum, it can be interpreted as a break pulse. For more information see
"HDQ / 1-Wire Switching Characteristics - HDQ Mode" and the HDQ/1-Wire chapter of the TRM.
Table 7-36. HDQ / 1-Wire Switching Characteristics - HDQ Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
5
tB
Break timing
190
µs
6
tBR
Break recovery time
40
µs
7
tCYCD
Write bit windows timing
190
µs
8
tDW1
Write one data valid after HDQ low
0.5
50
µs
9
tDW0
Write zero data hold after HDQ low
86
145
µs
tB
tBR
HDQ
Figure 7-25. HDQ Break and Break Recovery Timing — HDQ Interface Writing to Slave
tCYCH
tHW0
tHW1
HDQ
Figure 7-26. Device HDQ Interface Bit Read Timing (Data)
tCYCD
tDW0
tDW1
HDQ
Figure 7-27. Device HDQ Interface Bit Write Timing (Command / Address or Data)
Timing Requirements and Switching Characteristics
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Command_byte_written
Data_byte_received
tRSPS
0_(LSB)
Break
1
6
1
7_(MSB)
0_(LSB)
6
HDQ
Figure 7-28. HDQ Communication Timing
7.13.2 HDQ/1-Wire—1-Wire Mode
Table 7-37 and Table 7-38 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-29, Figure 7-30 and Figure 7-31).
Table 7-37. HDQ / 1-Wire Timing Requirements - 1-Wire Mode
NO.
MIN
MAX
UNIT
10
tPDH
PARAMETER
Presence pulse delay high
DESCRIPTION
15
60
µs
11
tPDL
Presence pulse delay low
60
240
µs
12
tRDV
Read data valid time
tLOWR
15
µs
13
tREL
Read data release time
0
45
µs
Table 7-38. HDQ / 1-Wire Switching Characteristics - 1-Wire Mode
NO.
MIN
MAX
UNIT
14
tRSTL
PARAMETER
Reset time low
DESCRIPTION
480
960
µs
15
tRSTH
Reset time high
480
16
tSLOT
Bit cycle time
60
120
µs
17
tLOW1
Write bit-one time
1
15
µs
18
tLOW0
Write bit-zero time(2)
60
120
µs
19
tREC
Recovery time
1
20
tLOWR
Read bit strobe time(1)
1
µs
µs
15
µs
(1) tLOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window.
(2) tLOW0 must be less than tSLOT.
tRSTH
tRTSL
tPDH
tPDL
1-WIRE
Figure 7-29. 1-Wire—Break (Reset)
tSLOT_and_tREC
tRDV_and_tREL
tLOWR
1-WIRE
Figure 7-30. 1-Wire—Read Bit (Data)
264
Timing Requirements and Switching Characteristics
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tSLOT_and_tREC
tLOW0
tLOW1
1-WIRE
Figure 7-31. 1-Wire—Write Bit-One Timing (Command / Address or Data)
7.14 Universal Asynchronous Receiver Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallelto-serial conversion on data received from the CPU. There are 10 UART modules in the device. Only one
UART supports IrDA features. Each UART can be used for configuration and data exchange with a
number of external peripheral devices or interprocessor communication between devices
The UARTi (where i = 1 to 10) include the following features:
• 16C750 compatibility
• 64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
• Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed
functional clock of 48 MHz or 192 MHz
• Break character detection and generation
• Configurable data format:
– Data bit: 5, 6, 7, or 8 bits
– Parity bit: Even, odd, none
– Stop-bit: 1, 1.5, 2 bit(s)
• Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
• Only UART1 module has extended modem control signals (CD, RI, DTR, DSR)
• Only UART3 supports IrDA
NOTE
For more information, see the UART section of the Device TRM.
Table 7-39, Table 7-40 and Figure 7-32 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
Table 7-39. Timing Requirements for UART
NO.
MIN
MAX
UNIT
4
tw(RX)
PARAMETER
Pulse width, receive data bit, 15/30/100pF high or low
DESCRIPTION
0.96U(1)
1.05U(1)
ns
5
tw(CTS)
Pulse width, receive start bit, 15/30/100pF high or low
0.96U(1)
1.05U(1)
ns
(2)
ns
ns
td(RTS-TX)
Delay time, transmit start bit to transmit data
P
td(CTS-TX)
Delay time, receive start bit to transmit data
P(2)
(1) U = UART baud time = 1/programmed baud rate
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz).
Table 7-40. Switching Characteristics Over Recommended Operating Conditions for UART
NO.
PARAMETER
DESCRIPTION
MIN
15 pF
f(baud)
2
3
tw(TX)
tw(RTS)
Maximum programmable baud rate
MAX
UNIT
12
30 pF
0.23
100 pF
0.115
MHz
Pulse width, transmit data bit, 15/30/100 pF high or low
U - 2(1)
U + 2(1)
ns
Pulse width, transmit start bit, 15/30/100 pF high or low
(1)
(1)
ns
U-2
U+2
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(1) U = UART baud time = 1/programmed baud rate
3
2
UARTi_TXD
Start
Bit
Data Bits
5
4
UARTi_RXD
Start
Bit
Data Bits
Figure 7-32. UART Timing
7.15 Multichannel Serial Peripheral Interface (MCSPI)
The MCSPI is a master/slave synchronous serial bus. There are four separate MCSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip
selects) and are able to work as both master and slave.
The MCSPI modules include the following main features:
• Serial clock with programmable frequency, polarity, and phase for each channel
• Wide selection of SPI word lengths, ranging from 4 to 32 bits
• Up to four master channels, or single channel in slave mode
• Master multichannel mode:
– Full duplex/half duplex
– Transmit-only/receive-only/transmit-and-receive modes
– Flexible input/output (I/O) port controls per channel
– Programmable clock granularity
– SPI configuration per channel. This means, clock definition, polarity enabling and word width
• Power management through wake-up capabilities
• Programmable timing control between chip select and external clock generation
• Built-in FIFO available for a single channel.
• Each SPI module supports multiply chip select pins spim_cs[i], whete i = 1 to 4.
NOTE
For more information, see the Serial Communication Interface section of the device TRM.
NOTE
The MCSPIm module (m = 1 to 4) is also referred to as SPIm.
CAUTION
The IO timings provided in this section are applicable for all combinations of
signals for SPI1 and SPI2. However, the timings are only valid for SPI3 and
SPI4 if signals within a single IOSET are used. The IOSETS are defined in the
Table 7-43.
266
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Table 7-41, Figure 7-33 and Figure 7-34 present Timing Requirements for McSPI - Master Mode.
Table 7-41. Timing Requirements for SPI - Master Mode (1)(8)
NO.
PARAMETER
DESCRIPTION
SM1
tc(SPICLK)
Cycle time, spi_sclk (1) (2)
MODE
SM2
tw(SPICLKL)
Typical Pulse duration, spi_sclk low
SM3
tw(SPICLKH)
Typical Pulse duration, spi_sclk high
SM4
tsu(MISO-SPICLK)
Setup time, spi_d[x] valid before spi_sclk active edge (1)
SPI1/2/3/4
(1)
(1)
(1)
th(SPICLK-MISO)
Hold time, spi_d[x] valid after spi_sclk active edge
td(SPICLK-SIMO)
Delay time, spi_sclk active edge to spi_d[x] transition
ns
ns
0.5*P-1
ns
4.4
ns
3.9
(1)
SM7
td(CS-SIMO)
Delay time, spi_cs[x] active edge to spi_d[x] transition
SM8
td(CS-SPICLK)
Delay time, spi_cs[x] active to spi_sclk first edge (1)
ns
SPI1
-4.27
4.27
ns
SPI2
-4.32
4.32
ns
SPI3
-5.37
4.23
ns
SPI4
-3.81
4..41
ns
5
ns
MASTER_PHA0
B-4.6 (6)
ns
MASTER_PHA1
A-4.6 (7)
ns
MASTER_PHA0
A-4.6 (7)
ns
MASTER_PHA1
B-4.6 (6)
ns
(5)
(5)
Delay time, spi_sclk last edge to spi_cs[x] inactive (1)
UNIT
0.5*P-1
(4)
SM6
td(SPICLK-CS)
MAX
(3)
(4)
SM5
SM9
MIN
20.8
(5)
(5)
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) 20.8ns cycle time = 48MHz, 26ns cycle time = 38.4MHz
(4) P = SPICLK period.
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(6) B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(8) The IO timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are only
valid for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.
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PHA=0
EPOL=1
spim_cs(OUT)
SM1
SM3
SM8
spim_sclk(OUT)
SM2
SM9
POL=0
SM3
SM1
SM2
POL=1
spim_sclk(OUT)
SM7
SM6
Bit n-1
spim_d(OUT)
SM6
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(OUT)
SM2
SM1
SM8
spim_sclk(OUT)
SM3
SM9
POL=0
SM1
SM2
SM3
POL=1
spim_sclk(OUT)
SM6
spim_d(OUT)
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
Figure 7-33. McSPI - Master Mode Transmit
268
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PHA=0
EPOL=1
spim_cs(OUT)
SM1
SM3
SM8
spim_sclk(OUT)
SM2
SM9
POL=0
SM3
SM1
SM2
POL=1
spim_sclk(OUT)
SM5
SM5
spim_d(IN)
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(OUT)
SM2
SM1
SM8
spim_sclk(OUT)
SM3
SM9
POL=0
SM1
SM2
SM3
POL=1
spim_sclk(OUT)
SM5
SM4
SM4
Bit n-1
spim_d(IN)
SM5
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 7-34. McSPI - Master Mode Receive
Table 7-42, Figure 7-35 and Figure 7-36 present Timing Requirements for McSPI - Slave Mode.
Table 7-42. Timing Requirements for SPI - Slave Mode
NO.
PARAMETER
DESCRIPTION
MODE
(1) (2)
(3)
SS1
tc(SPICLK)
Cycle time, spi_sclk
SS2
tw(SPICLKL)
Typical Pulse duration, spi_sclk low
SS3
tw(SPICLKH)
Typical Pulse duration, spi_sclk high
SS4
tsu(SIMO-SPICLK)
Setup time, spi_d[x] valid before spi_sclk active edge (1)
(1)
(1)
(1)
SS5
th(SPICLK-SIMO)
Hold time, spi_d[x] valid after spi_sclk active edge
SS6
td(SPICLK-SOMI)
Delay time, spi_sclk active edge to mcspi_somi transition
MIN
MAX
62.5
ns
0.45*P
(4)
ns
0.45*P
(4)
ns
5
ns
5
(1)
UNIT
ns
SPI1/2/3
2
26.1
ns
SPI4
2
18
ns
20.95
ns
(1)
SS7
td(CS-SOMI)
Delay time, spi_cs[x] active edge to mcspi_somi transition
SS8
tsu(CS-SPICLK)
Setup time, spi_cs[x] valid before spi_sclk first edge (1)
5
ns
SS9
th(SPICLK-CS)
Hold time, spi_cs[x] valid after spi_sclk last edge (1)
5
ns
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(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
(3) 62.5ns Cycle time = 16 MHz
(4) P = SPICLK period.
(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
PHA=0
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
spim_sclk(IN)
SS3
SS9
POL=0
SS2
SS1
SS3
POL=1
spim_sclk(IN)
SS7
SS6
Bit n-1
spim_d(OUT)
SS6
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
spim_sclk(IN)
SS3
SS9
POL=0
SS3
SS1
SS2
POL=1
spim_sclk(IN)
SS6
spim_d(OUT)
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
Figure 7-35. McSPI - Slave Mode Transmit
270
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PHA=0
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
spim_sclk(IN)
SS3
SS9
POL=0
SS2
SS1
SS3
POL=1
spim_sclk(IN)
SS5
SS4
SS4
SS5
Bit n-1
spim_d(IN)
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
spim_sclk(IN)
SS3
SS9
POL=0
SS3
SS1
SS2
POL=1
spim_sclk(IN)
SS4
SS5
SS4
Bit n-1
spim_d(IN)
SS5
Bit n-2
Bit n-3
Bit 1
Bit0
Figure 7-36. McSPI - Slave Mode Receive
In Table 7-43 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4.
Table 7-43. McSPI3/4 IOSETs
Signal
IOSET1
BALL
IOSET2
MUX
BALL
IOSET3
MUX
BALL
IOSET4
IOSET5
IOSET6
MUX
BALL
MUX
BALL
MUX
BALL
MUX
SPI3
spi3_sclk
AD9
8
E11
8
V2
7
B12
3
C18
2
AC4
1
spi3_d1
AF9
8
B10
8
Y1
7
A11
3
A21
2
AC7
1
spi3_d0
AE9
8
C11
8
W9
7
B13
3
G16
2
AC6
1
spi3_cs0
AF8
8
D11
8
V9
7
A12
3
D17
2
AC9
1
spi3_cs1
-
-
B11
8
-
-
E14
3
-
-
AC3
1
spi3_cs2
-
-
F11
8
-
-
-
-
-
-
-
-
spi3_cs3
-
-
A10
8
-
-
-
-
-
-
-
-
spi4_sclk
N7
8
G1
8
V7
7
AA3
2
AC8
1
-
-
spi4_d1
R4
8
G6
8
U7
7
AB9
2
AD6
1
-
-
SPI4
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Table 7-43. McSPI3/4 IOSETs (continued)
Signal
IOSET1
IOSET2
IOSET3
BALL
MUX
BALL
MUX
IOSET4
IOSET5
IOSET6
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
spi4_d0
N9
8
F2
8
V6
7
AB3
2
AB8
1
-
-
spi4_cs0
P9
8
F3
8
U6
7
AA4
2
AB5
1
-
-
spi4_cs1
P4
8
-
-
Y1
8
-
-
-
-
-
-
spi4_cs2
R3
8
-
-
W9
8
-
-
-
-
-
-
spi4_cs3
T2
8
-
-
V9
8
-
-
-
-
-
-
7.16 Quad Serial Peripheral Interface (QSPI)
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to
external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. It
works as a master only. There is one QSPI module in the device and it is primary intended for fast
booting from quad-SPI flash memories.
General SPI features:
• Programmable clock divider
• Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
• 4 external chip select signals
• Support for 3-, 4- or 6-pin SPI interface
• Programmable CS_N to DOUT delay from 0 to 3 DCLKs
• Programmable signal polarities
• Programmable active clock edge
• Software controllable interface allowing for any type of SPI transfer
NOTE
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The IO Timings provided in this section are only valid for some QSPI usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
CAUTION
The IO Timings provided in this section are only valid when all QSPI Chip
Selects used in a system are configured to use the same Clock Mode (either
Clock Mode 0 or Clock Mode3).
Table 7-44 and Table 7-45 present Timing and Switching Characteristics for Quad SPI Interface.
272
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Table 7-44. Switching Characteristics for QSPI
No
PARAMETER
DESCRIPTION
Mode
MIN
Q1
tc(SCLK)
Cycle time, sclk
Default
Timing
Mode,
Clock
Mode 0
13.02
MAX
UNIT
ns
Default
Timing
Mode,
Clock
Mode 3
20.8
ns
Y*P-1 (1)
ns
Q2
tw(SCLKL)
Pulse duration, sclk low
Q3
tw(SCLKH)
Pulse duration, sclk high
Y*P-1 (1)
ns
Q4
td(CS-SCLK)
Delay time, sclk falling edge to cs active edge, CS3:0
Default
Timing
Mode
-M*P-2.0 -M*P+2.0
(2) (3)
(2) (3)
ns
Q5
td(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge, CS3:0
Default
Timing
Mode
N*P-2.0
(2) (3)
N*P+2.0
(2) (3)
ns
Q6
td(SCLK-D1)
Delay time, sclk falling edge to d[0] transition
Default
Timing
Mode
-2
2
ns
Q7
tena(CS-D1LZ)
Enable time, cs active edge to d[0] driven (lo-z)
-P-3.5
-P+2.5
ns
Q8
tdis(CS-D1Z)
Disable time, cs active edge to d[0] tri-stated (hi-z)
-P-2.5
-P+2.0
ns
Q9
td(SCLK-D0)
Delay time, sclk first falling edge to first d[0] transition
-2.45 - P
1 .45 - P
ns
PHA=0
Only,
Default
Timing
Mode
(1) The Y parameter is defined as follows:
If DCLK_DIV is 0 or ODD then, Y equals 0.5.
If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).
For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on
CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division
factor DCLK_DIV can be found in the device TRM.
(2) P = SCLK period.
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.
N = 2 when Clock Mode 0.
N = 3 when Clock Mode 3.
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PHA=1
cs
Q5
Q1
POL=1
Q4
Q3
Q2
sclk
Q15
POL=1
Q14
rtclk
Q6
Q7
Q6
Command
Bit n-1
d[0]
Command
Bit n-2
d[3:1]
Q12 Q13
Read Data
Read Data
Bit 1
Bit 0
Q14
Q15
Q12 Q13
Read Data
Read Data
Bit 1
Bit 0
SPRS85v_TIMING_OSPI1_01
Figure 7-37. QSPI Read (Clock Mode 3)
PHA=0
cs
Q5
Q4
Q1
Q2
POL=0
Q3
sclk
POL=0
rtclk
Q7
d[0]
Q6
Q9
Command Command
Bit n-1
Bit n-2
Q12 Q13
Read Data
Bit 1
Q12 Q13
d[3:1]
Read Data
Bit 1
Q12 Q13
Read Data
Bit 0
Q12 Q13
Read Data
Bit 0
SPRS85v_TIMING_OSPI1_02
Figure 7-38. QSPI Read (Clock Mode 0)
274
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CAUTION
The IO Timings provided in this section are only valid for some QSPI usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-45. Timing Requirements for QSPI
No
PARAMETER
DESCRIPTION
Mode
MIN
Q12
tsu(D-RTCLK)
Setup time, d[3:0] valid before falling rtclk edge
Default
Timing
Mode,
Clock
Mode 0
5.1
ns
tsu(D-SCLK)
Setup time, d[3:0] valid before falling sclk edge
Default
Timing
Mode,
Clock
Mode 3
12.3
ns
th(RTCLK-D)
Hold time, d[3:0] valid after falling rtclk edge
Default
Timing
Mode,
Clock
Mode 0
-0.1
ns
th(SCLK-D)
Hold time, d[3:0] valid after falling sclk edge
Default
Timing
Mode,
Clock
Mode 3
0
ns
Q14
tsu(D-SCLK)
Setup time, final d[3:0] bit valid before final falling sclk edge
Default
Timing
Mode,
Clock
Mode 3
12.3-P
(1)
ns
Q5
th(SCLK-D)
Hold time, final d[3:0] bit valid after final falling sclk edge
Default
Timing
Mode,
Clock
Mode 3
0+P (1)
ns
Q13
MAX
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UNIT
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(1) P = SCLK period.
(2) Clock Modes 1 and 2 are not supported.
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although
nonstandard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Modes 0 and 3.
PHA=1
cs
Q5
POL=1
Q1
Q4
Q3
Q2
sclk
Q7
d[0]
Command
Bit n-1
Write Data
Bit 1
Command
Bit n-2
Q8
Q6
Q6
Q6
Q6
Write Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_03
Figure 7-39. QSPI Write (Clock Mode 3)
PHA=0
cs
Q5
Q4
POL=0
Q1
Q2
Q3
sclk
Q7
d[0]
Q9
Q6
Command Command
Bit n-1
Bit n-2
Q6
Q8
Q6
Write Data
Bit 1
Write Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_04
Figure 7-40. QSPI Write (Clock Mode 0)
276
Timing Requirements and Switching Characteristics
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NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for QSPI. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-46 Manual
Functions Mapping for QSPI for a definition of the Manual modes.
Table 7-46 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Timing Requirements and Switching Characteristics
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Table 7-46. Manual Functions Mapping for QSPI
BALL
T7
BALL NAME
QSPI_MODE0_MANUAL1
CFG REGISTER
MUXMODE
0
CFG_GPMC_A3_OUT
qspi1_cs2
A_DELAY (ps)
G_DELAY (ps)
gpmc_a3
114
1
P6
gpmc_a4
91
0
CFG_GPMC_A4_OUT
qspi1_cs3
R3
gpmc_a13
0
0
CFG_GPMC_A13_IN
qspi1_rtclk
T2
gpmc_a14
2575
966
CFG_GPMC_A14_IN
qspi1_d3
U2
gpmc_a15
2503
889
CFG_GPMC_A15_IN
qspi1_d2
U1
gpmc_a16
2528
1007
CFG_GPMC_A16_IN
qspi1_d0
U1
gpmc_a16
0
0
CFG_GPMC_A16_OUT
qspi1_d0
P3
gpmc_a17
2533
980
CFG_GPMC_A17_IN
qspi1_d1
R2
gpmc_a18
590
0
CFG_GPMC_A18_OUT
qspi1_sclk
P2
gpmc_cs2
0
0
CFG_GPMC_CS2_OUT
qspi1_cs0
P1
gpmc_cs3
70
0
CFG_GPMC_CS3_OUT
qspi1_cs1
7.17 Multichannel Audio Serial Port (McASP)
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio
applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital
audio interface transmission (DIT).
The device have integrated 8 McASP modules (McASP1-McASP8) with:
• McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain
• McASP3 through McASP8 modules supporting 4 channels with independent TX/RX clock/sync domain
NOTE
For more information, see the Multichannel Audio Serial Port section of the Device TRM.
CAUTION
The IO Timings provided in this section are only valid for some McASP usage modes when the corresponding Virtual IO
Timings or Manual IO Timings are configured as described in the tables found in this section.
Table 7-47, Table 7-48, Table 7-49 and Figure 7-41 present Timing Requirements for McASP1 to McASP8.
278
Timing Requirements and Switching Characteristics
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Table 7-47. Timing Requirements for McASP1 (1)
NO.
PARAMETER
DESCRIPTION
1
tc(AHCLKRX)
Cycle time, AHCLKR/X
2
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
3
tc(ACLKRX)
Cycle time, ACLKR/X
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
6
7
8
th(ACLK-AFSRX)
tsu(AXR-ACLK)
th(ACLK-AXR)
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKR/X
Hold time, AXR input valid after ACLKR/X
MODE
MIN
MAX
UNIT
20
ns
0.35P
ns
(2)
20
ns
0.5R - 3
ns
ACLKR/X int
20
ns
ACLKR/X ext in
ACLKR/X ext out
4
ns
(3)
ACLKR/X int
-1
ns
ACLKR/X ext in
ACLKR/X ext out
2.21
ns
ACLKR/X int
21.9
ns
ACLKR/X ext in
ACLKR/X ext out
4.42
ns
ACLKR/X int
-1
ns
ACLKR/X ext in
ACLKR/X ext out
2.52
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Table 7-48. Timing Requirements for McASP2 (1)
NO.
PARAMETER
DESCRIPTION
1
tc(AHCLKRX)
Cycle time, AHCLKR/X
2
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
3
tc(ACLKRX)
Cycle time, ACLKR/X
4
5
6
7
tw(ACLKRX)
tsu(AFSRX-ACLK)
th(ACLK-AFSRX)
tsu(AXR-ACLK)
Pulse duration, ACLKR/X high or low
Setup time, AFSR/X input valid before ACLKR/X
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKR/X
MODE
MIN
MAX
ns
0.35P
ns
Any Other
Conditions
20
ns
ACLKX/AFSX (In
Sync Mode),
ACLKR/AFSR (In
Async Mode), and
AXR are all inputs
12.5
ns
Any Other
Conditions
0.5R - 3
ns
ACLKX/AFSX (In
Sync Mode),
ACLKR/AFSR (In
Async Mode), and
AXR are all inputs
0.38R
ns
(2)
(3)
(3)
ACLKR/X int
20.7
ns
ACLKR/X ext in
ACLKR/X ext out
3
ns
ACLKR/X int
-1
ns
ACLKR/X ext in
ACLKR/X ext out
3
ns
ACLKR/X int
21.4
ns
ACLKR/X ext in
ACLKR/X ext out
3
ns
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UNIT
20
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Table 7-48. Timing Requirements for McASP2 (1) (continued)
NO.
8
PARAMETER
DESCRIPTION
th(ACLK-AXR)
Hold time, AXR input valid after ACLKR/X
MODE
MIN
ACLKR/X int
-1
MAX
UNIT
ns
ACLKR/X ext in
ACLKR/X ext out
3
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Table 7-49. Timing Requirements for McASP3/4/5/6/7/8
NO.
PARAMETER
DESCRIPTION
1
tc(AHCLKRX)
Cycle time, AHCLKR/X
2
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
3
tc(ACLKRX)
Cycle time, ACLKR/X
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
6
th(ACLK-AFSRX)
tsu(AXR-ACLK)
8
th(ACLK-AXR)
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKX
Hold time, AXR input valid after ACLKX
(1)
MODE
MIN
MAX
UNIT
20
ns
0.35P
ns
(2)
20
ns
0.5R - 3
ns
ACLKR/X int
20.2
ns
ACLKR/X ext in
ACLKR/X ext out
4.9
ns
(3)
ACLKR/X int
-1
ns
ACLKR/X ext in
ACLKR/X ext out
2.26
ns
ACLKX int
(ASYNC=0)
20.8
ns
ACLKR/X ext in
ACLKR/X ext out
5.75
ns
ACLKX int
(ASYNC=0)
-0.9
ns
ACLKR/X ext in
ACLKR/X ext out
2.87
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
280
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
ACLKR/X (CLKRP = CLKXP = 0)(A)
ACLKR/X (CLKRP = CLKXP = 1)(B)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0
A.
B.
For CLKRP = CLKXP =
receiver is configured for
For CLKRP = CLKXP =
receiver is configured for
A1
A30 A31 B0 B1
B30 B31 C0 C1
C2 C3
C31
0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
falling edge (to shift data in).
1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
rising edge (to shift data in).
Figure 7-41. McASP Input Timing
CAUTION
The IO Timings provided in this section are only valid for some McASP usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-50, Table 7-51, Table 7-52 and Figure 7-42 present Switching Characteristics Over
Recommended Operating Conditions for McASP1 to McASP8.
Table 7-50. Switching Characteristics Over Recommended Operating Conditions for McASP1
NO.
PARAMETER
DESCRIPTION
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
10
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
MODE
MIN
(1)
MAX
ns
0.5P 2.5 (2)
ns
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UNIT
20
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Table 7-50. Switching Characteristics Over Recommended Operating Conditions for McASP1
(1)
(continued)
NO.
PARAMETER
DESCRIPTION
11
tc(ACLKRX)
Cycle time, ACLKR/X
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
13
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
14
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output valid
MODE
MIN
MAX
UNIT
20
ns
0.5P 2.5 (3)
ns
ACLKR/X int
-0.21
6
ns
ACLKR/X ext in
ACLKR/X ext out
2
23.9
ns
ACLKR/X int
-1.8
6.9
ns
ACLKR/X ext in
ACLKR/X ext out
2
25.6
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Table 7-51. Switching Characteristics Over Recommended Operating Conditions for McASP2
NO.
PARAMETER
DESCRIPTION
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
10
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
11
tc(ACLKRX)
Cycle time, ACLKR/X
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
13
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
14
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output valid
MODE
MIN
MAX
(1)
UNIT
20
ns
0.5P 2.5 (2)
ns
20
ns
0.5P 2.5 (3)
ns
ACLKR/X int
0
6
ns
ACLKR/X ext in
ACLKR/X ext out
2
25.2
ns
ACLKR/X int
-1.29
6.11
ns
ACLKR/X ext in
ACLKR/X ext out
2
24.8
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Table 7-52. Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
NO.
PARAMETER
DESCRIPTION
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
10
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
11
tc(ACLKRX)
Cycle time, ACLKR/X
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
13
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
282
MODE
MIN
MAX
(1)
UNIT
20
ns
0.5P 2.5 (2)
ns
20
ns
0.5P 2.5 (3)
ns
ACLKR/X int
-0.74
6
ns
ACLKR/X ext in
ACLKR/X ext out
2
26.4
ns
Timing Requirements and Switching Characteristics
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Table 7-52. Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
(1)
(continued)
NO.
14
PARAMETER
DESCRIPTION
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output valid
MODE
MIN
MAX
UNIT
ACLKR/X int
-1.68
6.97
ns
ACLKR/X ext in
ACLKR/X ext out
1.07
25.9
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
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10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
ACLKR/X (CLKRP = CLKXP = 1)(A)
ACLKR/X (CLKRP = CLKXP = 0)(B)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
13
13
13
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
14
15
AXR[n] (Data Out/Transmit)
A0
A.
B.
For CLKRP = CLKXP =
receiver is configured for
For CLKRP = CLKXP =
receiver is configured for
A1
A30 A31 B0 B1
B30 B31 C0
C1 C2 C3
C31
1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
rising edge (to shift data in).
0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
falling edge (to shift data in).
Figure 7-42. McASP Output Timing
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
Table 7-53 through Table 7-60 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see
Figure 7-43 through Figure 7-50).
284
Timing Requirements and Switching Characteristics
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Table 7-53. Virtual Mode Case Details for McASP1
No.
CASE
CASE Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
COIFOI
CLKX / FSX: Output
CLKR / FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP1_VIRTUAL1_ASYNC_TX
AXR(Inputs)/CLKR/FSR
MCASP1_VIRTUAL3_ASYNC_RX
2
COIFIO
CLKX / FSR: Output
CLKR / FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP1_VIRTUAL1_ASYNC_TX
AXR(Inputs)/CLKR/FSR
MCASP1_VIRTUAL3_ASYNC_RX
CLKR / FSR: Output
CLKX / FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP1_VIRTUAL3_ASYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP1_VIRTUAL1_ASYNC_TX
CLKR / FSX: Output
CLKX / FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP1_VIRTUAL3_ASYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP1_VIRTUAL1_ASYNC_TX
3
4
CIOFIO
CIOFOI
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
CO-FOCI-FO-
CLKX / FSX: Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
FSX: Output CLKX:
Input
AXR(Outputs)/CLKX/FSX
MCASP1_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP1_VIRTUAL2_SYNC_RX
7
CI-FI-
CLKX / FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP1_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP1_VIRTUAL2_SYNC_RX
8
CO-FI-
CLKX: Output FSX:
Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-54. Virtual Mode Case Details for McASP2
No.
CASE
CASE
Description
Virtual Mode Settings
Notes
Signals
Virtual Mode Value
Virtual Mode Value when
ACLKR, AFSR, and AXR
are all inputs
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FS
X
MCASP2_VIRTUAL3_ASYNC_TX
N/A
AXR(Inputs)/CLKR/FSR
MCASP2_VIRTUAL2_ASYNC_RX
MCASP2_VIRTUAL1_AS
YNC_RX_80M
IP Mode : ASYNC
1
COIFOI
2
COIFIO
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FS
X
MCASP2_VIRTUAL3_ASYNC_TX
N/A
AXR(Inputs)/CLKR/FSR
MCASP2_VIRTUAL2_ASYNC_RX
N/A
3
CIOFIO
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FS
X
MCASP2_VIRTUAL2_ASYNC_RX
N/A
AXR(Inputs)/CLKR/FSR
MCASP2_VIRTUAL3_ASYNC_TX
N/A
4
CIOFOI
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FS
X
MCASP2_VIRTUAL2_ASYNC_RX
N/A
AXR(Inputs)/CLKR/FSR
MCASP2_VIRTUAL3_ASYNC_TX
N/A
See Figure 743
See Figure 744
See Figure 745
See Figure 746
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FS
X
Default (No Virtual Mode)
N/A
6
CI-FO-
FSX: Output
CLKX: Input
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
N/A
AXR(Outputs)/CLKX/FS
X
MCASP2_VIRTUAL4_SYNC_RX
N/A
AXR(Inputs)/CLKX/FSX
MCASP2_VIRTUAL4_SYNC_RX
N/A
See Figure 747
See Figure 748
Timing Requirements and Switching Characteristics
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Table 7-54. Virtual Mode Case Details for McASP2 (continued)
No.
7
CASE
CI-FI-
8
CO-FI-
CASE
Description
CLKX / FSX:
Input
CLKX:
Output FSX:
Input
Virtual Mode Settings
Notes
Signals
Virtual Mode Value
Virtual Mode Value when
ACLKR, AFSR, and AXR
are all inputs
AXR(Outputs)/CLKX/FS
X
MCASP2_VIRTUAL4_SYNC_RX
N/A
AXR(Inputs)/CLKX/FSX
MCASP2_VIRTUAL4_SYNC_RX
MCASP2_VIRTUAL5_SY
NC_RX_80M
AXR(Outputs)/CLKX/FS
X
Default (No Virtual Mode)
N/A
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
N/A
See Figure 749
See Figure 750
Table 7-55. Virtual Mode Case Details for McASP3
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX /
FSX: Output
CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
CLKX /
FSR: Output
CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
CLKR /
FSR: Output
CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
CLKR /
FSX: Output
CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
CO-FOCI-FO-
CLKX /
FSX: Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
7
CI-FI-
CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
8
CO-FI-
CLKX:
Output FSX:
Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-56. Virtual Mode Case Details for McASP4
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
286
COIFOI
COIFIO
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
See Figure 7-43
See Figure 7-44
Timing Requirements and Switching Characteristics
Copyright © 2015–2016, Texas Instruments Incorporated
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-56. Virtual Mode Case Details for McASP4 (continued)
No.
3
4
CASE
CIOFIO
CIOFOI
CASE
Description
Virtual Mode Settings
Notes
Signals
Virtual Mode Value
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
6
CI-FO-
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
7
CI-FI-
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
CLKX: Output
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
8
CO-FI-
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-57. Virtual Mode Case Details for McASP5
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
CO-FOCI-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
7
CI-FI-
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
8
CO-FI-
CLKX: Output
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-58. Virtual Mode Case Details for McASP6
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
Timing Requirements and Switching Characteristics
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Table 7-58. Virtual Mode Case Details for McASP6 (continued)
No.
1
2
3
4
CASE
COIFOI
COIFIO
CIOFIO
CIOFOI
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
6
CI-FO-
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
7
CI-FI-
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
8
CO-FI-
CLKX:
Output FSX:
Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-59. Virtual Mode Case Details for McASP7
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
6
CI-FO-
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
7
CI-FI-
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
CLKX:
Output FSX:
Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
8
288
CO-FI-
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Timing Requirements and Switching Characteristics
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-60. Virtual Mode Case Details for McASP8
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FOCI-FOCI-FICO-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
CLKX:
Output FSX:
Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
MCASP
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
Figure 7-43. McASP1-8 COIFOI – ASYNC Mode
Timing Requirements and Switching Characteristics
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MCASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
Figure 7-44. McASP1-8 COIFIO – ASYNC Mode
MCASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
Figure 7-45. McASP1-8 CIOFIO – ASYNC Mode
290
Timing Requirements and Switching Characteristics
Copyright © 2015–2016, Texas Instruments Incorporated
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
MCASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
Figure 7-46. McASP1-8 CIOFOI – ASYNC Mode
MCASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
Figure 7-47. McASP1-8 COIFOI – SYNC Mode
Timing Requirements and Switching Characteristics
Submit Documentation Feedback
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291
DRA744, DRA745, DRA746
DRA750, DRA751, DRA752
DRA754, DRA755, DRA756
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MCASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
Figure 7-48. McASP1-8 CIOFOI – SYNC Mode
MCASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
Figure 7-49. McASP1-8 CIOFIO – SYNC Mode
292
Timing Requirements and Switching Characteristics
Copyright © 2015–2016, Texas Instruments Incorporated
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
MCASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
Figure 7-50. McASP1-8 COIFIO – SYNC Mode
Virtual IO Timings Modes must be used to guarantee some IO timings for McASP1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-61 Virtual
Functions Mapping for McASP1 for a definition of the Virtual modes.
Table 7-61 presents the values for DELAYMODE bitfield.
Timing Requirements and Switching Characteristics
Submit Documentation Feedback
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Table 7-61. Virtual Functions Mapping for McASP1
BALL
BALL NAME
Delay Mode Value
MUXMODE[15:0]
MCASP1_VIRTUAL1_A
SYNC_TX
MCASP1_VIRTUAL2_S
YNC_RX
MCASP1_VIRTUAL3_A
SYNC_RX
0
1
2
3
mcasp1_ahclkx
E21
gpio6_14
11
15
14
F20
gpio6_15
11
15
14
mcasp1_axr8
mcasp1_axr9
F21
gpio6_16
11
15
14
mcasp1_axr10
D18
xref_clk0
0
15
14
mcasp1_axr4
E17
xref_clk1
0
15
14
mcasp1_axr5
B26
xref_clk2
5
15
14
mcasp1_axr6
C23
xref_clk3
5
15
14
mcasp1_axr7
C14
mcasp1_aclkx
8
15
14
D14
mcasp1_fsx
12
15
14
mcasp1_fsx
B14
mcasp1_aclkr
11
N/A
15
mcasp1_aclkr
mcasp1_aclkx
J14
mcasp1_fsr
11
N/A
15
mcasp1_fsr
G12
mcasp1_axr0
8
15
14
mcasp1_axr0
F12
mcasp1_axr1
8
15
14
mcasp1_axr1
G13
mcasp1_axr2
10
15
14
mcasp1_axr2
J11
mcasp1_axr3
10
15
14
mcasp1_axr3
E12
mcasp1_axr4
10
15
14
mcasp1_axr4
F13
mcasp1_axr5
10
15
14
mcasp1_axr5
C12
mcasp1_axr6
10
15
14
mcasp1_axr6
D12
mcasp1_axr7
10
15
14
mcasp1_axr7
B12
mcasp1_axr8
6
15
14
mcasp1_axr8
A11
mcasp1_axr9
6
15
14
mcasp1_axr9
B13
mcasp1_axr10
6
15
14
mcasp1_axr10
A12
mcasp1_axr11
6
15
14
mcasp1_axr11
E14
mcasp1_axr12
6
15
14
mcasp1_axr12
A13
mcasp1_axr13
6
15
14
mcasp1_axr13
G14
mcasp1_axr14
6
15
14
mcasp1_axr14
F14
mcasp1_axr15
6
15
14
mcasp1_axr15
1. NA in this table stands for Not Applicable.
Virtual IO Timings Modes must be used to guarantee some IO timings for McASP2. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Virtual IO Timings Modes. See Table 7-62 Virtual Functions Mapping for McASP2 for a definition of the Virtual modes.
Table 7-62 presents the values for DELAYMODE bitfield.
294
Timing Requirements and Switching Characteristics
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Table 7-62. Virtual Functions Mapping for McASP2
BALL
BALL NAME
Delay Mode Value
MUXMODE[15:0]
MCASP2_
VIRTUAL1
_
ASYNC_R
X_80M
MCASP2_
VIRTUAL2
_
ASYNC_R
X
MCASP2_
VIRTUAL3
_
ASYNC_TX
MCASP2_
VIRTUAL4
_
SYNC_RX
MCASP2_
VIRTUAL5
_
SYNC_RX_
80M
9
4
8
6
0
1
D18
xref_clk0
10
E17
xref_clk1
10
9
4
8
6
mcasp2_axr9
B26
xref_clk2
13
12
0
11
10
mcasp2_axr10
C23
xref_clk3
13
12
0
11
10
mcasp2_axr11
A19
mcasp2_aclkx
15
14
5
10
9
A18
mcasp2_fsx
15
14
5
10
9
mcasp2_fsx
E15
mcasp2_aclkr
15
14
10
N/A
N/A
mcasp2_aclkr
A20
mcasp2_fsr
15
14
10
N/A
N/A
mcasp2_fsr
B15
mcasp2_axr0
15
14
9
13
12
mcasp2_axr0
2
3
mcasp2_axr8
mcasp2_ahclkx
mcasp2_aclkx
A15
mcasp2_axr1
15
14
9
13
12
mcasp2_axr1
C15
mcasp2_axr2
15
14
4
10
9
mcasp2_axr2
A16
mcasp2_axr3
15
14
4
10
9
mcasp2_axr3
D15
mcasp2_axr4
15
14
7
13
12
mcasp2_axr4
B16
mcasp2_axr5
15
14
7
13
12
mcasp2_axr5
B17
mcasp2_axr6
15
14
7
13
12
mcasp2_axr6
A17
mcasp2_axr7
15
14
7
13
12
mcasp2_axr7
B18
mcasp3_aclkx
15
14
5
10
9
mcasp2_axr12
F15
mcasp3_fsx
15
14
4
10
9
mcasp2_axr13
B19
mcasp3_axr0
15
14
4
10
9
mcasp2_axr14
C17
mcasp3_axr1
15
14
3
10
8
mcasp2_axr15
1. NA in this table stands for Not Applicable.
Virtual IO Timings Modes must be used to guarantee some IO timings for McASP3/4/5/6/7/8. See Table 7-2 Modes Summary for a list of IO
timings requiring the use of Virtual IO Timings Modes. See Table 7-63 Virtual Functions Mapping for McASP3/4/5/6/7/8 for a definition of the
Virtual modes.
Table 7-63 presents the values for DELAYMODE bitfield.
Timing Requirements and Switching Characteristics
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Table 7-63. Virtual Functions Mapping for McASP3/4/5/6/7/8
BALL
BALL NAME
Delay Mode Value
MUXMODE[15:0]
0
1
2
MCASP3_VIRTUAL2_SYNC_RX
C15
mcasp2_axr2
8
A16
mcasp2_axr3
8
B18
mcasp3_aclkx
8
mcasp3_axr2
mcasp3_axr3
mcasp3_aclkx
mcasp3_aclkr
mcasp3_fsr
F15
mcasp3_fsx
8
mcasp3_fsx
B19
mcasp3_axr0
8
mcasp3_axr0
C17
mcasp3_axr1
6
mcasp3_axr1
E12
mcasp1_axr4
13
F13
mcasp1_axr5
13
C18
mcasp4_aclkx
15
MCASP4_VIRTUAL1_SYNC_RX
mcasp4_axr2
mcasp4_axr3
mcasp4_aclkx
mcasp4_aclkr
mcasp4_fsr
A21
mcasp4_fsx
15
mcasp4_fsx
G16
mcasp4_axr0
15
mcasp4_axr0
D17
mcasp4_axr1
15
mcasp4_axr1
C12
mcasp1_axr6
13
mcasp5_axr2
D12
mcasp1_axr7
13
mcasp5_axr3
AA3
mcasp5_aclkx
15
mcasp5_aclkx
mcasp5_aclkr
AB9
mcasp5_fsx
15
mcasp5_fsx
mcasp5_fsr
AB3
mcasp5_axr0
15
mcasp5_axr0
AA4
mcasp5_axr1
15
mcasp5_axr1
G13
mcasp1_axr2
13
mcasp6_axr2
J11
mcasp1_axr3
13
mcasp6_axr3
B12
mcasp1_axr8
10
mcasp6_axr0
A11
mcasp1_axr9
10
mcasp6_axr1
B13
mcasp1_axr10
10
mcasp6_aclkx
mcasp6_aclkr
A12
mcasp1_axr11
10
mcasp6_fsx
mcasp6_fsr
MCASP5_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
296
B14
mcasp1_aclkr
14
mcasp7_axr2
J14
mcasp1_fsr
14
mcasp7_axr3
E14
mcasp1_axr12
10
mcasp7_axr0
Timing Requirements and Switching Characteristics
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Table 7-63. Virtual Functions Mapping for McASP3/4/5/6/7/8 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE[15:0]
A13
mcasp1_axr13
10
mcasp7_axr1
G14
mcasp1_axr14
10
mcasp7_aclkx
mcasp7_aclkr
F14
mcasp1_axr15
10
mcasp7_fsx
mcasp7_fsr
0
1
2
MCASP8_VIRTUAL1_SYNC_RX
E15
mcasp2_aclkr
13
mcasp8_axr2
A20
mcasp2_fsr
13
mcasp8_axr3
D15
mcasp2_axr4
11
mcasp8_axr0
B16
mcasp2_axr5
11
mcasp8_axr1
B17
mcasp2_axr6
11
mcasp8_aclkx
mcasp8_aclkr
A17
mcasp2_axr7
11
mcasp8_fsx
mcasp8_fsr
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7.18 Universal Serial Bus (USB)
SuperSpeed USB DRD Subsystem has four instances in the device providing the following functions:
• USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
PHY and HS/FS (USB2.0) PHY.
• USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY.
• USB3: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS
PHYs.
• USB4: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS
PHYs.
NOTE
For more information, see the SuperSpeed USB DRD section of the Device TRM.
7.18.1 USB1 DRD PHY
The USB1 DRD interface supports the following applications:
• USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
• USB3.0 Super-Speed PHY port (1.8 V): this asynchronous differential super-speed interface is
compliant with the USB3.0 RX/TX PHY standard (USB3.0 standard v1.0) for a maximum data bit rate
of 5Gbps.
7.18.2 USB2 PHY
The USB2 interface supports the following applications:
• USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
7.18.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
TheUSB3 and USB4 DRD interfaces support the following application:
• USB ULPI port: this synchronous interface is compliant with the USB2.0 ULPI SDR standard (UTMI+
v1.22), for alternative off-chip USB2.0 PHY interface; that is, with external transceiver with a maximum
frequency of 60 MHz (synchronous slave mode, SDR, 12-pin, 8-data-bit).
NOTE
The Universal Serial Bus k ULPI modules are also refered as USBk where k = 3, 4.
Table 7-64, Table 7-65 and Figure 7-51 assume testing over the recommended operating conditions and
electrical characteristic conditions.
Table 7-64. Timing Requirements for ULPI SDR Slave Mode
NO.
298
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
US1
tc(clk)
Cycle time, usb_ulpi_clk period
16.66
ns
US5
tsu(ctrlV-clkH)
Setup time, usb_ulpi_dir/usb_ulpi_nxt valid before
usb_ulpi_clk rising edge
6.73
ns
US6
th(clkH-ctrlV)
Hold time, usb_ulpi_dir/usb_ulpi_nxt valid after usb_ulpi_clk
rising edge
-0.41
ns
Timing Requirements and Switching Characteristics
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Table 7-64. Timing Requirements for ULPI SDR Slave Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
US7
tsu(dV-clkH)
Setup time, usb_ulpi_d[7:0] valid before usb_ulpi_clk rising
edge
6.73
ns
US8
th(clkH-dV)
Hold time, usb_ulpi_d[7:0] valid after usb_ulpi_clk rising edge
-0.41
ns
Table 7-65. Switching Characteristics for ULPI SDR Slave Mode
MIN
MAX
UNIT
US4
NO.
td(clkH-stpV)
PARAMETER
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_stp valid
DESCRIPTION
0.44
8.35
ns
US9
td(clkL-doV)
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_d[7:0] valid
0.44
8.35
ns
US1
US2
US3
usbk_ulpi_clk
US4
US4
usbk_ulpi_stp
US6
US5
usbk_ulpi_dir_&_nxt
US7
US9
US8
usbk_ulpi_d[7:0]
Data_IN
US9
Data_OUT
Figure 7-51. HS USB3 and USB4 ULPI —SDR—Slave Mode—12-pin Mode
In Table 7-66 are presented the specific groupings of signals (IOSET) for use with USB3 and USB4
signals.
Table 7-66. USB3 and USB4 IOSETs
SIGNALS
IOSET1
BALL
IOSET2
MUX
BALL
MUX
USB3
usb3_ulpi_d0
AE1
2
AC3
3
usb3_ulpi_d1
AE5
2
AC9
3
usb3_ulpi_d2
AE3
2
AC6
3
usb3_ulpi_d3
AF1
2
AC7
3
usb3_ulpi_d4
AF4
2
AC4
3
usb3_ulpi_d5
AF3
2
AD4
3
usb3_ulpi_d6
AF6
2
AB4
3
usb3_ulpi_d7
AF2
2
AC5
3
usb3_ulpi_nxt
AE2
2
AC8
3
usb3_ulpi_dir
AE6
2
AD6
3
usb3_ulpi_stp
AD2
2
AB8
3
usb3_ulpi_clk
AD3
2
AB5
3
usb4_ulpi_d0
V6
6
usb4_ulpi_d1
U6
6
usb4_ulpi_d2
U5
6
usb4_ulpi_d3
V5
6
USB4
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Table 7-66. USB3 and USB4 IOSETs (continued)
SIGNALS
IOSET1
BALL
IOSET2
MUX
BALL
MUX
usb4_ulpi_d4
V4
6
usb4_ulpi_d5
V3
6
usb4_ulpi_d6
Y2
6
usb4_ulpi_d7
W2
6
usb4_ulpi_stp
V9
6
usb4_ulpi_clk
W9
6
usb4_ulpi_dir
V7
6
usb4_ulpi_nxt
U7
6
7.19 Serial Advanced Technology Attachment (SATA)
The SATA RX/TX PHY interface is compliant with the SATA standard v2.6 for a maximum data rate:
• Gen2i, Gen2m, Gen2x: 3Gbps.
• Gen1i, Gen1m, Gen1x: 1.5Gbps.
NOTE
For more information, see the SATA Controller section of the Device TRM.
7.20 Peripheral Component Interconnect Express (PCIe)
The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus
interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe
subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane)
(Single Lane and Flexible dual lane configuration).
The device PCIe supports the following features:
• 16-bit operation @250 MHz on PIPE interface (per 16-bit lane)
• Supports 2 ports x 1 lane or 1 port x 2 lanes configuration
• Single virtual channel (VC0), single traffic class (TC0)
• Single function in end-point mode
• Automatic width and speed negotiation
• Max payload: 128 byte outbound, 256 byte inbound
• Automatic credit management
• ECRC generation and checking
• Configurable BAR filtering
• Legacy interrupt reception (RC) and generation (EP)
• MSI generation and reception
• PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
• All PCI Device Power Management D-states with the exception of D3cold / L2 state
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and
the PCI Local Bus Specification, revision 3.0.
NOTE
For more information, see the PCIe Controller section of the Device TRM.
7.21 Controller Area Network Interface (DCAN)
300
Timing Requirements and Switching Characteristics
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The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 MBit/s
• 64 message objects
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Direct access to Message RAM during test mode
• CAN Rx/Tx pins are configurable as general-purpose IO pins
• Two interrupt lines (plus additional parity-error interrupts line)
• RAM initialization
• DMA support
NOTE
For more information, see the DCAN section of the Device TRM.
NOTE
The Controller Area Network Interface x (x = 1 to 2) is also referred to as DCANx.
Table 7-67, Table 7-68 and Figure 7-52 present timing and switching characteristics for DCANx Interface.
Table 7-67. Timing Requirements for DCANx Receive(1)
NO.
1
PARAMETER
DESCRIPTION
f(baud)
Maximum programmable baud rate
tw(DCANRX)
Pulse duration, receive data bit (DCANx_RX)
MIN
NOM
H - 15
MAX
UNIT
1
Mbps
H + 15
ns
(1) H = period of baud rate, 1/programmed baud rate.
Table 7-68. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
NO.
2
PARAMETER
DESCRIPTION
f(baud)
Maximum programmable baud rate
tw(DCANTX)
Pulse duration, transmit data bit (DCANx_TX)
MIN
H - 15
(1)
MAX
UNIT
1
Mbps
H + 15
ns
(1) H = period of baud rate, 1/programmed baud rate.
1
DCANx_RX
2
DCANx_TX
Figure 7-52. DCANx Timings
7.22 Ethernet Interface (GMAC_SW)
Timing Requirements and Switching Characteristics
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The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the Gigabit Media Independent Interface (G/MII)
in MII mode, Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent
Interface (RMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY)
management.
NOTE
For more information, see the Ethernet Subsystem section of the Device TRM.
NOTE
The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as
MIIn, RMIIn and RGMIIn
CAUTION
The IO timings provided in this section are only valid if signals within a single
IOSET are used. The IOSETs are defined in the Table 7-73, Table 7-76,
Table 7-81 and Table 7-88.
CAUTION
The IO Timings provided in this section are only valid for some GMAC usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-69 and Figure 7-53 present timing requirements for MIIn in receive operation.
7.22.1 GMAC MII Timings
Table 7-69. Timing Requirements for miin_rxclk - MII Operation
NO.
PARAMETER
DESCRIPTION
1
tc(RX_CLK)
Cycle time, miin_rxclk
2
3
4
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Pulse duration, miin_rxclk high
Pulse duration, miin_rxclk low
Transition time, miin_rxclk
SPEED
MIN
MAX
10 Mbps
400
100 Mbps
40
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
3
ns
100 Mbps
3
ns
ns
4
1
2
UNIT
3
miin_rxclk
4
Figure 7-53. Clock Timing (GMAC Receive) - MIIn operation
302
Timing Requirements and Switching Characteristics
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Table 7-70 and Figure 7-54 present timing requirements for MIIn in transmit operation.
Table 7-70. Timing Requirements for miin_txclk - MII Operation
NO.
PARAMETER
DESCRIPTION
SPEED
MIN
1
tc(TX_CLK)
Cycle time, miin_txclk
10 Mbps
400
2
tw(TX_CLKH)
Pulse duration, miin_txclk high
3
tw(TX_CLKL)
Pulse duration, miin_txclk low
4
tt(TX_CLK)
Transition time, miin_txclk
MAX
UNIT
ns
100 Mbps
40
10 Mbps
140
260
ns
ns
100 Mbps
14
26
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
3
ns
100 Mbps
3
ns
4
1
3
2
miin_txclk
4
Figure 7-54. Clock Timing (GMAC Transmit) - MIIn operation
Table 7-71 and Figure 7-55 present timing requirements for GMAC MIIn Receive 10/100Mbit/s.
Table 7-71. Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tsu(RXD-RX_CLK)
1
tsu(RX_DV-RX_CLK)
Setup time, receive selected signals valid before miin_rxclk
8
ns
Hold time, receive selected signals valid after miin_rxclk
8
ns
tsu(RX_ER-RX_CLK)
th(RX_CLK-RXD)
2
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
1
2
miin_rxclk (Input)
miin_rxd3−miin_rxd0,
miin_rxdv, miin_rxer (Inputs)
Figure 7-55. GMAC Receive Interface Timing MIIn operation
Table 7-72 and Figure 7-56 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.
Table 7-72. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit
10/100 Mbits/s
NO.
1
PARAMETER
td(TX_CLK-TXD)
td(TX_CLK-TX_EN)
DESCRIPTION
Delay time, miin_txclk to transmit selected signals valid
MIN
MAX
UNIT
0
25
ns
Timing Requirements and Switching Characteristics
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1
miin_txclk (input)
miin_txd3 − miin_txd0,
miin_txen (outputs)
Figure 7-56. GMAC Transmit Interface Timing MIIn operation
In Table 7-73 are presented the specific groupings of signals (IOSET) for use with GMAC MII signals.
Table 7-73. GMAC MII IOSETs
SIGNALS
304
IOSET5
IOSET6
BALL
MUX
mii1_txd3
C5
8
BALL
MUX
mii1_txd2
D6
8
mii1_txd1
B2
8
mii0_txd3
V5
3
mii0_txd2
V4
3
mii0_txd1
Y2
3
mii1_txd0
C4
8
mii1_rxd3
F5
8
mii1_rxd2
E4
8
mii1_rxd1
C1
8
mii1_rxd0
E6
8
mii1_col
B4
8
mii1_rxer
B3
8
mii1_txer
A3
8
mii1_txen
A4
8
mii1_crs
B5
8
mii1_rxclk
D5
8
mii1_txclk
C3
8
mii1_rxdv
C2
8
mii0_txd0
W2
3
mii0_rxd3
W9
3
mii0_rxd2
V9
3
mii0_rxd1
V6
3
mii0_rxd0
U6
3
mii0_txclk
U5
3
mii0_txer
U4
3
mii0_rxer
U7
3
mii0_rxdv
V2
3
mii0_crs
V7
3
mii0_col
V1
3
mii0_rxclk
Y1
3
mii0_txen
V3
3
Timing Requirements and Switching Characteristics
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7.22.2 GMAC MDIO Interface Timings
CAUTION
The IO Timings provided in this section are only valid for some GMAC usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-74, Table 7-74 and Figure 7-57 present timing requirements for MDIO.
Table 7-74. Timing Requirements for MDIO Input
No
PARAMETER
MDIO1
tc(MDC)
MDIO2
MDIO3
MDIO4
MDIO5
DESCRIPTION
MIN
MAX
UNIT
Cycle time, MDC
400
ns
tw(MDCH)
Pulse Duration, MDC High
160
ns
tw(MDCL)
Pulse Duration, MDC Low
160
ns
tsu(MDIO-MDC)
Setup time, MDIO valid before MDC High
90
ns
th(MDIO_MDC)
Hold time, MDIO valid from MDC High
0
ns
Table 7-75. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO
PARAMETER
DESCRIPTION
MDIO6
tt(MDC)
Transition time, MDC
MDIO7
td(MDC-MDIO)
Delay time, MDC High to MDIO valid
MIN
MAX
UNIT
5
ns
10
390
ns
1
MDIO2
MDIO3
MDCLK
MDIO6
MDIO6
MDIO4
MDIO5
MDIO
(input)
MDIO7
MDIO
(output)
Figure 7-57. GMAC MDIO diagrams
In Table 7-76 are presented the specific groupings of signals (IOSET) for use with GMAC MDIO signals.
Table 7-76. GMAC MDIO IOSETs
SIGNALS
IOSET7
IOSET8
IOSET9
IOSET10
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
mdio_d
F6
3
U4
0
AB4
1
B20
5
mdio_mclk
D3
3
V1
0
AC5
1
B21
5
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7.22.3 GMAC RMII Timings
The main reference clock REF_CLK (RMII_50MHZ_CLK) of RMII interface is internally supplied from
PRCM. The source of this clock could be either externally sourced from the RMII_MHZ_50_CLK pin of the
device or internally generated from DPLL_GMAC output clock GMAC_RMII_HS_CLK. Please see the
PRCM chapter of the device TRM for full details about RMII reference clock.
CAUTION
The IO Timings provided in this section are only valid for some GMAC usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-77, Table 7-78 and Figure 7-58 present timing requirements for GMAC RMIIn Receive.
Table 7-77. Timing Requirements for GMAC REF_CLK - RMII Operation
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII1 tc(REF_CLK)
Cycle time, REF_CLK
20
ns
RMII2 tw(REF_CLKH)
Pulse duration, REF_CLK high
7
13
ns
RMII3 tw(REF_CLKL)
Pulse duration, REF_CLK low
7
13
ns
RMII4 ttt(REF_CLK)
Transistion time, REF_CLK
3
ns
Table 7-78. Timing Requirements for GMAC RMIIn Receive
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII5
tsu(RXD-REF_CLK)
Setup time, receive selected signals valid before REF_CLK
4
ns
Hold time, receive selected signals valid after REF_CLK
2
ns
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
RMII6
th(REF_CLK-RXD)
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
RMII1
RMII3
RMII4
RMII2
RMII5
RMII6
REF_CLK (PRCM)
rmiin_rxd1−rmiin_rxd0,
rmiin_crs, rmin_rxer (inputs)
SPRS8xx_GMAC_RMIIRX_05
Figure 7-58. GMAC Receive Interface Timing RMIIn operation
Table 7-79, Table 7-79 and Figure 7-59 present switching characteristics for GMAC RMIIn Transmit
10/100Mbit/s.
Table 7-79. Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK RMII Operation
NO.
PARAMETER
DESCRIPTION
MIN
RMII7
tc(REF_CLK)
Cycle time, REF_CLK
20
RMII8
tw(REF_CLKH)
Pulse duration, REF_CLK high
7
306
MAX
UNIT
ns
13
ns
Timing Requirements and Switching Characteristics
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Table 7-79. Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK RMII Operation (continued)
NO.
PARAMETER
DESCRIPTION
RMII9
tw(REF_CLKL)
Pulse duration, REF_CLK low
RMII10
tt(REF_CLK)
Transistion time, REF_CLK
MIN
MAX
UNIT
7
13
ns
3
ns
Table 7-80. Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn
Transmit 10/100 Mbits/s
NO.
PARAMETER
DESCRIPTION
td(REF_CLK-TXD)
RMII11
tdd(REF_CLK-TXEN)
td(REF_CLK-TXD)
RMIIn
MIN
MAX
UNIT
RMII0
2
13.5
ns
RMII1
2
13.8
ns
Delay time, REF_CLK high to selected transmit signals
valid
tdd(REF_CLK-TXEN)
RMII7
RMII8
RMII9
RMII11
RMII10
REF_CLK (PRCM)
rmiin_txd1−rmiin_txd0,
rmiin_txen (Outputs)
SPRS8xx_GMAC_RMIITX_06
Figure 7-59. GMAC Transmit Interface Timing RMIIn Operation
In Table 7-81 are presented the specific groupings of signals (IOSET) for use with GMAC RMII signals.
Table 7-81. GMAC RMII IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
RMII_MHZ_50_CLK
U3
0
U3
0
rmii1_txd1
V5
2
rmii0_txd1
Y2
1
rmii0_txd0
W2
1
rmii0_rxd1
V6
1
rmii0_rxd0
U6
1
rmii0_txen
V3
1
rmii0_rxer
U7
1
rmii0_crs
V7
1
rmii1_txd0
V4
2
rmii1_rxd1
W9
2
rmii1_rxd0
V9
2
rmii1_rxer
Y1
2
rmii1_txen
U5
2
rmii1_crs
V2
2
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Manual IO Timings Modes must be used to guarantee some IO timings for GMAC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-82 Manual
Functions Mapping for GMAC RMII0 for a definition of the Manual modes.
Table 7-82 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-82. Manual Functions Mapping for GMAC RMII0
BALL
BALL NAME
GMAC_RMII0_MANUAL1
A_DELAY
(ps)
CFG REGISTER
MUXMODE
G_DELAY
(ps)
0
1
U3
RMII_MHZ_50_CLK
0
0
CFG_RMII_MHZ_50_CLK_IN
U6
rgmii0_txd0
500
500
CFG_RGMII0_TXD0_IN
RMII_MHZ_50_CLK
rmii0_rxd0
V6
rgmii0_txd1
840
1000
CFG_RGMII0_TXD1_IN
rmii0_rxd1
U7
rgmii0_txd2
360
840
CFG_RGMII0_TXD2_IN
rmii0_rxer
V7
rgmii0_txd3
600
1000
CFG_RGMII0_TXD3_IN
rmii0_crs
Manual IO Timings Modes must be used to guarantee some IO timings for GMAC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-83 Manual
Functions Mapping for GMAC RMII1 for a definition of the Manual modes.
Table 7-83 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
Table 7-83. Manual Functions Mapping for GMAC RMII1
BALL
BALL NAME
GMAC_RMII1_MANUAL1
A_DELAY
(ps)
CFG REGISTER
MUXMODE
G_DELAY
(ps)
0
2
U3
RMII_MHZ_50_CLK
0
0
CFG_RMII_MHZ_50_CLK_IN
V9
rgmii0_txctl
300
1200
CFG_RGMII0_TXCTL_IN
RMII_MHZ_50_CLK
rmii1_rxd0
W9
rgmii0_txc
300
1000
CFG_RGMII0_TXC_IN
rmii1_rxd1
Y1
uart3_txd
400
700
CFG_UART3_TXD_IN
rmii1_rxer
V2
uart3_rxd
300
500
CFG_UART3_RXD_IN
rmii1_crs
7.22.4 GMAC RGMII Timings
CAUTION
The IO Timings provided in this section are only valid for some GMAC usage
modes when the corresponding Virtual IO Timings or Manual IO Timings are
configured as described in the tables found in this section.
Table 7-84, Table 7-85 and Figure 7-60 present timing requirements for receive RGMIIn operation.
Table 7-84. Timing Requirements for rgmiin_rxc - RGMIIn Operation
NO.
1
2
308
PARAMETER
DESCRIPTION
SPEED
MIN
MAX
UNIT
tc(RXC)
Cycle time, rgmiin_rxc
10 Mbps
360
440
ns
100 Mbps
36
44
ns
tw(RXCH)
Pulse duration, rgmiin_rxc high
1000 Mbps
7.2
8.8
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
Timing Requirements and Switching Characteristics
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Table 7-84. Timing Requirements for rgmiin_rxc - RGMIIn Operation (continued)
NO.
3
4
PARAMETER
DESCRIPTION
SPEED
MIN
MAX
UNIT
tw(RXCL)
Pulse duration, rgmiin_rxc low
10 Mbps
160
240
ns
tt(RXC)
Transition time, rgmiin_rxc
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
0.75
ns
100 Mbps
0.75
ns
1000 Mbps
0.75
ns
Table 7-85. Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
5
tsu(RXD-RXCH)
Setup time, receive selected signals valid before rgmiin_rxc high/low
1
ns
6
th(RXCH-RXD)
Hold time, receive selected signals valid after rgmiin_rxc high/low
1
ns
(1) For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl.
1
4
2
rgmiin_rxc
4
3
(A)
5
1st Half-byte
6
2nd Half-byte
rgmiin_rxd[3:0]
rgmiin_rxctl
A.
B.
(B)
RGRXD[3:0]
RGRXD[7:4]
RXDV
RXERR
(B)
rgmiin_rxc must be externally delayed relative to the data and control pins.
Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on
rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.
Figure 7-60. GMAC Receive Interface Timing, RGMIIn operation
Table 7-86, Table 7-87 and Figure 7-61 present switching characteristics for transmit - RGMIIn for
10/100/1000Mbit/s.
Table 7-86. Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn
Operation for 10/100/1000 Mbit/s
NO.
1
2
3
4
PARAMETER
DESCRIPTION
SPEED
MIN
MAX
UNIT
tc(TXC)
Cycle time, rgmiin_txc
10 Mbps
360
440
ns
100 Mbps
36
44
ns
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, rgmiin_txc high
Pulse duration, rgmiin_txc low
Transition time, rgmiin_txc
1000 Mbps
7.2
8.8
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
0.75
ns
100 Mbps
0.75
ns
1000 Mbps
0.75
ns
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Table 7-87. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
NO.
5
6
PARAMETER
DESCRIPTION
tosu(TXD-TXC)
Output Setup time, transmit selected signals valid to
rgmiin_txc high/low
toh(TXC-TXD)
Output Hold time, transmit selected signals valid after
rgmiin_txc high/low
(1)
MODE
MIN
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
MAX
UNIT
ns
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
ns
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
ns
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
ns
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
(2)
(3)
(2)
(3)
(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 1000Mbps operation requires that the rgmii0_txc and rgmii0_txd[3:0] board propogation delays be matched to < 50pS.
(3) RGMII1 1000Mbps operation requires that the rgmii1_txc and rgmii1_txd[3:0] board propogation delays be matched to < 50pS.
1
4
2
3
4
(A)
rgmiin_txc
[internal delay enabled]
5
(B)
1st Half-byte
rgmiin_txd[3:0]
2nd Half-byte
6
(B)
rgmiin_txctl
A.
B.
TXEN
TXERR
TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
Figure 7-61. GMAC Transmit Interface Timing RGMIIn operation
In Table 7-88 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.
Table 7-88. GMAC RGMII IOSETs
SIGNALS
310
IOSET3
IOSET4
BALL
MUX
rgmii1_txd3
C3
3
rgmii1_txd2
C4
3
rgmii1_txd1
B2
3
rgmii1_txd0
D6
3
rgmii1_rxd3
B3
3
rgmii1_rxd2
B4
3
rgmii1_rxd1
B5
3
rgmii1_rxd0
A4
3
rgmii1_rxctl
A3
3
rgmii1_txc
D5
3
BALL
MUX
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Table 7-88. GMAC RGMII IOSETs (continued)
SIGNALS
IOSET3
IOSET4
BALL
MUX
BALL
MUX
rgmii1_txctl
C2
3
rgmii1_rxc
C5
rgmii0_txd3
3
V7
0
rgmii0_txd2
U7
0
rgmii0_txd1
V6
0
rgmii0_txd0
U6
0
rgmii0_rxd3
V4
0
rgmii0_rxd2
V3
0
rgmii0_rxd1
Y2
0
rgmii0_rxd0
W2
0
rgmii0_txc
W9
0
rgmii0_rxctl
V5
0
rgmii0_rxc
U5
0
rgmii0_txctl
V9
0
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for GMAC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-89 Manual
Functions Mapping for GMAC RGMII0 for a definition of the Manual modes.
Table 7-90 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-89. Manual Functions Mapping for GMAC RGMII0
BALL
BALL NAME
GMAC_RGMII0_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
U5
rgmii0_rxc
471
0
CFG_RGMII0_RXC_IN
rgmii0_rxc
0
V5
rgmii0_rxctl
30
1919
CFG_RGMII0_RXCTL_IN
rgmii0_rxctl
W2
rgmii0_rxd0
74
1688
CFG_RGMII0_RXD0_IN
rgmii0_rxd0
Y2
rgmii0_rxd1
94
1697
CFG_RGMII0_RXD1_IN
rgmii0_rxd1
V3
rgmii0_rxd2
0
1703
CFG_RGMII0_RXD2_IN
rgmii0_rxd2
V4
rgmii0_rxd3
70
1804
CFG_RGMII0_RXD3_IN
rgmii0_rxd3
W9
rgmii0_txc
90
70
CFG_RGMII0_TXC_OUT
rgmii0_txc
V9
rgmii0_txctl
70
70
CFG_RGMII0_TXCTL_OUT
rgmii0_txctl
U6
rgmii0_txd0
180
70
CFG_RGMII0_TXD0_OUT
rgmii0_txd0
V6
rgmii0_txd1
35
70
CFG_RGMII0_TXD1_OUT
rgmii0_txd1
U7
rgmii0_txd2
0
0
CFG_RGMII0_TXD2_OUT
rgmii0_txd2
V7
rgmii0_txd3
180
70
CFG_RGMII0_TXD3_OUT
rgmii0_txd3
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Manual IO Timings Modes must be used to guarantee some IO timings for GMAC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-90 Manual
Functions Mapping for GMAC RGMII1 for a definition of the Manual modes.
Table 7-90 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-90. Manual Functions Mapping for GMAC RGMII1
BALL
BALL NAME
GMAC_RGMII1_MANUAL1
A_DELAY (ps)
CFG REGISTER
MUXMODE
G_DELAY (ps)
3
C5
vin2a_d18
612
0
CFG_VIN2A_D18_IN
rgmii1_rxc
A3
vin2a_d19
4
927
CFG_VIN2A_D19_IN
rgmii1_rxctl
B3
vin2a_d20
136
1340
CFG_VIN2A_D20_IN
rgmii1_rxd3
B4
vin2a_d21
130
1450
CFG_VIN2A_D21_IN
rgmii1_rxd2
B5
vin2a_d22
144
1269
CFG_VIN2A_D22_IN
rgmii1_rxd1
A4
vin2a_d23
0
1330
CFG_VIN2A_D23_IN
rgmii1_rxd0
D5
vin2a_d12
65
70
CFG_VIN2A_D12_OUT
rgmii1_txc
C2
vin2a_d13
125
70
CFG_VIN2A_D13_OUT
rgmii1_txctl
C3
vin2a_d14
0
70
CFG_VIN2A_D14_OUT
rgmii1_txd3
C4
vin2a_d15
0
70
CFG_VIN2A_D15_OUT
rgmii1_txd2
B2
vin2a_d16
65
70
CFG_VIN2A_D16_OUT
rgmii1_txd1
D6
vin2a_d17
0
0
CFG_VIN2A_D17_OUT
rgmii1_txd0
7.23 Media Local Bus (MLB) interface
The MLBSS allows connection to a MOST (Media Oriented Systems Transport) network controller for
transport of media and control data between multimedia nodes. The MLBSS supports the following
features:
• 3 pin mode compliant to MediaLB Physical Layer Specification v4.0
• 6 pin mode (3 differential pairs) compliant to MediaLB Physical Layer Specification v4.0
• Supports 256/512/1024Fs in 3 pin mode and 2048Fs in 6 pin mode
• Supports all types of transfer (Sync, Isoc, Async/Packet, Control) over 64 logical channels
• 16KB buffering for synchronous /isochronous/control/packet data in the subsystem
NOTE
For more information, see the Media Local Bus (MLB) section of the Device TRM.
NOTE
MLB in 6-pin mode may require pullups/ pulldowns on SIG and DAT bus signals. For
additional details, please consult the MLB bus interface specification.
Table 7-91 and Figure 7-62 present Timing Requirements for MLKCLK 3-Pin Option.
Table 7-91. Timing Requirements for MLBCLK 3-Pin Option
NO.
PARAMETER
DESCRIPTION
MODE
MIN
1
tc(MLBCLK)
Cycle time, MLB_CLK
512FS
39
ns
1024FS
19.5
ns
512FS
14
ns
1024FS
9.3
ns
2
312
tw(MLBCLK)
Pulse duration, MLB_CLK high
MAX
UNIT
Timing Requirements and Switching Characteristics
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Table 7-91. Timing Requirements for MLBCLK 3-Pin Option (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
3
tw(MLBCLK)
Pulse duration, MLB_CLK low
512FS
14
MAX
UNIT
ns
1024FS
6.1
ns
2
4
1
MLB_CLK
3
4
Figure 7-62. MLB_CLK Timing
Table 7-92 and Table 7-93 present Timing Requirements and Switching Characteristics for MLB 3-Pin
Option.
Table 7-92. Timing Requirements for Receive Data for the MLB 3-Pin Option
NO.
PARAMETER
DESCRIPTION
MODE
MIN
5
tsu(MLBDAT-MLBCLKL)
Setup time, MLB_DAT/MLB_SIG input valid before MLB_CLK
low
512FS
1
ns
1024FS
1
ns
512FS
4
ns
1024FS
2
ns
6
th(MLBCLKL-MLBDAT)
Hold time, MLB_DAT/MLB_SIG input valid after MLB_CLK
low
MAX
UNIT
Table 7-93. Switching Characteristics Over Recommended Operating Conditions for MLB 3-Pin Option
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
7
td(MLBCLKH-MLBDATV)
Delay time, MLBCLKH rising to MLB_DAT/MLB_SIG valid
512FS
0
10
ns
1024FS
0
7
ns
512FS
0
14
ns
1024FS
0
6.1
ns
MIN
MAX
UNIT
8
tdis(MLBCLKL-
Disable time, MLBCLKH falling to MLB_DAT/MLB_SIG Hi-Z
MLBDATZ)
Table 7-94 and Figure 7-62 present Timing Requirements for MLKCLK 6-Pin Option.
Table 7-94. Timing Requirements for MLBCLK 6-Pin Option
NO.
PARAMETER
DESCRIPTION
MODE
1
tc(MLBCLKx)
Cycle time, MLB_CLKP/N
2048FS
10
ns
2
tw(MLBCLKx)
Pulse duration, MLB_CLKP/N high
2048FS
4.5
ns
3
tw(MLBCLKx)
Pulse duration, MLB_CLKP/N low
2048FS
4.5
ns
Table 7-95 and Table 7-96 present Timing Requirements and Switching Characteristics for MLB 6-Pin
Option.
Table 7-95. Timing Requirements for Receive Data for the MLB 6-Pin Option
(1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
5
tsu(DATx-CLKxH)
Setup time, MLBP_DATx/MLBP_SIGx input valid before
MLBP_CLKx rising
2048FS
1
MAX
ns
6
th(CLKxH-DATx)
Hold time, MLBP_DATx/MLBP_SIGx input valid after
MLBP_CLKx rising
2048FS
0.5
ns
Timing Requirements and Switching Characteristics
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UNIT
313
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(1) MLBP_SIGx/MLBP_DATx is valid at the receiver input for at least TBD.
Table 7-96. Switching Characteristics Over Recommended Operating Conditions for MLB 6-Pin Option (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
7
td(CLKxH-DATxV)
Delay time, MLBPCLKxH rising to MLB_DATx/MLB_SIGx valid
2048FS
0.5
7
ns
8
tdis(CLKPH-DATPZ)
Disable time, MLBPCLKxH rising to MLBP_DATx/MLBP_SIGx
Hi-Z
2048FS
0.5
7
ns
(1) MLBP_SIGx/MLBP_DATx is valid at the receiver input for at least TBD.
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for MLB. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-97 Manual
Functions Mapping for MLB for a definition of the Manual modes.
Table 7-97 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-97. Manual Functions Mapping for MLB
BALL
BALL NAME
A_DELAY (ps)
G_DELAY (ps)
0
5
AA3
mcasp5_aclkx
175
0
CFG_MCASP5_ACLKX_IN
-
mlb_clk
AA3
mcasp5_aclkx
430
411
CFG_MCASP5_ACLKX_OUT
-
mlb_clk
AB3
mcasp5_axr0
0
0
CFG_MCASP5_AXR0_IN
-
mlb_sig
AB3
mcasp5_axr0
0
0
CFG_MCASP5_AXR0_OEN
-
mlb_sig
AB3
mcasp5_axr0
0
0
CFG_MCASP5_AXR0_OUT
-
mlb_sig
AA4
mcasp5_axr1
0
0
CFG_MCASP5_AXR1_IN
-
mlb_dat
AA4
mcasp5_axr1
0
0
CFG_MCASP5_AXR1_OEN
-
mlb_dat
AA4
mcasp5_axr1
0
0
CFG_MCASP5_AXR1_OUT
-
mlb_dat
AB1
mlbp_clk_p
0
0
CFG_MLBP_CLK_P_IN
mlbp_clk_p
-
AB1
mlbp_clk_p
321
43
CFG_MLBP_CLK_P_OUT
mlbp_clk_p
-
AA2
mlbp_dat_n
30
1170
CFG_MLBP_DAT_N_IN
mlbp_dat_n
-
AA2
mlbp_dat_n
0
0
CFG_MLBP_DAT_N_OEN
mlbp_dat_n
-
AA2
mlbp_dat_n
0
0
CFG_MLBP_DAT_N_OUT
mlbp_dat_n
-
AA1
mlbp_dat_p
30
1170
CFG_MLBP_DAT_P_IN
mlbp_dat_p
-
AA1
mlbp_dat_p
0
0
CFG_MLBP_DAT_P_OEN
mlbp_dat_p
-
AA1
mlbp_dat_p
0
0
CFG_MLBP_DAT_P_OUT
mlbp_dat_p
-
AC2
mlbp_sig_n
55
1223
CFG_MLBP_SIG_N_IN
mlbp_sig_n
-
AC2
mlbp_sig_n
0
0
CFG_MLBP_SIG_N_OEN
mlbp_sig_n
-
AC2
mlbp_sig_n
0
0
CFG_MLBP_SIG_N_OUT
mlbp_sig_n
-
AC1
mlbp_sig_p
55
1223
CFG_MLBP_SIG_P_IN
mlbp_sig_p
-
AC1
mlbp_sig_p
0
0
CFG_MLBP_SIG_P_OEN
mlbp_sig_p
-
AC1
mlbp_sig_p
0
0
CFG_MLBP_SIG_P_OUT
mlbp_sig_p
-
314
MLB_MANUAL 1
CFG REGISTER
MUXMODE
Timing Requirements and Switching Characteristics
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7.24 eMMC/SD/SDIO
The Device includes the following external memory interfaces 4 MultiMedia Card/Secure Digital/Secure
Digital Input Output Interface (MMC/SD/SDIO).
NOTE
The eMMC/SD/SDIOi (i = 1 to 4) controller is also referred to as MMCi.
7.24.1 MMC1—SD Card Interface
MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card
applications:
• Default speed, 4-bit data, SDR, half-cycle
• High speed, 4-bit data, SDR, half-cycle
• SDR12, 4-bit data, half-cycle
• SDR25, 4-bit data, half-cycle
• UHS-I SDR50, 4-bit data, half-cycle
• UHS-I SDR104, 4-bit data, half-cycle
• UHS-I DDR50, 4-bit data
NOTE
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
Table 7-98 and Table 7-99 present Timing requirements and Switching characteristics for MMC1 - Default
Speed in receiver and transmitter mode (see Figure 7-63 and Figure 7-64)
Table 7-98. Timing Requirements for MMC1 - SD Card Default Speed Mode
PARAMETER
DESCRIPTION
DSSD5
NO.
tsu(cmdV-clkH)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
DSSD6
th(clkH-cmdV)
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
DSSD7
tsu(dV-clkH)
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
DSSD8
th(clkH-dV)
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
MIN
MAX
UNIT
25.83
ns
20.9
ns
25.83
ns
20.9
ns
Table 7-99. Switching Characteristics for MMC1 - SD Card Default Speed Mode
PARAMETER
DESCRIPTION
DSSD0
NO.
fop(clk)
Operating frequency, mmc1_clk
MIN
MAX
UNIT
24
DSSD1
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
MHz
ns
DSSD2
tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
DSSD3
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-14.93
14.93
ns
DSSD4
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-14.93
14.93
ns
Timing Requirements and Switching Characteristics
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(1) P = output mmc1_clk period in ns
DSSD2
DSSD1
DSSD0
mmc1_clk
DSSD6
DSSD5
mmc1_cmd
DSSD8
DSSD7
mmc1_dat[3:0]
MMC1_01
Figure 7-63. MMC/SD/SDIO in - Default Speed - Receiver Mode
DSSD2
DSSD1
DSSD0
mmcx_clk
DSSD3
mmcx_cmd
DSSD4
mmcx_dat[3:0]
MMC1_02
Figure 7-64. MMC/SD/SDIO in - Default Speed - Transmitter Mode
7.24.1.2 High speed, 4-bit data, SDR, half-cycle
Table 7-100 and Table 7-101 present Timing requirements and Switching characteristics for MMC1 - High
Speed in receiver and transmitter mode (see Figure 7-65 and Figure 7-66)
Table 7-100. Timing Requirements for MMC1 - SD Card High Speed
PARAMETER
DESCRIPTION
MIN
HSSD3
NO.
tsu(cmdV-clkH)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
6.64
MAX
UNIT
ns
HSSD4
th(clkH-cmdV)
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
2.6
ns
HSSD7
tsu(dV-clkH)
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
6.64
ns
HSSD8
th(clkH-dV)
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
2.6
ns
Table 7-101. Switching Characteristics for MMC1 - SD Card High Speed
NO.
HSSD1
PARAMETER
DESCRIPTION
fop(clk)
Operating frequency, mmc1_clk
MIN
MAX
UNIT
48
MHz
HSSD2H tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
HSSD2L tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
HSSD5
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-7.6
3.6
ns
HSSD6
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-7.6
3.6
ns
316
Timing Requirements and Switching Characteristics
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(1) P = output mmc1_clk period in ns
HSSD1
HSSD2L
HSSD2H
mmc1_clk
HSSD3
HSSD4
mmc1_cmd
HSSD7
HSSD8
mmc1_dat[3:0]
MMC1_03
Figure 7-65. MMC/SD/SDIO in - High Speed - Receiver Mode
HSSD1
HSSD2H
HSSD2L
mmc1_clk
HSSD5
HSSD5
mmc1_cmd
HSSD6
HSSD6
mmc1_dat[3:0]
MMC1_04
Figure 7-66. MMC/SD/SDIO in - High Speed - Transmitter Mode
7.24.1.3 SDR12, 4-bit data, half-cycle
Table 7-102 and Table 7-103 present Timing requirements and Switching characteristics for MMC1 SDR12 in receiver and transmitter mode(see Figure 7-67 and Figure 7-68).
Table 7-102. Timing Requirements for MMC1 - SD Card SDR12 Mode
NO.
PARAMETER
DESCRIPTION
SDR12 tsu(cmdV-clkH)
5
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
SDR12 th(clkH-cmdV)
6
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
SDR12 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
SDR12 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
MODE
MIN
MAX
UNIT
27.33
ns
Pad Loopback Clock
1.6
ns
Internal Loopback Clock
1.6
ns
27.33
ns
Pad Loopback Clock
1.6
ns
Internal Loopback Clock
1.6
ns
Table 7-103. Switching Characteristics for MMC1 - SD Card SDR12 Mode
PARAMETER
DESCRIPTION
SDR120
NO.
fop(clk)
Operating frequency, mmc1_clk
MIN
MAX
UNIT
24
MHz
SDR121
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
SDR122
tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
SDR123
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-19.13
16.93
ns
SDR124
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-19.13
16.93
ns
Timing Requirements and Switching Characteristics
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(1) P = output mmc1_clk period in ns
SDR122
SDR121
SDR120
mmc1_clk
SDR126
SDR125
mmc1_cmd
SDR128
SDR127
mmc1_dat[3:0]
MMC1_05
Figure 7-67. MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode
SDR122
SDR121
SDR120
mmc1_clk
SDR123
mmc1_cmd
SDR124
mmc1_dat[3:0]
MMC1_06
Figure 7-68. MMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode
7.24.1.4 SDR25, 4-bit data, half-cycle
Table 7-104 and Table 7-105 present Timing requirements and Switching characteristics for MMC1 SDR25 in receiver and transmitter mode (see Figure 7-69 and Figure 7-70).
Table 7-104. Timing Requirements for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
SDR25 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
SDR25 th(clkH-cmdV)
4
MODE
MIN
MAX
UNIT
6.64
ns
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.6
ns
SDR25 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
6.64
ns
SDR25 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
ns
Internal Loopback Clock
1.6
ns
Table 7-105. Switching Characteristics for MMC1 - SD Card SDR25 Mode
PARAMETER
DESCRIPTION
SDR251
NO.
fop(clk)
Operating frequency, mmc1_clk
SDR252
H
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
SDR252L tw(clkL)
318
MIN
MAX
UNIT
48
MHz
Timing Requirements and Switching Characteristics
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Table 7-105. Switching Characteristics for MMC1 - SD Card SDR25 Mode (continued)
PARAMETER
DESCRIPTION
MIN
MAX
SDR255
NO.
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-8.8
6.6
UNIT
ns
SDR256
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
6.6
ns
(1) P = output mmc1_clk period in ns
SDR251
SDR252L
SDR252H
mmc1_clk
SDR253
SDR254
mmc1_cmd
SDR257
SDR258
mmc1_dat[3:0]
MMC1_07
Figure 7-69. MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
mmc1_clk
HSSDR255
SDR255
mmc1_cmd
SDR256
SDR256
mmc1_dat[3:0]
MMC1_08
Figure 7-70. MMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode
7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
Table 7-106 and Table 7-107 present Timing requirements and Switching characteristics for MMC1 SDR50 in receiver and transmitter mode (see Figure 7-71 and Figure 7-72).
Table 7-106. Timing Requirements for MMC1 - SD Card SDR50 Mode
NO.
PARAMETER
DESCRIPTION
SDR50 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
SDR50 th(clkH-cmdV)
4
MODE
MIN
MAX
UNIT
2.82
ns
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.6
ns
SDR50 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
2.82
ns
SDR50 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
ns
Internal Loopback Clock
1.6
ns
Table 7-107. Switching Characteristics for MMC1 - SD Card SDR50 Mode
PARAMETER
DESCRIPTION
SDR501
NO.
fop(clk)
Operating frequency, mmc1_clk
SDR502
H
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
SDR502L tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
SDR505
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
td(clkL-cmdV)
MIN
-8.8
MAX
UNIT
96
MHz
6.6
Timing Requirements and Switching Characteristics
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Table 7-107. Switching Characteristics for MMC1 - SD Card SDR50 Mode (continued)
NO.
SDR506
PARAMETER
DESCRIPTION
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
MIN
MAX
UNIT
-3.66
1.46
ns
(1) P = output mmc1_clk period in ns
SDR501
SDR502L
SDR502H
mmc1_clk
SDR503
SDR504
mmc1_cmd
SDR507
SDR508
mmc1_dat[3:0]
MMC1_09
Figure 7-71. MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode
SDR501
SDR502H
SDR502L
mmc1_clk
SDR505
SDR505
mmc1_cmd
SDR506
SDR506
mmc1_dat[3:0]
MMC1_10
Figure 7-72. MMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode
7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
Table 7-108 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver
and transmitter mode (see Figure 7-73 and Figure 7-74)
Table 7-108. Switching Characteristics for MMC1 - SD Card SDR104 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
192
MHz
SDR1041 fop(clk)
Operating frequency, mmc1_clk
SDR1042 tw(clkH)
H
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
SDR1042 tw(clkL)
L
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
SDR1045 td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-1.09
0.49
ns
SDR1046 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-1.09
0.49
ns
320
Timing Requirements and Switching Characteristics
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(1) P = output mmc1_clk period in ns
SDR1041
SDR1042L
SDR1042H
mmc1_clk
SDR1043
SDR1044
mmc1_cmd
SDR1047
SDR1048
mmc1_dat[3:0]
MMC1_11
Figure 7-73. MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode
SDR1041
SDR1042H
SDR1042L
mmc1_clk
SDR1045
SDR1045
mmc1_cmd
SDR1046
SDR1046
mmc1_dat[3:0]
MMC1_12
Figure 7-74. MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode
7.24.1.7 UHS-I DDR50, 4-bit data
Table 7-109 and Table 7-110 present Timing requirements and Switching characteristics for MMC1 DDR50 in receiver and transmitter mode (see Figure 7-75 and Figure 7-76).
Table 7-109. Timing Requirements for MMC1 - SD Card DDR50 Mode
NO.
PARAME
TER
DESCRIPTION
MODE
DDR50 tsu(cmdV-clk)
5
Setup time, mmc1_cmd valid before mmc1_clk
transition
DDR50 th(clk-cmdV)
6
Hold time, mmc1_cmd valid after mmc1_clk transition
DDR50 tsu(dV-clk)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
transition
Pad Loopback
DDR50 th(clk-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk
transition
Pad Loopback
Internal Loopback
Internal Loopback
MIN
MAX
UNIT
3.13
ns
1.6
ns
3.13
ns
3.13
ns
1.6 (1)
ns
1.6
ns
(1) This Hold time requirement is larger than the Hold time provided by a typical SD card. Therefore, the trace length between the Device
and SD card must be sufficiently long enough to ensure that the Hold time is met at the Device.
Table 7-110. Switching Characteristics for MMC1 - SD Card DDR50 Mode
PARAMETER
DESCRIPTION
DDR500
NO.
fop(clk)
Operating frequency, mmc1_clk
MIN
MAX
UNIT
48
MHz
DDR501
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
DDR502
tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
DDR503
td(clk-cmdV)
Delay time, mmc1_clk transition to mmc1_cmd transition
1.225
6.6
DDR504
td(clk-dV)
Delay time, mmc1_clk transition to mmc1_dat[3:0] transition
1.225
6.6
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(1) P = output mmc1_clk period in ns
DDR500
DDR502
DDR501
mmc1_clk
DDR505
DDR506
mmc1_cmd
DDR507
DDR507
DDR508
DDR508
mmc1_dat[3:0]
MMC1_13
Figure 7-75. SDMMC - High Speed SD - DDR - Data/Command Receive
DDR500
DDR501
DDR502
mmc1_clk
DDR503(max)
DDR503(min)
mmc1_cmd
DDR504(max)
DDR504(max)
DDR504(min)
DDR504(min)
mmc1_dat[3:0]
MMC1_14
Figure 7-76. SDMMC - High Speed SD - DDR - Data/Command Transmit
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guarantee some IO timings for MMC1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-111 Virtual
Functions Mapping for MMC1 for a definition of the Virtual modes.
Table 7-111 presents the values for DELAYMODE bitfield.
Table 7-111. Virtual Functions Mapping for MMC1
BALL
322
BALL NAME
Delay Mode Value
MUXMODE[15:
0]
MMC1_VIRTUA
L1
MMC1_VIRTU
AL2
MMC1_VIRTUA
L5
MMC1_VIRTUA
L6
MMC1_VIRTUA
L7
0
W6
mmc1_clk
11
10
7
6
5
mmc1_clk
Y6
mmc1_cmd
11
10
7
6
5
mmc1_cmd
AA6
mmc1_dat0
11
10
7
6
5
mmc1_dat0
Y4
mmc1_dat1
11
10
7
6
5
mmc1_dat1
AA5
mmc1_dat2
11
10
7
6
5
mmc1_dat2
Y3
mmc1_dat3
11
10
7
6
5
mmc1_dat3
Timing Requirements and Switching Characteristics
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NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for MMC1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-112 Manual
Functions Mapping for MMC1 for a definition of the Manual modes.
Table 7-112 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Timing Requirements and Switching Characteristics
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Table 7-112. Manual Functions Mapping for MMC1
BALL
BALL NAME
MMC1_DDR_MANUAL1
MMC1_SDR104_MANUAL1
CFG REGISTER
MUXMODE
-
CFG_MMC1_CLK_IN
mmc1_clk
600
400
CFG_MMC1_CLK_OUT
mmc1_clk
-
-
CFG_MMC1_CMD_IN
mmc1_cmd
0
0
0
CFG_MMC1_CMD_OEN
mmc1_cmd
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
mmc1_clk
0
0
-
W6
mmc1_clk
1271
0
Y6
mmc1_cmd
229
0
Y6
mmc1_cmd
0
W6
0
Y6
mmc1_cmd
0
0
0
0
CFG_MMC1_CMD_OUT
mmc1_cmd
AA6
mmc1_dat0
850
0
-
-
CFG_MMC1_DAT0_IN
mmc1_dat0
AA6
mmc1_dat0
0
0
0
0
CFG_MMC1_DAT0_OEN
mmc1_dat0
AA6
mmc1_dat0
20
0
30
0
CFG_MMC1_DAT0_OUT
mmc1_dat0
Y4
mmc1_dat1
468
0
-
-
CFG_MMC1_DAT1_IN
mmc1_dat1
Y4
mmc1_dat1
0
0
0
0
CFG_MMC1_DAT1_OEN
mmc1_dat1
Y4
mmc1_dat1
0
0
0
0
CFG_MMC1_DAT1_OUT
mmc1_dat1
AA5
mmc1_dat2
466
0
-
-
CFG_MMC1_DAT2_IN
mmc1_dat2
AA5
mmc1_dat2
0
0
0
0
CFG_MMC1_DAT2_OEN
mmc1_dat2
AA5
mmc1_dat2
0
0
0
0
CFG_MMC1_DAT2_OUT
mmc1_dat2
Y3
mmc1_dat3
399
0
-
-
CFG_MMC1_DAT3_IN
mmc1_dat3
Y3
mmc1_dat3
0
0
0
0
CFG_MMC1_DAT3_OEN
mmc1_dat3
Y3
mmc1_dat3
0
0
0
0
CFG_MMC1_DAT3_OUT
mmc1_dat3
7.24.2 MMC2 — eMMC
MMC2 interface is compliant with the JC64 eMMC Standard v4.5 and it supports the following eMMC applications:
• Standard JC64 SDR, 8-bit data, half cycle
• High-speed JC64 SDR, 8-bit data, half cycle
• High-speed JC64 DDR, 8-bit data
• High-speed HS200 JC64 SDR, 8-bit data, half cycle
NOTE
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
Table 7-113 and Table 7-114 present Timing requirements and Switching characteristics for MMC2 - Standard SDR in receiver and Transmitter
mode (see Figure 7-77 and Figure 7-78).
324
Timing Requirements and Switching Characteristics
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Table 7-113. Timing Requirements for MMC2 - JC64 Standard SDR Mode
PARAMETER
DESCRIPTION
SSDR5
NO.
tsu(cmdV-clkH)
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
SSDR6
th(clkH-cmdV)
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
SSDR7
tsu(dV-clkH)
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
SSDR8
th(clkH-dV)
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
MIN
MAX
UNIT
14.53
ns
8.4
ns
14.53
ns
8.4
ns
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Table 7-114. Switching Characteristics for MMC2 - JC64 Standard SDR Mode
NO.
SSDR1
PARAMETER
DESCRIPTION
fop(clk)
Operating frequency, mmc2_clk
MIN
MAX
UNIT
24
MHz
SSDR2H tw(clkH)
Pulse duration, mmc2_clk high
0.5*P0.172 (1)
ns
SSDR2L tw(clkL)
Pulse duration, mmc2_clk low
0.5*P0.172 (1)
ns
SSDR3
td(clkL-cmdV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
-16.96
16.96
ns
SSDR4
td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-16.96
16.96
ns
(1) P = output mmc2_clk period in ns
SSDR2
SSDR2
SSDR1
mmc2_clk
SSDR6
SSDR5
mmc2_cmd
SSDR8
SSDR7
mmc2_dat[7:0]
MMC2_01
Figure 7-77. MMC/SD/SDIO in - Standard JC64 - Receiver Mode
SSDR2
SSDR2
SSDR1
mmc2_clk
SSDR3
mmc2_cmd
SSDR4
mmc2_dat[7:0]
MMC2_02
Figure 7-78. MMC/SD/SDIO in - Standard JC64 - Transmitter Mode
7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
Table 7-115 and Table 7-116 present Timing requirements and Switching characteristics for MMC2 - High
speed SDR in receiver and transmitter mode (see Figure 7-79 and Figure 7-80).
Table 7-115. Timing Requirements for MMC2 - JC64 High Speed SDR Mode
PARAMETER
DESCRIPTION
MIN
JC643
NO.
tsu(cmdV-clkH)
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
6.94
ns
JC644
th(clkH-cmdV)
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
2.6
ns
JC647
tsu(dV-clkH)
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
6.94
ns
JC648
th(clkH-dV)
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
2.6
ns
326
MAX
UNIT
Timing Requirements and Switching Characteristics
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Table 7-116. Switching Characteristics for MMC2 - JC64 High Speed SDR Mode
PARAMETER
DESCRIPTION
JC641
NO.
fop(clk)
Operating frequency, mmc2_clk
MIN
MAX
UNIT
48
JC642H
tw(clkH)
Pulse duration, mmc2_clk high
0.5*P0.172 (1)
MHz
ns
JC642L
tw(clkL)
Pulse duration, mmc2_clk low
0.5*P0.172 (1)
ns
JC645
td(clkL-cmdV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
-6.64
6.64
ns
JC646
td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-6.64
6.64
ns
(1) P = output mmc2_clk period in ns
JC641
JC642L
JC642H
mmc2_clk
JC643
JC644
mmc2_cmd
JC647
JC648
mmc2_dat[7:0]
MMC2_03
Figure 7-79. MMC/SD/SDIO in - High Speed JC64 - Receiver Mode
JC641
JC642L
JC642H
mmc2_clk
JC645
JC645
mmc2_cmd
JC646
JC646
mmc2_dat[7:0]
MMC2_04
Figure 7-80. MMC/SD/SDIO in - High Speed JC64 - Transmitter Mode
7.24.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
Table 7-117 presents Timing requirements and Switching characteristics for MMC2 - HS200 in receiver
and transmitter mode (see Figure 7-81).
Table 7-117. Switching Characteristics for MMC2 - JEDS84 HS200 Mode
NO.
HS2001
PARAMETER
DESCRIPTION
fop(clk)
Operating frequency, mmc2_clk
MIN
MAX
UNIT
192
MHz
HS2002H tw(clkH)
Pulse duration, mmc2_clk high
0.5*P0.172 (1)
ns
HS2002L tw(clkL)
Pulse duration, mmc2_clk low
0.5*P0.172 (1)
ns
HS2005
td(clkL-cmdV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
-1.136
0.536
ns
HS2006
td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-1.136
0.536
ns
Timing Requirements and Switching Characteristics
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(1) P = output mmc2_clk period in ns
HS2001
HS2002L
HS2002H
mmc2_clk
HS2005
HS2005
mmc2_cmd
HS2006
HS2006
mmc2_dat[7:0]
MMC2_05
Figure 7-81. eMMC in - HS200 SDR - Transmitter Mode
7.24.2.4 High-speed JC64 DDR, 8-bit data
Table 7-118 and Table 7-119 present Timing requirements and Switching characteristics for MMC2 - High
speed DDR in receiver and transmitter mode (see Figure 7-82 and Figure 7-83).
Table 7-118. Timing Requirements for MMC2 - JC64 High Speed DDR Mode
NO.
PARAMETER
DESCRIPTION
DDR3
tsu(cmdV-clk)
Setup time, mmc2_cmd valid before mmc2_clk
transition
DDR4
th(clk-cmdV)
Hold time, mmc2_cmd valid after mmc2_clk transition
DDR7
tsu(dV-clk)
Setup time, mmc2_dat[7:0] valid before mmc2_clk
transition
DDR8
th(clk-dV)
Hold time, mmc2_dat[7:0] valid after mmc2_clk
transition
MODE
MIN
MAX
UNIT
3.14
ns
1.8
ns
3.14
ns
Pad Loopback (1.8V)
1.8 (1)
ns
Pad Loopback (3.3V)
1.8
ns
(1)
ns
Internal Loopback
1.8
(1) This Hold time requirement is larger than the Hold time provided by a typical eMMC component. Therefore, the trace length between the
Device and eMMC component must be sufficiently long enough to ensure that the Hold time is met at the Device.
Table 7-119. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
PARAMETER
DESCRIPTION
DDR1
NO.
fop(clk)
Operating frequency, mmc2_clk
MIN
MAX
UNIT
48
MHz
DDR2H
tw(clkH)
Pulse duration, mmc2_clk high
0.5*P0.172 (1)
ns
DDR2L
tw(clkL)
Pulse duration, mmc2_clk low
0.5*P0.172 (1)
ns
DDR5
td(clk-cmdV)
Delay time, mmc2_clk transition to mmc2_cmd transition
2.9
7.14
ns
DDR6
td(clk-dV)
Delay time, mmc2_clk transition to mmc2_dat[7:0] transition
2.9
7.14
ns
(1) P = output mmc2_clk period in ns
Table 7-120 and Table 7-121 present Timing requirements and Switching characteristics for MMC2 - High
speed DDR in receiver and transmitter mode During Boot (see Figure 7-82 and Figure 7-83).
Table 7-120. Timing Requirements for MMC2 - JC64 High Speed DDR Mode During Boot
PARAMETER
DESCRIPTION
DDR3
NO.
tsu(cmdV-clk)
Setup time, mmc2_cmd valid before mmc2_clk transition
DDR4
th(clk-cmdV)
Hold time, mmc2_cmd valid after mmc2_clk transition
328
MODE
MIN
Boot (1.8V)
3.14
MAX
UNIT
ns
B3oot (3.3V)
3.14
ns
Boot (1.8V)
1.8 (1)
ns
Boot (3.3V)
1.8 (1)
ns
Timing Requirements and Switching Characteristics
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Table 7-120. Timing Requirements for MMC2 - JC64 High Speed DDR Mode During Boot (continued)
PARAMETER
DESCRIPTION
MODE
MIN
DDR7
NO.
tsu(dV-clk)
Setup time, mmc2_dat[7:0] valid before mmc2_clk
transition
Boot (1.8V)
3.14
MAX
UNIT
ns
Boot (3.3V)
3.14
ns
DDR8
th(clk-dV)
Hold time, mmc2_dat[7:0] valid after mmc2_clk transition
Boot (1.8V)
1.8 (1)
ns
Boot (3.3V)
1.8 (1)
ns
(1) This Hold time requirement is larger than the Hold time provided by a typical eMMC component. Therefore, the trace length between the
Device and eMMC component must be sufficiently long enough to ensure that the Hold time is met at the Device.
Table 7-121. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode During Boot
NO.
DDR1
PARAMETER
DESCRIPTION
fop(clk)
Operating frequency, mmc2_clk
DDR2H tw(clkH)
MODE
MIN
Pulse duration, mmc2_clk high
MAX
UNIT
48
MHz
0.5*P0.172
ns
0.5*P0.172
ns
(1)
DDR2L tw(clkL)
Pulse duration, mmc2_clk low
(1)
DDR5
DDR6
td(clk-cmdV)
td(clk-dV)
Delay time, mmc2_clk transition to mmc2_cmd transition
Delay time, mmc2_clk transition to mmc2_dat[7:0] transition
Boot (1.8V)
2.9
7.14
ns
Boot (3.3V)
2.9
7.14
ns
Boot (1.8V)
2.9
7.14
ns
Boot (3.3V)
2.9
7.14
ns
(1) P = output mmc2_clk period in ns
DDR1
DDR2H
DDR2L
mmc2_clk
DDR3
DDR4
mmc2_cmd
DDR8
DDR8
DDR7
DDR8
DDR7
DDR7
DDR7
mmc2_dat[7:0]
MMC2_07
Figure 7-82. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode
DDR1
DDR2
DDR2
mmc2_clk
DDR5
DDR5
DDR5
DDR5
mmc2_cmd
DDR6
DDR6
DDR6
DDR6
DDR6
DDR6
mmc2_dat[7:0]
MMC2_08
Figure 7-83. MMC/SD/SDIO in - High Speed DDR JC64 - Transmitter Mode
Timing Requirements and Switching Characteristics
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NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for MMC2. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-122 Manual
Functions Mapping for MMC2 DDR for a definition of the Manual modes.
Table 7-122 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
330
Timing Requirements and Switching Characteristics
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Table 7-122. Manual Functions Mapping for MMC2 DDR
BALL
BALL NAME
MMC2_DDR_MANUAL1
CFG REGISTER
MUXMODE
0
CFG_GPMC_A19_IN
mmc2_dat4
A_DELAY (ps)
G_DELAY (ps)
270
1
K7
gpmc_a19
K7
gpmc_a19
0
0
CFG_GPMC_A19_OEN
mmc2_dat4
K7
gpmc_a19
170
0
CFG_GPMC_A19_OUT
mmc2_dat4
M7
gpmc_a20
758
0
CFG_GPMC_A20_IN
mmc2_dat5
M7
gpmc_a20
0
0
CFG_GPMC_A20_OEN
mmc2_dat5
M7
gpmc_a20
81
0
CFG_GPMC_A20_OUT
mmc2_dat5
J5
gpmc_a21
286
0
CFG_GPMC_A21_IN
mmc2_dat6
J5
gpmc_a21
0
0
CFG_GPMC_A21_OEN
mmc2_dat6
J5
gpmc_a21
123
0
CFG_GPMC_A21_OUT
mmc2_dat6
K6
gpmc_a22
346
0
CFG_GPMC_A22_IN
mmc2_dat7
K6
gpmc_a22
0
0
CFG_GPMC_A22_OEN
mmc2_dat7
K6
gpmc_a22
55
0
CFG_GPMC_A22_OUT
mmc2_dat7
J7
gpmc_a23
0
0
CFG_GPMC_A23_IN
mmc2_clk
J7
gpmc_a23
422
0
CFG_GPMC_A23_OUT
mmc2_clk
J4
gpmc_a24
642
0
CFG_GPMC_A24_IN
mmc2_dat0
J4
gpmc_a24
0
0
CFG_GPMC_A24_OEN
mmc2_dat0
J4
gpmc_a24
0
0
CFG_GPMC_A24_OUT
mmc2_dat0
J6
gpmc_a25
128
0
CFG_GPMC_A25_IN
mmc2_dat1
J6
gpmc_a25
0
0
CFG_GPMC_A25_OEN
mmc2_dat1
J6
gpmc_a25
0
0
CFG_GPMC_A25_OUT
mmc2_dat1
H4
gpmc_a26
395
0
CFG_GPMC_A26_IN
mmc2_dat2
H4
gpmc_a26
0
0
CFG_GPMC_A26_OEN
mmc2_dat2
H4
gpmc_a26
0
0
CFG_GPMC_A26_OUT
mmc2_dat2
H5
gpmc_a27
623
0
CFG_GPMC_A27_IN
mmc2_dat3
H5
gpmc_a27
0
0
CFG_GPMC_A27_OEN
mmc2_dat3
H5
gpmc_a27
54
0
CFG_GPMC_A27_OUT
mmc2_dat3
H6
gpmc_cs1
0
0
CFG_GPMC_CS1_IN
mmc2_cmd
H6
gpmc_cs1
0
0
CFG_GPMC_CS1_OEN
mmc2_cmd
H6
gpmc_cs1
0
0
CFG_GPMC_CS1_OUT
mmc2_cmd
Timing Requirements and Switching Characteristics
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Manual IO Timings Modes must be used to guarantee some IO timings for MMC2. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-123 Manual Functions Mapping for MMC2 with Internal Loopback Clock and for HS200 for a
definition of the Manual modes.
Table 7-123 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-123. Manual Functions Mapping for MMC2 With Internal Loopback Clock and for HS200
BALL
BALL NAME
MMC2_DDR_LB_MANUAL1
MMC2_STD_HS_LB_MANUAL1
A_DELAY (ps)
G_DELAY
(ps)
A_DELAY (ps)
G_DELAY (ps)
MMC2_HS200_MANUAL1
A_DELAY (ps)
CFG REGISTER
G_DELAY (ps)
MUXMODE
1
K7
gpmc_a19
49
0
850
0
-
-
CFG_GPMC_A19_IN
mmc2_dat4
K7
gpmc_a19
0
0
0
0
274
0
CFG_GPMC_A19_OEN
mmc2_dat4
K7
gpmc_a19
170
0
0
0
162
0
CFG_GPMC_A19_OUT
mmc2_dat4
M7
gpmc_a20
463
0
1264
0
-
-
CFG_GPMC_A20_IN
mmc2_dat5
M7
gpmc_a20
0
0
0
0
401
0
CFG_GPMC_A20_OEN
mmc2_dat5
M7
gpmc_a20
81
0
0
0
73
0
CFG_GPMC_A20_OUT
mmc2_dat5
J5
gpmc_a21
8
0
786
0
-
-
CFG_GPMC_A21_IN
mmc2_dat6
J5
gpmc_a21
0
0
0
0
465
0
CFG_GPMC_A21_OEN
mmc2_dat6
J5
gpmc_a21
123
0
0
0
115
0
CFG_GPMC_A21_OUT
mmc2_dat6
K6
gpmc_a22
0
102
902
0
-
-
CFG_GPMC_A22_IN
mmc2_dat7
K6
gpmc_a22
0
0
0
0
633
0
CFG_GPMC_A22_OEN
mmc2_dat7
K6
gpmc_a22
55
0
0
0
47
0
CFG_GPMC_A22_OUT
mmc2_dat7
J7
gpmc_a23
592
2815
0
2764
-
-
CFG_GPMC_A23_IN
mmc2_clk
J7
gpmc_a23
422
0
0
0
935
280
CFG_GPMC_A23_OUT
mmc2_clk
J4
gpmc_a24
384
0
1185
0
-
-
CFG_GPMC_A24_IN
mmc2_dat0
J4
gpmc_a24
0
0
0
0
621
0
CFG_GPMC_A24_OEN
mmc2_dat0
J4
gpmc_a24
0
0
0
0
0
0
CFG_GPMC_A24_OUT
mmc2_dat0
J6
gpmc_a25
0
0
670
0
-
-
CFG_GPMC_A25_IN
mmc2_dat1
J6
gpmc_a25
0
0
0
0
183
0
CFG_GPMC_A25_OEN
mmc2_dat1
J6
gpmc_a25
0
0
0
0
0
0
CFG_GPMC_A25_OUT
mmc2_dat1
H4
gpmc_a26
171
0
972
0
-
-
CFG_GPMC_A26_IN
mmc2_dat2
H4
gpmc_a26
0
0
0
0
467
0
CFG_GPMC_A26_OEN
mmc2_dat2
H4
gpmc_a26
0
0
0
0
0
0
CFG_GPMC_A26_OUT
mmc2_dat2
H5
gpmc_a27
315
0
1116
0
-
-
CFG_GPMC_A27_IN
mmc2_dat3
H5
gpmc_a27
0
0
0
0
262
0
CFG_GPMC_A27_OEN
mmc2_dat3
H5
gpmc_a27
54
0
0
0
46
0
CFG_GPMC_A27_OUT
mmc2_dat3
H6
gpmc_cs1
0
0
250
0
-
-
CFG_GPMC_CS1_IN
mmc2_cmd
332
Timing Requirements and Switching Characteristics
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Table 7-123. Manual Functions Mapping for MMC2 With Internal Loopback Clock and for HS200 (continued)
BALL
BALL NAME
MMC2_DDR_LB_MANUAL1
MMC2_STD_HS_LB_MANUAL1
MMC2_HS200_MANUAL1
A_DELAY (ps)
G_DELAY
(ps)
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
CFG REGISTER
MUXMODE
1
H6
gpmc_cs1
0
0
0
0
684
0
CFG_GPMC_CS1_OEN
mmc2_cmd
H6
gpmc_cs1
0
0
0
0
76
0
CFG_GPMC_CS1_OUT
mmc2_cmd
Timing Requirements and Switching Characteristics
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7.24.3 MMC3 and MMC4—SDIO/SD
MMC3 and MMC4 interfaces are compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic
SDIO devices, it supports the following applications:
• MMC3 8-bit data and MMC4 4-bit data, SD Default speed, SDR
• MMC3 8-bit data and MMC4 4-bit data, SD High speed, SDR
• MMC3 8-bit data and MMC4 4-bit data, UHS-1 SDR12 (SD Standard v3.01), 4-bit data, SDR, half
cycle
• MMC3 8-bit data and MMC4 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle
• MMC3 8-bit data, UHS-I SDR50
NOTE
The eMMC/SD/SDIOj (j = 3 to 4) controller is also referred to as MMCj.
NOTE
For more information, see the MMC/SDIO chapter of the Device TRM.
7.24.3.1 MMC3 and MMC4, SD Default Speed
Figure 7-84, Figure 7-85, and Table 7-124 through Table 7-127 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmitter mode.
Table 7-124. Timing Requirements for MMC3 - Default Speed Mode (1)
NO.
PARAMETER
DESCRIPTION
DS5
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
DS6
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
DS7
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
DS8
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
MIN
MAX
UNIT
25.83
ns
20.9
ns
25.83
ns
20.9
ns
(1) i in [i:0] = 7
Table 7-125. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode (2)
NO.
PARAMETER
DESCRIPTION
DS0
fop(clk)
Operating frequency, mmc3_clk
MIN
MAX
UNIT
24
DS1
tw(clkH)
Pulse duration, mmc3_clk high
0.5*P0.270 (1)
MHz
ns
DS2
tw(clkL)
Pulse duration, mmc3_clk low
0.5*P0.270 (1)
ns
DS3
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-14.93
14.93
ns
DS4
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-14.93
14.93
ns
MAX
UNIT
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 7-126. Timing Requirements for MMC4 - Default Speed Mode (1)
NO.
PARAMETER
DESCRIPTION
DS5
tsu(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
DS6
th(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
DS7
tsu(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
DS8
th(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
334
MIN
28.53
ns
20.9
ns
28.53
ns
20.9
ns
Timing Requirements and Switching Characteristics
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(1) i in [i:0] = 3
Table 7-127. Switching Characteristics for MMC4 - Default Speed Mode (2)
NO.
PARAMETER
DESCRIPTION
DS0
fop(clk)
Operating frequency, mmc4_clk
MIN
MAX
UNIT
24
DS1
tw(clkH)
Pulse duration, mmc4_clk high
0.45*P
(1)
MHz
DS2
tw(clkL)
Pulse duration, mmc4_clk low
0.45*P
(1)
DS3
td(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
-14.93
14.93
ns
DS4
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-14.93
14.93
ns
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
DS2
DS1
DS0
mmcj_clk
DS6
DS5
mmcj_cmd
DS8
DS7
mmcj_dat[i:0]
MMC3/4_07
Figure 7-84. MMC/SD/SDIOj in - Default Speed - Receiver Mode
DS2
DS1
DS0
mmcj_clk
DS3
mmcj_cmd
DS4
mmcj_dat[i:0]
MMC3/4_08
Figure 7-85. MMC/SD/SDIOj in - Default Speed - Transmitter Mode
7.24.3.2 MMC3 and MMC4, SD High Speed
Figure 7-86, Figure 7-87, and Table 7-128 through Table 7-131 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO High speed in receiver and transmitter
mode.
Table 7-128. Timing Requirements for MMC3 - SD/SDIO High Speed Mode (1)
NO.
PARAMETER
DESCRIPTION
MIN
HS3
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
6.64
MAX
ns
HS4
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
2.6
ns
HS7
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
6.64
ns
HS8
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
2.6
ns
Timing Requirements and Switching Characteristics
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UNIT
335
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(1) i in [i:0] = 7
Table 7-129. Switching Characteristics for MMC3 - SD/SDIO High Speed Mode (2)
NO.
PARAMETER
DESCRIPTION
HS1
fop(clk)
Operating frequency, mmc3_clk
MIN
MAX
UNIT
48
MHz
HS2H
tw(clkH)
Pulse duration, mmc3_clk high
0.5*P0.270 (1)
ns
HS2L
tw(clkL)
Pulse duration, mmc3_clk low
0.5*P0.270 (1)
ns
HS5
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-7.6
3.6
ns
HS6
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-7.6
3.6
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 7-130. Timing Requirements for MMC4 - High Speed Mode (1)
NO.
PARAMETER
DESCRIPTION
MIN
HS3
tsu(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
6.64
MAX
UNIT
ns
HS4
th(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
1.6
ns
HS7
tsu(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
6.64
ns
HS8
th(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
1.6
ns
(1) i in [i:0] = 3
Table 7-131. Switching Characteristics for MMC4 - High Speed Mode (2)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
48
MHz
HS1
fop(clk)
Operating frequency, mmc4_clk
HS2H
tw(clkH)
Pulse duration, mmc4_clk high
0.45*P
(1)
HS2L
tw(clkL)
Pulse duration, mmc4_clk low
0.45*P
(1)
HS5
td(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
-8.8
6.6
ns
HS6
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
6.6
ns
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
HS1
HS2L
HS2H
mmcj_clk
HS3
HS4
mmcj_cmd
HS7
HS8
mmcj_dat[i:0]
MMC3/4_09
Figure 7-86. MMC/SD/SDIOj in - High Speed - Receiver Mode
336
Timing Requirements and Switching Characteristics
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HS1
HS2H
HS2L
mmcj_clk
HS5
HS5
mmcj_cmd
HS6
HS6
mmcj_dat[i:0]
MMC3/4_10
Figure 7-87. MMC/SD/SDIOj in - High Speed - Transmitter Mode
7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
Figure 7-88, Figure 7-89, and Table 7-132, through Table 7-135 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.
Table 7-132. Timing Requirements for MMC3 - SDR12 Mode (1)
PARAMETER
DESCRIPTION
SDR125
NO.
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
SDR126
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
SDR127
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
SDR128
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
MIN
MAX
UNIT
27.33
ns
1.6
ns
27.33
ns
1.6
ns
(1) i in [i:0] = 7
Table 7-133. Switching Characteristics for MMC3 - SDR12 Mode (2)
PARAMETER
DESCRIPTION
SDR120
NO.
fop(clk)
Operating frequency, mmc3_clk
MIN
MAX
UNIT
24
MHz
SDR121
tw(clkH)
Pulse duration, mmc3_clk high
0.5*P0.270 (1)
ns
SDR122
tw(clkL)
Pulse duration, mmc3_clk low
0.5*P0.270 (1)
ns
SDR123
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-19.13
16.93
ns
SDR124
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-19.13
16.93
ns
MAX
UNIT
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 7-134. Timing Requirements for MMC4 - SDR12 Mode (1)
PARAMETER
DESCRIPTION
SDR125
NO.
tsu(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
SDR126
th(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
SDR127
tsu(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
SDR128
th(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
MIN
27.33
ns
1.6
ns
27.33
ns
1.6
ns
(1) j in [i:0] = 3
Table 7-135. Switching Characteristics for MMC4 - SDR12 Mode (2)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR120
fop(clk)
Operating frequency, mmc4_clk
SDR121
tw(clkH)
Pulse duration, mmc4_clk high
0.45*P
(1)
24
MHz
ns
SDR122
tw(clkL)
Pulse duration, mmc4_clk low
0.45*P
(1)
ns
SDR125
td(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
-19.13
16.93
ns
SDR126
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-19.13
16.93
ns
Timing Requirements and Switching Characteristics
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(1) P = output mmc4_clk period in ns
(2) j in [i:0] = 3
SDR122
SDR121
SDR120
mmcj_clk
SDR126
SDR125
mmcj_cmd
SDR128
SDR127
mmcj_dat[i:0]
MMC3/4_11
Figure 7-88. MMC/SD/SDIOj in - SDR12 - Receiver Mode
SDR122
SDR121
SDR120
mmcj_clk
SDR123
mmcj_cmd
SDR124
mmcj_dat[i:0]
MMC3/4_12
Figure 7-89. MMC/SD/SDIOj in - SDR12 - Transmitter Mode
7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
Figure 7-90, Figure 7-91, and Table 7-136 through Table 7-139 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR25 in receiver and transmitter mode.
Table 7-136. Timing Requirements for MMC3 - SDR25 Mode (1)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR253
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
6.64
ns
SDR254
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
1.6
ns
SDR257
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
6.64
ns
SDR258
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
1.6
ns
(1) i in [i:0] = 7
Table 7-137. Switching Characteristics for MMC3 - SDR25 Mode (2)
PARAMETER
DESCRIPTION
SDR251
NO.
fop(clk)
Operating frequency, mmc3_clk
SDR252
H
tw(clkH)
Pulse duration, mmc3_clk high
0.5*P0.270 (1)
ns
SDR252L tw(clkL)
Pulse duration, mmc3_clk low
0.5*P0.270 (1)
ns
SDR255
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-8.8
6.6
ns
SDR256
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-8.8
6.6
ns
338
MIN
MAX
UNIT
48
MHz
Timing Requirements and Switching Characteristics
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(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 7-138. Timing Requirements for MMC4 - SDR25 Mode (1)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR255
tsu(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
6.64
ns
SDR256
th(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
1.6
ns
SDR257
tsu(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
6.64
ns
SDR258
th(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
1.6
ns
(1) i in [i:0] = 3
Table 7-139. Switching Characteristics for MMC4 - SDR25 Mode (2)
PARAMETER
DESCRIPTION
SDR251
NO.
fop(clk)
Operating frequency, mmc4_clk
MIN
MAX
UNIT
48
SDR252
H
tw(clkH)
Pulse duration, mmc4_clk high
0.45*P
(1)
MHz
SDR252L tw(clkL)
Pulse duration, mmc4_clk low
0.45*P
(1)
SDR255
td(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
-8.8
6.6
ns
SDR256
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
6.6
ns
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
SDR251
SDR252L
SDR252H
mmcj_clk
SDR253
SDR254
mmcj_cmd
SDR257
SDR258
mmcj_dat[i:0]
MMC3/4_13
Figure 7-90. MMC/SD/SDIOj in - SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
mmcj_clk
SDR255
SDR255
mmcj_cmd
SDR256
SDR256
mmcj_dat[i:0]
MMC3/4_14
Figure 7-91. .MMC/SD/SDIOj in - SDR25 - Transmitter Mode
7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
Figure 7-92, Figure 7-93, Table 7-140, and Table 7-141 present Timing requirements and Switching
characteristics for MMC3 - SDIO High speed SDR50 in receiver and transmitter mode.
Timing Requirements and Switching Characteristics
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Table 7-140. Timing Requirements for MMC3 - SDR50 Mode (1)
PARAMETER
DESCRIPTION
MIN
SDR503
NO.
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
2.82
MAX
UNIT
ns
SDR504
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
1.6
ns
SDR507
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
2.82
ns
SDR508
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
1.6
ns
(1) i in [i:0] = 7
Table 7-141. Switching Characteristics for MMC3 - SDR50 Mode (2)
PARAMETER
DESCRIPTION
SDR501
NO.
fop(clk)
Operating frequency, mmc3_clk
MIN
MAX
UNIT
64
MHz
SDR502
H
tw(clkH)
Pulse duration, mmc3_clk high
0.5*P0.270 (1)
ns
SDR502L tw(clkL)
Pulse duration, mmc3_clk low
0.5*P0.270 (1)
ns
SDR505
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-3.66
1.46
ns
SDR506
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-3.66
1.46
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
SDR501
SDR502L
SDR502H
mmcj_clk
SDR503
SDR504
mmcj_cmd
SDR507
SDR508
mmcj_dat[7:0]
MMC3/4_05
Figure 7-92. MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode
SDR501
SDR502H
SDR502L
mmcj_clk
SDR505
SDR505
mmcj_cmd
SDR506
SDR506
mmcj_dat[7:0]
MMC3/4_06
Figure 7-93. MMC/SD/SDIOj in - High Speed SDR50 - Transmitter Mode
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for MMC3. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-142 Manual
Functions Mapping for MMC3 for a definition of the Manual modes.
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Table 7-142 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-142. Manual Functions Mapping for MMC3
BALL
BALL NAME
MMC3_MANUAL1
A_DELAY (ps)
G_DELAY (ps)
CFG REGISTER
MUXMODE
0
AD4
mmc3_clk
0
386
CFG_MMC3_CLK_IN
mmc3_clk
AD4
mmc3_clk
605
0
CFG_MMC3_CLK_OUT
mmc3_clk
AC4
mmc3_cmd
0
0
CFG_MMC3_CMD_IN
mmc3_cmd
AC4
mmc3_cmd
0
0
CFG_MMC3_CMD_OEN
mmc3_cmd
AC4
mmc3_cmd
0
0
CFG_MMC3_CMD_OUT
mmc3_cmd
AC7
mmc3_dat0
171
0
CFG_MMC3_DAT0_IN
mmc3_dat0
AC7
mmc3_dat0
0
0
CFG_MMC3_DAT0_OEN
mmc3_dat0
AC7
mmc3_dat0
0
0
CFG_MMC3_DAT0_OUT
mmc3_dat0
AC6
mmc3_dat1
221
0
CFG_MMC3_DAT1_IN
mmc3_dat1
AC6
mmc3_dat1
0
0
CFG_MMC3_DAT1_OEN
mmc3_dat1
AC6
mmc3_dat1
0
0
CFG_MMC3_DAT1_OUT
mmc3_dat1
AC9
mmc3_dat2
0
0
CFG_MMC3_DAT2_IN
mmc3_dat2
AC9
mmc3_dat2
0
0
CFG_MMC3_DAT2_OEN
mmc3_dat2
AC9
mmc3_dat2
0
0
CFG_MMC3_DAT2_OUT
mmc3_dat2
AC3
mmc3_dat3
474
0
CFG_MMC3_DAT3_IN
mmc3_dat3
AC3
mmc3_dat3
0
0
CFG_MMC3_DAT3_OEN
mmc3_dat3
AC3
mmc3_dat3
0
0
CFG_MMC3_DAT3_OUT
mmc3_dat3
AC8
mmc3_dat4
792
0
CFG_MMC3_DAT4_IN
mmc3_dat4
AC8
mmc3_dat4
0
0
CFG_MMC3_DAT4_OEN
mmc3_dat4
AC8
mmc3_dat4
0
0
CFG_MMC3_DAT4_OUT
mmc3_dat4
AD6
mmc3_dat5
782
0
CFG_MMC3_DAT5_IN
mmc3_dat5
AD6
mmc3_dat5
0
0
CFG_MMC3_DAT5_OEN
mmc3_dat5
AD6
mmc3_dat5
0
0
CFG_MMC3_DAT5_OUT
mmc3_dat5
AB8
mmc3_dat6
942
0
CFG_MMC3_DAT6_IN
mmc3_dat6
AB8
mmc3_dat6
0
0
CFG_MMC3_DAT6_OEN
mmc3_dat6
AB8
mmc3_dat6
0
0
CFG_MMC3_DAT6_OUT
mmc3_dat6
AB5
mmc3_dat7
636
0
CFG_MMC3_DAT7_IN
mmc3_dat7
AB5
mmc3_dat7
0
0
CFG_MMC3_DAT7_OEN
mmc3_dat7
AB5
mmc3_dat7
0
0
CFG_MMC3_DAT7_OUT
mmc3_dat7
Manual IO Timings Modes must be used to guarantee some IO timings for MMC4. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-143 Manual
Functions Mapping for MMC4 for a definition of the Manual modes.
Table 7-143 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-143. Manual Functions Mapping for MMC4
BALL
BALL NAME
MMC4_MANUAL1
MMC4_DS_MANUAL1
CFG REGISTER
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
0
0
CFG_UART1_CTSN_IN
E25
uart1_ctsn
0
0
MUXMODE
3
mmc4_clk
E25
uart1_ctsn
1147
0
0
0
CFG_UART1_CTSN_OUT
mmc4_clk
C27
uart1_rtsn
1834
0
307
0
CFG_UART1_RTSN_IN
mmc4_cmd
C27
uart1_rtsn
0
0
0
0
CFG_UART1_RTSN_OEN
mmc4_cmd
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Table 7-143. Manual Functions Mapping for MMC4 (continued)
BALL
BALL NAME
MMC4_MANUAL1
A_DELAY
(ps)
G_DELAY
(ps)
MMC4_DS_MANUAL1
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
3
C27
uart1_rtsn
0
0
0
0
CFG_UART1_RTSN_OUT
mmc4_cmd
D27
uart2_ctsn
2165
0
785
0
CFG_UART2_CTSN_IN
mmc4_dat2
D27
uart2_ctsn
0
0
0
0
CFG_UART2_CTSN_OEN
mmc4_dat2
D27
uart2_ctsn
0
0
0
0
CFG_UART2_CTSN_OUT
mmc4_dat2
C28
uart2_rtsn
1929
64
613
0
CFG_UART2_RTSN_IN
mmc4_dat3
C28
uart2_rtsn
0
0
0
0
CFG_UART2_RTSN_OEN
mmc4_dat3
C28
uart2_rtsn
0
0
0
0
CFG_UART2_RTSN_OUT
mmc4_dat3
D28
uart2_rxd
1935
128
683
0
CFG_UART2_RXD_IN
mmc4_dat0
D28
uart2_rxd
0
0
0
0
CFG_UART2_RXD_OEN
mmc4_dat0
D28
uart2_rxd
0
0
0
0
CFG_UART2_RXD_OUT
mmc4_dat0
D26
uart2_txd
2172
44
835
0
CFG_UART2_TXD_IN
mmc4_dat1
D26
uart2_txd
0
0
0
0
CFG_UART2_TXD_OEN
mmc4_dat1
D26
uart2_txd
0
0
0
0
CFG_UART2_TXD_OUT
mmc4_dat1
7.25 General-Purpose Interface (GPIO)
The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO
module provides 32 dedicated general-purpose pins with input and output capabilities; thus, the generalpurpose interface supports up to 247 pins.
These pins can be configured for the following applications:
• Data input (capture)/output (drive)
• Keyboard interface with a debounce cell
• Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations
• Wake-up request generation in idle mode upon the detection of external events
NOTE
For more information, see the General-Purpose Interface chapter of the Device TRM.
NOTE
The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi.
7.26 Audio Tracking Logic (ATL)
The device contains four ATL modules that can be used for asynchronous sample rate conversion of
audio. The ATL calculates the error between two time bases, such as audio syncs, and optionally
generates an averaged clock using cycle stealing via software.
NOTE
For more detailed information on the ATL peripheral, see the Audio Tracking Logic (ATL)
chapter of the device-specific Technical Reference Manual.
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NOTE
Audio Tracking Logic x (x= 1 to 4) module is also referred to as ATLx.
7.26.1 ATL Electrical Data/Timing
Table 7-144 and Figure 7-94 present switching characteristics for ATL
Table 7-144. Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
NO.
1
PARAMETER
tc(ATLCLKOUT)
DESCRIPTION
MIN
MAX
UNIT
Cycle time, ATL_CLKOUTx
20
ns
(1)
2
tw(ATLCLKOUTL)
Pulse Duration, ATL_CLKOUTx low
0.45*P - M
ns
3
tw(ATLCLKOUTH)
Pulse Duration, ATL_CLKOUTx high
0.45*P - M(1)
ns
(1) P = ATL_CLKOUTx period.
M = internal ATL PCLK period.
1
2
atl_clkx
3
ATL_01
Figure 7-94. ATL_CLKOUTx Timing
7.27 System and Miscellaneous interfaces
The Device includes the following System and Miscellaneous interfaces:
• Sysboot Interface
• System DMA Interface
• Interrupt Controllers (INTC) Interface
• Observability Signal (OBS) Interface
7.28 Test Interfaces
The Device includes the following Test interfaces:
• IEEE 1149.1 Standard-Test-Access Port (JTAG)
• Compact JTAG Interface (cJTAG)
• Trace Port Interface Unit (TPIU)
• Advanced Event Triggering Interface (AET)
7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)
interface is used for BSDL testing and emulation of the device. The trstn pin only needs to be released
when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan
functionality. For maximum reliability, the device includes an internal Pulldown (IPD) on the trstn pin to
ensure that trstn is always asserted upon power up and the device's internal emulation logic is always
properly initialized. JTAG controllers from Texas Instruments actively drive trstn high. However, some
third-party JTAG controllers may not drive trstn high but expect the use of a Pullup resistor on trstn. When
using this type of JTAG controller, assert trstn to initialize the device after powerup and externally drive
trstn high before attempting any emulation or boundary-scan operations.
The main JTAG features include:
• 32KB embedded trace buffer (ETB)
Timing Requirements and Switching Characteristics
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•
•
•
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5-pin system trace interface for debug
Supports Advanced Event Triggering (AET)
All processors can be emulated via JTAG ports
All functions on EMU pins of the device:
– EMU[1:0] - cross-triggering, boot mode (WIR), STM trace
– EMU[4:2] - STM trace only (single direction)
7.28.1.1 JTAG Electrical Data/Timing
Table 7-145, Table 7-146 and Figure 7-95 assume testing over the recommended operating conditions
and electrical characteristic conditions below.
Table 7-145. Timing Requirements for IEEE 1149.1 JTAG
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
1
tc(TCK)
Cycle time, TCK
62.29
ns
1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
24.92
ns
1b
tw(TCKL)
Pulse duration, TCK low (40% of tc)
24.92
ns
tsu(TDI-TCK)
Input setup time, TDI valid to TCK high
6.23
ns
tsu(TMS-TCK)
Input setup time, TMS valid to TCK high
6.23
ns
th(TCK-TDI)
Input hold time, TDI valid from TCK high
31.15
ns
th(TCK-TMS)
Input hold time, TMS valid from TCK high
31.15
ns
3
4
Table 7-146. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
2
PARAMETER
td(TCKL-TDOV)
DESCRIPTION
Delay time, TCK low to TDO valid
MIN
MAX
UNIT
0
30.5
ns
1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
JTAG_01
Figure 7-95. JTAG Timing
Table 7-147, Table 7-148 and Figure 7-96 assume testing over the recommended operating conditions
and electrical characteristic conditions below.
Table 7-147. Timing Requirements for IEEE 1149.1 JTAG With RTCK
NO.
DESCRIPTION
MIN
MAX
UNIT
1
tc(TCK)
Cycle time, TCK
62.29
ns
1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
24.92
ns
1b
tw(TCKL)
Pulse duration, TCK low (40% of tc)
24.92
ns
tsu(TDI-TCK)
Input setup time, TDI valid to TCK high
6.23
ns
tsu(TMS-TCK)
Input setup time, TMS valid to TCK high
6.23
ns
3
344
PARAMETER
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Table 7-147. Timing Requirements for IEEE 1149.1 JTAG With RTCK (continued)
NO.
PARAMETER
4
DESCRIPTION
MIN
MAX
UNIT
th(TCK-TDI)
Input hold time, TDI valid from TCK high
31.15
ns
th(TCK-TMS)
Input hold time, TMS valid from TCK high
31.15
ns
Table 7-148. Switching Characteristics Over Recommended Operating Conditions for
IEEE 1149.1 JTAG With RTCK
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
0
27
ns
5
td(TCK-RTCK)
Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is
the only tap selected - when the ARM is in the scan chain, the delay
time is a function of the ARM functional clock).
6
tc(RTCK)
Cycle time, RTCK
62.29
ns
7
tw(RTCKH)
Pulse duration, RTCK high (40% of tc)
24.92
ns
8
tw(RTCKL)
Pulse duration, RTCK low (40% of tc)
24.92
ns
5
TCK
6
7
8
RTCK
JTAG_02
Figure 7-96. JTAG With RTCK Timing
7.28.1.2 Compact JTAG Interface (cJTAG)
The cJTAG module is a component which can run a 2-pin communication protocol on top of an IEEE
1149.1 JTAG Test Access Port (TAP). The cJTAG logic serializes the IEEE 1149.1 transactions, using a
variety of compression formats, to reduce the number of pins needed to implement a JTAG debug and
boundary scan port.
Table 7-149, Table 7-150 and Figure 7-97 assume testing over the recommended operating conditions
and electrical characteristic conditions below.
Table 7-149. Timing Requirements for IEEE 1149.7 cJTAG
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
CJ1
tc(TCK)
Cycle time, TCK
62.29
ns
CJ1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
24.92
ns
CJ1b
tw(TCKL)
Pulse duration, TCK low(40% of tc)
24.92
ns
CJ9a
tsu(TMSC-TCKre)
Input setup time, TMSC valid to TCK high (RE timing
selected)
12.46
ns
CJ10a
tsu(TMSC-TCKfe)
Input setup time, TMSC valid to TCK low (FE timing
selected)
12.46
ns
CJ9b
th(TCKre-TMSC)
Input hold time, TMSC valid from TCK high (RE timing
selected)
0.00
ns
CJ10b
th(TCKfe-TMSC)
Input hold time, TMSC valid from TCK low (FE timing
selected)
0.00
ns
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Table 7-150. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.7 cJTAG
MIN
MAX
UNIT
CJ11
NO.
td(TCKL-TMSCV)
PARAMETER
Delay time, TCK low to TMSC valid
DESCRIPTION
0
12.45
ns
CJ13
td(TCKH-TMSCZ)
Delay time, TCK high to TMSC HiZ
0
20.7
ns
CJ12
td(TMSCV-KPRV)
Delay time, TMSC valid to Keeper Valid
0
18
ns
CJ2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
29.14
ns
CJ1
CJ1b
CJ1a
jtag_tck
CJ9a
CJ10a
CJ9b
CJ10b
CJ11
CJ13
jtag_tms_tmsc(IN)
CJ2
jtag_tms_tmsc(OUT)
JTAG_03
Figure 7-97. cJTAG Interface Timing—Normal Mode
7.28.2 Trace Port Interface Unit (TPIU)
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in Table 7-152.
7.28.2.1 TPIU PLL DDR Mode
Table 7-151 and Figure 7-98 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 7-151. Switching Characteristics for TPIU
NO.
PARAMETER
DESCRIPTION
MIN
MAX
5.56
UNIT
TPIU1
tc(clk)
Cycle time, TRACECLK period
TPIU4
td(clk-ctlV)
Skew time, TRACECLK transition to TRACECTL
transition
-0.96
0.96
ns
ns
TPIU5
td(clk-dataV)
Skew time, TRACECLK transition to TRACEDATA[17:0]
-0.96
0.96
ns
TPIU1
TPIU2
TPIU3
TRACECLK
TPIU4
TPIU4
TRACECTL
TPIU5
TPIU5
TRACEDATA[X:0]
TPIU_01
Figure 7-98. TPIU—PLL DDR Transmit Mode(1)
(1) In d[X:0], X is equal to 15 or 17.
In Table 7-152 are presented the specific groupings of signals (IOSET) for use with TPIU signals.
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Table 7-152. TPIU IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
emu0
G21
0
G21
0
emu1
D24
0
D24
0
emu2
F10
2
F10
2
emu3
D7
2
D7
2
emu4
A7
2
A7
2
emu5
E1
5
G11
2
emu6
G2
5
E9
2
emu7
H7
5
F9
2
emu8
G1
5
F8
2
emu9
G6
5
E7
2
emu10
F2
5
D8
2
emu11
F3
5
A5
2
emu12
D1
5
C6
2
emu13
E2
5
C8
2
emu14
D2
5
C7
2
emu15
F4
5
A8
2
emu16
C1
5
C9
2
emu17
E4
5
A9
2
emu18
F5
5
B9
2
emu19
E6
5
A10
2
Timing Requirements and Switching Characteristics
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8 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test design implementation to confirm system functionality.
8.1
Introduction
This chapter is intended to communicate, guide and illustrate a PCB design strategy resulting in a PCB
that can support TI’s latest Application Processor. This Processor is a high-performance processor
designed for automotive Infotainment and Advanced Driver Assistance Systems based on enhanced
OMAP™ architecture integrated on a 28-nm CMOS process technology.
These guidelines first focus on designing a robust Power Delivery Network (PDN) which is essential to
achieve the desirable high performance processing available on Device. The general principles and stepby-step approach for implementing good power integrity (PI) with specific requirements will be described
for the key Device power domains.
TI strongly believes that simulating a PCB’s proposed PDN is required for first pass PCB design success.
Key Device processor high-current power domains need to be evaluated for Power Rail IR Drop,
Decoupling Capacitor Loop-Inductance and Power Rail Target Impedance. Only then can a PCB’s PDN
performance be truly accessed by comparing these model PI parameters vs. TI’s recommended values.
Ultimately for any high-volume product, TI recommends conducting a “Processor PDN Validation” test on
prototype PCBs across processor “split lots” to verify PDN robustness meets desired performance goals
for each customer’s worst-case scenario. Please contact your TI representative to receive guidance on
PDN PI modeling and validation testing.
Likewise, the methodology and requirements needed to route Device high-speed, differential interfaces
(i.e. USB2.0, USB3.0, HDMI, PCI, SATA), single-ended interfaces (i.e. DDR2/DDR3, QSPI) and general
purpose interfaces using LVCMOS drivers that meet timing requirements while minimizing signal integrity
(SI) distortions on the PCB’s signaling traces. Signal trace lengths and flight times are aligned with FR-4
standard specification for PCBs.
Several different PCB layout stack-up examples have been presented to illustrate a typical number of
layers, signal assignments and controlled impedance requirements. Different Device interface signals
demand more or less complexity for routing and controlled impedance stack-ups. Optimizing the PCB’s
PDN stack-up needs with all of these different types of signal interfaces will ultimately determine the final
layer count and layer assignments in each customer’s PCB design.
This guideline must be used as a supplement in complement to TI’s Application Processor, Power
Management IC (PMIC) and Audio Companion components along with other TI component technical
documentation (i.e. Technical Reference Manual, Data Manual, Data Sheets, Silicon Errata, Pin-Out
Spreadsheet, Application Notes, etc.).
NOTE
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or
statutory, including any implied warranty of merchantability of fitness for a specific purpose,
for customer boards. The data described in this appendix are intended as guidelines only.
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NOTE
These PCB guidelines are in a draft maturity and consequently, are subject to change
depending on design verification testing conducted during IC development and validation.
Note also that any references to Application Processor’s ballout or pin muxing are subject to
change following the processor’s ballout maturity.
8.1.1
Initial Requirements and Guidelines
Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to
be between 35 Ω and 65 Ω to minimize the overshoot or undershoot on far-end loads.
Characteristic impedance for differential interfaces must be routed as differential traces on the same layer.
The trace width and spacing must be chosen to yield the recommended differential impedance. For more
information see Section 8.5.1.
The PDN must be optimized for low trace resistance and low trace inductance for all high-current power
nets from PMIC to the device.
An external interface using a connector must be protected following the IEC61000-4-2 level 4 system
ESD.
8.2
Power Optimizations
This section describes the necessary steps for designing a robust Power Distribution Network (PDN):
• Section 8.2.1, Step 1: PCB Stack-up
• Section 8.2.2, Step 2: Physical Placement
• Section 8.2.3, Step 3: Static Analysis
• Section 8.2.4, Step 4: Frequency Analysis
8.2.1
Step 1: PCB Stack-up
The PCB stack-up (layer assignment) is an important factor in determining the optimal performance of the
power distribution system. An optimized PCB stack-up for higher power integrity performance can be
achieved by following these recommendations:
• Power and ground plane pairs must be closely coupled together. The capacitance formed between the
planes can decouple the power supply at high frequencies. Whenever possible, the power and ground
planes must be solid to provide continuous return path for return current.
• Use a thin dielectric between the power and ground plane pair. Capacitance is inversely proportional to
the separation of the plane pair. Minimizing the separation distance (the dielectric thickness)
maximizes the capacitance.
• Optimize the power and ground plane pair carrying high current supplies to key component power
domains as close as possible to the same surface where these components are placed (see Figure 81). This will help to minimize “loop inductance” encountered between supply decoupling capacitors and
component supply inputs and between power and ground plane pairs.
NOTE
1-2oz for planes per total thickness and layer count is preferred!
NOTE
PCB thermal spreading can help to reduce Processor junction temperatures and is more
effective when using heavier Cu weights on the outer Gnd plane layers.
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Capacitor
Trace
DIE
Package
Via
3
1
Power/Ground
2
Ground/Power
Note: 1. BGA via pair loop inductance
2. Power/Ground net spreading inductance
3. Capacitor trace inductance
Loop inductance
SPRABP6-001
Figure 8-1. Minimize Loop Inductance With Proper Layer Assignment
The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a
significant impact on the parasitic inductances of power current path as shown in Figure 8-1. For this
reason, it is recommended to consider layer order in the early stages of the PCB PDN design cycle,
putting high-priority supplies in the top half of the stackup (assuming high load and priority components
are mounted on the top-side of PCB) and low-priority supplies in the bottom half of the stackup as shown
in the examples below (vias have parasitic inductances which impact the bottom layers more, so it is
advised to put the sensitive and high-priority power supplies on the top/same layers).
Two PCB stack-ups with layer assignments and via types that can enable an optimize PDN are shown in
Figure 8-2 and Figure 8-3.
TOP/SIGNAL1
GROUND
POWER
SIGNAL2
SIGNAL3
POWER
GROUND
BOTTOM/SIGNAL4
SPRABP6-002
Figure 8-2. Layer PCB With High Density Interconnect (HDI) Vias
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TOP/SIGNAL1
POWER
GROUND
SIGNAL2
SIGNAL3
GROUND
POWER
BOTTOM/SIGNAL4
SPRABP6-003
Figure 8-3. Layer PCB With Plated Through Holes (PTH) Vias
8.2.2
Step 2: Physical Placement
A critical step in designing an optimized PDN is that proper care must be taken to making sure that the
initial floor planning of the PCB layout is done with good power integrity design guidelines in mind. The
following points are important for optimizing a PCB’s PDN:
• Minimizing the physical distance between power sources and key high load components is the first
step toward optimization. Placing source and load components on the same side of the PCB is
desirable. This will minimize via inductance impact for high current loads and steps
• External trace routing between components must be as wide as possible. The wider the traces, the
lower the DC resistance and consequently the lower the static IR drop.
• Whenever possible for the internal layers (routing and plane), wide traces and copper area fills are
preferred for PDN layout. The routing of power nets in plane provide for more interplane capacitance
and improved high frequency performance of the PDN.
• Whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling
capacitors, power inductors and current sensing resistors). Do not share vias among multiple
capacitors for connecting power supply and ground planes.
• Placement of vias must be as close as possible or even within a component’s solder pad if the PCB
technology you are using provides this capability.
Figure 8-4 shows an example of acceptable width for power net routing but with poor via placement.
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SWPS040-211
Figure 8-4. Poor Via Assignment for PDN
Figure 8-5 shows an improved power net routing with better via assignment and placement,
respectively.
SWPS040-212
•
352
Figure 8-5. Improved Via Assignment for PDN
To avoid any “ampacity” issue – maximum current-carrying capacity of each transitional via should be
evaluated to determine the appropriate number of vias required to connect components.
Figure 8-6 and Figure 8-7 show examples of “via starvation” on a power net transitioning from top
routing layer to internal layers and the improved layout, respectively. Adding vias to bring the “via-topad” ratio to 1:1 will improve PDN performance.
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SWPS040-213
One via for 5 capacitor pads is NOT good practice
Figure 8-6. Via Starvation
SWPS040-214
Added vias
•
Figure 8-7. Improved Layout With More Transitional Vias
For noise sensitive power supplies (i.e. Phase Lock-Loops, analog signals like audio and video), a Gnd
shield can be used to isolate coplanar supplies that may have high step currents or high frequency
switching transitions from coupling into low-noise supplies.
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vdd_mpu
vss
vdd
PCB_PO_8
Figure 8-8. Coplanar Shielding of Power Net Using Ground Guard-band
8.2.3
Step 3: Static Analysis
Delivering reliable power to circuits is always of critical importance because voltage drops (also known as
IR drops) can happen at every level within an electronic system, on-chip, within a package, and across the
board. Robust system performance can only be ensured by understanding how the system elements will
perform under typical stressful Use Cases. Therefore, it is a good practice to perform a Static or DC
Analysis.
Static or DC analysis and design methodology results in a PDN design that minimizes voltage or IR drops
across power and ground planes, traces and vias. This ensures the application processor’s internal
transistors will be operating within their specified voltage ranges for proper functionality. The amount of IR
drop that will be encounter is based upon amount power drawn for a desired Use Case and PCB trace
(widths, geometry and number of parallel traces) and via (size, type and number) characteristics.
Components that are distant from their power source are particularly susceptible to IR drop. Designs that
rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively
impact system performance. Early assessments a PDN’s static (DC) performance helps to determine
basic power distribution parameters such as best system input power point, optimal PCB layer stackup,
and copper area needed for load currents.
The resistance Rs of a plane conductor
for a unit length and unit width is called
the surface resistivity (ohms per square).
L
r
1
=
σ ×t t
l
R = Rs ×
w
Rs =
W
t
SWPS040-178
Figure 8-9. Depiction of Sheet Resistivity and Resistance
Ohm’s Law (V = I × R) relates conduction current to voltage drop. At DC, the relation coefficient is a
constant and represents the resistance of the conductor. Even current carrying conductors will dissipate
power at high currents even though their resistance may be very small. Both voltage drop and power
dissipation are proportional to the resistance of the conductor.
Figure 8-10 shows a PCB-level static IR drop budget defined between the power management device
(PMIC) pins and the application processor’s balls when the PMIC is supplying power.
• It is highly recommended to physically place the PMIC as close as possible to the processor and on
the same side. The orientation of the PMIC vs. processor should be aligned to minimize distance for
the highest current rail.
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PCB
Static IR drop and Effective Resistance
Load
Component
Source
Component
BGA pad on PCB
PCB_PO_10
Figure 8-10. Static IR Drop Budget for PCB Only
The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR
or DC analysis/design methodology consists of designing the PDN such that the voltage drop (under DC
operating conditions) across power and ground pads of the transistors of the application processor device
is within a specified value of the nominal voltage for proper functionality of the device.
A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal
voltage. For a 1.35-V supply, this would be ≤20 mV.
To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and
simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration
violations of current-carrying vias, and “Swiss-cheese” effects via placement has on power rails. It is
recommended to perform the following analyses:
• Lumped resistance/IR drop analysis
• Distributed resistance/IR drop analysis
NOTE
The PMIC companion device supporting Processor has been designed with voltage sensing
feedback loop capabilities that enable a remote sense of the SMPS output voltage at the
point of use.
The NOTE above means the SMPS feedback signals and returns must be routed across PCB and
connected to the Device input power ball for which a particular SMPS is supplying power. This feedback
loop provides compensation for some of the voltage drop encountered across the PDN within limits. As
such, the effective resistance of the PDN within this loop should be determined in order to optimize
voltage compensation loop performance. The resistance of two PDN segments are of interest: one from
the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the
entire PDN route from SMPS output pin/ball to the Processor input power.
In the following sections each methodology is described in detail and an example has been provided of
analysis flow that can be used by the PCB designer to validate compliance to the requirements on their
PCB PDN design.
8.2.3.1
PDN Resistance and IR Drop
Lumped methodology consists of grouping all of the power pins on both the PMIC (voltage source) and
processor (current sink) devices. Then the PMIC source is set to an expected Use Case voltage level and
the processor load has its Use Case current sink value set as well. Now the lumped/effective resistance
for the power rail trace/plane routes can be determine based upon the actual layout’s power rail etch wide,
shape, length, via count and placement Figure 8-11 illustrates the pin-grouping/lumped concept.
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The lumped methodology consists of importing the PCB layout database (from Cadence Allegro tool or
any other layout design tool) into the static IR drop modeling and simulation tool of preference for the PCB
designer. This is followed by applying the correct PCB stack-up information (thickness, material
properties) of the PCB dielectric and metallization layers. The material properties of dielectric consist of
permittivity (Dk) and loss tangent (Df).
For the conductor layers, the correct conductivity needs to be programmed into the simulation tool. This is
followed by pin-grouping of the power and ground nets, and applying appropriate voltage/current sources.
The current and voltage information can be obtained from the power and voltage specifications of the
device under different operating conditions / Use Cases.
Sources
Multiport net
Sources
Branch
Grouped Power/Ground
pins to create 1 equivalent
resistive branch
Port/Pin
Sinks
Sinks
SWPS040-179
Figure 8-11. Pin-grouping concept: Lumped and Distributed Methodologies
8.2.4
Step 4: Frequency Analysis
Delivering low noise voltage sources are very important to allowing a system to operate at the lowest
possible Operational Performance Point (OPP) for any one Use Case. An OPP is a combination of the
supply voltage level and clocking rate for key internal processor domains. A SCH and PCB designed to
provide low noise voltage supplies will then enable the processor to enter optimal OPPs for each Use
Case that in turn will minimize power dissipation and junction temperatures on-die. Therefore, it is a good
engineering practice to perform a Frequency Analysis over the key power domains.
Frequency analysis and design methodology results in a PDN design that minimizes transient noise
voltages at the processor’s input power balls. This allows the processor’s internal transistors to operate
near the minimum specified operating supply voltage levels. To accomplish this one must evaluate how a
voltage supply will change due to impedance variations over frequency. This analysis will focus on the
decoupling capacitor network (VDD_xxx and VSS/Gnd rails) at the load. Sufficient capacitance with a
distribution of self-resonant points will provide for an overall lower impedance vs frequency response for
each power domain.
Decoupling components that are distant from their load’s input power are susceptible to encountering
spreading loop inductance from the PCB design. Early analysis of each key power domain’s frequency
response helps to determine basic decoupling capacitor placement, optimal footprint, layer assignment,
and types needed for minimizing supply voltage noise/fluctuations due to switching and load current
transients.
NOTE
Evaluation of loop inductance values for decoupling capacitors placed ~300mils closer to the
load’s input power balls has shown an 18% reduction in loop inductance due to reduced
distance.
•
356
Decoupling capacitors must be carefully placed in order to minimize loop inductance impact on supply
voltage transients. A real capacitor has characteristics not only of capacitance but also inductance and
resistance.
Figure 8-12 shows the parasitic model of a real capacitor. A real capacitor must be treated as an RLC
circuit with effective series resistance (ESR) and effective series inductance (ESL).
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C
ESL
ESR
SWPS040-175
Figure 8-12. Characteristics of a Real Capacitor With ESL and ESR
The magnitude of the impedance of this series model is given as:
Z =
1 ö
æ
ESR 2 +ωESL
ç ωESL - ωC ÷
ø
è
2
where : w = 2π¦
SWPS040-e002
Figure 8-13. Series Model Impedance Equation
Figure 8-14 shows the resonant frequency response of a typical capacitor with a self-resonant frequency
of 55 MHz. The impedance of the capacitor is a combination of its series resistance and reactive
capacitance and inductance as shown in the equation above.
S-Parameter Magnitude
Job: GCM155R71E153KA55_15NF;
1.0e+01
1.0e+00
1.0e–01
1.0e–02
XC=1/ωC
XL=ωL
1.0e–03
Resonant frequency
(55 MHz) (minimum)
1.0e–04
1.00e–002
1.00e+000
1.00e+002
1.00e+004
1.00e+006
1.00e+008
Frequency (MHz)
SWPS040-176
Figure 8-14. Typical Impedance Profile of a Capacitor
Because a capacitor has series inductance and resistance that impacts its effectiveness, it is important
that the following recommendations are adopted in placing capacitors on the PDN.
Wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and
resistance. This was shown earlier in Figure 8-1. The capacitor mounting inductance and resistance
values include the inductance and resistance of the pads, trace, and vias. Whenever possible, use
footprints that have the lowest inductance configuration as shown in Figure 8-15
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The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance
of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize
distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing.
Further improvements can be made to the mounting by placing vias to the side of capacitor lands or
doubling the number of vias as shown in Figure 8-15. If the PCB manufacturing processes allow it and if
cost-effective, via-in-pad (VIP) geometries are strongly recommended.
In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the
effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the
capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on
the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z
is due to PCB thickness (as shown in Figure 8-2).
From left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in Figure 815 are known as:
• 2-via, Skinny End Exit (2vSEE)
• 2-via, Wide End Exit (2vWEE)
• 2-via, Wide Side Exit (2vWSE)
• 4-via, Wide Side Exit (4vWSE)
• 2-via, In-Pad (2vIP)
Via
Via-in-pad
Pad
Trace
Mounting geometry for reduced inductance
SWPS040-177
Figure 8-15. Capacitor Placement Geometry for Improved Mounting Inductance
NOTE
Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case)
vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was
used in place of 2vSEE.
Decoupling Capacitor (Dcap) Strategy:
1. Use lowest inductance footprint and trace connection scheme possible for given PCB technology and
layout area in order to minimize Dcap loop inductance to power pin as much as possible (see Figure 815).
2. Place Dcaps on “same-side” as component within their power plane outline to minimize “decoupling
loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB
layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify
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minimum inductance for top vs bottom-side placement.
3. Place Dcaps on “opposite-side” as component within their power plane outline if “same-side” is not
feasible or if distance to power pin is greater than ~500mils for top-side location. Use PI modeling CAD
tool to verify minimum inductance for top vs bottom-side placement.
4. Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component
power pins, etc.).
5. Place all voltage and gnd plane vias “as close as possible” to point of use (i.e. Dcap pads, component
power pins, etc.).
6. Use a “Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small
number of vias within restricted PCB areas (i.e. underneath BGA components).
Frequency analysis for the MPU power domain has yielded the vdd_mpu Impedance vs Frequency
response shown in Section 8.3.7.2, vdd_mpu Example Analysis. As the example shows the overall MPU
PDN Reff meets the maximum recommended PDN resistance of 10mΩ.
8.2.5
System ESD Generic Guidelines
8.2.5.1
System ESD Generic PCB Guideline
Protection devices must be placed close to the ESD source which means close to the connector. This
allows the device to subtract the energy associated with an ESD strike before it reaches the internal
circuitry of the application board.
To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero
turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the lowresistive, low-inductive path from the signal to the ground is granted and not increasing the impedance
between signal and ground.
For ESD protection array being railed to a power supply when no decoupling capacitor is available in close
vicinity, consider using a decoupling capacitor (≥ 0.1 µF) tight to the VCC pin of the ESD protection. A
positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse.
Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and
GND in Figure 8-16) from connector to external protection because the interconnect may see between 15A to 30-A current in a short period of time during the ESD event.
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Bypass
capacitor
0.1 mf
(minimum)
Stub
inductance
Connector
Stub
inductance
Interconnection
inductance
vcc
Signal
VCC
VCC
Protected
circuit
Stub
inductance
Minimize such
inductance by
optimizing layout
ESD
strike
External
protection
Ground
inductance
Keep distance
between protected
circuit and external
protection
Signal
Keep external
protection closed by
connector
SPRABP6-004
Figure 8-16. Placement Recommendation for an ESD External Protection
NOTE
To ensure normal behavior of the ESD protection (unwanted leakage), it is better to ground
the ESD protection to the board ground rather than any local ground (example isolated shield
or audio ground).
8.2.5.2
•
•
•
•
•
•
•
•
360
Miscellaneous EMC Guidelines to Mitigate ESD Immunity
Avoid running critical signal traces (clocks, resets, interrupts, control signals, and so forth) near PCB
edges.
Add high frequency filtering: Decoupling capacitors close to the receivers rather than close to the
drivers to minimize ESD coupling.
Put a ground (guard) ring around the entire periphery of the PCB to act as a lightning rod.
Connect the guard ring to the PCB ground plane to provide a low impedance path for ESD-coupled
current on the ring.
Fill unused portions of the PCB with ground plane.
Minimize circuit loops between power and ground by using multilayer PCB with dedicated power and
ground planes.
Shield long line length (strip lines) to minimize radiated ESD.
Avoid running traces over split ground planes. It is better to use a bridge connecting the two planes in
one area.
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BAD
BETTER
SWPS040-220
•
8.2.6
Figure 8-17. Trace Examples
Always route signal traces and their associated ground returns as close to one another as possible to
minimize the loop area enclosed by current flow:
– At high frequencies current follows the path of least inductance.
– At low frequencies current flows through the path of least resistance.
EMI / EMC Issues Prevention
All high-speed digital integrated circuits can be sources of unwanted radiation, which can affect nearby
sensitive circuitry and cause the final product to have radiated emissions levels above the limits allowed
by the EMC regulations if some preventative steps are not taken.
Likewise, analog and digital circuits can be susceptible to interference from the outside world and picked
up by the circuitry interconnections.
To minimize the potential for EMI/EMC issues, the following guidelines are recommended to be followed.
8.2.6.1
Signal Bandwidth
To evaluate the frequency of a digital signal, an estimated rule of thumb is to consider its bandwidth fBW
with respect to its rise time, tR:
fBW ≈ 0.35 / tR
This frequency actually corresponds to the break point in the signal spectrum, where the harmonics start
to decay at 40 dB per decade instead of 20 dB per decade.
8.2.6.2
Signal Routing
8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
Keep radio frequency (RF) sensitive circuitry (like GPS receivers, GSM/WCDMA, Bluetooth/WLAN
transceivers, frequency modulation (FM) radio) away from high-speed ICs (the device, power and audio
manager, chargers, memories, and so forth) and ideally on the opposite side of the PCB. For improved
protection it is recommended to place these emission sources in a shield can. If the shield can have a
removable lid (two-piece shield), ensure there is low contact impedance between the fence and the lid.
Leave some space between the lid and the components under it to limit the high-frequency currents
induced in the lid. Limit the shield size to put any potential shield resonances above the frequencies of
interest; see Figure 8-14, Typical Impedance Profile of a Capacitor.
8.2.6.2.2 Signal Routing—Outer Layer Routing
In case there is a need to use the outer layers for routing outside of shielded areas, it is recommended to
route only static signals and ensure that these static signals do not carry any high-frequency components
(due to parasitic coupling with other signals). In case of long traces, make provision for a bypass capacitor
near the signal source.
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Routing of high-frequency clock signals on outer layers, even for a short distance, is discouraged,
because their emissions energy is concentrated at the discrete harmonics and can become significant
even with poor radiators.
Coplanar shielding of traces on outer layers (placing ground near the sides of a track along its length) is
effective only if the distance between the trace sides and the ground is smaller that the trace height above
the ground reference plane. For modern multilayer PCBs this is often not possible, so coplanar shielding
will not be effective. Do not route high-frequency traces near the periphery of the PCB, as the lack of a
ground reference near the trace edges can increase EMI: see Section 8.2.6.3, Ground Guidelines.
8.2.6.3
Ground Guidelines
8.2.6.3.1 PCB Outer Layers
Ideally the areas on the top and bottom layers of the PCB that are not enclosed by a shield should be
filled with ground after the routing is completed and connected with an adequate number of vias to the
ground on the inner ground planes.
8.2.6.3.2 Metallic Frames
Ensure that all metallic parts are well connected to the PCB ground (like LCD screens metallic frames,
antennas reference planes, connector cages, flex cables grounds, and so forth). If using flex PCB ribbon
cables to bring high-frequency signals off the PCB, ensure they are adequately shielded (coaxial cables or
flex ribbons with a solid reference ground).
8.2.6.3.3 Connectors
For high-frequency signals going to connectors choose a fully shielded connector, if possible (for example,
SD card connectors). For signals going to external connectors or which are routed over long distances, it
is recommended to reduce their bandwidth by using low-pass filters (resistor, capacitor (RC) combinations
or lossy ferrite inductors). These filters will help to prevent emissions from the board and can also improve
the immunity from external disturbances.
8.2.6.3.4 Guard Ring on PCB Edges
The major advantage of a multilayer PCB with ground-plane is the ground return path below each and
every signal or power trace.
As shown in Figure 8-18 the field lines of the signal return to PCB ground as long as an infinite ground is
available.
Traces near the PCB-edges do not have this infinite ground and therefore may radiate more than the
others. Thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in
the vicinity of PCB edges, or, if not avoidable, must be accompanied by a guard ring on the PCB edge.
SWPS040-199
Figure 8-18. Field Lines of a Signal Above Ground
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Signal
Power
Ground
Signal
SWPS040-200
Figure 8-19. Guard Ring Routing
The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB
edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on
the borders of all layers (including power layer) must be applied as shown in Figure 8-19.
As these traces must have the same (HF–) potential as the ground plane they must be connected to the
ground plane at least every 10 mm.
8.2.6.3.5 Analog and Digital Ground
For the optimum solution, the AGND and the DGND planes must be connected together at the power
supply source in a same point. This ensures that both planes are at the same potential, while the transfer
of noise from the digital to the analog domain is minimized.
8.3
Core Power Domains
This section provides boundary conditions and theoretical background to be applied as a guide for
optimizing a PCB design. The decoupling capacitor and PDN characteristics tables shown below give
recommended capacitors and PCB parameters to be followed for schematic and PCB designs. Board
designs that meet the static and dynamic PDN characteristics shown in tables below will be aligned to the
expected PDN performance needed to optimize SoC performance.
8.3.1
General Constraints and Theory
•
•
•
•
•
•
•
Max PCB static/DC voltage drop (IRd) budget of 1.5% of supply voltage when using PMICs without
remote sensing as measured from PMIC’s power inductor and filter capacitor node to Processor input
including any ground return losses.
Max PCB static/DC voltage drop (IRd) budget can be relaxed to 5% of supply voltage when using
PMICs with remote sensing at the load as measured from PMIC’s power inductor and filter capacitor
node to Device’s supply input including any ground return losses.
PMIC component DM and guidelines should be referenced for the following:
– Routing remote feedback sensing to optimize per each SMPS’s implementation
– Selecting power filtering capacitor values and PCB placement.
Max Effective Resistance (Reff) budget can range from 4 – 50mΩ for key Device power rails not
including ground returns depending upon maximum load currents and maximum DC voltage drop
budget (as discussed above).
Max Device supply input voltage difference budget of 5mV under max current loading shall be
maintained across all balls connected to a common power rail. This represents any voltage difference
that may exist between a remote sense point to any power input.
Max PCB Loop Inductance (LL) budget between Device’s power inputs and local bulk and high
frequency decoupling capacitors including ground returns should range from 0.4 – 2.5nH depending
upon maximum transient load currents.
Max PCB dynamic/AC peak-to-peak transient noise voltage budgets between PMIC and Device
including ground returns are as follows:
– +/-3% of nominal supply voltage for frequencies below the PMIC bandwidth (typ Fpmic ~
200kHz)
– +/-5% of nominal supply voltage for frequencies between Fpmic to Fpcb (typ 20 – 100MHz)
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Max PCB Impedance (Z) vs Frequency (F) budget between Device’s power inputs and PMIC’s output
power filter node including ground return is determined by applying the Frequency Domain Target
Impedance Method to determine the PCB’s maximum frequency of interest (Fpcb). Ideally a properly
designed and decoupled PDN will exhibit smoothly increasing Z vs. F curve. There are 2 general
regions of interest as can be seen in Figure 8-20.
– 1st area is from DC (0Hz) up to Fpmic (typ a few 100 kHz) where a PMIC’s transient response
characteristic (i.e. Switching Freq, Compensation Loop BW) dominate. A PDN’s Z is typically very
low due to power filtering & bulk capacitor values when PDN has very low trace resistance (i.e.
good Reff performance). The goal is to maintain a smoothly increasing Z that is less than Zt1 over
this low frequency range. This will ensure that a max transient current event will not cause a
voltage drop more than the PMIC’s current step response can support (typ 3%).
– 2nd area is from Fpmic up to Fpcb (typ 20-100MHz) where a PCB’s inherent characteristics (i.e.
parasitic capacitance, planar spreading inductances) dominate. A PDN’s Z will naturally increase
with frequency. At frequencies between Fpmic up to Fpcb, the goal is to maintain a smoothly
increasing Z to be less than Zt2. This will ensue that the high frequency content of a max transient
current event will not cause a voltage drop to be more than 5% of the min supply voltage.
Figure 8-20. PDN’s Target impedance
1.Voltage Rail Drop includes regulation accuracy, voltage distribution drops, and all dynamic events
such as transient noise, AC ripple, voltage dips etc.
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2.Typical max transient current is defined as 50% of max current draw possible.
8.3.2
Voltage Decoupling
Recommended power supply decoupling capacitors main characteristics for commercial products whose
ambient temperature is not to exceed +85C are shown in table below:
Table 8-1. Commercial Applications Recommended Decoupling Capacitors Characteristics(1)(2)(3)
Value
Voltage
[V]
Package
Stability
Dielectric
Capacitan
ce
Tolerance
Temp
Range [°C]
Temp
Sensitivity
[%]
REFERENCE
22µF
6,3
0603
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM188R60J226MEA0L
10µF
4,0
0402
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM155R60G106ME44
4.7µF
6,3
0402
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM155R60J475ME95
2.2µF
6,3
0402
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM155R60J225ME95
1µF
6,3
0201
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM033R60J105MEA2
470nF
6,3
0201
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM033R60G474ME90
220nF
6,3
0201
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM033R60J224ME90
100nF
6,3
0201
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM033R60J104ME19
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
(3) In comparison with the EIA Class 1 dielectrics, Class 2 dielectric capacitors tend to have severe temperature drift, high dependence of
capacitance on applied voltage, high voltage coefficient of dissipation factor, high frequency coefficient of dissipation, and problems with
aging due to gradual change of crystal structure. Aging causes gradual exponential loss of capacitance and decrease of dissipation
factor.
Recommended power supply decoupling capacitors main characteristics for automotive products are
shown in table below:
Table 8-2. Automotive Applications Recommended Decoupling Capacitors Characteristics
(1)(2)
Value
Voltage
[V]
Package
Stability
Dielectric
Capacitan
ce
Tolerance
Temp
Range [°C]
Temp
Sensitivity
[%]
REFERENCE
22µF
6,3
1206
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM31CR70J226ME23
10µF
6,3
0805
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM21BR70J106ME22
4.7µF
10
0805
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM21BC71A475MA73
2.2µF
6,3
0603
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM188R70J225ME22
1µF
16
0603
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM188R71C105MA64
470nF
16
0603
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM188R71C474MA55
220nF
25
0603
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM188L81C224MA37
100nF
16
0402
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM155R71C104MA55
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
8.3.3
Static PDN Analysis
One power net parameter derived from a PCB’s PDN static analysis is the Effective Resistance (Reff).
This is the total PCB power net routing resistance that is the sum of all the individual power net segments
used to deliver a supply voltage to the point of load and includes any series resistive elements (i.e. current
sensing resistor) that may be installed between the PMIC outputs and Processor inputs.
8.3.4
Dynamic PDN Analysis
Three power net parameters derived from a PCB’s PDN dynamic analysis are the Loop Inductance (LL),
Impedance (Z) and PCB Frequency of Interest (Fpcb).
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•
•
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LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s
power supply and ground reference terminals when viewed from the decoupling capacitor with a
“theoretical shorted” applied across the Processor’s supply inputs to ground reference.
Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max
transient current events.
Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar
spreading and internal package inductances.
Table 8-3. Recommended PDN and Decoupling Characteristics
PDN Analysis:
Static
Supply
Max Reff
(7)
[mΩ]
Dynamic
(1)(2)(3)(4)(5)
Number of Recommended Decoupling Capacitors per
Supply
Dec. Cap.
Max LL(8) (6)
[nH]
Impedance
[mΩ]
Frequency
of Interest
[MHz]
100
nF(6)
220
nF
470
nF
1μF
2.2 μF 4.7 μF 10 μF
22 μF
vdd_mpu
10
2
57
20
12
2
2
3
1
1
vdd_dspeve
13
2.5
54
20
8
1
1
2
1
1
vdd
27
2
87
50
6
1
1
1
1
1
vdd_gpu
18
2.5
207
50
6
1
1
1
1
1
vdd_iva
48
2
800
100
5
vdds_ddr1
10
2.5
200
100
8
4
2
2
1
vdds_ddr2
10
2.5
200
100
8
4
2
2
1
cap_vbbldo_dsp
eve
N/A
6
N/A
N/A
cap_vbbldo_gpu
N/A
6
N/A
N/A
cap_vbbldo_iva
N/A
6
N/A
N/A
cap_vbbldo_mpu
N/A
6
N/A
N/A
cap_vddram_cor
e1
N/A
6
N/A
N/A
cap_vddram_cor
e2
N/A
6
N/A
N/A
cap_vddram_cor
e3
N/A
6
N/A
N/A
cap_vddram_cor
e4
N/A
6
N/A
N/A
cap_vddram_cor
e5
N/A
6
N/A
N/A
cap_vddram_dsp
eve1
N/A
6
N/A
N/A
cap_vddram_dsp
eve2
N/A
6
N/A
N/A
cap_vddram_gpu
N/A
6
N/A
N/A
cap_vddram_iva
N/A
6
N/A
N/A
cap_vddram_mp
u1
N/A
6
N/A
N/A
cap_vddram_mp
u2
N/A
6
N/A
N/A
1
1
1
1
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Specifications chapter.
(2) ESL must be as low as possible and must not exceed 0.5 nH.
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)
based on the Recommended Operating Conditions table of the Specifications chapter.
(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor
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power balls.
(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.
(6) High-frequency (30 to 70MHz) PCB decoupling capacitors
(7) Maximum Reff from SMPS to Processor.
(8) Maximum Loop Inductance for decoupling capacitor.
NOTE
For power IC which can support more than 10µF close to processor, a bulk capacitor of at
least 22µF is strongly recommended for VDD_MPU power domains.
8.3.5
Power Supply Mapping
TPS65917 or TPS659039 are the Power Management ICs (PMICs) that should be used for the Device
designs. TI requires use of these PMICs for the following reasons:
• TI has validated their use with the Device
• Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
• Support for power sequencing requirements (refer to Section 5.9 Power Supply Sequences)
• Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the
most stringent of the rails combined should be implemented for the particular supply rail.
It is possible that some voltage domains on the device are unused in some systems. In such cases, to
ensure device reliability, it is still required that the supply pins for the specific voltage domains are
connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,
thereby having a single power supply driving the combined CORE, IVA and GPU domains.
For the combined rail, the following relaxations do apply:
• The AVS voltage of active rail in the combined rail needs to be used to set the power supply
• The decoupling capacitance should be set according to the active rail in the combined rail
Table 8-4 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS659039 PMIC.
Table 8-4. TPS659039 Power Supply Connections(1)
SMPS
Valid Combination
1:
Reference Platform
Valid Combination
2:
MPU Centric
Valid Combination
3:
DSPEVE Centric(3)
Valid Combination
4: IVA Centric
TPS659039 Current
Rating Limitation (4)
vdd_mpu
vdd_mpu
vdd_mpu, vdd_gpu,
vdd_iva
vdd_mpu
SMPS12: 6A
SMPS123: 9A
SMPS3(2)
Free (DDR Memory)
Free (DDR Memory)
Free (DDR Memory)
Free (DDR Memory)
SMPS3: 3A
SMPS4/5
vdd_dspeve
vdd_dspeve,
vdd_gpu, vdd_iva
vdd_dspeve
vdd_dspeve,
vdd_gpu
SMPS45: 4A
SMPS6
vdd_gpu
vdd
vdd
vdd
SMPS6: 2-3A
(BOOST_CURRENT
=0/1)
SMPS7
vdd
Free
Free
Free
2A
SMPS8
vdd_iva
Free
Free
vdd_iva
1A
SMPS9
vdds18v
vdds18v
vdds18v
vdds18v
1A
(2)
SMPS1/2/3
(5)
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(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and
peak) is within the limits of the PMIC for all rails of the device
(2) Dual phase (SMPS1/2) can be used as long as the peak power consumption is maintained below the SMPS1/2 capacity
(a) For the latest rated output current specifications for the TPS659039 device, please refer to the PMIC data manual.
(b) MPU power consumption is highly system dependent. A detailed power consumption estimate must be performed to confirm
compatibility. Example: Single vs Dual MPU, OPP_NOM vs OPP_OD vs OPP_HIGH, TPS659039 configured with VI≥3V vs VI<3V,
etc. Contact your TI representative for details.
(3) Combination 3 must only be used in systems where the MPU frequency is 1 GHz or lower. If greater than 1 GHz MPU is required, then
the vdd_mpu domain must be powered independently.
(4) Refer to the PMIC data manual for the latest TPS659039 specifications
(5) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power
dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj
Table 8-5 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS65917 PMIC.
Table 8-5. TPS65917 Power Supply Connections
TPS65917
Valid Combination 1:
Valid Combination 2
TPS65917
Current Rating Limitation (1) (3)
SMPS1
vdd_mpu
vdd_mpu
SMPS1: 3.5A ≤ OPP_NOM (dual
or single) OR ≤ OPP_OD (single
ONLY)
3.5A
SMPS2
(2)
vdd_dspeve, vdd_gpu, vdd_iva
vdd
SMPS3
(2)
vdd
vdd_dspeve, vdd_gpu, vdd_iva
3A
SMPS4
(3)
vdds18v
vdds18v
1.5A
SMPS5
(4)
Free (DDR Memory)
Free (DDR Memory)
2A
(1) Refer to the TPS65917 Data Manual for exact current rating limitations, including assumed VIN and other parameters. Values provided in
this table are for comparison purposes.
(2) DSP, EVE, GPU, and IVAHD power consumption is highly application-specific. Separate analysis must be performed to ensure output
current ratings (average and peak) is within the limits of the PMIC. VDD only supports OPP_NOM.
(3) Highly application-specific. Separate analysis must be performed to ensure average and peak power is within the limits of the PMIC.
(4) Furthermore, if SMPS5 is used for DDR power, both total memory + SoC power must be within the PMIC limits.
8.3.6
DPLL Voltage Requirement
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage
inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The
TPS65917 and TPS659039 PMIC LDOLN outputs are specifically designed to meet this low noise
requirement.
NOTE
For more information about Input Voltage Sources, see Section 6.2 DPLLs, DLLs
Specifications.
Table 8-4 presents the voltage inputs that supply the DPLLs.
Table 8-6. Input Voltage Power Supplies for the DPLLs
368
POWER SUPPLY
DPLLs
vdda_abe_per
DPLL_PER, DPLL_ABE and PER HSDIVIDER analog power supply
vdda_ddr
DPLL_DDR and DDR HSDIVIDER analog power supply
vdda_debug
DPLL_DEBUG analog power supply
vdda_dsp_eve
DPLL_DSP and DPLL_EVE analog power supply
vdda_gmac_core
DPLL_CORE and HSDIVIDER analog power supply
vdda_gpu
DPLL_GPU analog power supply
vdda_iva
DPLL_IVA analog power supply
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Table 8-6. Input Voltage Power Supplies for the DPLLs (continued)
8.3.7
POWER SUPPLY
DPLLs
vdda_video
DPLL_VIDEO1 and DPLL_VIDEO2 analog power supply
vdda_mpu
DPLL_MPU analog power supply
vdda_osc
not DPLL input but is required to be supplied by low noise input voltage
Example PCB Design
The following sections describe an example PCB design and its resulting PDN performance for the
vdd_mpu key processor power domain.
8.3.7.1
Example Stack-up
Layer Assignments:
• Layer Top: Signal and Segmented Power Plane
– Processor and PMIC components placed on Top-side
• Layer 2: Gnd Plane1
• Layer 3: Signals
• Layer n: Power Plane1
• Layer n+1: Power Plane 2
• Layer n+2: Signal
• Layer n+3: Gnd Plane2
• Layer Bottom: Signal and Segmented Power Planes
– Decoupling caps, etc.
Via Technology: Through-hole
Copper Weight:
• ½ oz for all signal and plane layers other thanGnd Plane1 and Gnd Plane2 set to 2oz for improved
thermal heat spreading
• Total PCB Thickness 0.080inches
8.3.7.2
vdd_mpu Example Analysis
Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not
exceed 10mΩ.
Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and
decoupling capacitances should not exceed 2.0nH (ESL NOT included)
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS
output power balls should not exceed 57mΩ at 20MHz.
Table 8-7. Example PCB vdd_mpu PI Analysis Summary
Parameter
Recommendation
Processor OPP
High
Clocking Rate
1.5 GHz
Example PCB
Voltage Level
1.22V
1.22V
Max Current Draw
5.12 A
5.12 A
Max Effective Resistance: Power
Inductor Segment Total Reff
10mΩ
9.0mΩ
Max Loop Inductance
2.0nH
1.0 – 1.4nH
Impedance Target
57mΩ F<20Mhz
57mΩ F<20Mhz
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Figure 8-21, Figure 8-22, Figure 8-23, and Figure 8-24 show a PCB layout example and the resulting PI
analysis results.
U45
PMIC
SMPS (3000mA)
SW1
SMPS1_SW
L17
1.0uH, 4.5A, 1616
IHLP-1616ABER1R0M11
PCB – Top-side
C410
22uF, 4V, 0603
GRM188R60G226MEA0L
PCB – Bottom-side
(E11, E12, E13)
SMPS2 (3000mA)
SMPS1_SW
SW2
U52
R181
0.001ohm, 1%, 4W, 2725
CSS2725FT1L00
PCB – Top-side
6A
C365, 366, 368, 369,
370, 384, 385, 387,
389, 391, 392, 396
0.1uF, 6.3V, X5R, 0201
GRM033R60J104KE19D
PCB – Bottom-side
C378
22uF, 4V, 0603
GRM188R60G226MEA0L
PCB – Bottom-side
SMPS3 (3000mA)
SW3
Device SoC
vdd_mpu
vdd_mpu
(N18, K18, L19
L15
1.0uH, 4.5A, 1616
IHLP-1616ABER1R0M11
PCB – Top-side
(E11, E12, E13)
SMPS1_SW
SMPS_1_2_3
N17, M17, L17
M18, L18, P18
K17, L15, L16
M15, M16, P17
R18)
C92, 96
0.22uF, 6.3V, X5R,
0201
ECJ-ZEB0J224M
PCB – Top-side
L13x
1.0uH, 4.5A, 1616
IHLP-1616ABER1R0M11
PCB – Top-side
C93, 94
(E11, E12, E13)
0.47uF, 4V, X5R,
0201
AMK063BJ474MP-F
PCB – Top-side
C350
22uF, 4V, 0603
GRM188R60G226MEA0L
PCB – Bottom-side
C91, 95, 367
PS_EVM_3V3
1.0uF, 6.3V, X5R, 0201
GRM033R60J105MEA2D
PCB – 2 Top-side & 1 Bottom
U39
INA226
A0
VIN+
C359
A1
VIN-
2.2uF, 6.3V, X5R,
0402
C1005X5R0J225M
PCB – Bottom-side
PM I2C Addr: 100 0001
C360
4.7uF, 6.3V, X5R,
0402
GRM155R60J475ME8
7D
PCB – Bottom-side
C356
22uF, 4V, X5R, 0603
GRM188R60G226ME
A0L
PCB – Bottom-side
Figure 8-21. vdd_mpu Simplified SCH Diagram
Sense Resistor (R181; 2725)
PMIC (U45)
Device (U52)
Power Inductors (L13, 15 & 17; 1616)
vdd_mpu
“Ball-Field”
Top -side segmented planes
(vdd_mpu = Green)
4 of 22 Decoupling Caps
(C96, 385, 387, 389; 0201)
Multiple vias connecting power
segments on different layers
Figure 8-22. vdd_mpu routing [Top Layer]
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Interior Power Plane #2, Layer 9 of 16
(vdd_mpu = Green)
Figure 8-23. vdd_mpu routing [Internal Power Plane #2]
Bulk Caps underneath
power inductors
(C410, C378, C350; 0603)
Larger Value Decoupling Caps
(2.2uF C359, 4.7uF C360 & 22uF C356;
0402 & 0603)
Remaining 15 of 22 Decoupling Caps
(C96, 385, 387, 389; 0201)
PCB_CPD_4
Figure 8-24. vdd_mpu routing and cap placements [Bottom Layer]
Table 8-8. PCB Etch Resistance Breakdown - From PMIC Source to Device Load
Net[from]
Component [from]:
Net[to]
Component [to]:
Etch Resistance (Ω)
% of Total Etch
Resistance
SW1
L17
SW1
U45
0,001038
13%
SW2
L15
SW2
U45
0,000898
12%
SW3
L13
SW3
U45
0,000861
11%
SW1
L17
SMPS_1_2_3
R181
0,000696
9%
SW2
L15
SMPS_1_2_3
R181
0,000541
7%
SW3
L13
SMPS_1_2_3
R181
0,000526
7%
vdd_mpu
R181
vdd_mpu
U52
0,006311
78%
vdd_mpu
R181
vdd_mpu
U52
0,006311
81%
vdd_mpu
R181
vdd_mpu
U52
0,006311
82%
Total Etch Resistance from SW1 =
0,008045
100%
Total Etch Resistance from SW2 =
0,00775
100%
Total Etch Resistance from SW3 =
0,007698
100%
Max Value =
0,008045
Table 8-9. PCB Etch Resistance Breakdown - From Power Inductor to Device Load
Net[from]
Component [from]:
Net[to]
Component [to]:
Etch Resistance (Ω)
% of Total Etch
Resistance
SMPS_1_2_3
L17
SMPS_1_2_3
R181
0,000696
10%
SMPS_1_2_3
L15
SMPS_1_2_3
R181
0,000541
8%
SMPS_1_2_3
L13
SMPS_1_2_3
R181
0,000526
8%
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Table 8-9. PCB Etch Resistance Breakdown - From Power Inductor to Device Load (continued)
Net[from]
Component [from]:
Net[to]
Component [to]:
Etch Resistance (Ω)
% of Total Etch
Resistance
vdd_mpu
R181
vdd_mpu
U52
0,006311
90%
vdd_mpu
R181
vdd_mpu
U52
0,006311
92%
vdd_mpu
R181
vdd_mpu
U52
0,006311
92%
Total Etch Resistance =
0,007007
100%
Total Etch Resistance =
0,006852
100%
Total Etch Resistance =
0,006837
100%
Max Value =
0,007007
Table 8-10. PDN Effective Resistance - From PMIC Source to Device Load
PDN Elements
Etch
Inductor
Sense Resistor
Max PDN Effectiv Resistance from Source
IR
•
•
•
•
PDN Effective Resistance
(Ω)
% of Total Etch Resistance
0,008045
89%
0
0%
0,001
11%
0,009045
100%
Drop: vdd_mpu (PCB RevJan14, Sentinel PSI)
Source Conditions: 1.22V @ 5,12A
Recommended Reff < 10mΩ
Reff = Total Trace Resistance + Sence Resistor = 8,04mΩ + 1mΩ = 9,04mΩ
Voltage / IR Drop: 1,22 - 1,179 = 52,6 mV
PCB_CPD_5
Figure 8-25. vdd_mpu Voltage/IR Drop [All Layers]
Dynamic analysis of this PCB design for the MPU power domain determined the vdd_mpu decoupling
capacitor loop inductance and impedance vs frequency analysis shown below. As you can see, the loop
inductance values ranged from 1.0 to 1.4nH and were less than maximum 2.0nH recommended.
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NOTE
Comparing loop inductances for capacitors at different distances from the processor’s input
power balls shows an 18% reduction for caps placed closer. This was derived by averaging
the inductances for the 3 caps with distances over 800mils (Avg LL = 1.33nH) vs the 3 caps
with distances less than 600mils (Avg LL = 1.096nH).
Table 8-11. Rail - vdd_mpu
Cap Ref
Des
Model Port
#
Loop Inductacne
[nH]
Footprint
Types
PCB Side
Distance to
Ball-Field
[mils]
Value [μF]
Size
C356
1
1,4
4vWSE
Bottom
897
22
0603
C359
2
1,26
4vWSE
Bottom
855
2,2
0402
C360
3
1,33
4vWSE
Bottom
850
4,7
0402
C365
4
1,14
4vWSE
Bottom
817
0,1
0201
C366
5
1,13
4vWSE
Bottom
755
0,1
0201
C367
6
1,07
4vWSE
Bottom
758
1
0201
C368
7
1,12
4vWSE
Bottom
811
0,1
0201
C369
8
1,06
4vWSE
Bottom
690
0,1
0201
C370
9
1,12
4vWSE
Bottom
680
0,1
0201
C384
10
1,04
4vWSE
Bottom
686
0,1
0201
C385
11
1,07
4vWSE
Top
686
0,1
0201
C387
12
1,16
4vWSE
Top
755
0,1
0201
C389
13
1,18
4vWSE
Top
693
0,1
0201
C391
14
1,14
4vWSE
Bottom
693
0,1
0201
C392
15
1,18
4vWSE
Bottom
542
0,1
0201
C396
16
1,11
4vWSE
Bottom
745
0,1
0201
C91
17
1,1
4vWSE
Bottom
515
1
0201
C92
18
1,09
4vWSE
Bottom
622
0,22
0201
C93
19
1,01
4vWSE
Bottom
504
0,47
0201
C94
20
1,13
4vWSE
Bottom
604
0,47
0201
C95
21
1,04
4vWSE
Bottom
612
1
0201
C96
22
1,08
4vWSE
Top
612
0,22
0201
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Loop Inductance range: 1,01 - 1,40 nH
PCB_CPD_6
Figure 8-26. vdd_mpu Decoupling Cap Loop Inductances
Figure 8-27 shows vdd_mpu Impedance vs Frequency characteristics.
310mΩ @ 100MHz
30mΩ @ 10MHz
160mΩ @ 50MHz
56,6mΩ @ 20MHz
PCB_CPD_7
Figure 8-27. vdd_mpu Impedance vs Frequency
8.4
8.4.1
Single-Ended Interfaces
General Routing Guidelines
The following paragraphs detail the routing guidelines that must be observed when routing the various
functional LVCMOS interfaces.
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•
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Line spacing:
– For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the
crosstalk between switching signals between the different lines. On the PCB, this is not achievable
everywhere (for example, when breaking signals out from the device package), but it is
recommended to follow this rule as much as possible. When violating this guideline, minimize the
length of the traces running parallel to each other (see Figure 8-28).
W
D+
S = 2 W = 200 µm
SWPS040-185
•
•
•
8.4.2
Figure 8-28. Ground Guard Illustration
Length matching (unless otherwise specified):
– For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 25 mm.
– For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 2.5 mm.
Characteristic impedance
– Unless otherwise specified, the characteristic impedance for single-ended interfaces is
recommended to be between 35-Ω and 65-Ω.
Multiple peripheral support
– For interfaces where multiple peripherals have to be supported in the star topology, the length of
each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify
signal integrity based on simulations including actual PCB extraction.
QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the QSPI
interfaces.
• The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.
• The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must
be approximately equal to the signal propagation delay from the QSPI device CLK pin to the
qspi1_rtclk ball (C to D).
• The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be
approximately equal to the signal propagation delay of the control and data signals between the QSPI
device and the SoC device (E to F, or F to E).
• The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the
QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip)
• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-29.
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Propagation delays and matching:
– A to C = C to D = E to F.
– Matching skew: < 60pS
– A to B < 450pS
– B to C = as small as possible (<60pS)
Locate both R2 resistors
close together near the QSPI device
A
B
C
R1
R2
0 Ω*
10 Ω
R2
10 Ω
qspi1_sclk
QSPI device
clock input
D
qspi1_rtclk
E
F
QSPI deice
IOx, CS#
qspi1_d[x], qspi1_cs[y]
PCB_QSPI_1
Figure 8-29. QSPI Interface High Level Schematic
NOTE
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for finetuning if needed.
8.5
8.5.1
Differential Interfaces
General Routing Guidelines
To maximize signal integrity, proper routing techniques for differential signals are important for high-speed
designs. The following general routing guidelines describe the routing guidelines for differential lanes and
differential signals.
• As much as possible, no other high-frequency signals must be routed in close proximity to the
differential pair.
• Must be routed as differential traces on the same layer. The trace width and spacing must be chosen
to yield the differential impedance value recommended.
• Minimize external components on differential lanes (like external ESD, probe points).
• Through-hole pins are not recommended.
• Differential lanes mustn’t cross image planes (ground planes).
• No sharp bend on differential lanes.
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•
•
8.5.2
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Number of vias on the differential pairs must be minimized, and identical on each line of the differential
pair. In case of multiple differential lanes in the same interface, all lines should have the same number
of vias.
Shielded routing is to be promoted as much as possible (for instance, signals must be routed on
internal layers that are inside power and/or ground planes).
USB 2.0 Board Design and Layout Guidelines
This section discusses schematic guidelines when designing a universal serial bus (USB) system.
8.5.2.1
Background
Clock frequencies generate the main source of energy in a USB design. The USB differential DP/DM pairs
operate in high-speed mode at 480 Mbps. System clocks can operate at 12 MHz, 48 MHz, and 60 MHz.
The USB cable can behave as a monopole antenna; take care to prevent RF currents from coupling onto
the cable.
When designing a USB board, the signals of most interest are:
• Device interface signals: Clocks and other signal/data lines that run between devices on the PCB.
• Power going into and out of the cable: The USB connector socket pin 1 (VBUS ) may be heavily
filtered and need only pass low frequency signals of less than ~100 KHz. The USB socket pin 4
(analog ground) must be able to return the current during data transmission, and must be filtered
sparingly.
• Differential twisted pair signals going out on cable, DP and DM: Depending upon the data transfer rate,
these device terminals can have signals with fundamental frequencies of 240 MHz (high speed), 6
MHz (full speed), and 750 kHz (low speed).
• External crystal circuit (device terminals XI and X0): 12 MHz, 19.2 MHz, 24 MHz, and 48 MHz
fundamental. When using an external crystal as a reference clock, a 24 MHz and higher crystal is
highly recommended.
8.5.2.2
USB PHY Layout Guide
The following sections describe in detail the specific guidelines for USB PHY Layout.
8.5.2.2.1 General Routing and Placement
Use the following routing and placement guidelines when laying out a new design for the USB physical
layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI)
problems on a four-or-more layer evaluation module (EVM).
• Place the USB PHY and major components on the un-routed board first. For more details, see
Section 8.5.2.2.2.3.
• Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.
• Route the high-speed USB signals on the plane closest to the ground plane, whenever possible.
• Route the high-speed USB signals using a minimum of vias and corners. This reduces signal
reflections and impedance changes.
• When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90°
turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
• Do not route USB traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
• Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is
unavoidable, then the stub should be less than 200 mils.
• Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
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8.5.2.2.2 Specific Guidelines for USB PHY Layout
The following sections describe in detail the specific guidelines for USB PHY Layout.
8.5.2.2.2.1 Analog, PLL, and Digital Power Supply Filtering
To minimize EMI emissions, add decoupling capacitors with a ferrite bead at power supply terminals for
the analog, phase-locked loop (PLL), and digital portions of the chip. Place this array as close to the chip
as possible to minimize the inductance of the line and noise contributions to the system. An analog and
digital supply example is shown in Figure 8-30. In case of multiple power supply pins with the same
function, tie them up to a single low-impedance point in the board and then add the decoupling capacitors,
in addition to the ferrite bead. This array of caps and ferrite bead improve EMI and jitter performance.
Take both EMI and jitter into account before altering the configuration.
Analog
Power Supply
Digital
Power Supply
Ferrite Bead
0.1 µF
0.01 µF
0.001 µF
10 µF
0.1 µF
0.01 µF
0.001 µF
10 µF
SoC Board
Ferrite Bead
Figure 8-30. Suggested Array Capacitors and a Ferrite Bead to Minimize EMI
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Consider the recommendations listed below to achieve proper ESD/EMI performance:
• Use a 0.01 μF cap on each cable power VBUS line to chassis GND close to the USB connector pin.
• Use a 0.01 μF cap on each cable ground line to chassis GND next to the USB connector pin.
• If voltage regulators are used, place a 0.01 μF cap on both input and output. This is to increase the
immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet.
8.5.2.2.2.2 Analog, Digital, and PLL Partitioning
If separate power planes are used, they must be tied together at one point through a low-impedance
bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail
close to the device. The analog ground, digital ground, and PLL ground must be tied together to the lowimpedance circuit board ground plane.
8.5.2.2.2.3 Board Stackup
Because of the high frequencies associated with the USB, a printed circuit board with at least four layers
is recommended; two signal layers separated by a ground and power layer as shown in Figure 8-31.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 8-31. Four-Layer Board Stack-Up
The majority of signal traces should run on a single layer, preferably SIGNAL1. Immediately next to this
layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in
the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must
be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.
8.5.2.2.2.4 Cable Connector Socket
Short the cable connector sockets directly to a small chassis ground plane (GND strap) that exists
immediately underneath the connector sockets. This shorts EMI (and ESD) directly to the chassis ground
before it gets onto the USB cable. This etch plane should be as large as possible, but all the conductors
coming off connector pins 1 through 6 must have the board signal GND plane run under. If needed, scoop
out the chassis GND strap etch to allow for the signal ground to extend under the connector pins. Note
that the etches coming from pins 1 and 4 (VBUS power and GND) should be wide and via-ed to their
respective planes as soon as possible, respecting the filtering that may be in place between the connector
pin and the plane. See Figure 8-32 for a schematic example.
Place a ferrite in series with the cable shield pins near the USB connector socket to keep EMI from getting
onto the cable shield. The ferrite bead between the cable shield and ground may be valued between 10 Ω
and 50 Ω at 100 MHz; it should be resistive to approximately 1 GHz. To keep EMI from getting onto the
cable bus power wire (a very large antenna) a ferrite may be placed in series with cable bus power,
VBUS, near the USB connector pin 1. The ferrite bead between connector pin 1 and bus power may be
valued between 47 Ω and approximately 1000 Ω at 100 MHz. It should continue being resistive out to
approximately 1 GHz, as shown in Figure 8-32.
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5
SHIELD_GND
4
GND
3
DP
2
DM
1
VBUS
Ferrite Bead
+5 V
U2
6
SHIELD_GND
USB Socket
U1
Ferrite Bead
Figure 8-32. USB Connector
8.5.2.2.2.5 Clock Routings
To address the system clock emissions between devices, place a ~10 to 130 Ω resistor in series with the
clock signal. Use a trial and error method of looking at the shape of the clock waveform on a high-speed
oscilloscope and of tuning the value of the resistance to minimize waveform distortion. The value on this
resistor should be as small as possible to get the desired effect. Place the resistor close to the device
generating the clock signal. If an external crystal is used, follow the guidelines detailed in the Selection
and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122).
When routing the clock traces from one device to another, try to use the 3W spacing rule. The distance
from the center of the clock trace to the center of any adjacent signal trace should be at least three times
the width of the clock trace. Many clocks, including slow frequency clocks, can have fast rise and fall
times. Using the 3W rule cuts down on crosstalk between traces. In general, leave space between each of
the traces running parallel between the devices. Avoid using right angles when routing traces to minimize
the routing distance and impedance discontinuities. For further protection from crosstalk, run guard traces
beside the clock signals (GND pin to GND pin), if possible. This lessens clock signal coupling, as shown in
Figure 8-33.
3W
3W
W
Trace
Figure 8-33. 3W Spacing Rule
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8.5.2.2.2.6 Crystals/Oscillator
Keep the crystal and its load capacitors close to the USB PHY pins, XI and XO (see Figure 8-34). Note
that frequencies from power sources or large capacitors can cause modulations within the clock and
should not be placed near the crystal. In these instances, errors such as dropped packets occur. A
placeholder for a resistor, in parallel with the crystal, can be incorporated in the design to assist oscillator
startup.
Power is proportional to the current squared. The current is I = C*dv/dt, because dv/dt is a function of the
PHY, current is proportional to the capacitive load. Cutting the load to 1/2 decreases the current by 1/2
and the power to 1/4 of the original value. For more details on crystal selection, see the Selection and
Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122).
X1
0.1 µF
Power Pins
XTAL
X0
0.001 µF
USB PHY
Figure 8-34. Power Supply and Clock Connection to the USB PHY
8.5.2.2.2.7 DP/DM Trace
Place the USB PHY as close as possible to the USB 2.0 connector. The signal swing during high-speed
operation on the DP/DM lines is relatively small (400 mV ± 10%), so any differential noise picked up on
the twisted pair can affect the received signal. When the DP/DM traces do not have any shielding, the
traces tend to behave like an antenna and picks up noise generated by the surrounding components in
the environment. To minimize the effect of this behavior:
• DP/DM traces should always be matched lengths and must be no more than 4 inches in length;
otherwise, the eye opening may be degraded (see Figure 8-35).
• Route DP/DM traces close together for noise rejection on differential signals, parallel to each other and
within two mils in length of each other. The measurement for trace length must be started from
device's balls.
• A high-speed USB connection is made through a shielded, twisted pair cable with a differential
characteristic impedance of 90 Ω ±15%. In layout, the impedance of DP and DM should each be 45 Ω
± 10%.
• DP/DM traces should not have any extra components to maintain signal integrity. For example, traces
cannot be routed to two USB connectors.
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Minimize
This Distance
VBUS
GND
D+
USB PHY
Cable
Connector
D+
Connector
D-
D-
Figure 8-35. USB PHY Connector and Cable Connector
8.5.2.2.2.8 DP/DM Vias
When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up
interference from the other layers of the board. Be careful when designing test points on twisted pair lines;
through-hole pins are not recommended.
8.5.2.2.2.9 Image Planes
An image plane is a layer of copper (voltage plane or ground plane), physically adjacent to a signal routing
plane. Use of image planes provides a low impedance, shortest possible return path for RF currents. For a
USB board, the best image plane is the ground plane because it can be used for both analog and digital
circuits.
• Do not route traces so they cross from one plane to the other. This can cause a broken RF return path
resulting in an EMI radiating loop as shown in Figure 8-36. This is important for higher frequency or
repetitive signals. Therefore, on a multi-layer board, it is best to run all clock signals on the signal
plane above a solid ground plane.
• Avoid crossing the image power or ground plane boundaries with high-speed clock signal traces
immediately above or below the separated planes. This also holds true for the twisted pair signals (DP,
DM). Any unused area of the top and bottom signal layers of the PCB can be filled with copper that is
connected to the ground plane through vias.
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Do
Don't
•
Figure 8-36. Do Not Cross Plane Boundaries
Do not overlap planes that do not reference each other. For example, do not overlap a digital power
plane with an analog power plane as this produces a capacitance between the overlapping areas that
could pass RF emissions from one plane to the other, as shown in Figure 8-37.
Analog Power Plane
Unwanted Capacitance
Digital Power Plane
•
Figure 8-37. Do Not Overlap Planes
Avoid image plane violations. Traces that route over a slot in an image plane results in a possible RF
return loop, as shown in Figure 8-38.
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RF Return
Current
RF Return
Current
Slot in Image Plane
Slot in Image Plane
Bad
Better
Figure 8-38. Do Not Violate Image Planes
8.5.2.2.2.10 JTAG Interface
For test and debug of the USB PHY only, an IEEE Standard 1149.1-1990, IEEE Standard Test Access
Port and Boundary-Scan Architecture (JTAG) and Serial Test and Configuration Interface (STCI) may be
available on the System-on-Chip (SoC). If available, keep the USB PHY JTAG interface less than six
inches; keeping this distance short reduces noise coupling from other devices and signal loss due to
resistance.
8.5.2.2.2.11 Power Regulators
Switching power regulators are a source of noise and can cause noise coupling if placed close to sensitive
areas on a circuit board. Therefore, the switching power regulator should be kept away from the DP/DM
signals, the external clock crystal (or clock oscillator), and the USB PHY.
8.5.2.3
Electrostatic Discharge (ESD)
International Electronic Commission (IEC) 61000-4-xx is a set of about 25 testing specifications from the
IEC. IEC ESD Stressing is done both un-powered and with power applied, and with the device functioning.
There must be no physical damage, and the device must keep working normally after the conclusion of
the stressing. Typically, equipment has to pass IEC stressing at 8 kV contact and 15 kV air discharge, or
higher. To market products/systems in the European community, all products/systems must be CE
compliant and have the CE Mark. To obtain the CE Mark, all products/systems need to go through and
pass IEC standard requirements; for ESD, it is 61000-4-2. 61000-4-2 requires that the products/systems
pass contact discharge at 8 kV and air discharge at 15 kV. When performing an IEC ESD Stressing, only
pins accessible to the outside world need to pass the test. The system into which the integrated circuit (IC)
is placed makes a difference in how well the IC does. For example:
• Cable between the zap point and the IC attenuate the high frequencies in the waveform.
• Series inductance on the PCB board attenuates the high frequencies.
• Unless the capacitor’s ground connection is inductive, capacitance to ground shunts away high
frequencies.
8.5.2.3.1 IEC ESD Stressing Test
The following sections describe in detail the IEC ESD Stressing Test modes and test types.
8.5.2.3.1.1 Test Mode
The IEC ESD Stressing test is done through two modes: contact discharge mode and air discharge mode.
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For the contact discharge test mode, the preferred way is direct contact applied to the conductive surfaces
of the equipment under test (EUT). In the case of the USB system, the conductive surface is the outer
casing of the USB connector. The electrode of the ESD generator is held in contact with the EUT or a
coupling plane prior to discharge. The arc formation is created under controlled conditions, inside a relay,
resulting in repeatable waveforms; however, this arc does not accurately recreate the characteristic unique
to the arc of an actual ESD event.
8.5.2.3.1.2 Air Discharge Mode
The air discharge usually applies to a non-conductive surface of the EUT. Instead of a direct contact with
the EUT, the charged electrode of the ESD generator is brought close to the EUT, and a spark in the air to
the EUT actuates the discharge. Compared to the contact discharge mode, the air discharge is more
realistic to the actual ESD occurrence. However, due to the variations of the arc length, it may not be able
to produce repeatable waveform.
8.5.2.3.1.3 Test Type
The IEC ESD Stressing test has two test types: direct discharge and indirect discharge. Direct discharge
is applies directly to the surface or the structure of the EUT. It includes both contact discharge and air
discharge modes. Indirect discharge applies to a coupling plane in the vicinity of the EUT. The indirect
discharge is used to simulate personal discharge to objects which are adjacent to the EUT. It includes
contact discharge mode only.
8.5.2.3.2 TI Component Level IEC ESD Test
TI Component Level IEC ESD Test tests only the IC terminals that are exposed in system level
applications. It can be used to determine the robustness of on-chip protection and the latch-up immunity.
The IC can only pass the TI Component Level IEC ESD test when there is no latch-up and IC is fully
functional after the test.
8.5.2.3.3 Construction of a Custom USB Connector
A standard USB connector, either type A or type B, provides good ESD protection. However, if a custom
USB connector is desired, the following guidelines should be observed to ensure good ESD protection.
• There should be an easily accessible shield plate next to the connector for air-discharge mode
purpose.
• Tie the outer shield of the connector to GND. When a cable is inserted into the connector, the shield of
the cable should first make contact with the outer shield.
• If the connector includes power and GND, the lead of power and GND need to be longer than the
leads of signal.
• The connector needs to have a key to ensure proper insertion of the cable.
• See the standard USB connector for reference.
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8.5.2.3.4 ESD Protection System Design Consideration
ESD protection system design consideration is covered in Section 8.5.2.2 of this document. The following
are additional considerations for ESD protection in a system.
• Metallic shielding for both ESD and EMI
• Chassis GND isolation from the board GND
• Air gap designed on board to absorb ESD energy
• Clamping diodes to absorb ESD energy
• Capacitors to divert ESD energy
• The use of external ESD components on the DP/DM lines may affect signal quality and are not
recommended.
8.5.2.4
•
•
•
8.5.3
References
USB 2.0 Specification, Intel, 2000, http://www.usb.org/developers/docs/
High
Speed
USB
Platform
Design
Guidelines,
Intel,
http://www.intel.com/technology/usb/download/usb2dg_R1_0.pdf
Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122)
2000,
USB 3.0 Board Design and Layout Guidelines
This section provides the timing specification for the USB3.0 (USB1 in the device) interface as a PCB
design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew,
signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to
ensure the USB3.0 interface requirements are met. The design rules stated within this document are
targeted at DEVICE mode electrical compliance. HOST mode and/or systems that do not include the 3m
USB cable and far-end 11-inch PCB trace required by DEVICE mode compliance testing may not need
the complete list of optimizations shown in this document; however, applying these optimizations to HOST
mode systems will lead to optimal DEVICE mode performance.
8.5.3.1
USB 3.0 interface introduction
The USB 3.0 has two unidirectional differential pairs: TXp/TXn pair and RXp/RXn pair. AC coupling caps
are needed on the board for TX traces.
Figure 8-39 present high level schematic diagram for USB 3.0 interface.
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GND
Device
AC Caps
GND GND
CMF
Vias (if necessary)
Vias (if necessary)
usb_rxp0
usb_rxn0
CMF
Vias (if necessary)
Vias (if necessary)
GND
USB 3.0
usb_txp0
usb_txn0
USB 3.0 connector
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Place near connector, and keep routing short
SPRS85x_PCB_USB30_1
Figure 8-39. USB 3.0 Interface High Level Schematic
NOTE
ESD components should be on a PCB layer next to a system GND plane layer so the
inductance of the via to GND will be minimal.
If vias are used, place the vias near the AC Caps or CMFs and under the SoC BGA, if
necessary.
AC Cap
SoC TX
USB 3.0 connector
via
Figure 8-40 present placement diagram for USB 3.0 interface.
AC Cap
via
via
CMF
SoC RX
via
CMF
SPRS85x_PCB_USB30_2
Figure 8-40. USB 3.0 placement diagram
Table 8-12. USB1 Component Reference
INTERFACE
COMPONENT
SUPPLIER
PART NUMBER
ESD
TI
TPD1E05U06
USB3 PHY
CMF
Murata
DLW21SN900HQ2
C
-
100nF (typical size: 0201)
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USB 3.0 General routing rules
Some general routing guidelines regarding USB 3.0:
• Avoid crossing splits reference plane(s).
• Shorter trace length is preferred.
• Minimize the via usage and layer transition
• Keep large spacing between TX and RX pairs.
• Intra-lane delay mismatch between DP and DM less than 1ps. Same for RXp and RXn.
• Distance between common mode filter (CMF) and ESD protection device should be as short as
possible
• Distance between ESD protection device and USB connector should be as short as possible.
• Distance between AC capacitors (TX only) and CMF should be as short as possible.
• USB 3.0 signals should always be routed over an adjacent ground plane.
Table 8-13 and Table 8-14 present routing specification and recommendations for USB1 in the device.
Table 8-13. USB1 Routing Specifications
PARAMETER
MIN
TYP
MAX
UNIT
3500
Mils
3
6
Mils
0
Stubs
90
96.3
Ω
2
Vias
Number of ground plane cuts allowed within
USB3 routing region (except for specific
ground carving as explained in this
document)
0
Cuts
Number of layers between USB3.0 routing
region and reference ground plane
0
Layers
Device balls to USB 3.0 connector trace
length
Skew within a differential pair
Number of stubs allowed on TX/RX traces
TX/RX pair differential impedance
83.7
Number of vias on each TX/RX trace (1)
Differential pair to any other trace spacing (2)
(3) (4)
2xDS
3xDS
PCB trace width
6
Mils
PCB BGA escape via pad size
18
Mils
PCB BGA escape via hole size
10
Mils
(1) Vias must be used in pairs and spaced equally along a signal path.
(2) DS = differential spacing of the traces.
(3) Exceptions may be necessary in the SoC package BGA area.
(4) GND guard-bands on the same layer may be closer, but should not be allowed to affect the impedance of the differential pair routing.
GND guard-bands to isolate USB3.0 differential pairs from all other signals are recommended.
Table 8-14. USB1 Routing Recommendations
388
Item
Description
Reason
ESD location
Place ESD component on same layer as connector (no via or stub to
ESD component)
Eliminate reflection loss from via
& stub to ESD
ESD part number
TPD1E05U06
Minimize capacitance (0.42pF)
CMF part number
DLW21SN900HQ2
Manufacturer’s recommended
device
Connector
Use USB3.0 connector with supporting s-parameter model
Enable full signal chain
simulation
Carve Ground
Carve GND underneath AC Caps, ESD, CMF, and connector
Minimize capacitance under ESD
and CMF
Round pads
Minimize pad size and round the corners of the pads for the ESD
and CMF components
Minimize capacitance
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Table 8-14. USB1 Routing Recommendations (continued)
Item
Description
Reason
Vias
Max 2 vias per signal trace. If vias are required, place vias close to
the AC Caps and CMFs. Vias under the SoC grid array may be used
if necessary to route signals away from BGA pattern.
Vias significantly degrade signal
integrity at 2.5GHz
via
Figure 8-41 presents an example layout, demonstrating the “carve GND” concept.
USB 3.0 connector
AC Cap
CMF
via
via
AC Cap
via
CMF
Top Layer: Routing from SoC through
AC Caps, CMF, and ESD to connector.
Layer2, GND: Gaps carved in GND underneath
AC Caps, CMF, ESD, and connector.
Layer3, Signal: Implement as keep-out
zone underneath carved GND areas.
Layer4, GND Plane underneath AC Caps,
CMF, ESD, and connector.
SPRS85x_PCB_USB30_3
Figure 8-41. USB 3.0 Example “carve GND” layout
8.5.4
HDMI Board Design and Layout Guidelines
This section provides the timing specification for the HDMI interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. TI has performed the simulation and system design work to ensure the HDMI interface
requirements are met. The design rules stated within this document are targeted at resolutions less than
or equal to 1080p60 with 8-bit color; deep color (10-bit) requires further signal integrity optimization.
8.5.4.1
HDMI Interface Schematic
The HDMI bus is separated into three main sections (HDMI Ethernet and the optional Audio Return
Channel are not specifically supported by this Device):
1. Transition Minimized Differential Signaling (TMDS) high speed digital video interface
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2. Display Data Channel (I2C bus for configuration and status exchange between two devices)
3. Consumer Electronics Control (optional) for remote control of connected devices.
The DDC and CEC are low speed interfaces, so nothing special is required for PCB layout of these
signals.
The TMDS channels are high speed differential pairs and therefore require the most care in layout.
Specifications for TMDS layout are below.
Figure 8-42 shows the HDMI interface schematic.
CMF
HDMI connector
hdmi_tx*hdmi_tx*+
GND
HDMI
GND
Device
Place near connector, and keep routing short
SPRS85x_PCB_HDMI_1
Figure 8-42. HDMI Interface High Level Schematic
Figure 8-43 presents placement diagram for HDMI interface.
HDMI connector
CMF
CMF
CMF
CMF
SPRS85x_PCB_HDMI_2
Figure 8-43. HDMI Placement Diagram
Table 8-15. HDMI Component Reference
INTERFACE
HDMI
390
DEVICE
SUPPLIER
ESD
TI
TPD1E05U06
CMF
Murata
DLW21SN900HQ2
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PART NUMBER
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8.5.4.2
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
TMDS General Routing Guidelines
The TMDS signals are high speed differential pairs. Care must be taken in the PCB layout of these signals
to ensure good signal integrity.
The TMDS differential signal traces must be routed to achieve 100 Ohms (+/- 10%) differential impedance
and 60 ohms (+/-10%) single ended impedance. Single ended impedance control is required because
differential signals can’t be closely coupled on PCBs and therefore single ended impedance becomes
important.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 60 ohms impedance traces as possible. For best accuracy, work with your PCB fabricator to
ensure this impedance is met.
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier, and trace width variations don’t affect impedance as much, therefore it’s
easier to maintain accurate impedance over the length of the signal. The wider traces also show reduced
skin effect and therefore often result in better signal integrity.
Some general routing guidelines regarding TMDS:
• Avoid crossing splits reference plane(s).
• Shorter trace length is preferred.
• Distance between common mode filter (CMF) and ESD protection device should be as short as
possible
• Distance between ESD protection device and HDMI connector should be as short as possible.
Table 8-16 shows the routing specifications for the TMDS signals.
Table 8-16. TMDS Routing Specifications
PARAMETER
MIN
TYP
Device balls to HDMI header trace length
Skew within a differential pair
3
Number of stubs allowed on TMDS traces
MAX
UNIT
4000
Mils
5
Mils
0
stubs
TMDS pair differential impedance
90
100
110
Ω
TMDS single-ended impedance
54
60
66
Ω
0
Vias
2×DS
3xDS
Number of vias on each TMDS trace
TMDS differential pair to any other trace spacing (1) (2) (3)
Number of ground plane cuts allowed within HDMI routing region (except for specific
ground carving as explained in this document)
Number of layers between HDMI routing region and reference ground plane
PCB trace width
Mils
0
Cuts
0
Layers
4.4
Mils
(1) DS = differential spacing of the traces.
(2) Exceptions may be necessary in the SoC package BGA area.
(3) GND guard-bands may be closer, but should not be allowed to affect the impedance of the differential pair routing. GND guard-bands to
isolate HDMI differential pairs from all other signals is recommended.
Table 8-17. TDMS Routing Recommendations
Item
Description
Reason
ESD part number
TPD1E05U06
Minimize capacitance (0.42pF)
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Table 8-17. TDMS Routing Recommendations (continued)
Item
Description
Reason
Carve Ground
Carve GND underneath ESD and CMF
Minimize capacitance under ESD
and CMF
Round pads
Reduce pad size and round the corners of the pads for the ESD and
CMF components
Minimize capacitance
Routing layer
Route all signals only on the same layer as SoC
Minimize reflection loss
Figure 8-44presents an example layout, demonstrating the “carve GND” concept.
HDMI connector
CMF
ia
v AC Cap
CMF
CMF
a
iv AC Cap
a
iv
CMF
CMF
a
iv
CMF
Top Layer: Routing from SoC through CMF,
and ESD to connector.
Layer2, GND: Gaps carved in GND underneath,
CMF, ESD, and connector.
SPRS85x_PCB_HDMI_3
Figure 8-44. HDMI Example “carve GND” layout
8.5.4.3
TPD5S115
The TPD5S115 is an integrated HDMI companion chip solution. The device provides a regulated 5 V
output (5VOUT) for sourcing the HDMI power line. The TPD5S115 exceeds the IEC61000-4-2 (Level 4)
ESD protection level.
8.5.4.4
HDMI ESD Protection Device (Required)
Interfaces that connect to a cable such as HDMI generally require more ESD protection than can be built
into the processor’s outputs. Therefore this HDMI interface requires the use of an ESD protection chip to
provide adequate ESD.
When selecting an ESD protection chip, choose the lowest capacitance ESD protection available to
minimize signal degradation. In no case should be ESD protection circuit capacitance be more than 5pF.
TI manufactures these devices that provide ESD protection for HDMI signals such as the TPDxE05U06.
For more information see the www.ti.com website.
8.5.4.5
PCB Stackup Specifications
Table 8-18 shows the stackup and feature sizes required for HDMI.
Table 8-18. HDMI PCB Stackup Specifications
392
PARAMETER
MIN
TYP
MAX
UNIT
PCB Routing/Plane Layers
4
6
-
Layers
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Table 8-18. HDMI PCB Stackup Specifications (continued)
PARAMETER
MIN
TYP
MAX
UNIT
Signal Routing Layers
2
3
-
Layers
Number of ground plane cuts allowed within HDMI routing
region
-
-
0
Cuts
Number of layers between HDMI routing region and
reference ground plane
-
-
0
Layers
PCB Trace width
8.5.4.6
4
Mils
Grounding
Each TMDS channel has its own shield pin and they should be grounded to provide a return current path
for the TMDS signal.
8.5.5
SATA Board Design and Layout Guidelines
The device provides one SATA port. This section provides the timing specification for the SATA interface
as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace
skew, signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design
work to ensure the SATA interface requirements are met.
8.5.5.1
SATA Interface Schematic
Figure 8-45 shows the data portion of the SATA interface schematic.
DEVICE
SATA Interface
sata1_rxn0
C
sata1_rxp0
C
sata1_txn0l
C
sata1_txp0
C
SATA
Connector
PCB_SATA_1
Figure 8-45. SATA Interface High Level Schematic
NOTE
AC coupling capacitors (C) are required on the receive and transmit data pairs. Table 8-19
shows the requirements for these capacitors.
Table 8-19. SATA AC Coupling Capacitors Requirements
PARAMETER
MIN
TYP
MAX
UNIT
SATA AC coupling capacitor value
0.3
10
12
nF
0402
0603
EIA(1)(2)
SATA AC coupling capacitor package size
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
8.5.5.2
Compatible SATA Components and Modes
Table 8-20 shows the compatible SATA components and supported modes. Note that the only supported
configuration is an internal cable from the processor host to the SATA device.
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Table 8-20. Compatible SATA Components and Modes
8.5.5.3
PARAMETER
MIN
MAX
UNIT
Transfer Rates
1.5
3
Gbps
Internal Cable
-
-
-
SUPPORTED
YES
PCB Stackup Specifications
Table 8-21 shows the stackup and feature sizes required for these types of SATA connections.
Table 8-21. SATA PCB Stackup Specifications
PARAMETER
MIN
TYP
MAX
UNIT
Number of ground plane cuts allowed within SATA routing
region
-
-
0
Cuts
Number of layers between SATA routing area and
reference plane
-
-
0
Layers
8.5.5.4
PCB Routing clearance
4
Mils
PCB Trace width
4
Mils
Routing Specifications
The SATA data signal traces must be routed to achieve 100 Ohms (+/-10%) differential impedance and 60
ohms (+/-10%) single ended impedance. The signal ended impedance is required because differential
signals can’t be closely coupled on PCBs and therefore single ended impedance becomes important. 60
ohms is chosen for the single ended impedance to minimize problems caused by too low an impedance.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 100 ohms differential and 60 ohms single ended impedance traces as possible. For best
accuracy, work with your PCB fabricator to ensure this impedance is met.
Table 8-22 shows the routing specifications for the SATA data signals.
Table 8-22. SATA Routing Specifications
PARAMETER
MIN
TYP
SATA signal trace length (device balls to SATA connector)
Differential pair trace skew matching
Number of stubs allowed on SATA traces
MAX
UNIT
3050(1)
Mils
5
Mils
0
stubs
TX/RX pair differential impedance
90
100
110
Ω
TX/RX single-ended impedance
54
60
66
Ω
0
Vias
(2)
Number of vias on each SATA trace
SATA differential pair to any other trace spacing
2×DS(3)
(1) Beyond this, signal integrity may suffer.
(2) Inline pads may be used for probing.
(3) DS = differential spacing of the SATA traces.
Table 8-23. SATA Routing Recommendations
Item
ESD part number
394
Applications, Implementation, and Layout
Description
Reason
None
ESD suppression generally not
used on SATA
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8.5.6
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
PCIe Board Design and Layout Guidelines
The PCIe interface on the device provides support for a 5.0 Gbps lane with polarity inversion.
8.5.6.1
PCIe Connections and Interface Compliance
The PCIe interface on the device is compliant with the PCIe revision 2.0 specification. Please refer to the
PCIe specifications for all connections that are described in it. Those recommendations are more
descriptive and exhaustive than what is possible here.
The use of PCIe compatible bridges and switches is allowed for interfacing with more than one other
processor or PCIe device.
8.5.6.1.1 Coupling Capacitors
AC coupling capacitors are required on the transmit data pair. Table 8-24 shows the requirements for
these capacitors.
Table 8-24. PCIe AC Coupling Capacitors Requirements
PARAMETER
MIN
PCIe AC coupling capacitor value
90
PCIe AC coupling capacitor package size
TYP
MAX
UNIT
100
110
nF
0402
0603
EIA(1)(2)
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
8.5.6.1.2 Polarity Inversion
The PCIe specification requires polarity inversion support. This means for layout purposes, polarity is
unimportant because each signal can change its polarity on die inside the chip. This means polarity within
a lane is unimportant for layout.
8.5.6.2
Non-standard PCIe connections
The following sections contain suggestions for any PCIe connection that is NOT described in the official
PCIe specification, such as an on-board Device to Device or Device to other PCIe compliant processor
connection.
8.5.6.2.1 PCB Stackup Specifications
Table 8-25 shows the stackup and feature sizes required for these types of PCIe connections.
Table 8-25. PCIe PCB Stackup Specifications
PARAMETER
MIN
TYP
MAX
UNIT
Number of ground plane cuts allowed within PCIe routing
region
-
-
0
Cuts
Number of layers between PCIe routing area and reference
plane (1)
-
-
0
Layers
PCB Routing clearance
4
Mils
PCB Trace width
4
Mils
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(1) A reference plane may be a ground plane or the power plane referencing the PCIe signals.
8.5.6.2.2 Routing Specifications
8.5.6.2.2.1 Impedance
The PCIe data signal traces must be routed to achieve 100-Ω (±10%) differential impedance and 60-Ω
(±10%) single-ended impedance. The single-ended impedance is required because differential signals are
extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.
These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0
document, available from PCI-SIG (www.pcisig.com).
These impedances are impacted by trace width, trace spacing, distance between signals and referencing
planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal
pairs result in as close to 100-Ω differential impedance and 60-Ω single-ended impedance as possible. For
best accuracy, work with your PCB fabricator to ensure this impedance is met. See Table 8-26 below.
8.5.6.2.2.2 Differential Coupling
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production. For PCBs with very tight space limitations (which are usually small) this can work, but for
most PCBs, the loosely coupled option is probably best.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier (because each trace is not so fixed in position relative to the other), and
trace width variations don’t affect impedance as much, therefore it’s easier to maintain an accurate
impedance over the length of the signal. For longer routes, the wider traces also show reduced skin effect
and therefore often result in better signal integrity with a larger eye diagram opening.
Table 8-26 shows the routing specifications for the PCIe data signals.
Table 8-26. PCI-E Routing Specifications
PARAMETER
MIN
TYP
PCIe signal trace length
Differential pair trace matching
MAX
UNIT
4700(1)
Mills
5
Number of stubs allowed on PCIe traces(3)
TX/RX pair differential impedance
90
100
TX/RX single-ended impedance
54
60
(2)
Mils
0
stubs
110
Ω
66
Ω
Pad size of vias on PCIe trace
25(4)
Mils
Hole size of vias on PCIe trace
14
Mils
Number of vias on each PCIe trace
0
Vias
PCIe differential pair to any other trace spacing
2×DS(5)
(1) Beyond this, signal integrity may suffer.
(2) For example, RXP0 within 5 Mils of RXN0.
(3) Inline pads may be used for probing.
(4) 35-Mil antipad maximum recommended.
(5) DS = differential spacing of the PCIe traces.
Table 8-27. PCI-E Routing Recommendations
Item
ESD part number
396
Applications, Implementation, and Layout
Description
Reason
None
ESD suppression generally not
used on PCIe
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8.5.6.2.2.3 Pair Length Matching
Each signal in the differential pair should be matched to within 5 mils of its matching differential signal.
Length matching should be done as close to the mismatch as possible.
8.5.6.3
LJCB_REFN/P Connections
A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two
modes of Common Refclk Rx Architecture are supported:
• External REFCLK Mode: An common external 100MHz clock source is distributed to both the Device
and the link partner
• Output REFCLK Mode: A 100MHz HCSL clock source is output by the device and used by the link
partner
In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100MHz clock source compliant to
the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs.
Alternatively, an LVDS clock source can be used with the following additional requirements:
• External AC coupling capacitors described in Table 8-28 should be populated at the ljcb_clkn /
ljcb_clkp inputs.
• All termination requirements (ex. parallel 100ohm termination) from the clock source manufacturer
should be followed.
In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on
the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External nearside termination to ground described in Table 8-29 is required on both of the ljcb_clkn / ljcb_clkp outputs
in this mode.
Table 8-28. LJCB_REFN/P Requirements in External LVDS REFCLK Mode
PARAMETER
MIN
TYP
ljcb_clkn / ljcb_clkp AC coupling capacitor value
100
ljcb_clkn / ljcb_clkp AC coupling capacitor package size
0402
MAX
UNIT
nF
0603
EIA(1)(2)
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
Table 8-29. LJCB_REFN/P Requirements in Output REFCLK Mode
PARAMETER
MIN
TYP
MAX
UNIT
ljcb_clkn / ljcb_clkp near-side termination to ground value
47.5
50
52.5
Ohms
8.6
8.6.1
Clock Routing Guidelines
32-kHz Oscillator Routing
When designing the printed-circuit board:
• Keep the crystal as close as possible to the crystal pins X1 and X2.
• Keep the trace lengths short and small to reduce capacitor loading and prevent unwanted noise
pickup.
• Place a guard ring around the crystal and tie the ring to ground to help isolate the crystal from
unwanted noise pickup.
• Keep all signals out from beneath the crystal and the X1 and X2 pins to prevent noise coupling.
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•
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Finally, an additional local ground plane on an adjacent PCB layer can be added under the crystal to
shield it from unwanted pickup from traces on other layers of the board. This plane must be isolated
from the regular PCB ground plane and tied to the GND pin of the RTC. The plane must not be any
larger than the perimeter of the guard ring. Make sure that this ground plane does not contribute to
significant capacitance (a few pF) between the signal line and ground on the connections that run from
X1 and X2 to the crystal.
Cap
Via to GND
X
1
Crystal
Cap
IC
X
2
Local ground plane
SWPS040-196
Figure 8-46. Slow Clock PCB Requirements
8.6.2
Oscillator Ground Connection
Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in
the ground plane causes a voltage drop in the ground. Figure 8-47 shows the grounding scheme for slow
(low frequency) clock generated from the internal oscillator.
Device
rtc_osc_xo
rtc_osc_xi_clkin32
Rd
(Optional)
Crystal
Cf1
Cf2
SPRS85v_PCB_CLK_OSC_2
Figure 8-47. Grounding Scheme for Low-Frequency Clock
Figure 8-48 shows the grounding scheme for high-frequency clock.
398
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Device
xi_oscj
xo_oscj
Rd
(Optional)
Crystal
Cf1
vssa_oscj
Cf2
SPRS85v_PCB_CLK_OSC_3
(1)
j in *_osc = 0 or 1
Figure 8-48. Grounding Scheme for High-Frequency Clock
8.7
DDR2/DDR3 Board Design and Layout Guidelines
8.7.1
DDR2/DDR3 General Board Layout Guidelines
To
•
•
•
•
•
•
•
•
•
•
•
8.7.2
help ensure good signaling performance, consider the following board design guidelines:
Avoid crossing splits in the power plane.
Minimize Vref noise.
Use the widest trace that is practical between decoupling capacitors and memory module.
Maintain a single reference.
Minimize ISI by keeping impedances matched.
Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
Use proper low-pass filtering on the Vref pins.
Keep the stub length as short as possible.
Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
Maintain a common ground reference for all bypass and decoupling capacitors.
Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
DDR2 Board Design and Layout Guidelines
8.7.2.1
Board Designs
TI only supports board designs that follow the guidelines outlined in this document. The switching
characteristics and the timing diagram for the DDR2 memory controller are shown in Table 8-30 and
Figure 8-49.
Table 8-30. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller
NO.
DDR21
PARAMETE
R
tc(DDR_CLK)
DESCRIPTION
MIN
MAX
UNIT
Cycle time, DDR_CLK
2.5
8
ns
1
ddrx_ck
PCB_DDR2_0
Figure 8-49. DDR2 Memory Controller Clock Timing
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DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application
Report (Literature Number: SPRAAV0).
8.7.2.2.1 DDR2 Interface Schematic
Figure 8-50 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-51 the x16
DDR2 system schematic is identical except that the high-word DDR2 device is deleted.
When not using all or part of a DDR2 interface, the proper method of handling the unused pins is to tie off
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. The vdds_ddrx and
ddrx_vref0 power supply pins need to be connected to their respective power supplies even if DDRx is not
being used. All other DDR interface pins can be left unconnected. Note that the supported modes for use
of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.
400
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DDR2
ddrx_d0
DQ0
ddrx_d7
ddrx_dqm0
ddrx_dqs0
DQ7
LDM
LDQS
ddrx_dqsn0
ddrx_d8
LDQS
DQ8
ddrx_d15
ddrx_dqm1
ddrx_dqs1
DQ15
UDM
UDQS
ddrx_dqsn1
ddrx_odt0
UDQS
ODT
T0
DDR2
ddrx_odt1
NC
ODT
ddrx_d16
DQ0
ddrx_d23
ddrx_dqm2
ddrx_dqs2
ddrx_dqsn2
ddrx_d24
DQ7
LDM
LDQS
LDQS
DQ8
ddrx_d31
ddrx_dqm3
ddrx_dqs3
ddrx_dqsn3
DQ15
UDM
UDQS
UDQS
ddrx_ba0
T0
BA0
BA0
ddrx_ba2
ddrx_a0
T0
T0
BA2
A0
BA2
A0
T0
T0
NC
T0
T0
A14
CS
A14
CS
CAS
RAS
CAS
T0
T0
T0
T0
WE
CKE
CK
CK
VREF
WE
CKE
CK
CK
VREF
ddrx_a14
ddrx_csn0
ddrx_csn1
ddrx_casn
ddrx_rasn
ddrx_wen
ddrx_cke
ddrx_ck
ddrx_nck
ddrx_vref0
(B)
0.1 µF
ddrx_rst
T0
A.
B.
0.1 µF
(B)
vdds_ddrx
(A)
RAS
VREF
0.1 µF
VREF
1 K Ω 1%
VREF
(B)
0.1 µF
0.1 µF
1 K Ω 1%
NC
Termination is required. See terminator comments.
PCB_DDR2_1
vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.
One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.
Figure 8-50. 32-Bit DDR2 High-Level Schematic
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DDR2
ddrx_d0
DQ0
ddrx_d7
ddrx_dqm0
ddrx_dqs0
DQ7
LDM
LDQS
ddrx_dqsn0
ddrx_d8
LDQS
DQ8
ddrx_d15
ddrx_dqm1
ddrx_dqs1
ddrx_dqsn1
DQ15
UDM
UDQS
UDQS
ddrx_odt0
ddrx_odt1
ddrx_d16
T0
NC
NC
ddrx_d23
ddrx_dqm2
NC
NC
1 KΩ
ddrx_d24
NC
1 KΩ
ddrx_d31
ddrx_dqm3
ddrx_dqsn3
ddrx_dqs3
NC
NC
ODT
vdds_ddrx
(A)
ddrx_dqsn2
ddrx_dqs2
vdds_ddrx
(A)
1 KΩ
1 KΩ
ddrx_ba0
T0
BA0
ddrx_ba2
ddrx_a0
T0
T0
BA2
A0
T0
T0
NC
T0
T0
T0
T0
T0
T0
A14
CS
ddrx_a14
ddrx_csn0
ddrx_csn1
ddrx_casn
ddrx_rasn
ddrx_wen
ddrx_cke
ddrx_ck
ddrx_nck
CAS
ddrx_vref0
VREF
0.1 µF
ddrx_rst
T0
A.
B.
vdds_ddrx
RAS
WE
CKE
CK
CK
(B)
0.1 µF
0.1 µF
VREF
(A)
1 K Ω 1%
VREF
(B)
0.1 µF
1 K Ω 1%
NC
Termination is required. See terminator comments.
PCB_DDR2_2
vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.
One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.
Figure 8-51. 16-Bit DDR2 High-Level Schematic
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8.7.2.2.2 Compatible JEDEC DDR2 Devices
Table 8-31 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.
Table 8-31. Compatible JEDEC DDR2 Devices (Per Interface)
NO.
PARAMETER
CJ21
JEDEC DDR2 device speed grade(1)
CJ22
JEDEC DDR2 device bit width
CJ23
JEDEC DDR2 device count(2)
CJ24
JEDEC DDR2 device ball count(3)
MIN
MAX
UNIT
DDR2-800
x16
x16
1
2
Devices
Bits
84
92
Balls
(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) One DDR2 device is used for a 16-bit DDR2 memory system. Two DDR2 devices are used for a 32-bit DDR2 memory system.
(3) The 92-ball devices are retained for legacy support. New designs will migrate to 84-ball DDR2 devices. Electrically, the 92- and 84-ball
DDR2 devices are the same.
8.7.2.2.3 PCB Stackup
The minimum stackup required for routing the Device is a six-layer stackup as shown in Table 8-32.
Additional layers may be added to the PCB stackup to accommodate other circuitry or to reduce the size
of the PCB footprint.
Table 8-32. Minimum PCB Stackup
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly horizontal
2
Plane
Ground
3
Plane
Power
4
Signal
Internal routing
5
Plane
Ground
6
Signal
Bottom routing mostly vertical
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Complete stackup specifications are provided in Table 8-33.
Table 8-33. PCB Stackup Specifications
NO.
PARAMETER
MIN
PS21
PCB routing/plane layers
6
PS22
Signal routing layers
3
PS23
Full ground reference layers under DDR2 routing region(1)
1
PS24
Full vdds_ddrx power reference layers under the DDR2 routing
region(1)
1
PS25
Number of reference plane cuts allowed within DDR routing region(2)
TYP
PS26
Number of layers between DDR2 routing layer and reference plane
PS27
PCB routing feature size
4
PS28
PCB trace width, w
4
PS29
Single-ended impedance, Zo
PS210
Impedance control
UNIT
0
(3)
(5)
MAX
0
50
Z-5
Z
Mils
Mils
75
Ω
Z+5
Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers. A full ground reference layer should be placed adjacent to each DDR routing
layer in PCB stack up.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS29.
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8.7.2.2.4 Placement
Figure 8-52 shows the required placement for the Device as well as the DDR2 devices. The dimensions
for this figure are defined in Table 8-34. The placement does not restrict the side of the PCB on which the
devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and
allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR2 device is omitted
from the placement.
y2
DDR2 Controller
y1
y1
x1
y2
PCB_DDR2_3
Figure 8-52. Device and DDR2 Device Placement
Table 8-34. Placement Specifications DDR2
NO.
PARAMETER
MIN
MAX
UNIT
KOD21
X1
2000
Mils
KOD22
Y1
500
Mils
KOD23
Y2
1300
Mils
4
W
(1)
KOD24
DDR2 keepout region
KOD25
Clearance from non-DDR2 signal to DDR2 keepout region (2) (3)
(1) DDR2 keepout region to encompass entire DDR2 routing area.
(2) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR2 and should be
separated by this specification.
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8.7.2.2.5 DDR2 Keepout Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in Figure 8-53. The size of this region varies with
the placement and DDR routing. Additional clearances required for the keepout region are shown in
Table 8-34.
DDR2 Controller
DDR2 Device
DDR2 Device
DDR2 Device
DDR2 Device
The region shown in Table 8-34 should encompass all the DDR2 circuitry and varies depending on
placement. Non-DDR2 signals should not be routed on the DDR signal layers within the DDR2 keepout
region. Non-DDR2 signals may be routed in the region, provided they are routed on layers separated from
DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this
region. In addition, the vdds_ddrx power plane should cover the entire keepout region. Routes for the two
DDR interfaces must be separated by at least 4x; the more separation, the better.
Device
PCB_DDR2_4
Figure 8-53. DDR2 Keepout Region
8.7.2.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 8-35 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 8-35. Bulk Bypass Capacitors
NO.
PARAMETER
BC21
vdds_ddrx bulk bypass capacitor (≥1µF) count
BC22
vdds_ddrx bulk bypass total capacitance
MIN
(1)
TYP
MAX
UNIT
1
Devices
22
μF
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the highspeed (HS) bypass capacitors and DDR2 signal routing.
8.7.2.2.7 High-Speed Bypass Capacitors
TI recommends that a PDN/power integrity analysis is performed to ensure that capacitor selection and
placement is optimal for a given implementation. This section provides guidelines that can serve as a
good starting point.
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High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-36 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. HS bypass capacitor value is < 1µF
3. Minimize the distance from the bypass cap to the pins/balls being bypassed.
4. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
5. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
6. Minimize via sharing. Note the limites on via sharing shown in Table 8-36.
Table 8-36. High-Speed Bypass Capacitors
NO.
PARAMETER
MIN
HS21
HS bypass capacitor package size(1)
HS22
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)
processor HS bypass capacitor count per vdds_ddrx rail
HS24
processor vdds_ddrx HS bypass capacitor total capacitance
MAX
UNIT
0402
10 Mils
400(12)
(12)
HS23
TYP
0201
See Table 8-3 and
(12)
(5)
Number of connection vias for each device power/ground ball
HS26
Trace length from device power/ground ball to connection via(2)
HS27
Distance, HS bypass capacitor to DDR device being bypassed(6)
HS28
Number of connection vias for each HS capacitor(8)(9)
4
HS29
DDR2 device HS bypass capacitor count(7)
12
HS210
DDR2 device HS bypass capacitor total capacitance
HS211
Trace length from bypass capacitor connect to connection via(2)(9)
HS212
Number of connection vias for each DDR2 device power/ground
ball(10)
HS213
Trace length from DDR2 device power/ground ball to connection
via(2)(8)
Mils
Devices
See Table 8-3 and (11)
HS25
(7)
(11)
μF
1
Vias
35
70
Mils
150
Mils
(14)
Vias
(13)
Devices
μF
0.85
35
100
1
Mils
Vias
35
60
Mils
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of vdds_ddrx balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR2 device power/ground ball to the center of the capacitor package.
(7) Per DDR2 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
(12) For more information, see Section 8.3, Core Power Domains
(13) For more information refer to DDR2 specification.
(14) Preferred configuration is 4 vias: 2 to power and 2 to ground.
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8.7.2.2.8 Net Classes
Table 8-37 lists the clock net classes for the DDR2 interface. Table 8-38 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 8-37. Clock Net Class Definitions
CLOCK NET CLASS
CK
PIN NAMES
ddrx_ck / ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
DQS1
ddrx_dqs1 / ddrx_dqsn1
(1)
ddrx_dqs2 / ddrx_dqsn2
DQS3(1)
ddrx_dqs3 / ddrx_dqsn3
DQS2
(1) Only used on 32-bit wide DDR2 memory systems.
Table 8-38. Signal Net Class Definitions
SIGNAL NET CLASS
ASSOCIATED CLOCK
NET CLASS
ADDR_CTRL
CK
DQ0
DQS0
ddrx_d[7:0], ddrx_dqm0
DQ1
DQS1
ddrx_d[15:8], ddrx_dqm1
DQ2(1)
DQS2
ddrx_d[23:16], ddrx_dqm2
DQ3(1)
DQS3
ddrx_d[31:24], ddrx_dqm3
PIN NAMES
ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
(1) Only used on 32-bit wide DDR2 memory systems.
8.7.2.2.9 DDR2 Signal Termination
Signal terminators are required in CK and ADDR_CTRL net classes. Serial terminators may be used on
data lines to reduce EMI risk; however, serial terminations are the only type permitted. ODTs are
integrated on the data byte net classes. They should be enabled to ensure signal integrity.Table 8-39
shows the specifications for the series terminators.
Table 8-39. DDR2 Signal Terminations
NO.
PARAMETER
MIN
ST21
CK net class(1)(2)
0
ST22
ADDR_CTRL net class(1)(2)(3)(4)
0
ST23
Data byte net classes (DQS0-DQS3, DQ0-DQ3)
(5)
0
TYP
22
MAX
UNIT
10
Ω
Zo
Ω
Zo
Ω
(1) Only series termination is permitted, parallel or SST specifically disallowed on board.
(2) Only required for EMI reduction.
(3) Terminator values larger than typical only recommended to address EMI issues.
(4) Termination value should be uniform across net class.
(5) No external terminations allowed for data byte net classes. ODT is to be used.
8.7.2.2.10 VREF Routing
VREF (ddrx_vref0) is used as a reference by the input buffers of the DDR2 memories as well as the
processor. VREF is intended to be half the DDR2 power supply voltage and should be created using a
resistive divider as shown in Figure 8-51. Other methods of creating VREF are not recommended.
Figure 8-54 shows the layout guidelines for VREF.
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VREF Bypass Capacitor
DDR2 Device
DDR2 Device
VREF Nominal Max Trace
width is 20 mils
DDR2 Controller
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
PCB_DDR2_5
Figure 8-54. VREF Routing and Topology
8.7.2.3
DDR2 CK and ADDR_CTRL Routing
B
DDR2 Device
DDR2 Device
Figure 8-55 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A =
(A'+A'') should be maximized.
C
A”
DDR2 Controller
T
A’
PCB_DDR2_6
Figure 8-55. CK and ADDR_CTRL Routing and Topology
Table 8-40. CK and ADDR_CTRL Routing Specification (1)
NO.
PARAMETER
RSC21
Center-to-center ddrx_ck - ddrx_nck spacing
RSC22
ddrx_ck / ddrx_nck skew(1)
RSC23
CK A-to-B/A-to-C skew mismatch
(2)
MIN
MAX
UNIT
2w
5
ps
10
ps
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Table 8-40. CK and ADDR_CTRL Routing Specification
NO.
(1)
(continued)
PARAMETER
MAX
UNIT
10
ps
CK/ADDR_CTRL trace length(4)
680
ps
RSC27
ADDR_CTRL-to-CK skew mismatch
25
ps
RSC28
ADDR_CTRL-to-ADDR_CTRL skew mismatch
25
ps
RSC29
Center-to-center ADDR_CTRL to other DDR2 trace spacing(3)
4w
RSC210
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(3)
3w
25
ps
25
ps
RSC24
CK B-to-C skew mismatch
RSC25
Center-to-center CK to other DDR2 trace spacing(3)
RSC26
RSC211
ADDR_CTRL A-to-B/A-to-C skew mismatch
RSC212
ADDR_CTRL B-to-C skew mismatch
MIN
4w
(2)
(1) The length of segment A = A' + A′′ as shown in Figure 8-55.
(2) Series terminator, if used, should be located closest to the Device.
(3) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) This is the longest routing length of the CK and ADDR_CTRL net classes.
(5) Length of A should be maximized.
DDR2 Device
DDR2 Device
Figure 8-56 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
E2
E3
E0
E1
DDR2 Controller
PCB_DDR2_7
Figure 8-56. DQS and DQ Routing and Topology
Table 8-41. DQS and DQ Routing Specification
NO.
PARAMETER
MIN
MAX
UNIT
5
ps
RSDQ21
Center-to-center DQS-DQSn spacing in E0|E1|E2|E3
RSDQ22
DQS-DQSn skew in E0|E1|E2|E3
2w
RSDQ23
Center-to-center DQS to other DDR2 trace spacing(1)
RSDQ24
DQS/DQ trace length (2)(3)(4)
325
ps
RSDQ25
DQ-to-DQS skew mismatch(2)(3)(4)
10
ps
RSDQ26
DQ-to-DQ skew mismatch(2)(3)(4)
10
ps
1
Vias
25
ps
4w
(2)(3)(4)
RSDQ27
DQ-to-DQ/DQS via count mismatch
RSDQ28
Center-to-center DQ to other DDR2 trace spacing(1)(5)
4w
RSDQ29
Center-to-center DQ to other DQ trace spacing(1)(6)(7)
3w
RSDQ210
DQ/DQS E skew mismatch(2)(3)(4)
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(1) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated
DQS (2 DQSs) per DDR EMIF used.
(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS
(4 DQSs) per DDR EMIF used.
(4) There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data
byte 1.
(5) DQs from other DQS domains are considered other DDR2 trace.
(6) DQs from other data bytes are considered other DDR2 trace.
(7) This is the longest routing distance of each of the DQS and DQ net classes.
8.7.3
DDR3 Board Design and Layout Guidelines
8.7.3.1
Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-42 and
Figure 8-57.
Table 8-42. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Controller
NO.
1
PARAMETER
tc(DDR_CLK)
Cycle time, DDR_CLK
MIN
MAX
UNIT
1.875
2.5(1)
ns
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
1
DDR_CLK
Figure 8-57. DDR3 Memory Controller Clock Timing
8.7.3.1.1 DDR3 versus DDR2
This specification only covers device PCB designs that use DDR3 memory. Designs using DDR2 memory
should use the PCB design specifications for DDR2 memory . While similar, the two memory systems
have different requirements. It is currently not possible to design one PCB that covers both DDR2 and
DDR3.
8.7.3.2
DDR3 EMIFs
The processor contains two separate DDR3 EMIFs. This specification covers one of these EMIFs (ddr1_*)
and, thus, needs to be implemented twice, once for each EMIF. The PCB layout generally turns out to be
a semi-mirror with ddr2_* being a flipped version of ddr1_*; the only exception being the DDR3 devices
themselves are not flipped unless mounted on opposite sides of the PCB. Requirements are identical
between the two EMIFs.
8.7.3.3
DDR3 Device Combinations
Because there are several possible combinations of device counts and single- or dual-side mounting,
Table 8-43 summarizes the supported device configurations.
Table 8-43. Supported DDR3 Device Combinations(1)
NUMBER OF DDR3 DEVICES
DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
16
N
16
2
8
Y(2)
16
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Table 8-43. Supported DDR3 Device Combinations(1) (continued)
NUMBER OF DDR3 DEVICES
DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
2
16
N
32
2
16
3
16
N
32
4
8
N
32
4
8
5
8
Y
(2)
Y
(3)
N
32
32
32
(1) This table is per EMIF.
(2) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
(3) This is two mirrored pairs of DDR3 devices.
8.7.3.4
DDR3 Interface Schematic
8.7.3.4.1 32-Bit DDR3 Interface
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR
devices look like two 8-bit devices. Figure 8-58 and Figure 8-59 show the schematic connections for 32-bit
interfaces using x16 devices.
8.7.3.4.2 16-Bit DDR3 Interface
Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-58
and Figure 8-59); only the high-word DDR memories are removed and the unused DQS inputs are tied off.
When not using all of part of a DDR interface, the proper method of handling the unused pins is to tie off
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these
signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection
against external electrical noise causing activity on the signals.
The vdds_ddrx and ddrx_vref0 power supply pins need to be connected to their respective power supplies
even if ddrx is not being used. All other DDR interface pins can be left unconnected. Note that the
supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.
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Figure 8-58. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices
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Figure 8-59. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Compatible JEDEC DDR3 Devices
Table 8-44 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1066 devices in the x8 or x16 widths.
Table 8-44. Compatible JEDEC DDR3 Devices (Per Interface)
N
O.
1
PARAMETER
CONDITION
JEDEC DDR3 device speed grade(1)
MIN
MAX
DDR clock rate = 400MHz
DDR3-800
DDR3-1600
400MHz< DDR clock rate ≤ 533MHz
DDR3-1066
DDR3-1600
UNIT
2
JEDEC DDR3 device bit width
x8
x16
Bits
3
JEDEC DDR3 device count(2)
2
4
Devices
(1) Refer to Table 8-42 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of
supported DDR clock rates.
(2) For valid DDR3 device configurations and device counts, see Section 8.7.3.4, Figure 8-58, and Figure 8-59.
8.7.3.6
PCB Stackup
The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in Table 8-45.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in
Table 8-46.
Table 8-45. Six-Layer PCB Stackup Suggestion
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly vertical
2
Plane
Ground
3
Plane
Split power plane
4
Plane
Split power plane or Internal routing
5
Plane
Ground
6
Signal
Bottom routing mostly horizontal
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Table 8-46. PCB Stackup Specifications
NO.
PARAMETER
MIN
PS1
PCB routing/plane layers
6
PS2
Signal routing layers
3
PS3
Full ground reference layers under DDR3 routing region(1)
TYP
MAX
1
(1)
PS4
Full 1.5-V power reference layers under the DDR3 routing region
PS5
Number of reference plane cuts allowed within DDR routing region(2)
0
PS6
Number of layers between DDR3 routing layer and reference plane(3)
0
PS7
PCB routing feature size
4
PS8
PCB trace width, w
4
PS9
Single-ended impedance, Zo
PS10
UNIT
(5)
Impedance control
1
50
Z-5
Z
Mils
Mils
75
Ω
Z+5
Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9.
8.7.3.7
Placement
Figure 8-60 shows the required placement for the processor as well as the DDR3 devices. The
dimensions for this figure are defined in Table 8-47. The placement does not restrict the side of the PCB
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3
devices are omitted from the placement.
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x3
x2
x1
y1
y2
y2
DDR3
Controller
y2
y2
y2
PCB_DDR3_3
Figure 8-60. Placement Specifications
Table 8-47. Placement Specifications DDR3
NO.
PARAMETER
MIN
MAX
UNIT
KOD31
X1
500
Mils
KOD32
X2
600
Mils
KOD33
X3
600
Mils
KOD34
Y1
1800
Mils
KOD35
Y2
600
Mils
KOD36
DDR3 keepout region (1)
KOD37
Clearance from non-DDR3 signal to DDR3 keepout region (2) (3)
4
W
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(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be
separated by this specification.
8.7.3.8
DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in Figure 8-61. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in Table 847. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.
Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the
DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this
region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the
two signals from the DDR3 controller should be separated from each other by the specification in Table 847, (see KOD37).
DDR3 Keepout Region
DDR3
Controller
PCB_DDR3_4
Figure 8-61. DDR3 Keepout Region
8.7.3.9
Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.
Table 8-48 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk
bypass capacitance may be needed for other circuitry.
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Table 8-48. Bulk Bypass Capacitors
NO.
PARAMETER
MIN
MAX
UNIT
1
vdds_ddrx bulk bypass capacitor count(1)
1
Devices
2
vdds_ddrx bulk bypass total capacitance
22
μF
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the highspeed (HS) bypass capacitors and DDR3 signal routing.
8.7.3.10 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-49 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in Table 8-49.
Table 8-49. High-Speed Bypass Capacitors
NO.
PARAMETER
MIN
1
HS bypass capacitor package size(1)
2
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)
3
processor HS bypass capacitor count per vdds_ddrx rail (12)
4
processor HS bypass capacitor total capacitance per vdds_ddrx rail (12)
TYP
MAX
UNIT
0201
0402
10 Mils
400
See Table 8-3 and (11)
Mils
Devices
See Table 8-3 and (11)
μF
(5)
5
Number of connection vias for each device power/ground ball
6
Trace length from device power/ground ball to connection via(2)
7
Distance, HS bypass capacitor to DDR device being bypassed
8
DDR3 device HS bypass capacitor count(7)
9
DDR3 device HS bypass capacitor total capacitance(7)
Vias
35
(6)
(8)(9)
10
Number of connection vias for each HS capacitor
11
Trace length from bypass capacitor connect to connection via(2)(9)
12
Number of connection vias for each DDR3 device power/ground ball(10)
13
Trace length from DDR3 device power/ground ball to connection via(2)(8)
70
Mils
150
Mils
12
Devices
0.85
μF
2
Vias
35
100
1
Mils
Vias
35
60
Mils
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
(12) For more information, see Section 8.3, Core Power Domains
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8.7.3.10.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Because these are returns for signal current, the signal via size may be used for these
capacitors.
8.7.3.11 Net Classes
Table 8-50 lists the clock net classes for the DDR3 interface. Table 8-51 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
Table 8-50. Clock Net Class Definitions
CLOCK NET CLASS
CK
processor PIN NAMES
ddrx_ck/ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
DQS1
ddrx_dqs1 / ddrx_dqsn1
(1)
ddrx_dqs2 / ddrx_dqsn2
DQS3(1)
ddrx_dqs3 / ddrx_dqsn3
DQS2
(1) Only used on 32-bit wide DDR3 memory systems.
Table 8-51. Signal Net Class Definitions
SIGNAL NET CLASS
ASSOCIATED CLOCK
NET CLASS
ADDR_CTRL
CK
DQ0
DQS0
ddrx_d[7:0], ddrx_dqm0
DQ1
DQS1
ddrx_d[15:8], ddrx_dqm1
DQ2(1)
DQS2
ddrx_d[23:16], ddrx_dqm2
DQ3(1)
DQS3
ddrx_d[31:24], ddrx_dqm3
processor PIN NAMES
ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
(1) Only used on 32-bit wide DDR3 memory systems.
8.7.3.12 DDR3 Signal Termination
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.
8.7.3.13 VREF_DDR Routing
ddrx_vref0 (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the
processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the
DDR3 VDDS and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF
bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing
congestion.
8.7.3.14 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.
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8.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in Table 8-52.
8.7.3.15.1 Four DDR3 Devices
Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one
bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two
pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
8.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
Figure 8-62 shows the topology of the CK net classes and Figure 8-63 shows the topology for the
corresponding ADDR_CTRL net classes.
+ –
+ –
+ –
+ –
AS+
AS-
AS+
AS-
AS+
AS-
AS+
AS-
DDR Differential CK Input Buffers
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
Processor
Differential Clock
Output Buffer
A2
A3
A3
A4
AT
Cac
+
–
Rcp
A1
A2
A3
A3
A4
0.1 µF
AT
Routed as Differential Pair
Figure 8-62. CK Topology for Four x8 DDR3 Devices
Processor
Address and Control
Output Buffer
A1
A2
A3
A4
AS
AS
AS
AS
DDR Address and Control Input Buffers
A3
Address and Control
Terminator
Rtt
Vtt
AT
Figure 8-63. ADDR_CTRL Topology for Four x8 DDR3 Devices
8.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
Figure 8-64 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-65
shows the corresponding ADDR_CTRL routing.
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DDR_1V5
A3
A3
=
A3
A3
A4
A4
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
A1
Figure 8-64. CK Routing for Four Single-Side DDR3 Devices
Rtt
A3
=
A4
A3
AT
Vtt
AS
A2
Figure 8-65. ADDR_CTRL Routing for Four Single-Side DDR3 Devices
To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of
increased routing and assembly complexity. Figure 8-66 and Figure 8-67 show the routing for CK and
ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.
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A1
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DDR_1V5
A3
A3
=
A3
A3
A4
A4
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
A1
Figure 8-66. CK Routing for Four Mirrored DDR3 Devices
Rtt
=
A4
A3
AT
Vtt
AS
A3
A2
Figure 8-67. ADDR_CTRL Routing for Four Mirrored DDR3 Devices
8.7.3.15.2 Two DDR3 Devices
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.
8.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 8-68 shows the topology of the CK net classes and Figure 8-69 shows the topology for the
corresponding ADDR_CTRL net classes.
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+ –
+ –
AS+
AS-
AS+
AS-
DDR Differential CK Input Buffers
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
Processor
Differential Clock
Output Buffer
A2
A3
AT
Cac
+
–
Rcp
A1
A2
A3
0.1 µF
AT
Routed as Differential Pair
Figure 8-68. CK Topology for Two DDR3 Devices
Processor
Address and Control
Output Buffer
A1
A2
AS
AS
DDR Address and Control Input Buffers
A3
Address and Control
Terminator
Rtt
Vtt
AT
Figure 8-69. ADDR_CTRL Topology for Two DDR3 Devices
8.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
Figure 8-70 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-71
shows the corresponding ADDR_CTRL routing.
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A1
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DDR_1V5
A3
A3
=
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
A1
Figure 8-70. CK Routing for Two Single-Side DDR3 Devices
Rtt
A3
=
AT
Vtt
AS
A2
Figure 8-71. ADDR_CTRL Routing for Two Single-Side DDR3 Devices
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. Figure 8-72 and Figure 8-73 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
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A1
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DDR_1V5
A3
A3
=
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
A1
Figure 8-72. CK Routing for Two Mirrored DDR3 Devices
Rtt
=
AT
Vtt
AS
A3
A2
Figure 8-73. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
8.7.3.15.3 One DDR3 Device
A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as
one bank (CS), 16 bits wide.
8.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
Figure 8-74 shows the topology of the CK net classes and Figure 8-75 shows the topology for the
corresponding ADDR_CTRL net classes.
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DDR Differential CK Input Buffer
AS+
AS-
+ –
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
Processor
Differential Clock
Output Buffer
A2
AT
Cac
+
–
Rcp
A1
A2
0.1 µF
AT
Routed as Differential Pair
Figure 8-74. CK Topology for One DDR3 Device
AS
DDR Address and Control Input Buffers
Processor
Address and Control
Output Buffer
A1
A2
Address and Control
Terminator
Rtt
AT
Vtt
Figure 8-75. ADDR_CTRL Topology for One DDR3 Device
8.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
Figure 8-76 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-77
shows the corresponding ADDR_CTRL routing.
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A1
A1
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
DDR_1V5
Rcp
Cac
Rcp
0.1 µF
AT
AT
=
AS+
AS-
A2
A2
A1
Figure 8-76. CK Routing for One DDR3 Device
Rtt
AT
=
Vtt
AS
A2
Figure 8-77. ADDR_CTRL Routing for One DDR3 Device
8.7.3.16 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return
currents to transition between reference planes if one of the reference planes is ground. The goal is to
minimize the size of the return current loops.
8.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-78
and Figure 8-79 show these topologies.
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Processor
DQS
IO Buffer
DDR
DQS
IO Buffer
DQSn+
DQSnRouted Differentially
n = 0, 1, 2, 3
Figure 8-78. DQS Topology
Processor
DQ and DM
IO Buffer
DDR
DQ and DM
IO Buffer
Dn
n = 0, 1, 2, 3
Figure 8-79. DQ/DM Topology
8.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
Figure 8-80 and Figure 8-81 show the DQS and DQ/DM routing.
DQSn+
DQSn-
DQS
Routed Differentially
n = 0, 1, 2, 3
Figure 8-80. DQS Routing With Any Number of Allowed DDR3 Devices
Dn
DQ and DM
n = 0, 1, 2, 3
Figure 8-81. DQ/DM Routing With Any Number of Allowed DDR3 Devices
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8.7.3.17 Routing Specification
8.7.3.17.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
Given the clock and address pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 8-82 and Figure 8-83 show
this distance for four loads and two loads, respectively. It is from this distance that the specifications on
the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly
for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net
class. For CK and ADDR_CTRL routing, these specifications are contained in Table 8-52.
(A)
A1
A8
CACLMY
CACLMX
A8
(A)
A8
(A)
A8
(A)
A8
(A)
Rtt
A3
=
A.
A4
A3
AT
Vtt
AS
A2
It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 8-82. CACLM for Four Address Loads on One Side of PCB
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(A)
A1
A8
CACLMY
CACLMX
A8
(A)
A8
(A)
Rtt
A3
=
A.
AT
Vtt
AS
A2
It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 8-83. CACLM for Two Address Loads on One Side of PCB
Table 8-52. CK and ADDR_CTRL Routing Specification(2)(3)
MAX
UNIT
CARS31
NO.
A1+A2 length
PARAMETER
MIN
TYP
500(1)
ps
CARS32
A1+A2 skew
29
ps
CARS33
A3 length
125
ps
CARS34
(4)
A3 skew
6
ps
CARS35
A3 skew(5)
6
ps
CARS36
A4 length
125
ps
CARS37
A4 skew
6
ps
CARS38
AS length
5(1)
17
ps
CARS39
AS skew
1.3(1)
14
ps
CARS310
AS+/AS- length
5
12
ps
CARS311
AS+/AS- skew
1
ps
CARS312
AT length(6)
75
ps
CARS313
AT skew(7)
14
ps
CARS314
(8)
AT skew
CARS315
CK/ADDR_CTRL trace length
CARS316
Vias per trace
CARS317
Via count difference
1
(9)
CARS318
Center-to-center CK to other DDR3 trace spacing
CARS319
Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)
4w
CARS320
Center-to-center ADDR_CTRL to other ADDR_CTRL trace
spacing(9)
3w
CARS321
CK center-to-center spacing(11)(12)
ps
3(1)
vias
1(15)
vias
4w
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1020
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Table 8-52. CK and ADDR_CTRL Routing Specification(2)(3) (continued)
NO.
PARAMETER
CARS322
CK spacing to other net(9)
CARS323
Rcp(13)
CARS324
Rtt(13)(14)
MIN
TYP
MAX
UNIT
Zo-1
Zo
Zo+1
Ω
Zo-5
Zo
Zo+5
Ω
4w
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rice time and fall time confirms desired operation.
(2) The use of vias should be minimized.
(3) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump
between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.
(4) Non-mirrored configuration (all DDR3 memories on same side of PCB).
(5) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(6) While this length can be increased for convenience, its length should be minimized.
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(8) CK net class only.
(9) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
(11) CK spacing set to ensure proper differential impedance.
(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.
(15) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
8.7.3.17.2 DQS and DQ Routing Specification
Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,
a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as
DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four
DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.
NOTE
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.
Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 8-84 shows this distance for
four loads. It is from this distance that the specifications on the lengths of the transmission lines for the
data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-53.
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DQLMX0
DB0
DB1
DQ[0:7]/DM0/DQS0
DQ[8:15]/DM1/DQS1
DQLMX1
DQ[16:23]/DM2/DQS2
DB2
DQLMY0
DQLMX2
DQLMY3
DQLMY2
DB3
DQLMY1
DQ[23:31]/DM3/DQS3
DQLMX3
3
2
1
0
DB0 - DB3 represent data bytes 0 - 3.
There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3
Figure 8-84. DQLM for Any Number of Allowed DDR3 Devices
Table 8-53. Data Routing Specification(2)
MAX
UNIT
DRS31
NO.
DB0 length
PARAMETER
MIN
340
ps
DRS32
DB1 length
340
ps
DRS33
DB2 length
340
ps
DRS34
DB3 length
340
ps
DRS35
DBn skew(3)
5
ps
DRS36
DQSn+ to DQSn- skew
1
ps
DRS37
DQSn to DBn skew(3)(4)
5(10)
ps
DRS38
Vias per trace
2(1)
vias
DRS39
Via count difference
0(10)
vias
(6)
DRS310
Center-to-center DBn to other DDR3 trace spacing
DRS311
Center-to-center DBn to other DBn trace spacing
(7)
DRS312
DQSn center-to-center spacing(8) (9)
DRS313
DQSn center-to-center spacing to other net
TYP
4
w(5)
3
w(5)
4
w(5)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rice time and fall time confirms desired operation.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(4) Each DQS pair is length matched to its associated byte.
(5) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(6) Other DDR3 trace spacing means other DDR3 net classes not within the byte.
(7) This applies to spacing within the net classes of a byte.
(8) DQS pair spacing is set to ensure proper differential impedance.
(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.
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9 Device and Documentation Support
TI offers an extensive line of development tools, including methods to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules as listed below.
9.1
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, DRA7xx). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
For orderable part numbers of DRA7xx devices in the ABC package type, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the Silicon Errata (literature
number SPRZ398).
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9.1.1
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
Standard Package Symbolization
JACINTO
aBBBBBBrzYyPPPQ1
XXXXXXX
PIN ONE INDICATOR
842
PPP G1
O
SWPS857_PACK_01
Figure 9-1. Printed Device Reference
NOTE
Some devices have a cosmetic circular marking visible on the top of the device package
which results from the production test process. These markings are cosmetic only with no
reliability impact.
9.1.2
Device Naming Convention
Table 9-1. Nomenclature Description
FIELD PARAMETER
a
BBBBBB
r
z
FIELD DESCRIPTION
Device evolution
stage(1)
Base production part
number
Device revision
Device Speed
VALUE
DESCRIPTION
X
Prototype
P
Preproduction (production test flow, no reliability data)
BLANK
Production
DRA744
J6 Low Tier
DRA745
J6 Mid Tier
DRA746
J6 High Tier
DRA750
J6EP Low Tier
DRA751
J6EP Mid Tier
DRA752
J6EP High Tier
DRA754
J6EX Low Tier
DRA755
J6EX Mid Tier
DRA756
J6EX High Tier
BLANK
SR 1.0
A
SR 1.1
B
SR 2.0
P
High speed grade
L
Overdrive speed grade
J
Nominal speed grade
OTHER
Alternate speed grade
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Table 9-1. Nomenclature Description (continued)
FIELD PARAMETER
Yy
FIELD DESCRIPTION
Device type
PPP
Package designator
Q1
Automotive Designator
VALUE
General purpose (Prototype and Production)
E
Emulation (E) devices
D
High security prototype devices with TI Development keys (D)
Yn
Letter followed by number indicates HS Device with customer key
ABC
BLANK
Q1
XXXXXXX
842
DESCRIPTION
G
ABC S-PBGA-N760 (23mm x 23mm) Package
not meeting automotive qualification
meeting Q100 equal requirements, with exceptions as specified in DM.
Lot Trace Code
Production Code, For TI use only
O
Pin one designator
G1
ECAT—Green package designator
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent
evolutionary stages of product development from engineering prototypes through fully qualified production devices.
Prototype devices are shipped against the following disclaimer:
“This product is still in development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of
merchantability of fitness for a specific purpose, of this device.
NOTE
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
9.2
Tools and Software
The following products support development for DRA7xx platforms:
DRA75xx Pad Configuration Tool is an interactive pad-configuration tool that allows the user to
visualize the device pad configuration state on power-on reset and then customize the configuration of
the pads for the specific use-case and identify the device register settings associated to that
configuration.
DRA7xx Register Descriptor Tool is an interactive device register configuration tool that allows users
to visualize the register state on power-on reset, and then customize the configuration of the device for
the specific use-case.
DRA7xx Clock Tree Tool is interactive clock tree configuration software that allows the user to
visualize the device clock tree, interact with clock tree elements and view the effect on PRCM
registers, interact with the PRCM registers and view the effect on the device clock tree, and view a
trace of all the device registers affected by the user interaction with the clock tree.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office
or authorized distributor.
9.3
Documentation Support
The following documents describe the DRA75x/DRA74x devices.
436
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SPRUHI2DRA75x, DRA74x Infotainment Applications Processor Technical Reference
Manual Details the integration, the environment, the functional description, and the
programming models for each peripheral and subsystem in the DRA7xx family of devices.
Errata
DRA75x, DRA74x Silicon Errata Describes known advisories on silicon and provides
workarounds.
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9.3.1
SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be
required to take whatever measures may be required to correct this interference.
9.3.2
Information About Cautions and Warnings
This book may contain cautions and warnings.
CAUTION
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your
software or equipment.
WARNING
This is an example of a warning statement.
A warning statement describes a situation that could potentially cause
harm to you.
The information in a caution or a warning is provided for your protection. Please read each caution and
warning carefully.
9.4
Receiving Notification of Documentation Updates
To receive notification of documentation updates — including silicon errata — go to the product folder for
your device on www.ti.com. In the upper right-hand corner, click the "Alert me" button. This registers you
to receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document.
9.5
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9-2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DRA744
Click here
Click here
Click here
Click here
Click here
DRA745
Click here
Click here
Click here
Click here
Click here
DRA746
Click here
Click here
Click here
Click here
Click here
DRA750
Click here
Click here
Click here
Click here
Click here
DRA751
Click here
Click here
Click here
Click here
Click here
DRA752
Click here
Click here
Click here
Click here
Click here
DRA754
Click here
Click here
Click here
Click here
Click here
DRA755
Click here
Click here
Click here
Click here
Click here
DRA756
Click here
Click here
Click here
Click here
Click here
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9.6
www.ti.com
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki.
Established to help developers get started with Embedded Processors from Texas
Instruments and to foster innovation and growth of general knowledge about the hardware
and software surrounding these devices.
9.7
Trademarks
C66x, ICEPick and SmartReflex are trademarks of Texas Instruments Incorporated.
ARM is a registered trademark of ARM Limited.
ETB, ARM9, CoreSight, Cortex, and Neon are trademarks of ARM Limited.
HDMI is a trademark of HDMI Licensing, LLC.
HDQ is a trademark of Benchmarq.
1-Wire is a registered trademark of Dallas Semiconductor.
POWERVR and SGX544 are trademarks or registered trademarks of Imagination Technologies Ltd.
SD is a registered trademark of Toshiba Corporation.
MMC and eMMC are trademarks of MultiMediaCard Association.
JTAG is a registered trademark of JTAG Technologies, Inc.
PCI-Express is a registered trademark of PCI-SIG.
MediaLB is a trademark of Standard Microsystems Corporation.
Vivante is a registered trademark of Vivante Corporation.
All other trademarks are the property of their respective owners.
9.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
9.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
438
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DRA754, DRA755, DRA756
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SPRS950A – DECEMBER 2015 – REVISED APRIL 2016
10 Mechanical Packaging and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10.1 Mechanical Data
Figure 10-1. Mechanical Package
Mechanical Packaging and Orderable Information
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Product Folder Links: DRA744 DRA745 DRA746 DRA750 DRA751 DRA752 DRA754 DRA755 DRA756
Copyright © 2015–2016, Texas Instruments Incorporated
439
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRA744BJGABCQ1
PREVIEW
FCBGA
ABC
760
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-250C-168 HR
DRA744BJGABCQ1
JACINTOTM
DRA744BJGABCRQ1
PREVIEW
FCBGA
ABC
760
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-250C-168 HR
DRA744BJGABCQ1
JACINTOTM
DRA745BLGABCQ1
PREVIEW
XCEPT
BGA
760
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-250C-168 HR
-40 to 125
DRA745BLGABCQ1
JACINTOTM
DRA745BLGABCRQ1
PREVIEW
XCEPT
BGA
760
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-250C-168 HR
-40 to 125
DRA745BLGABCQ1
JACINTOTM
DRA746APGABCQ1
ACTIVE
FCBGA
ABC
760
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-250C-168 HR
DRA746APGABCQ1
JACINTO
DRA746BPGABCQ1
PREVIEW
FCBGA
ABC
760
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-250C-168 HR
DRA746BPGABCQ1
JACINTOTM
DRA746BPGABCRQ1
PREVIEW
FCBGA
ABC
760
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-250C-168 HR
DRA746BPGABCQ1
JACINTOTM
DRA750BJGABCQ1
PREVIEW
XCEPT
BGA
760
TBD
Call TI
Call TI
-40 to 125
DRA750BJGABCRQ1
PREVIEW
XCEPT
BGA
760
TBD
Call TI
Call TI
-40 to 125
DRA752BPGABCQ1
PREVIEW
XCEPT
BGA
760
TBD
Call TI
Call TI
-40 to 125
DRA752BPGABCRQ1
PREVIEW
XCEPT
BGA
760
TBD
Call TI
Call TI
-40 to 125
DRA754BJGABCQ1
PREVIEW
XCEPT
BGA
760
TBD
Call TI
Call TI
-40 to 125
DRA754BJGABCRQ1
PREVIEW
XCEPT
BGA
760
TBD
Call TI
Call TI
-40 to 125
DRA755BLGABCQ1
PREVIEW
XCEPT
BGA
760
TBD
Call TI
Call TI
-40 to 125
DRA755BLGABCRQ1
PREVIEW
XCEPT
BGA
760
TBD
Call TI
Call TI
-40 to 125
DRA756
ACTIVE
TBD
Call TI
Call TI
DRA756BPGABCQ1
PREVIEW
FCBGA
ABC
760
60
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-250C-168 HR
-40 to 125
DRA756BPGABCQ1
JACINTOTM
DRA756BPGABCRQ1
PREVIEW
FCBGA
ABC
760
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-250C-168 HR
-40 to 125
DRA756BPGABCQ1
JACINTOTM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jul-2016
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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