TI1 M38510/65002B2A Triple 3-input positive-nand gate Datasheet

 SCLS083D − DECEMBER 1982 − REVISED AUGUST 2003
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 20-µA Max ICC
SN54HC10 . . . J OR W PACKAGE
SN74HC10 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
1B
1A
NC
VCC
1C
SN54HC10 . . . FK PACKAGE
(TOP VIEW)
VCC
1C
1Y
3C
3B
3A
3Y
2A
NC
2B
NC
2C
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1Y
NC
3C
NC
3B
2Y
GND
NC
3Y
3A
1A
1B
2A
2B
2C
2Y
GND
D Typical tpd = 9 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
NC − No internal connection
description/ordering information
The ’HC10 devices contain three independent 3-input NAND gates. They perform the Boolean function
Y = A • B • C or Y = A + B + C in positive logic.
ORDERING INFORMATION
PACKAGE†
TA
PDIP − N
SN74HC10N
Tube of 50
SN74HC10D
Reel of 2500
SN74HC10DR
Reel of 250
SN74HC10DT
SOP − NS
Reel of 2000
SN74HC10NSR
HC10
SSOP − DB
Reel of 2000
SN74HC10DBR
HC10
Tube of 90
SN74HC10PW
Reel of 2000
SN74HC10PWR
Reel of 250
SN74HC10PWT
CDIP − J
Tube of 25
SNJ54HC10J
SNJ54HC10J
CFP − W
Tube of 150
SNJ54HC10W
SNJ54HC10W
LCCC − FK
Tube of 55
SNJ54HC10FK
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Tube of 25
SOIC − D
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
SN74HC10N
HC10
HC10
SNJ54HC10FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
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&)$#!" #&(! ! 0 12 (( &%!%" % !%"!%)
$(%"" !+%-"% !%)* (( !+% &)$#!" &)$#!
&#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"*
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS083D − DECEMBER 1982 − REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
A
B
C
OUTPUT
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
X
L
H
logic diagram (positive logic)
A
B
C
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS083D − DECEMBER 1982 − REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC10
VCC
Supply voltage
VIH
VCC = 2 V
VCC = 4.5 V
High-level input voltage
VCC = 6 V
VCC = 2 V
VIL
VI
VO
Input voltage
NOM
MAX
2
5
6
NOM
MAX
2
5
6
1.5
3.15
3.15
4.2
4.2
0
VCC = 6 V
UNIT
V
V
0.5
0.5
1.35
1.35
1.8
1.8
VCC
VCC
VCC = 2 V
VCC = 4.5 V
Input transition rise/fall time
MIN
1.5
0
Output voltage
∆t/∆v
MIN
VCC = 4.5 V
VCC = 6 V
Low-level input voltage
SN74HC10
0
VCC
VCC
0
1000
1000
500
500
400
400
V
V
V
ns
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
Ci
SN54HC10
SN74HC10
MIN
MIN
MAX
MAX
UNIT
2V
1.9
1.998
1.9
1.9
IOH = −20 µA
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
IOH = −4 mA
IOH = −5.2 mA
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 µA
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
2
40
20
µA
10
10
10
pF
VI = VIH or VIL
VI = VIH or VIL
VI = VCC or 0
VI = VCC or 0,
TA = 25°C
MIN
TYP
MAX
4.5 V
IOL = 4 mA
IOL = 5.2 mA
II
ICC
VCC
IO = 0
6V
2 V to 6 V
POST OFFICE BOX 655303
3
• DALLAS, TEXAS 75265
V
V
3
SCLS083D − DECEMBER 1982 − REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
SN54HC10
SN74HC10
MIN
MIN
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
35
95
145
120
tpd
A, B, or C
Y
4.5 V
10
19
29
24
6V
9
16
25
20
tt
Y
MIN
MAX
MAX
2V
23
75
110
95
4.5 V
6
15
22
19
6V
5
13
19
16
UNIT
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
No load
TYP
UNIT
25
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
Input
VCC
50%
50%
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
50%
10%
tPHL
90%
90%
tr
Input
50%
10%
90%
90%
tr
tPHL
VCC
50%
10% 0 V
Out-of-Phase
Output
90%
tf
VOH
50%
10%
VOL
tf
tPLH
50%
10%
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-8403801VCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
84038012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84038012A
SNJ54HC
10FK
8403801CA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8403801CA
SNJ54HC10J
8403801DA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8403801DA
SNJ54HC10W
JM38510/65002B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
65002B2A
JM38510/65002BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65002BCA
M38510/65002B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
65002B2A
M38510/65002BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65002BCA
SN54HC10J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54HC10J
SN74HC10D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10DT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
Addendum-Page 1
5962-8403801VC
A
SNV54HC10J
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
SN74HC10N
ACTIVE
PDIP
N
14
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
Device Marking
(4/5)
SN74HC10N
SN74HC10N3
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
-40 to 85
SN74HC10NE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC10N
SN74HC10NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10NSRE4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10PWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10PWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SN74HC10PWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC10
SNJ54HC10FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84038012A
SNJ54HC
10FK
SNJ54HC10J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8403801CA
SNJ54HC10J
SNJ54HC10W
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8403801DA
SNJ54HC10W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC10, SN54HC10-SP, SN74HC10 :
• Catalog: SN74HC10, SN54HC10
• Automotive: SN74HC10-Q1, SN74HC10-Q1
• Enhanced Product: SN74HC10-EP, SN74HC10-EP
• Military: SN54HC10
• Space: SN54HC10-SP
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74HC10DR
SOIC
D
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
6.5
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.0
2.1
8.0
16.0
Q1
SN74HC10DT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HC10NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74HC10PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74HC10PWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HC10DR
SOIC
D
14
2500
367.0
367.0
38.0
SN74HC10DT
SOIC
D
14
250
367.0
367.0
38.0
SN74HC10NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74HC10PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74HC10PWT
TSSOP
PW
14
250
367.0
367.0
35.0
Pack Materials-Page 2
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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