TI1 LMK04816 Low-noise clock jitter cleaner with dual loop pll Datasheet

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LMK04816
Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK04816 Evaluation Board Operating Instructions
Texas Instruments
June 2012
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Table of Contents
TABLE OF CONTENTS.............................................................................................................................................. 2
GENERAL DESCRIPTION .......................................................................................................................................... 4
EVALUATION BOARD KIT CONTENTS ..................................................................................................................................4
AVAILABLE LMK04816 EVALUATION BOARDS ....................................................................................................................4
AVAILABLE LMK04816 FAMILY DEVICES ...........................................................................................................................4
QUICK START ......................................................................................................................................................... 5
DEFAULT CODELOADER MODES FOR EVALUATION BOARDS....................................................................................................6
EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04816 ............................................................................. 7
1. START CODELOADER 4 APPLICATION..............................................................................................................................7
2. SELECT DEVICE ..........................................................................................................................................................7
3. PROGRAM/LOAD DEVICE.............................................................................................................................................8
4. RESTORING A DEFAULT MODE ......................................................................................................................................8
5. VISUAL CONFIRMATION OF FREQUENCY LOCK ..................................................................................................................9
6. ENABLE CLOCK OUTPUTS .............................................................................................................................................9
PLL LOOP FILTERS AND LOOP PARAMETERS......................................................................................................... 11
PLL 1 LOOP FILTER ......................................................................................................................................................11
122.88 MHz VCXO PLL ........................................................................................................................................11
PLL2 LOOP FILTER .......................................................................................................................................................12
EVALUATION BOARD INPUTS AND OUTPUTS ....................................................................................................... 13
RECOMMENDED TEST EQUIPMENT...................................................................................................................... 21
PROGRAMMING 0-DELAY MODE IN CODELOADER .............................................................................................. 22
OVERVIEW..................................................................................................................................................................22
DUAL LOOP 0-DELAY MODE EXAMPLES ...........................................................................................................................22
Programming Steps ............................................................................................................................................22
Details ................................................................................................................................................................22
SINGLE LOOP 0-DELAY MODE EXAMPLES .........................................................................................................................24
Programming Steps ............................................................................................................................................24
Details ................................................................................................................................................................24
APPENDIX A: CODELOADER USAGE ...................................................................................................................... 26
PORT SETUP TAB .........................................................................................................................................................26
CLOCK OUTPUTS TAB ...................................................................................................................................................27
PLL1 TAB...................................................................................................................................................................29
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency .......................................................................30
PLL2 TAB...................................................................................................................................................................31
BITS/PINS TAB ............................................................................................................................................................32
REGISTERS TAB ............................................................................................................................................................37
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ................................................................................. 38
PLL1 .........................................................................................................................................................................38
122.88 MHz VCXO Phase Noise ..........................................................................................................................38
Clock Output Measurement Technique ..............................................................................................................39
Buffered Phase Noise .........................................................................................................................................39
CLOCK OUTPUTS (CLKOUT) ...........................................................................................................................................40
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LMK04816B CLKout Phase Noise ........................................................................................................................40
LMK04816B OSCout Phase Noise .......................................................................................................................41
APPENDIX C: SCHEMATICS ................................................................................................................................... 43
POWER SUPPLIES .........................................................................................................................................................43
LMK04816B DEVICE WITH LOOP FILTER AND CRYSTAL CIRCUITS .........................................................................................44
REFERENCE INPUTS (CLKIN0, CLKIN1, & CLKIN2), EXTERNAL VCXO (OSCIN) & VCO CIRCUITS ...............................................45
CLOCK OUTPUTS (OSCOUT0, CLKOUT0 TO CLKOUT3) ......................................................................................................46
CLOCK OUTPUTS (CLKOUT4 TO CLKOUT7) ......................................................................................................................47
CLOCK OUTPUTS (CLKOUT8 TO CLKOUT11) ....................................................................................................................48
UWIRE HEADER, LOGIC I/O PORTS AND STATUS LEDS........................................................................................................ 49
USB INTERFACE...........................................................................................................................................................50
APPENDIX D: BILL OF MATERIALS ........................................................................................................................ 51
APPENDIX E: PCB LAYERS STACKUP ..................................................................................................................... 56
APPENDIX F: PCB LAYOUT .................................................................................................................................... 57
LAYER #1 – TOP ..........................................................................................................................................................57
LAYER #2 – RF GROUND PLANE (INVERTED) .....................................................................................................................58
LAYER #3 – VCC PLANES ...............................................................................................................................................59
LAYER #4 – GROUND PLANE (INVERTED)..........................................................................................................................60
LAYER # 5 – VCC PLANES 2............................................................................................................................................61
LAYER #6 – BOTTOM....................................................................................................................................................62
LAYERS #1 AND 6 – TOP AND BOTTOM (COMPOSITE) .........................................................................................................63
APPENDIX G: PROPERLY CONFIGURING LPT PORT ............................................................................................... 65
LPT DRIVER LOADING ...................................................................................................................................................65
CORRECT LPT PORT/ADDRESS .......................................................................................................................................65
CORRECT LPT MODE ....................................................................................................................................................66
APPENDIX H: TROUBLESHOOTING INFORMATION ............................................................................................... 67
1)
2)
3)
CONFIRM COMMUNICATIONS ...............................................................................................................................67
CONFIRM PLL1 OPERATION/LOCKING ....................................................................................................................67
CONFIRM PLL2 OPERATION/LOCKING ....................................................................................................................68
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General Description
The LMK04816 Evaluation Board simplifies evaluation of the LMK04816B Low-Noise Clock
Jitter Cleaner with Dual Loop PLLs. Texas Instruments‟s CodeLoader software can be used to
program the internal registers of the LMK04816B device through the MICROWIRETM interface.
The CodeLoader software will run on a Windows 2000 or Windows XP PC and can be
downloaded from http://www.ti.com/tool/codeloader/.
Evaluation Board Kit Contents
The evaluation board kit includes:
(1) LMK04816 Evaluation Board from Table 1
(1) CodeLoader uWire cable (LPT  uWire)
Available LMK04816 Evaluation Boards
The LMK04816 Evaluation Board supports any of the four devices offered in the LMK04816
Family. A commercial-quality VCXO is also mounted to the board to provide a known
reference point for evaluating device performance and functionality.
Table 1: Available Evaluation Board Configurations
Evaluation Board ID
Device
LMK04816BEVAL
LMK04816B
PLL1 VCXO
122.88 MHz Crystek VCXO
Model CVHD-950-122.880
Available LMK04816 Family Devices
Table 2: LMK04816B Devices
Device
Reference
Inputs
LMK04816B
3
Buffered/
Divided
OSCin
Outputs
1
4
Programmable
LVDS/LVPECL/
LVCMOS
Outputs
12
VCO Frequency
2370 to 2600 MHz
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Quick Start
Full evaluation board instructions are downloadable from the LMK04816B device product folder
at www.ti.com.
1. Connect a power supply voltage of 5 V to the Vcc SMA connector. The onboard
LP3878-ADJ LDO regulator will output a low-noise 3.3 V supply to operate the device.
2. Connect a reference clock from a signal source to the CLKin1 SMA port. Use 122.88
MHz for default. The reference frequency depends on the device programming.
3. Connect the uWire header to a PC parallel port using the CodeLoader cable. A USB
interface is also available (search for “USB2UWIRE-IFACE” at www.ti.com).
4. Program the device with a default mode using CodeLoader. Ctrl+L must be pressed at
least once to load all registers. Alternatively click menu “Keyboard Controls”  “Load
Device”. CodeLoader can be downloaded from www.ti.com/tool/codeloader/.
5. Measurements may be made on an active output clock port via its SMA connector.
5.0 V
CLKout0
CLKout0*
Power
CLKout2
CLKout2*
1
5.0 V
3.3 V
(LDO)
CL
CL Kou
Ko t4
ut4
*
Factory default is LDO is used.
Customer may reconfigure to
power LMK directly.
*
t1 0
o u t1 0
K
CL Kou
CL
LMK04816
uWire
header
OSCout0
OSCout0*
0
Kin
C L n0 *
Ki
CL in2
K
C L n 2*
Ki
CL
Reference clock from
signal generator or other
external source.
122.88 MHz
(Default)
2
CL
CL Kou
Ko t8
u t8
*
CL
CL Kout
Ko 6*
u t6
Parallel Port Ribbon Cable
C
i n1
LK
4
Program with CodeLoader
Be sure to press ‘Ctrl - L’
Reference
3
Parallel Port
Connector
Laptop or PC
Figure 1: Quick Start Diagram
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Default CodeLoader Modes for Evaluation Boards
CodeLoader saves the state of the selected LMK04816B device when exiting the software. To
ensure a common starting point, the following modes listed in Table 3 may be restored by
clicking “Mode” and selecting the appropriate device configuration, as shown in Figure 2 in the
case of the LMK04816 device. Similar default modes are available for each LMK04816B
device in CodeLoader. Choose a mode with CLKin0 for differential clock signal or CLKin1 for a
single ended signal.
Figure 2: Selecting a Default Mode for the LMK04816 Device
After restoring a default mode, press Ctrl+L to program the device. The default modes also
disable certain outputs, so make sure to enable the output under test to make measurements.
Table 3: Default CodeLoader Modes for LMK04816
Default CodeLoader Mode
122.88 MHz CLKin1, 122.88 MHz
VCXO
122.88 MHz CLKin1, Dual Loop 0delay, 122.88 MHz VCXO
122.88 MHz CLKin1, 122.88 MHz
VCXO
122.88 MHz CLKin1, 122.88 MHz
VCXO
122.88 MHz CLKin1, Dual Loop 0delay, 122.88 MHz VCXO
122.88 MHz CLKin1, 122.88 MHz
VCXO
Device Mode
CLKin
Frequency
OSCin
Frequency
Dual PLL, Internal VCO
122.88 MHz
122.88 MHz
122.88 MHz
122.88 MHz
122.88 MHz
20.48 MHz
122.88 MHz
122.88 MHz
122.88 MHz
122.88 MHz
122.88 MHz
20.48 MHz
Dual PLL, Internal VCO,
0-Delay with Internal
Feedback
Dual PLL, Internal VCO,
PLL2 Crystal Oscillator
Enabled
Dual PLL, Internal VCO
Dual PLL, Internal VCO,
0-Delay with Internal
Feedback
Dual PLL, Internal VCO,
PLL2 Crystal Oscillator
Enabled
The next section outlines step-by-step procedures for using the evaluation board with the
LMK04816. For boards with another part number, make sure to select the corresponding part
number under the “Device” menu.
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Example: Using CodeLoader to Program the LMK04816
The purpose of this section is to walk the user through using CodeLoader 4 to make some
measurements with the LMK04816 device as an example. For more information on CodeLoader
refer to Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader/.
Before proceeding, be sure to follow the Quick Start section above to ensure proper connections.
1. Start CodeLoader 4 Application
Click “Start”  “Programs”  “CodeLoader 4”  “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
2. Select Device
Click “Select Device”  “Clock Conditioners”  “LMK04816”
Once started CodeLoader 4 will load the last used device. To load a new device click “Select
Device” from the menu bar, then select the subgroup and finally device to load. For this
example, the LMK04816B is chosen. Selecting the device does cause the device to be
programmed.
Figure 3 – Selecting the LMK04816B device
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3. Program/Load Device
Assuming the Port Setup settings are correct, press the
“Ctrl+L” shortcut or click “Keyboard Controls” 
“Load Device” from the menu to program the device to
the current state of the newly loaded LMK04816 file.
Figure 4 – Loading the Device
Once the device has been initially loaded, CodeLoader
will automatically program changed registers so it is
not necessary to re-load the device upon subsequent
changes in the device configuration. It is possible to disable this functionality by ensuring there
is no checkmark by the “Options”  “AutoReload with Changes.”
Because a default mode will be restored in the next step, this step isn‟t really needed but included
to emphasize the importance of pressing “Ctrl+L” to load the device at least once after starting
CodeLoader, restoring a mode, or restoring a saved setup using the File menu.
See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader/ for more information on Port Setup. Appendix H:
Troubleshooting Information contains information on troubleshooting communications.
4. Restoring a Default Mode
Click “Mode”  “LMK04816, 122.88 MHz VCXO, 122.88 MHz CLKin1”; then press Ctrl+L.
Figure 5: Setting the Default mode for LMK04816
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting
point. This is important because when CodeLoader is closed, it remembers the last settings used
for a particular device. Again, remember to press Ctrl+L as the first step after loading a default
mode.
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5. Visual Confirmation of Frequency Lock
After a default mode is restored and loaded, LED D5 should illuminate when PLL1 and PLL2
are locked to the reference clock applied to CLKin1. This assumes LD_MUX = PLL1/2 DLD
and LD_TYPE = Active High, which are the default settings.
6. Enable Clock Outputs
While the LMK04816B offers programmable clock output buffer formats, the evaluation board
is shipped with preconfigured output terminations to match the default buffer type for each
output. Refer to the CLKout port description in the Evaluation Board Inputs and Outputs section.
To measure phase noise at one of the clock outputs, for example, CLKout0:
1. Click on the Clock Outputs tab,
2. Uncheck “Powerdown” in the Digital Delay box to enable the channel,
3. Set the following settings as needed:
a. Digital Delay value
b. Clock Divider value
c. Analog Delay select and Analog Delay value (if not “Bypassed”)
d. Clock Output type.
Figure 6: Setting Digital Delay, Clock Divider, Analog Delay, and Output Format for CLKout0
4. Depending on the configured output type, the clock output SMAs can be interfaced to a
test instrument with a single-ended 50-ohm input as follows.
a. For LVDS:
i. A balun (like ADT2-1T) is recommended for differential-to-single-ended
conversion.
b. For LVPECL:
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50-ohm load and
the other side can be run single-ended to the instrument.
c. For LVCMOS:
i. There are two single-ended outputs,
CLKoutX and CLKoutX*, and each
output can be set to Normal, Inverted, or
Off. There are nine (9) combinations of
LVCMOS modes in the Clock Output list.
ii. One side of the LVCMOS signal can be
terminated with a 50-ohm load and the
other side can be run single-ended to the
instrument.
iii. A balun may also be used. Ensure
Figure 7: Setting LVCMOS modes
CLKoutX and CLKoutX* states are
complementary to each other, i.e.:
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Norm/Inv or Inv/Norm.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
National‟s Clock Design Tool can be used to calculate divider values to achieve desired clock
output frequencies. See: http://www.ti.com/tool/codeloader/.
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PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL‟s
purpose is to substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for
the phase noise of a “dirty” reference clock. The first PLL is typically configured with a narrow
loop bandwidth in order to minimize the impact of the reference clock phase noise. The reference
clock consequently serves only as a frequency reference rather than a phase reference.
The loop filters on the LMK04816 evaluation board are setup using the approach above. The
loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop
filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop
bandwidth values depend on the phase noise performance of the oscillator mounted on the board.
The following tables contain the parameters for PLL1 and PLL2 for each oscillator option.
National‟s Clock Design Tool can be used to optimize PLL phase noise/jitter for given
specifications. See: http://www.ti.com/tool/codeloader/.
PLL 1 Loop Filter
Table 4: PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO
122.88 MHz VCXO PLL
Phase Margin
49˚
Kφ (Charge Pump)
100 uA
Loop Bandwidth
12 Hz
Phase Detector Freq
VCO Gain
1.024 MHz
2.5 kHz/Volt
Reference Clock
Frequency
122.88 MHz
Output Frequency
122.88 MHz (To PLL 2)
Loop Filter
Components
C1_A1 = 100 nF
C2_A1 = 680 nF
R2_A1 = 39 kΩ
Note: PLL Loop Bandwidth is a function of K , Kvco, N as well as loop components. Changing
K and N will change the loop bandwidth.
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PLL2 Loop Filter
Table 5: PLL2 Loop Filter Parameters for LMK04816B
C1_A2
C2_A2
C3 (internal)
C4 (internal)
R2_A2
R3 (internal)
R4 (internal)
Charge Pump
Current, K
Phase Detector
Frequency
Frequency
Kvco
N
Phase Margin
Loop
Bandwidth
LMK04816B
0.047
3.9
0
0
0.62
0.2
0.2
nF
nF
nF
nF
kΩ
kΩ
kΩ
3.2
mA
122.88
MHz
2457.6
18.8
20
75
MHz
MHz/V
321
kHz
degrees
Note: PLL Loop Bandwidth is a function of K , Kvco, N as well as loop components. Changing
K and N will change the loop bandwidth.
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Evaluation Board Inputs and Outputs
The following table contains descriptions of the inputs and outputs for the evaluation board.
Unless otherwise noted, the connectors described can be assumed to be populated by default.
Additionally, some applicable CodeLoader programming controls are noted for convenience.
Refer to the LMK04816 Family Datasheet for complete register programming information.
Table 6: Evaluation Board Inputs and Outputs
Connector Name
Signal Type,
Input/Output
Description
Clock outputs with programmable output buffers.
The output terminations by default on the evaluation
board are shown below, and the output type selected by
default in CodeLoader is indicated by an asterisk (*):
Clock output pair
Populated:
CLKout0, CLKout0*,
CLKout2, CLKout2*,
CLKout4, CLKout4*,
CLKout6, CLKout6*,
CLKout8, CLKout8*,
CLKout10, CLKout10*
Not Populated:
CLKout1, CLKout1*,
CLKout3, CLKout3*,
CLKout5, CLKout5*,
CLKout7, CLKout7*,
CLKout9, CLKout9*,
CLKout11, CLKout11*
CLKout0
CLKout1
CLKout2
CLKout3
CLKout4
CLKout5
CLKout6
CLKout7
CLKout8
CLKout9
CLKout10
CLKout11
Analog,
Output
Default Board
Termination
LVPECL*
LVPECL
LVPECL*
LVPECL
LVDS* / LVCMOS
LVDS / LVCMOS
LVDS* / LVCMOS
LVDS / LVCMOS
LVDS* / LVCMOS
LVDS / LVCMOS
LVPECL*
LVPECL
Each CLKout pair has a programmable LVDS,
LVPECL, or LVCMOS buffer. The output buffer type
can be selected in CodeLoader in the Clock Outputs
tab via the CLKoutX_TYPE control.
All clock outputs are AC-coupled to allow safe testing
with RF test equipment.
All LVPECL clock outputs are source-terminated using
240-ohm resistors.
If an output pair is programmed to LVCMOS, each
output can be independently configured (normal,
inverted, or off/tri-state).
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Connector Name
E V A L U A T I O N
B O A R D
Signal Type,
Input/Output
O P E R A T I N G
I N S T R U C T I O N S
Description
Buffered output of OSCin port.
The output terminations on the evaluation board are
shown below, the output type selected by default in
CodeLoader is indicated by an asterisk (*):
Default Board
OSC output pair
Termination
OSCout0
LVDS* / LVCMOS
Populated:
OSCout0, OSCout0*,
Analog,
Output
Only OSCout0 has a programmable LVDS, LVPECL,
or LVCMOS output buffer. The OSCout0 buffer type
can be selected in CodeLoader on the Clock Outputs
tab via the OSCout0_TYPE control.
OSCout0 is AC-coupled to allow safe testing with RF
test equipment.
If OSCout0 is programmed as LVCMOS, each output
can be independently configured (normal, inverted,
inverted, and off/tri-state).
Main power supply input for the evaluation board.
A 3.9 V DC power source applied to this SMA will, by
default, source the onboard LDO regulators that power
the inner layer planes that supply the LMK04816B and
its auxiliary circuits (e.g. VCXO).
Vcc
Power,
Input
Populated:
J1
Power,
Input
Populated:
VccVCO/Aux
Power,
Input
The LMK04816B contains internal voltage regulators
for the VCO, PLL and other internal blocks. The clock
outputs do not have an internal regulator, so a clean
power supply with sufficient output current capability
is required for optimal performance.
On-board LDO regulators and 0 resistor options
provide flexibility to supply and route power to various
devices. See schematics for more details.
Alternative power supply input for the evaluation board
using two unshielded wires (Vcc and GND).
Apply power to either Vcc SMA or J1, but not both.
Optional Vcc input to power the VCO circuit if
separated voltage rails are needed. The VccVCO/Aux
input can power these circuits directly or supply the onboard LDO regulators. 0 Ω resistor options provide
flexibility to route power.
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Connector Name
Populated:
VccVCXO/Aux
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Signal Type,
Input/Output
Description
Power,
Input
Optional Vcc input to power the VCXO circuit if
separated voltage rails are needed. The
VccVCXO/Aux input can power these circuits directly
or supply the on-board LDO regulators. 0 Ω resistor
options provide flexibility to route power.
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Connector Name
E V A L U A T I O N
B O A R D
Signal Type,
Input/Output
O P E R A T I N G
I N S T R U C T I O N S
Description
Reference Clock Inputs for PLL1 (CLKin0, 1, 2).
CLKin1 can alternatively be used as an External
Feedback Clock Input (FBCLKin) in 0-delay mode or
an RF Input (Fin) in External VCO mode.
Reference Clock Inputs for PLL1 (CLKin0, 1, 2)
FBCLKin/CLKin1* is configured by default for a
single-ended reference clock input from a 50-ohm
source. The non-driven input pin (FBCLKin/CLKin1)
is connected to GND with a 0.1 uF. CLKin0/CLKin0*
is configured by default for a differential reference
clock input from a 50-ohm source.
Populated:
CLKin0, CLKin0*,
FBCLKin*/CLKin1*
CLKin2/CLKin2*
Not Populated:
FBCLKin/CLKin1
CLKin1* is the default reference clock input selected in
CodeLoader. The clock input selection mode can be
programmed on the Bits/Pins tab via the
CLKin_Select_MODE control. Refer to the
LMK04816 Family Datasheet section “Input Clock
Switching” for more information.
Analog,
Input
AC coupled Input Clock Swing Levels
Input
Mode
Min Max
Differential
Bipolar or
0.5
3.1
CMOS
Single Ended
0.25 2.4
Units
Vpp
Vpp
External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use with FBCLKin as an external
feedback clock input to PLL1 for 0-delay mode. See
section, Programming 0-Delay Mode in CodeLoader
below, for more details on using 0-delay mode with the
evaluation board and the evaluation board software.
RF Input (Fin) for External VCO
CLKin1 is also shared for use with Fin as an RF input
for external VCO mode using the onboard VCO
footprint (U3) or add-on VCO board. To enable Dual
PLL mode with External VCO, the following registers
must be properly configured in CodeLoader:
MODE = (3) Dual PLL, Ext VCO (Fin), (5)
Dual PLL, Ext VCO, 0-Delay, (11) PLL2, Ext
VCO (Fin)
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Connector Name
E V A L U A T I O N
B O A R D
Signal Type,
Input/Output
O P E R A T I N G
I N S T R U C T I O N S
Description
Feedback VCXO clock input to PLL1 and Reference
clock input to PLL2.
By default, these SMAs are not connected to the traces
going to the OSCin/OSCin* pins of the LMK04816B.
Instead, the single-ended output of the onboard VCXO
(U2) drives the OSCin* input of the device and the
OSCin input of the device is connected to GND with
0.1 uF.
Not populated:
OSCin, OSCin*
Analog,
Input
A VCXO add-on board may be optionally attached via
these SMA connectors with minor modification to the
components going to the OSCin/OSCin* pins of
device. This is useful if the VCXO footprint does not
accommodate the desired VCXO device.
A single-ended or differential signal may be used to
drive the OSCin/OSCin* pins and must be AC coupled.
If operated in single-ended mode, the unused input
must be connected to GND with 0.1 uF.
Test point:
VTUNE1_TP
Not populated:
Vtune1
Test point:
VTUNE2_TP
Refer to the LMK04816 Family Datasheet section
“Electrical Characteristics” for PLL2 Reference Input
(OSCin) specifications.
Tuning voltage output from the loop filter for PLL1.
Analog,
Output
Analog,
Output
If a VCXO add-on board is used, this tuning voltage
can be connected to the voltage control pin of the
external VCXO when this SMA connector is installed
and connected through R72 by the user.
Tuning voltage output from the loop filter for PLL2.
10-pin header for uWire programming interface and
programmable logic I/O pins for the LMK04816B.
Populated:
uWire
Test points:
DATAuWire_TP
CLKuWIRE_TP
LEuWIRE_TP
CMOS,
Input/Output
The uWire interface includes CLKuWire,
DATAuWire, and LEuWire signals.
The programmable logic I/O signals accessible through
this header include: SYNC, Status_Holdover,
Status_LD, Status_CLKin0, and Status_CLKin1.
These logic I/O signals also have dedicated SMAs and
test points.
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Connector Name
E V A L U A T I O N
B O A R D
Signal Type,
Input/Output
O P E R A T I N G
I N S T R U C T I O N S
Description
Programmable status output pin. By default, set to
output the digital lock detect status signal for PLL1 and
PLL2 combined.
In the default CodeLoader modes, LED D5 will
illuminate green when PLL lock is detected by the
LMK04816B (output is high) and turn off when lock is
lost (output is low).
Test point:
LD_TP
Not populated:
Status_LD
CMOS,
Output
The status output signal for the Status_LD pin can be
selected on the Bits/Pins tab via the LD_MUX control.
Refer to the LMK04816 Family Datasheet section
“Status Pins” and “Digital Lock Detect” for more
information.
Note: Before a high-frequency internal signal (e.g. PLL
divider output signal) is selected by LD_MUX, it is
suggested to first remove the 270 ohm resistor to
prevent the LED from loading the output.
Programmable status output pin. By default, set to the
output holdover mode status signal.
In the default CodeLoader mode, LED D8 will
illuminate red when holdover mode is active (output is
high) and turn off when holdover mode is not active
(output is low).
Test point:
Holdover_TP
Not populated:
Status_Hold
CMOS,
Output
The status output signal for the Status_Holdover pin
can be selected on the Bits/Pins tab via the
HOLDOVER_MUX control.
Refer to the LMK04816 Family Datasheet section
“Status Pins” and “Holdover Mode” for more
information.
Note: Before a high-frequency internal signal (e.g. PLL
divider output signal) is selected by
HOLDOVER_MUX, it is suggested to first remove the
270 ohm resistor to prevent the LED from loading the
output.
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Connector Name
E V A L U A T I O N
B O A R D
Signal Type,
Input/Output
O P E R A T I N G
I N S T R U C T I O N S
Description
Programmable status I/O pins. By default, set as input
pins for controlling input clock switching of CLKin0
and CLKin1.
These inputs will not be functional because
CLKin_Select_MODE is set to 0 (CLKin0 Manual) by
default in the Bits/Pins tab in CodeLoader. To enable
input clock switching, CLKin_Select_MODE must be
3 or 6 and Status_CLKinX_TYPE must be 0 to 3 (pin
enabled as an input).
Test point:
CLKin0_SEL_TP
CLKin1_SEL_TP
Not populated:
Status_CLKin0,
Status_CLKin1
Input Clock Switching – Pin Select Mode
When CLKin_SELECT_MODE is 3, the
Status_CLKinX pins select which clock input is active
as follows:
Status_CLKin1 Status_CLKin0 Active Clock
0
0
CLKin0
0
1
CLKin1
1
0
Reserved
1
1
Holdover
CMOS,
Input/Output
Input Clock Switching – Auto with Pin Select
When CLKin_SELECT_MODE is 6, the active clock is
selected using the Status_CLKinX pins upon an input
clock switch event as follows:
Active
Status_CLKin1 Status_CLKin0
Clock
X
0
CLKin0
1
0
CLKin1
0
0
Reserved
Refer to the LMK04816 Family Datasheet section
“Input Clock Switching” for more information.
Status Outputs
When Status_CLKinX_TYPE is 3 to 6 (pin enabled as
an output), the status output signal for the
corresponding Status_CLKinX pin can be programmed
on the Bits/Pins tab via the Status_CLKinX_MUX
control.
Refer to the LMK04816 Family Datasheet section
“Status Pins” for more information.
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Connector Name
E V A L U A T I O N
B O A R D
Signal Type,
Input/Output
O P E R A T I N G
I N S T R U C T I O N S
Description
Programmable status I/O pin. By default, set as an
input pin for synchronize the clock outputs with a fixed
and known phase relationship between each clock
output selected for SYNC. A SYNC event also causes
the digital delay values to take effect.
Test point:
SYNC_TP
Not populated:
SYNC
CMOS,
Input/Output
In the default CodeLoader mode, SYNC will asserted
when the SYNC pin is low and the outputs to be
synchronized will be held in a logic low state. When
SYNC is unasserted, the clock outputs to be
synchronized are activated and will be initially phase
aligned with each other except for outputs programmed
with different digital delay values.
A SYNC event can also be programmed by toggling
the SYNC_POL_INV bit in the Bits/Pins tab in
CodeLoader.
Refer to the LMK04816 Family Datasheet section
“Clock Output Synchronization” for more information.
Status Output
When SYNC_MUX is 3 to 6 (pin enabled as output), a
status signal for the SYNC pin can be selected on the
Bits/Pins tab via the SYNC_MUX control.
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Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply, particularly when the devices on the
board are being directly powered (onboard LDO regulators bypassed).
Phase Noise / Spectrum Analyzer
To measure phase noise and RMS jitter, an Agilent E5052 Signal Source Analyzer is
recommended. An Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also
usable although the architecture of the E5052 is superior for phase noise measurements. At
frequencies less than 100 MHz the local oscillator noise of the E4445A is too high and
measurements will reflect the E4445A‟s internal local oscillator performance, not the device
under test.
Oscilloscope
To measure the output clocks for AC performance, such as rise time or fall time, propagation
delay, or skew, it is suggested to use a real-time oscilloscope with at least 1 GHz analog input
bandwidth (2.5+ GHz recommended) with 50 ohm inputs and 10+ Gsps sample rate. To
evaluate clock synchronization or phase alignment between multiple clock outputs, it‟s
recommended to use phase-matched, 50-ohm cables to minimize external sources of skew or
other errors/distortion that may be introduced if using oscilloscope probes.
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Programming 0-Delay Mode in CodeLoader
Overview
When enabling the 0-Delay mode the feedback path of the VCO is altered to include a clock
output. See the datasheet for more details on 0-Delay functionality.
The current version of the CodeLoader software does not include this extra divider in the
frequency calculations when in holdover mode. To successfully lock the LMK04816 device in a
0-Delay mode the user must program the device “manually” account for this divider.
Programming “manually” means that the VCO frequency and therefore the clock output
frequencies displayed by the CodeLoader software may be incorrect. For the LMK04816 device
to lock properly the divider values must be programmed correctly. The frequencies displayed in
the application are only for the benefit of the user and for proper automatic programming of the
OSCin_FREQ register which will not be affected by 0-Delay.
When using the device in Dual Loop mode vs. Single Loop mode different procedures are used
to cause the device to lock when using the CodeLoader software. The following two sections
describe the process for when the LMK04816 device is programmed for a Dual Loop mode and
Single Loop mode respectively. Each section contains a brief introduction, the programming
steps to execute to make the device lock, and finally a detailed section discussing the
workaround and some example cases.
Dual Loop 0-Delay Mode Examples
In Dual Loop 0-Delay Modes, MODE = 2 or MODE = 5, the feedback from the VCXO of PLL1
to the PLL1 N divider is broken and a clock output will drive the PLL1 N divider. This permits
phase alignment between the clock output and the clock input (0-Delay). As such, the PLL1_N
and PLL1_R divide values may need to be adjusted to permit the LMK04816 to lock.
Programming Steps
1. Program a Dual Loop 0-Delay mode.
2. Enable the feedback mux. EN_FEEDBACK_MUX = 1.
3. Select clock output for feedback with the feedback mux. FEEDBACK_MUX = User
value.
4. Program the VCXO (VCO) frequency of PLL1 tab to the clock output frequency selected
by the feedback mux.
If for any reason the CLKout frequency is less than the phase detector frequency, the PLL1 R
divider must be increased so that the phase detector is at the same or lower value than the
CLKout frequency.
Details
When using the CodeLoader software in Dual Loop 0-Delay mode, programming the VCXO
(VCO) frequency of the PLL1 tab to the frequency of the fed back output clock will re-program
the PLL1 N divider to allow the LMK04816 will be able to lock. The PLL1 loop has been
altered and actual VCXO no longer directly feeds into PLL1 N divider. The VCXO is only used
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by the reference input of PLL2 now. The PLL2 reference frequency will remain at the VCXO
frequency.
When the PLL1 VCXO frequency is different from the PLL2 reference frequency, a warning
will be displayed on the clock outputs tab informing the user that PLL1 VCO and PLL2
reference frequency are mismatched and the one or more of the PLLs are out of lock. While
there still could be an error in the divider values which may cause a non-locked PLL, this
warning by itself may no longer be assumed true. It is up to the user to ensure the PLL dividers
are programmed correctly.
To illustrate the proper programming of the LMK04816 device in dual loop 0-delay mode the
following case examples are provided. Note that in one of the cases, the feedback frequency
from the clock output matches the VCXO frequency and CodeLoader will display the proper
frequency values.
Dual Loop 0-Delay (MODE=2 or 5) Case 1: For example the default configuration, 122.88 MHz
CLKin, 122.88 MHz VCXO, of the LMK04816 has the following register programming.
Case2:
Default 0-Delay
Mode
(CLKout8 =
122.88 MHz)
Case 3:
Default 0-Delay
Mode (Updated
CLKout8 =
245.76 MHz)
Case 4:
Default 0-Delay
Mode (Updated
CLKout8 =
61.44 MHz)
122.88
122.88
122.88
122.88
122.88
122.88
61.44
245.76
120
120
60
240
2949.12 MHz
2949.12 MHz
2949.12 MHz
2949.12 MHz
2949.12 MHz
2949.12 MHz
2949.12 MHz
2949.12 MHz
12
2
Bypassed
12
12
2
Bypassed
24
12
2
Bypassed
12
12
2
Bypassed
48
245.76 MHz
122.88 MHz
245.76 MHz
61.44 MHz
245.76 MHz
122.88 MHz
245.76 MHz
61.44 MHz
Case 1:
Default Mode
No 0-Delay
Actual PLL1
VCXO Frequency
Reported PLL1
VCXO Frequency
PLL1 N
Actual PLL2
VCO Frequency
Reported PLL2
VCO Frequency
PLL2_N
PLL2_P (Pre-N)
PLL2 VCO Divider
CLKout8 Divide
Actual CLKout8
Output Frequency
Reported CLKotu8
Output Frequency
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Single Loop 0-Delay Mode Examples
In Single Loop 0-Delay Mode, MODE = 8, the feedback from the VCO of PLL2 to the
PLL2_P/PLL2 N divider is broken and a fed back clock output will drive the PLL2 N divider
directly. This permits phase alignment between the clock output and the OSCin input (0-Delay).
As such, the PLL2_N, PLL2_R, and PLL2_N_CAL divide values may need to be adjusted to
permit the LMK04816 to lock.
Programming Steps
1. Program the Single Loop 0-Delay mode.
2. Enable the feedback mux. EN_FEEDBACK_MUX = 1.
3. Select clock output for feedback with the feedback mux. FEEDBACK_MUX = User
value.
4. Program the VCO frequency of PLL2 tab to: The actual VCO frequency * PLL2_P
(which is PLL2 PreN) / CLKout Divider.
Entered CodeLoader 4 VCO Frequency = Actual VCO Frequency * PLL2_P /
CLKout Divider.
5. Updated the PLL2_N_CAL register on the Bits/Pins tab to the N value when in non-0Delay mode.
6. Press Ctrl-L to cause all registers to be programmed.
The reason is to cause the programming of register R30 to start the VCO
calibration routine now that the proper PLL2_N_CAL value is programmed.
PLL2_N_CAL value is automatically updated when a new VCO frequency is
entered and the PLL2_N value is calculated. In this case the VCO frequency
entered is wrong and the PLL2_N_CAL value will be incorrect.
If for any reason the CLKout frequency is less than the phase detector frequency, the PLL2 R
divider must be increased so that the phase detector is at the same or lower value than the
CLKout frequency.
Details
The 0-Delay mode for Single Loop mode is more complicated to program than for Dual Loop
mode in part because of the PLL2_N_CAL register. When performing the VCO calibration the
device uses PLL2_N_CAL for in non-0-Delay mode. Once the VCO is calibrated the device
enters 0-Delay mode. For more information on the PLL programming equations, refer to PLL
PROGRAMMING in the applications section of the datasheet.
In Table 7 case 1 illustrates the register programming when note using 0-Delay.
Case 2 shows 0-Delay with a clock out divider of 2. Since PLL2_P = 2, this substitution of
which circuit is performing the divide by two results in no impact o the software. All the values
display correctly.
Case 3 shows 0-Delay mode with a CLKout divider not equal to the PLL2_P value. So the
proper frequency to program in the VCO to lock the VCO to 2949.12 MHz will be 491.52 MHz.
This is calculated by Actual VCO Frequency * PLL2_P / CLKoutX_Y_DIV.
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Case 4 shows 0-Delay mode with CLKout divider not equal to the PLL2_P value; however the
CLKout frequency will be less than the current phase detector frequency. This requires PLL2_R
to be increased from a value of 1 to 2 to reduce the PLL2 phase detector frequency from 122.88
MHz to 61.44 MHz. Now the adjusted VCO frequency can be programmed to allow PLL2 to
lock.
In any case where the actual VCO frequency and the display VCO frequency are not equal the
user is required to manually update the PLL2_N_CAL register with the PLL2_N value to be
used as if the device were operating in the non-0-Delay mode. Once this update has been
performed, Ctrl-L will reload the part and cause the VCO calibration to occur with the proper
PLL2_N_CAL value.
Table 7 - Single PLL 0-Delay Operation Examples
Case 2:
Default 0-Delay
Mode
(CLKout8 =
1474.56 MHz)
Case 3:
Default 0-Delay
Mode (Updated
CLKout8 =
245.76 MHz)
Case 4:
Default 0-Delay
Mode (Updated
CLKout8 =
61.44 MHz)
2949.12 MHz
2949.12 MHz
2949.12 MHz
2949.12 MHz
2949.12 MHz
2949.12 MHz
491.52 MHz
122.88 MHz
1
12
12
2
Bypassed
12
1
12
12
2
Bypassed
2
1
2
12
2
Bypassed
12
2
1
24
2
Bypassed
48
245.76
1474.56 MHz
245.76 MHz
61.44 MHz
245.76
1474.56 MHz
40.96 MHz
2.56 MHz
Case 1:
Default Mode
No 0-Delay
Actual PLL2
VCO Frequency
Reported PLL2
VCO Frequency
PLL2_R
PLL2_N
PLL2_N_CAL
PLL2_P (Pre-N)
PLL2 VCO Divider
CLKout8 Divide
Actual CLKout8
Output Frequency
Reported CLKout8
Output Frequency
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Appendix A: CodeLoader Usage
Code Loader is used to program the evaluation board with either an LPT port using the included
CodeLoader cable or with a USB port using the optional USB-to-uWire cable available from
http://store.ti.com/. The part number is USB2UWIRE-IFACE.
Port Setup Tab
Figure 8: Port Setup tab
On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that
will be used to program the device on the evaluation board. If parallel port is selected, the user
should ensure that the correct port address is entered.
The Pin Configuration field is hardware dependent and normally does not need to be changed by
the user. Figure 8 shows the default settings.
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Clock Outputs Tab
Figure 9: Clock Outputs tab
The Clock Outputs tab allows the user to control the output channel blocks, including:
Clock Group Source from either VCO or OSCin (via OSC Mux1 and OSC Mux2)
Channel Powerdown (affects digital and analog delay, clock divider, and buffer blocks)
Digital Delay value and Half Step
Clock Divide value
Analog Delay value and Delay bypass/enable (per output)
Clock Output format (per output)
This tab also allows the user to select the VCO Divider value (2 to 8). Note that the total PLL2
N divider value is the product of the VCO Divider value and the PLL N Prescaler and N Counter
values (shown in the PLL2 tab), and is given by:
PLL2 N Total = VCO Divider * PLL2 N Prescaler * PLL2 N Counter
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Clicking on the cyan-colored PLL2 block that contains R, PDF and N values will bring the
PLL2 tab into focus where these values may be modified, if needed.
Clicking on the values in the box containing the Internal Loop Filter component (R3, C3, R4,
C4) allow one to step through the possible values. Left click to increase the component value,
and right click to decrease the value. These values can also be changed in the Bits/Pins tab.
The Reference Oscillator value field may be changed in either the Clock Outputs tab or the
PLL2 tab. The PLL2 Reference frequency should match the frequency of the onboard VCXO or
Crystal (i.e. VCO frequency in the PLL1 tab); if not, a warning message will appear to indicate
that the PLL(s) may be out of lock, as highlighted by the red box in Figure 10.
Figure 10: Warning message indicating mismatch between
PLL1 VCO frequency (30.72MHz) and PLL2 reference frequency (122.88 MHz)
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PLL1 Tab
Figure 11: PLL1 tab
The PLL1 tab allows the user to change the following parameters in Table 8.
Table 8: Registers Controls and Descriptions in PLL1 tab
Control Name
Reference Oscillator
Frequency (MHz)
Phase Detector Frequency
(MHz)
Register Name
n/a
VCO Frequency (MHz)
n/a
R Counter
PLL1_R
Description
CLKin frequency of the selected reference
clock.
PLL1 Phase Detector Frequency (PDF).
This value is calculated as:
PLL1 PDF = CLKin Frequency / (PLL1_R *
CLKinX_PreR_DIV), where
CLKinX_PreR_DIV is the predivider value
of the selected input clock.
The VCO Frequency should be the OSCin
frequency, except when operating in Dual
PLL with 0-delay feedback. This value is
calculated as:
VCO Freq (OSCin freq) = PLL1 PDF *
PLL1_N.
In Dual PLL mode with 0-delay feedback,
the VCO frequency should be set to the
feedback clock input frequency. See the
section Setting the PLL1 VCO Frequency
and PLL2 Reference Frequency for details.
PLL1 R Counter value (1 to 16383).
n/a
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N Counter
Phase Detector Polarity
PLL1_N
PLL1_CP_POL
Charge Pump Gain
PLL1_CP_GAIN
Charge Pump State
PLL1_CP_TRI
O P E R A T I N G
I N S T R U C T I O N S
PLL1 N Counter value (1 to 16383).
PLL1 Phase Detector Polarity.
Click on the polarity sign to toggle polarity
“+” or “–”.
PLL1 Charge Pump Gain.
Left-click/right-click to increase/decrease
charge pump gain (100, 200, 400, 1600 uA).
PLL1 Charge Pump State.
Click to toggle between Active and Tri-State.
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency
When operating in Dual PLL mode without 0-delay feedback, the VCO frequency value on the
PLL1 tab must match the Reference Oscillator (OSCin) frequency value on the PLL2 tab;
otherwise, the one or both PLLs may be out of lock. Updating the Reference Oscillator
frequency on the PLL2 tab will automatically update the value of OSCin_FREQ on the
Bits/Pins tab.
However, when operating in Dual PLL mode with 0-delay feedback, it may be valid for the VCO
frequency value on the PLL1 tab to be different from the Reference Oscillator (OSCin)
frequency value on the PLL2 tab. This is because in 0-delay mode, the PLL1 feedback clock is
taken from an output clock instead of the OSCin clock. For example, if the CLKin frequency (to
PLL1_R) is 30.72 MHz, the 0-delay feedback clock frequency (to PLL1_N) is 30.72 MHz, and
the VCXO frequency is 122.88 MHz, then the VCO frequency value on the PLL1 tab should be
30.72 MHz (0-delay feedback frequency) and the Reference Oscillator frequency value on the
PLL2 tab should be 122.88 MHz (VCXO frequency). Because of the mismatched frequencies, a
warning message will indicate this condition on the Clock Outputs tab but may be disregarded
in a case like this.
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PLL2 Tab
Figure 12: PLL2 tab
The PLL2 tab allows the user to change the following parameters in Table 9.
Table 9: Registers Controls and Descriptions in PLL2 tab
Control Name
Reference Oscillator
Frequency (MHz)
Phase Detector Frequency
(MHz)
Register Name
OSCin_FREQ
VCO Frequency (MHz)
n/a
Doubler
EN_PLL2_REF_2X
R Counter
N Counter
PLLN Prescaler
PLL2_R
PLL2_N
PLL2_P
n/s
31
Description
OSCin frequency from the External VCXO
or Crystal.
PLL2 Phase Detector Frequency (PDF).
This value is calculated as:
PLL2 PDF = OSCin Frequency
*(2EN_PLL2_REF_2X) / PLL2_R.
Internal VCO Frequency should be within
the allowable range of the LMK04816B
device.
This value is calculated as:
VCO Frequency = PLL2 PDF * (PLL2_N *
PLL2_P * VCO divider value).
PLL2 Doubler.
0 = Bypass Doubler
1 = Enable Doubler
PLL2 R Counter value (1 to 4095).
PLL2 N Counter value (1 to 262143).
PLL2 N Prescaler value (2 to 8).
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Phase Detector Polarity
PLL2_CP_POL
Charge Pump Gain
PLL2_CP_GAIN
Charge Pump State
PLL2_CP_TRI
O P E R A T I N G
I N S T R U C T I O N S
PLL2 Phase Detector Polarity.
Click on the polarity sign to toggle polarity
“+” or “–”.
PLL2 Charge Pump Gain.
Left-click/right-click to increase/decrease
charge pump gain (100, 400, 1600, 3200
uA).
PLL2 Charge Pump State.
Click to toggle between Active and Tri-State.
Changes made on this tab will be reflected in the Clock Outputs tab. The VCO Frequency
should conform to the specified internal VCO frequency range for the LMK04816B device (per
Table 2).
Bits/Pins Tab
Figure 13: Bits/Pins tab
The Bits/Pins tab allows the user to program bits directly, many of which are not available on
other tabs. Brief descriptions for the controls on this tab are provided in Table 10 to supplement
the datasheet. Refer to the LMK04816 Family Datasheet for more information.
TIP: Right-clicking any register name in the Bits/Pins tab will display a Help prompt with the
register address, data bit location/length, and a brief register description.
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Table 10: Register Controls and Descriptions on Bits/Pins tab
Group
Register Name
RESET
POWERDOWN
MODE
Mode Control
PD_OSCin
FEEDBACK_MUX
OSCin_FREQ
VCO_MUX
uWire_LOCK
CLKin_Select_MODE
EN_CLKin1
CLKin
EN_CLKin0
EN_CLKin2
CLKinX_BUF_TYPE
EN_LOS
LOS_TIMEOUT
IO
Control
Crystal
EN_PLL2_XTAL
XTAL_LVL
LD_MUX
LD_TYPE
HOLDOVER_MUX
Description
Resets the device to default register values. RESET
must be cleared for normal operation to prevent an
unintended reset every time R0 is programmed.
Places the device in powerdown mode.
Selects the operating mode (topology) for the
LMK04816 device.
Powers down the OSCin buffer. For use in Clock
Distribution mode if OSCin path is not used.
Selects the feedback source for 0-delay mode.
Must be set to the OSCin frequency range for
PLL2. Used for proper operation of the internal
VCO calibration routine.
Entering a reference oscillator frequency on PLL2
tab will automatically update OSCin_FREQ to the
proper frequency range.
Selects between VCO and VCO divider to drive the
clock distribution path. The VCO divider is only
valid if MODE is selecting the Internal VCO.
When checked, no other uWire programming will
have effect. Must be unchecked to enable uWire
programming of registers R0 to R30.
Selects operational mode for how the device selects
the reference clock for PLL1.
Enables CLKin1 as a usable reference input during
auto switching mode.
Enables CLKin0 as a usable reference input during
auto switching mode.
Enables CLKin2 as a usable reference input during
auto switching mode.
Selects the CLKinX input buffer to Bipolar
(internal 0 mV offset) or MOS (internal 55 mV
offset).
Enable the Loss-Of-Signal (LOS) detect circuitry.
Sets the timeout value for the LOS detect circuitry
to assert a loss of signal state on a clock input.
Enables Crystal Oscillator
Sets peak amplitude on the tunable crystal. Values
listed are for a 20.48 MHz crystal.
Sets the selected signal on the Status_LD pin.
Sets I/O pin type on the Status_LD pin.
Sets the selected signal on the Status_HOLDOVER
pin.
33
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E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
DAC/Holdover
IO Control – Sync
HOLDOVER_TYPE
Status_CLKin0 _MUX
Status_CLKin0_TYPE
Status_CLKin1_MUX
Status_CLKin1_TYPE
CLKin_Sel_INV
Sets I/O pin type on the Status_Holdover pin.
Sets the selected signal on the Status_CLKin0 pin.
Sets I/O pin type on the Status_CLKin0 pin.
Sets the selected signal on the Status_CLKin1 pin.
Sets I/O pin type on the Status_CLKin1 pin.
Inverts the Status_CLKin0/1 pin polarity when set
to an input type. Significant when
CLKin_SELECT_MODE is 3 or 6.
SYNC_MUX
Sets the selected signal on the SYNC pin.
SYNC_TYPE
Sets I/O pin type on the SYNC pin.
SYNC_POL_INV
Sets polarity on SYNC input to active low when
checked. Toggling this bit will initiate a SYNC
event.
SYNC_PLL1_DLD
Engage SYNC mode until PLL1 DLD is true
SYNC_PLL2_DLD
Engage SYNC mode until PLL2 DLD is true
NO_SYNC_CLKoutX_Y Synchronization will not affect selected clock
outputs, where X = even-numbered output and Y =
odd-numbered output.
SYNC_QUAL
Sets the SYNC to qualify mode for dynamic digital
delay.
EN_SYNC
Must be set when using SYNC, but may be cleared
after the SYNC event. When using dynamic digital
delay (SYNC_QUAL = 1), EN_SYNC must always
be set.
Changing this value from 0 to 1 can cause a SYNC
event, so clocks which should not be SYNCed
when setting this bit should have the
NO_SYNC_CLKoutX_Y bit set.
NOTE: This bit is not a valid method of generating
a SYNC event. Use one of the other SYNC
generation methods to ensure a proper SYNC
occurs.
SYNC_EN_AUTO
Enable auto SYNC when R0 to R5 is written.
HOLDOVER_MODE
Sets holdover mode to be disabled or enabled.
FORCE_HOLDOVER
Engages holdover when checked regardless of
HOLDOVER_MODE value. Turns the DAC on.
EN_TRACK
Enables DAC tracking. DAC tracks the PLL1
Vtune to provide for an accurate HOLDOVER
mode. DAC_CLK_DIV should also be set so that
DAC update rate is <= 100 kHz.
EN_VTUNE_RAIL_DET Allows rail-to-rail operation of VCXO with default
of 0. Allows use of DAC_LOW_TRIP,
DAC_HIGH_TRIP. Must be used with
EN_MAC_DAC = 1. CLKin_SELECT_MODE
must be 4 or 6 (auto mode) to use.
34
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L M K 0 4 8 1 6
E V A L U A T I O N
HOLD_DLD_CNT
DAC_CLK_DIV
EN_MAN_DAC
MAN_DAC
DAC_LOW_TRIP
DAC_HIGH_TRIP
PLL1_WND_SIZE
PLL1
PLL1_DLD_CNT
CLKinX_PreR_DIV
PLL1_N_DLY
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
In HOLDOVER mode, wait for this many clocks of
PLL1 PDF within the tolerances of PLL1_WND
_SIZE before exiting holdover mode.
DAC update clock is the PLL1 phase detector
divided by this divisor. For proper operation, DAC
update clock rate should be <= 100 kHz.
DAC update rate = PLL1 phase detector frequency /
DAC_CLK_DIV
Enables manual DAC mode and set DAC voltage
when in holdover.
Sets the value for the DAC when EN_MAN_DAC
is 1 and holdover is engaged. Readback from this
register is the current DAC value whether in
manual DAC mode or DAC tracking mode
Value from GND in ~50mV steps at which a clock
switch event is generated. If Holdover mode is
enabled, it will be engaged upon the clock switch
event.
NOTE: EN_VTUNE_RAIL_DET must be enabled
for this to be valid.
Value from VCC (3.3V) in ~50mV steps at which
clock switch event is generated. If Holdover mode
is enabled, it will be engaged upon the clock switch
event.
NOTE: EN_VTUNE_RAIL_DET must be enabled
for this to be valid.
If the phase error between the PLL1 reference and
feedback clocks is less than specified time, then the
PLL1 lock counter increments.
NOTE: Final lock detect valid signal is determined
when the PLL1 lock counter meets or exceeds the
PLL1_DLD_CNT value.
The reference and feedback of PLL1 must be within
the window of phase error as specified by
PLL1_WND_SIZE for this many cycles before
PLL1 digital lock detect is asserted.
The PreR dividers divide the CLKinX reference
before the PLL1_R divider.
Unique divides on individual CLKinX signals
allows switchover from one clock input to another
clock input without needing to reprogram the
PLL1_R divider to keep the device in lock.
N delay causes clock outputs to lead clock input
when in a 0-delay mode. Increasing the N delay
value increases the output phase lead relative to the
input.
35
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L M K 0 4 8 1 6
E V A L U A T I O N
PLL1_R_DLY
PLL2_WND_SIZE
PLL2_DLD_CNT
PLL2
EN_PLL2_REF_2X
PLL2_N_CAL
PLL2_R3_LF
PLL2_R4_LF
PLL2_C3_LF
PLL2_C4_LF
PLL2_FAST_PDF
Program Pins
SYNC
Status_CLKin0
Status_CLKin1
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
R delay causes clock outputs to lag clock input
when in a 0-delay mode. Increasing the R delay
value increases the output phase lag relative to the
input.
If the phase error between the PLL2 reference and
feedback clock is less than specified time, then the
PLL2 lock counter increments.
The reference and feedback of PLL2 must be within
the window of phase error as specified by
PLL2_WND_SIZE for this many cycles before
PLL2 digital lock detect is asserted.
Enables the doubler block to doubles the reference
frequency into the PLL2 R counter. This can allow
for frequency of 2/3, 2/5, etc. of OSCin to be used
at the phase detector of PLL2.
The PLL2_N_CAL register contains the N value
used for the VCO calibration routine. Except
during 0-delay modes, the PLL2_N and
PLL2_N_CAL registers will be exactly the same.
Set the corresponding integrated PLL2 loop filter
values: R3, R4, C3, and C4.
It is also possible to set these values by clicking on
the loop filter values on the Clock Outputs tab.
Enable this bit when using a PLL2 phase detector
frequency > 100 MHz.
Sets these pins on the uWire header to logic high
(checked) or logic low (unchecked).
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E V A L U A T I O N
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O P E R A T I N G
I N S T R U C T I O N S
Registers Tab
Figure 14: Registers Tab
The Registers tab shows the value of each register. This is convenient for programming the
device to the desired settings, then exporting to a text file the register values in hexadecimal for
use in your own application.
By clicking in the “bit field” it is possible to manually change the value of registers by typing „1‟
and „0.‟
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L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Appendix B: Typical Phase Noise Performance Plots
PLL1
The LMK04816B‟s dual PLL architecture achieves ultra low jitter and phase noise by allowing
the external VCXO or Crystal‟s phase noise to dominate the final output phase noise at low
offset frequencies and the internal VCO‟s phase noise to dominate the final output phase noise at
high offset frequencies. This results in the best overall noise and jitter performance.
Table 11 lists the test conditions used for output clock phase noise measurements with the
Crystek 122.88 MHz VCXO.
Table 11: LMK04816B Test Conditions
Parameter
PLL1 Reference clock input
PLL1 Reference Clock frequency
PLL1 Phase detector frequency
PLL1 Charge Pump Gain
VCXO frequency
PLL2 phase detector frequency
PLL2 Charge Pump Gain
PLL2 REF2X mode
Value
CLKin0 single-ended input, CLKin0* AC-coupled to GND
122.88 MHz
122.88 MHz
100 uA
122.88 MHz
122.88 MHz
3200 uA
Disabled
122.88 MHz VCXO Phase Noise
The phase noise of the reference is masked by the phase noise of this VCXO by using a narrow
loop bandwidth for PLL1 while retaining the frequency accuracy of the reference clock input.
This VCXO sets the reference noise to PLL2. Figure 15 shows the open loop typical phase noise
performance of the CVHD-950-122.88 Crystek VCXO.
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E V A L U A T I O N
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O P E R A T I N G
I N S T R U C T I O N S
Phase Noise (dBc/Hz)
VCXO Phase Noise
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
CVHD-950-122.88
10
100
1000
10000
100000
1000000 10000000
1E+08
Offset (Hz)
Figure 15: Crystek CVHD-950-122.88 MHz VCXO Phase Noise at 122.88 MHz
Table 12: VCXO Phase Noise
at 122.88 MHz (dBc/Hz)
Phase
Offset
Noise
10 Hz
-76.6
100 Hz -108.9
1 kHz -137.4
10 kHz -153.3
100 kHz -162.0
1 MHz -165.7
10 MHz -168.1
40 MHz -168.1
Table 13: VCXO RMS Jitter
to high offset of 20 MHz
at 122.88 MHz (rms fs)
Low
Jitter
Offset
10 Hz
515.4
100 Hz
60.5
1 kHz
36.2
10 kHz
35.0
100 kHz
34.5
1 MHz
32.9
10 MHz
22.7
Clock Output Measurement Technique
The same technique was used to measure phase noise for all three output types available on the
programmable OSCout and CLKout buffers. This was achieved by terminating one side of the
LVPECL, LVDS, or LVCMOS output with a 50-ohm load, and measuring the other side singleended using an Agilent E5052B Source Signal Analyzer.
Buffered Phase Noise
Both OSCout0 and OSCout1 frequencies are 122.88 MHz since the OSCout Divider is bypassed.
OSCout0 is programmed to LVCMOS mode.
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O P E R A T I N G
I N S T R U C T I O N S
Clock Outputs (CLKout)
The LMK04816 Family features programmable LVDS, LVPECL, and LVCMOS buffer modes
for the CLKoutX and OSCout0 output pairs. Included below are various phase noise
measurements for each output format.
LMK04816B CLKout Phase Noise
-80
-90
Phase Noise (dBc/Hz)
-100
-110
1228.8 MHz LVDS
1228.8 MHz LVPECL16
-120
491.52 MHz LVDS
491.52 MHz LVPECL16
-130
245.76 MHz LVDS
245.76 MHz LVCMOS
-140
245.76 MHz LVPECL16
122.88 MHz LVDS
-150
122.88 MHz LVCMOS
122.88 MHz LVPECL16
-160
-170
100
1,000
10,000
100,000
1,000,000
10,000,000
Frequency Offset (Hz)
Figure 16: LMK04816B CLKout Phase Noise
Table 14: LMK04816B Phase Noise (dBc/Hz) Phase Noise and RMS Jitter (fs)
Offset
100 Hz
1 kHz
10 kHz
100 kHz
800 kHz
1 MHz
10 MHz
20 MHz
RMS Jitter (fs)
10 kHz to 20 MHz
RMS Jitter (fs)
100 Hz to 20 MHz
1228.80 MHz 1228.80 MHz
LVDS
LVPECL
-91.2
-90.5
-111.2
-110.8
-121.0
-121.1
-121.3
-121.2
-133.8
-133.7
-135.8
-135.7
-150.2
-150.4
-150.8
-151.0
491.52 MHz
LVDS
-97.5
-118.7
-128.5
-129.5
-141.9
-143.4
-153.1
-153.8
491.52 MHz
LVPECL
-98.2
-119.4
-128.6
-129.5
-141.9
-143.8
-155.7
-155.7
92.9
93.4
97.5
94.5
104.0
105.3
109.0
105.4
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E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
For the LMK04816B, the internal VCO frequency is 2457.60 MHz. The divide-by-10 CLKout
frequency is 245.76 MHz, and the divide-by-20 CLKout frequency is 122.88 MHz.
Table 15: LMK04816B Phase Noise and RMS Jitter for Different CLKout Output Formats and Frequencies
245.76
245.76
245.76
122.88
122.88
122.88
Offset
LVDS
LVCMOS
LVPECL
LVDS
LVCMOS
LVPECL
100 Hz
-105.8
-104.5
-106.5
-108.6
-113.0
-111.4
1 kHz
-124.7
-124.9
-125.4
-130.2
-132.1
-131.0
10 kHz
-134.8
-134.4
-134.9
-140.7
-140.7
-141.0
100 kHz
-135.5
-135.4
-135.8
-141.7
-141.7
-141.9
800 kHz
-147.8
-147.7
-148.0
-152.6
-153.5
-154.1
1 MHz
-149.6
-149.4
-149.7
-153.3
-155.2
-155.5
10 MHz
-156.1
-158.1
-158.4
-158.4
-161.5
-161.1
20 MHz
-156.3
-158.2
-158.9
-159.5
-161.6
-161.3
RMS Jitter (fs)
106.9
101.5
96.4
134.2
109.7
108.2
10 kHz to 20 MHz
RMS Jitter (fs)
116.8
112.4
106.4
143.2
118.9
117.9
100 Hz to 20 MHz
LMK04816B OSCout Phase Noise
-80
-90
-100
-110
122.88 MHz LVCMOS
OSCin through CLKout
Title
-120
122.88 MHz OSCout0
LVPECL16
-130
-140
-150
-160
-170
100
1,000
10,000
100,000
1,000,000
10,000,000
Title
Figure 17: LMK04816B OSCout Phase Noise
41
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E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Table 16: LMK04816B OSCout Phase Noise and RMS Jitter (fs)
OSCout0
OSCin thru
Offset
LVPECL
CLKout
-110.3
-110.0
100 Hz
-136.9
-138.9
1 kHz
-151.1
-150.0
10 kHz
-154.3
-154.6
100 kHz
-158.9
-156.6
800 kHz
-159.2
-156.6
1 MHz
-159.4
-156.8
10 MHz
-157.6
-156.9
20 MHz
RMS Jitter (fs)
138.4
120.0
10 kHz to 20 MHz
RMS Jitter (fs)
143.7
126.2
100 Hz to 20 MHz
42
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L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Appendix C: Schematics
Power Supplies
1
Vcc
Vcc
2
Direct Power
VccTP
TESTPOINT
J1
1
2
C310
10µF
R330
DNP
1000
LDO Power Options
C317
10µF
3
OUT
DNP
TAB ADJ
4
R338
240
R336
DNPC316
0.1µF
C326
0.1µF
C322
0.1µF
DNPC320
0.1µF
C323
0.01µF
R343
DNPC333
DNP
Aux Power for XO/VCXO, Status LEDs
VccPLLPlane
VccCLKoutPlane
VccAuxPlane
Vcc
VccAuxPlane
1
3
5
7
DNP
2
4
6
8
GND Header
GND
VccPLLPlane
VccCLKoutPlane
TESTPOINT
VccAuxPlane
Vcc
Vcc_TP
1
3
5
DNP
DNPC328
0.1µF
2
4
6
4
R350
C340
4.7µF
51k
8
2
7
9
IN
OUT
SD
ADJ
NC
BYP
NC
DAP GND
GND_TP
DNP
VccCLKoutPlane
LDO_Out_LP3878
TESTPOINT
C341 R351
2200pF 2.00k
1
0
C342
1µF
C352
10µF
C346
0.1µF
0
LP3878-ADJ 3.3 V component values:
C340 = 4.7 uF
R351= 2.00 k
C346 = 0.01 uF
R356= 866
C352 = 10 uF
R350= 51 k
C341 = 2.2 nF
Vcc_VCXO
VccPLLPlane
VccAuxPlane
R352
DNP
0
R20
DNP
0
R54
DNP
0
Vcc10_CG3_p47
2
D
R359
Vcc_VCXO_LDO
U305
6
C359
0.47µF
R369
51k
4
7
IN
1
OUT
2
5
3
EN
NC
NC
DAP GND
R19
R362
0
C360
0.47µF
Switch resistor
for power.
0
DNPC336
0.1µF
CG1
Vcc7_OSC
0
C361
0.1µF
OSC
R366
Vcc11_CLKout_CG4
C
VccLDOin
0
R368
0
R363
DNP
0
VccVCO/Aux
1
LP5900SD-3.3
R370
DNP
0
R372
142-0711-201
120 FB
DNPC364 DNPC365 DNPC366
1µF
0.1µF
0.01µF
Vcc13_CLKout_CG0
CG0
U303
6
R360
DNP
51k
C350
0.47µF
Vcc12_CLKout_CG5
CG5
Vcc13_CG0_p64
PLL2
Vcc_VCO
VccAuxPlane
R229
120 FB
DNPC356 DNPC357 DNPC358
1µF
470pF
47pF
Vcc9_PLL2
0
CG2
CG4
Vcc12_CG5_p57
PDCP2
DNPC335
0.1µF
Vcc10_CLKout_CG3
120 FB
DNPC353 DNPC354 DNPC355
1µF
0.1µF
0.01µF
120 FB
B
Vcc8_PDCP2
Vcc3_CLKout_CG2
CG3
Vcc11_CG4_p52
R371
PDCP1
C329
0.1µF
R346
Vcc2_CLKout_CG1
120 FB
DNPC347 DNPC348 DNPC349
1µF
470pF
47pF
R365
0
120 FB
LP5900SD-3.3
R373
0
142-0711-201
0
R355
DNPC343 DNPC344 DNPC345
1µF
0.1µF
0.01µF
R361
0
120 FB
Vcc3_CG2_p18
R356
866
C
R348
DNPC337 DNPC338 DNPC339
1µF
470pF
47pF
R354
0
3
Vcc2_CG1_p17
R347
R358
VccVCXO/Aux
1
0
DNP
Power Planes for LMK CLKout Outputs
6
R364
Vcc6_PDCP1
R345
5
LP3878SD-ADJ
CLKin
2
V_LM3878-ADJ
0
1000
R349
0
U302
Digital
Vcc5_CLKin
R341
DNPC332
100pF
A
0
R333
Vcc Header
DNPC334
0.1µF
LP3878SD-ADJ
VCO
Vcc4_Digital
R331
VccPLLPlane
1000
Vcc1_VCO
0
R329
C319
0.1µF
1000
R337
0
VccCLKoutPlane
R342
C331
1µF
R344
392
C325
1µF
C315
0.01µF
DNPC327
100pF
R339
DNP
0
C330
0.1µF
B
C314
0.1µF
C321
1µF
R335
DNP
0
1
LM317AEMP
R340
0
C318
1µF
C324
10µF
2
IN
C313
1µF
VccAuxPlane
V_LM317
U301
R334
DNP
0
6
R327
C312
0.1µF
LDO_Out_LM317
TESTPOINT
R332
0
VccLDOin
C311
1µF
VccCLKoutPlane
1
2
TERMBLOCK_2
5
VccPLLPlane
2
3
4
5
R328
DNP
1000
A
4
Power Plane for LMK Except Outputs
VccPLLPlane
R326
DNP
1000
1
142-0701-201
3
4
7
IN
OUT
EN
NC
NC
DAP GND
1
2
5
3
Vcc_VCO_LDO
R367
DNP
0
C351
0.47µF
LP5900SD-3.3
GND
LP5900 Component values
C359 = 0.47 uF
C360 = 0.47 uF
R369 = 51 k
D
LP5900SD-3.3
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this
LP5900 Component values GND
C359 = 0.47 uF
C360 = 0.47 uF
R369 = 51 k
1
Designed for: Evaluation Customer
Mod. Date: 4/26/2012
Project: LMK04816 Evaluation Board
Sheet:2 of 9
Size: B
Schematic: 870600769
Rev: 1.0
Assembly Variant: LVPECL240 - 2011-07-26
File: Power.SchDoc
Contact: http://www.national.com/support
or any information contained therein. Texas Instruments and/or its licensors do not
Designators greater than and equal to 300 are placed on bottom of PCBspecification
Sheet Title: Power Supplies
warrant that this design will meet the specifications, will be suitable for your application or fit for
any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate
and test your design implementation to confirm the system functionality for your application.
2
3
4
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5
http://www.ti.com
© Texas Instruments CopyrightYear
6
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
LMK04816B Device with Loop Filter and Crystal Circuits
1
2
3
4
5
6
Crystal-mode Loop Filter
OSCin*
CLKout2
OSCin
C27
Vcc10_CLKout_CG3
uWire_DATA
45
uWire_CLK
44
uWire_LE
43
uWire_DATA
uWire_CLK
R306
DNP
0
Vcc9_PLL2
42
41
Vcc8_PDCP2
40
OSCout0_N
39
OSCout0_P
38
OSCin_N
36
OSCin_P
35
R62
4.7k
D1
SMV1249-074LF
Vtune_XTAL
DNPC33
0.1µF
B
R307
3
DNP
10k
R308
DNP
0
C32
R69
DNP
0
B3
4
C304
1000pF
CLKin2*
R71
DNP
0
Status_LD
R73
R72
DNP
0
C34 4.7k
C36
2pF
DNP
Vcc5_CLKin
R66
DNP
0
OSCinP
OSCin Tuneable Crystal
VCXO Loop Filter
C2_A1
0.68µF
R74
C
R75
DNP
0
0
DNPC2pA1
2.7µF
C39
DNP
PLL1 Loop Filters
R2_A1
39k
Cb1_B1 DNP Cb2_B1
0.33µF
DNP
Status_Hold
1
Vtune_VCXO
Vcc_VCXO_LDO
DNP C40 Vcc_VCXO_OpAmp
R78
R309
DNP
DNP
DNP
0
DNP
C41
DNP
0.1µF
4
Vcc_VCXO_OpAmp
Vcc4_Digital
2
R70
OSCin_1_P
Vtune_XTAL
Vcc3_CLKout_CG2
P
R68
DNP
51
Crystal Loop Filter
Vtune1 Monitoring
SD
CPout1_1
C1_A1
0.1µF
Status_Hold R76
DNP
0
R77
DNP
0
PD
SCTDNP NC
0
0
Vtune1
6
S
R63
DNP
0
R67
2200pF
CPout1
Status_LD
5
3
BALUN - ADT2-1T+
0.1µF
C38
0.1µF
VTUNE1_TP
R64
DNP
51
R65
DNP
100
DNP
Vcc6_PDCP1
34
2pF
DNP
Vcc7_OSC
37
2200pF
Y300
DNP
DNP
Y301
R61
51
C28
C29
uWire_LE
OSCinN
0
R60
DNP
0
2
46
33
R59
OSCin_1_N
0.1µF
CLKin2_N
CLKin2_P
C2_A2
3900pF
R2_A2
620
47
SMA
CLKin0_N
DNPC2pA2
C1_A2
100pF
47pF
48
32
Vcc5
CLKin2
31
30
CLKin0*
29
CLKin0
28
Status_Holdover
Vcc3
CPout1
Status_LD
CLKin0_P
26
25
Status_Hold 27
Vcc2_CLKout_CG1
18
17
Vcc2
C
CLKin1_P
CLKout3
CLKin1_N
CLKout3*
FBCLKin*/CLKin1*
Vcc6
FBCLKin/CLKin1
CLKout2*
VCXO-mode Loop Filter
5
LDObyp2
A
Cb2pB1
10µF
R310
DNP
10k
3
R311 DNPC305
DNP
10k
0.1µF
V+
V-
2
Vcc7
VCO_Vtune
0
1
CLKout6_N
49
CLKout6_P
CLKout7_N
50
CLKout6*
CLKout7_P
51
CLKout7
CLKout7*
CLKout8_P
53
52
Vcc11
CLKout8_N
54
CLKout8
CLKout9_N
55
CLKout8*
CLKout9_P
56
CLKout9
Vcc12
CLKout9*
CLKout10_P
58
57
CLKout10_N
59
CLKout10
CLKout11_N
60
CLKout10*
CLKout11_P
61
CLKout11*
Status_CLKin0
62
CLKout11
Status_CLKin1
63
LDObyp1
Vcc4
CLKout3_P 16
DAP PAD
24
CLKout3_N 15
OSCout0
0
GND
CLKout2_N 14
OSCout0*
Vcc1
23
CLKout2_P 13
C37
0.1µF
NC
CLKout5
12
C35
10µF
Vcc8
LMK04816B
22
11
NC
CLKout5_P
10
Vcc1_VCO
CPout2
CLKout5*
9
Vcc9
NC
21
8
SYNC*
CLKout5_N
7
R376
DNP
51
LEuWire
CLKout4*
SYNC
SYNC
NC
DNPCb2pVCO
DNPCb2_VCO
DNP
DNPCb1_VCO DNP
DNP
Rb2_VCO
DNP
DNP
U1
LMK04816
CLKuWire
20
6
R51
DNP
0
VTUNE2_TP
R53
DNP
0
0
DATAuWire
CLKout1
R2_B2
470
R55
Vcc10
CLKout4_N
5
R305
DNP
0
CLKout6
PLL2 Loop Filters
C2pB2
0.12uF
R304
R52
DNP
0
Vcc11_CLKout_CG4
CLKout1*
CLKout4
CLKout1_P 4
B
CLKout0*
19
CLKout1_N 3
CLKout0
CLKout4_P
CLKout0_N 2
Status_CLKin0
Vcc13
CLKout0_P 1
Vcc12_CLKout_CG5
Status_CLKin1
64
Vcc13_CLKout_CG0
DNPC2_B2
DNP
Status_LD
Status_CLKin0
A
C1_B2
100pF
Vtune2 Swith MA Monitoring via Status LD
Status_CLKin1
1
U4
LMP7731MF
Rb2_B1
3.9k
D
D
Designators greater than and equal to 200 are placed on bottom of PCB
1
2
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this
specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for
any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate
and test your design implementation to confirm the system functionality for your application.
3
4
44
SNLU107
Designed for: Evaluation Customer
Mod. Date: 4/26/2012
Project: LMK04816 Evaluation Board
Sheet Title: Main Sheet / IC
Sheet:3 of 9
Size: B
Schematic: 870600769
Rev: 1.0
Assembly Variant: LVPECL240 - 2011-07-26
File: LMK04816_PLL.SchDoc
Contact: http://www.national.com/support
5
http://www.ti.com
© Texas Instruments CopyrightYear
6
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Reference Inputs (CLKin0, CLKin1, & CLKin2), External VCXO (OSCin) & VCO Circuits
1
2
OSCin VCXO
VCC_VCXO_TP
Vcc_VCXO
OSCin
R23
DNP
0
DNP
SMA
R18
FB 1000 ohm 600 mA
C11
10µF
A
3
4
CLKin0*
C1
C9
82pF
0
3
2
C368
100pF
GND_VCXO
R21
1
CLKin0
C5
SMA
0
GND_VCXO
Vtune
2
NC
3
Vs
RF*
GND
RF
6
0
Vcc_VCO
R22
0
Vcc_VCO_OpAmp
Vcc_VCO_LDO
R300
DNP
0
C302
0.1µF
5
R302
DNP
10k
0
R303
DNP
10k
3
DNPC303
0.1µF
V+
V-
GND
Vtune
GND
GND
GND
DNP GND
Fout
GND
5
6
7
8
1
R27
270
DNP
SMA
B
C14
R25
DNP
51
12
11
10
9
CLKin1_N
0.1µF DNPC16
0.1µF
R28
DNP
100
C18
DNP
CRO2949A-LF
R230
DNP
0
FBCLKin/CLKin1
U300
LMP7731MF
R26
270
GND
Mod
GND
GND
DNPC17
100pF
0.1µF
C20
R30
CLKin1_P
C19
0.1µF
0
0
CLKin1
2
VCO_Vtune
1
2
3
4
R29
0
R24
18
DNPC15
100pF
GND
GND
Vcc
GND
PLL2 External VCO Loop Filter
Vcc_VCO_OpAmp
C13
0
SMA
C300
4
FBCLKin/CLKin1 Impedance Matching and Attenuation
0
C12
0.1µF
FBCLKin*/CLKin1*
U3
0.1µF
CLKin0_P
0.1µF DNPC7
0.1µF
R14
DNP
51
R15
DNP
270
VCC_VCO_TP
R1
DNP
OSCinN
0
Switch resistor for signal
(shared pad)
GND_VCXO
R353
R17
DNP
270
0
100
OSCin*
C301
CLKin0_2_P
0
C4
0.1µF
DNP
C6
R11
R13
A
R9
100
R4
4
R375
0
R301
DNP
0
R6
DNP
270
0
5
DNP
SMA
B
6
SD
CLKin0_N
0.1µF DNPC3
0.1µF
R5
DNP
51
R10
DNP
120
CVHD-950-122.88
R374
0
P
R7
DNP
270
R8
DNP
51
5
NC DNPSCT
R12
U2
1
DNPC3_AB1
100pF
S
BALUN - ADT2-1T+
R16
DNP
120
Vtune_VCXO
PD
CLKin0_2_N
0
4
16
15
14
13
C367
0.1µF
DNPC8
0.1µF
C2
R3
B1
0
6
CLKin0 Impedance Matching and Attenuation
R2
OSCinP
SMA
C10
2200pF
5
Switch resistor for signal
(shared pad)
R31
DNP
270
R32
DNP
270
R33
DNP
51
CLKin2
C
CLKin2*
SMA
0.1µF
0
C24
0.1µF
R37
CLKin2_1_N
B2
3
1
SMA
R34
DNP
51
R36
C21
2
CLKin2
C
PD
S
NC DNPSCT
P
SD
6
R39
DNP
270
R41
DNP
51
BALUN - ADT2-1T+
R47
CLKin2_N
0
4
5
C22
CLKin2_2_N
R42
DNP
100
CLKin2_2_P
CLKin2_P
0
0
R49
DNP
270
C23
0.1µF
C25
R46
CLKin2_1_P
0
R40
DNP
270
R48
DNP
51
R50
DNP
270
0
C26
0.1µF
D
D
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this
specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for
any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate
and test your design implementation to confirm the system functionality for your application.
1
2
3
4
45
SNLU107
Designed for: Evaluation Customer
Mod. Date: 4/26/2012
Project: LMK04816 Evaluation Board
Sheet Title: Clock Inputs
Sheet:5 of 9
Size: B
Schematic: 870600769
Rev: 1.0
Assembly Variant: LVPECL240 - 2011-07-26
File: InClks.SchDoc
Contact: http://www.national.com/support
5
http://www.ti.com
© Texas Instruments CopyrightYear
6
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Clock Outputs (OSCout0, CLKout0 to CLKout3)
1
2
3
4
OSCout0
5
6
Default: LVDS, AC coupled
VccCLKoutPlane
R88
DNP
120
R89
DNP
82
R90
DNP
51
OSCout0
C44
A
OSCout0_1_P
OSCout0_P
R91 0.1µF
DNP
62
R231
240
GND
R93
DNP
62
0.1µF
OSCout0_1_N
GND
R94
DNP
120
Default: LVPECL, AC coupled
R95
DNP
82
CLKout1
VccCLKoutPlane
Default: LVPECL, AC coupled
VccCLKoutPlane
R98
DNP
82
R99
DNP
51
R100
DNP
120
CLKout0
C47
CLKout0_1_P
CLKout0_P
R103
240
SMA
R96
DNP
51
VccCLKoutPlane
R97
DNP
120
OSCout0*
0.1µF
R232
240
B
R92
DNP
68
C45
DNP
C46
OSCout0_N
CLKout0
A
SMA
R106
DNP
62
0.1µF
R101
DNP
82
C48
R1050.1µF
DNP
62
R104
240
R107
68
C49
CLKout0*
CLKout0_1_N
CLKout0_N
R111
240
GND
R113
DNP
120
R112
240
R114
DNP
51
GND
R115
DNP
120
CLKout3
Default: LVPECL, AC coupled
R120
DNP
82
C53
R121
DNP
51
0.1µF
R116
DNP
82
0.1µF
R122
DNP
120
R123
DNP
82
R124
51
CLKout3_1_N
CLKout3_N
SMA
R127 0.1µF
DNP
62
R126
240
CLKout2*
CLKout2_1_N
GND
D
R135
DNP
51
GND
R136
DNP
120
4
46
SNLU107
R137
DNP
82
SMA
R138
51
VccCLKoutPlane
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this
specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for
any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate
and test your design implementation to confirm the system functionality for your application.
3
DNP
0.1µF
R134
240
VccCLKoutPlane
2
CLKout3
CLKout3_1_P
CLKout3_P
SMA
1. Designators greater than and equal to 300 are placed on bottom of PCB
0.1µF
C58
Notes:
1
SMA
R130
DNP
R131
DNP
62
GND
0.1µF
0.1µF
R140
DNP
82
DNP
68
C56
DNP
CLKout2_N
CLKout3*
C54
R129
C57
R139
DNP
120
R117
51
C
68
C55
R132
DNP
62
R133
240
CLKout1
CLKout1_1_P
SMA
DNP
Default: LVPECL, AC coupled
CLKout2
CLKout2_1_P
R128
DNP
62
GND
0.1µF
VccCLKoutPlane
CLKout2_P
R125
240
DNP
VccCLKoutPlane
VccCLKoutPlane
R119
DNP
120
SMA
R108
CLKout1_P
SMA
VccCLKoutPlane
CLKout2
C
0.1µF
R118
DNP
82
R110
DNP
62
C52
GND
0.1µF
C51
DNP
68
C50
DNP
R109
62 DNP
GND
B
CLKout1*
CLKout1_1_N
CLKout1_N
SMA
R102
51
D
Designed for: Evaluation Customer
Mod. Date: 4/26/2012
Project: LMK04816 Evaluation Board
Sheet Title: Clock Outputs 1/3
Sheet:6 of 9
Size: B
Schematic: 870600769
Rev: 1.0
Assembly Variant: LVPECL240 - 2011-07-26
File: OutClks0.SchDoc
Contact: http://www.national.com/support
5
http://www.ti.com
© Texas Instruments CopyrightYear
6
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Clock Outputs (CLKout4 to CLKout7)
1
2
3
CLKout4
A
4
CLKout5
Default: LVDS or LVCMOS, AC coupled
VccCLKoutPlane
R143
DNP
120
R144
DNP
82
C59
R141
DNP
51
R150
DNP
62
0.1µF
R145
DNP
120
CLKout6_P
33
R156
DNP
240
R157
DNP
51
R234
CLKout6_N
33
0.1µF
0.1µF
R162
DNP
82
SMA
R158
51
VccCLKoutPlane
CLKout7
R163
DNP
51
B
Default: LVDS or LVCMOS, AC coupled
R167
DNP
120
CLKout6
R168
DNP
82
C66
R173
R170
DNP
240
R171
DNP
62
GND
R175
DNP
62
CLKout6*
CLKout6_1_N
0.1µF
R184
DNP
82
CLKout7*
CLKout7_1_N
SMA
DNP
0.1µF
R174
68
C68
0.1µF
C69
R164
51
CLKout7_N
SMA
DNP
R176
DNP
62
R183
DNP
120
R161
DNP
120
68
C67
CLKout6_2_N
GND
D
R172
DNP
62
R177
DNP
240
CLKout5
DNP
VccCLKoutPlane
R166
DNP
82
C65
CLKout6_1_P
GND
C
0.1µF
CLKout5_1_P
GND
CLKout6_2_P
R169
DNP
240
DNP
CLKout5_P
SMA
VccCLKoutPlane
R233
SMA
R152
C64
Default: LVDS or LVCMOS, AC coupled
R165
DNP
120
0.1µF
R154
DNP
62
CLKout4*
VccCLKoutPlane
CLKout6
CLKout5*
DNP
68
C62
CLKout4_1_N
GND
R149
DNP
62
GND
0.1µF
0.1µF
R160
DNP
82
R142
51
CLKout5_1_N
R148
DNP
240
DNP
CLKout4_N
B
R146
DNP
82
C60
CLKout5_N
SMA
R151
C63
R159
DNP
120
A
68
C61
R153
DNP
62
R155
DNP
240
Default: LVDS or LVCMOS, AC coupled
CLKout4
CLKout4_1_P
GND
6
VccCLKoutPlane
CLKout4_P
R147
DNP
240
5
DNP
CLKout7_P
SMA
R178
DNP
240
R179
DNP
51
VccCLKoutPlane
GND
R180
DNP
120
C
0.1µF
C70
0.1µF
R181
DNP
82
CLKout7
CLKout7_1_P
SMA
DNP
R182
51
VccCLKoutPlane
Notes:
D
1. Designators greater than and equal to 300 are placed on bottom of PCB
1
2
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this
specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for
any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate
and test your design implementation to confirm the system functionality for your application.
3
4
47
SNLU107
Designed for: Evaluation Customer
Mod. Date: 4/26/2012
Project: LMK04816 Evaluation Board
Sheet Title: Clock Outputs 2/3
Sheet:7 of 9
Size: B
Schematic: 870600769
Rev: 1.0
Assembly Variant: LVPECL240 - 2011-07-26
File: OutClks1.SchDoc
Contact: http://www.national.com/support
5
http://www.ti.com
© Texas Instruments CopyrightYear
6
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Clock Outputs (CLKout8 to CLKout11)
1
2
3
CLKout8
A
4
5
CLKout9
Default: LVDS or LVCMOS, AC coupled
VccCLKoutPlane
R185
DNP
120
Default: LVDS or LVCMOS, AC coupled
A
VccCLKoutPlane
R186
DNP
82
R187
DNP
51
R188
DNP
120
CLKout8
C71
CLKout8_1_P
CLKout8_P
R191
DNP
240
6
R193
DNP
62
0.1µF
R189
DNP
82
C72
R195
R192
DNP
240
R194
DNP
62
GND
R198
DNP
62
0.1µF
0.1µF
CLKout8*
C75
CLKout8_1_N
CLKout8_N
R202
DNP
120
R203
DNP
82
DNP
0.1µF
CLKout9
CLKout9_1_P
SMA
DNP
C76
CLKout9_P
SMA
0.1µF
R199
DNP
240
R196
68
C74
DNP
R197
62DNP
CLKout9*
CLKout9_1_N
SMA
DNP
CLKout9_N
SMA
68
C73
GND
R190
51
R200
DNP
240
R204
DNP
51
R201
DNP
120
0.1µF
R205
DNP
82
R206
51
VccCLKoutPlane
GND
B
VccCLKoutPlane
CLKout10
GND
B
CLKout11
Default: LVPECL, AC coupled
VccCLKoutPlane
R207
DNP
120
R208
DNP
82
R209
DNP
51
CLKout10_1_P
CLKout10_P
R214 0.1µF
DNP
62
R210
DNP
120
CLKout10
C77
R213
240
Default: LVPECL, AC coupled
VccCLKoutPlane
SMA
R211
DNP
82
C78
CLKout11_N
R215
240
R217
R216
DNP
62
0.1µF
68
C79
GND
R219
DNP
62
C
0.1µF
R223
DNP
120
GND
R224
DNP
82
R218
DNP
R220
DNP
62
CLKout10*
0.1µF
C82
SMA
CLKout11_P
0.1µF
R221
240
D
GND
CLKout10_1_N
CLKout10_N
CLKout11*
CLKout11_1_N
SMA
DNP
68
C80
DNP
C81
R212
51
R222
240
R225
DNP
51
VccCLKoutPlane
GND
R226
DNP
120
0.1µF
R227
DNP
82
CLKout11
CLKout11_1_P
SMA
DNP
R228
51
VccCLKoutPlane
Notes:
D
1. Designators greater than and equal to 300 are placed on bottom of PCB
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this
specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for
any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate
and test your design implementation to confirm the system functionality for your application.
1
C
2
3
4
48
SNLU107
Designed for: Evaluation Customer
Mod. Date: 4/26/2012
Project: LMK04816 Evaluation Board
Sheet Title: Clock Outputs 3/3
Sheet:8 of 9
Size: B
Schematic: 870600769
Rev: 1.0
Assembly Variant: LVPECL240 - 2011-07-26
File: OutClks2.SchDoc
Contact: http://www.national.com/support
5
http://www.ti.com
© Texas Instruments CopyrightYear
6
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
uWire Header, Logic I/O Ports and Status LEDs
1
2
3
4
CLKin Select
CLKin1_SEL
2
1
142-0711-201
DNP
CLKin0_SEL
2
A
DNP
TESTPOINT
CLKuWire_TP
R79
DNP
270
D2
D3
Red
Red
TESTPOINT
R313
27k
R317
TESTPOINT 15k
R318
uWire_CLKin1_SEL
TESTPOINT
15k
DATAuWire_TP
15k
R316
27k
B
TESTPOINT
LEuWire_TP
R321
uWire_LE
15k
DNPC308
100pF
Status_CLKin1
R322
27k
Status_CLKin0
SYNC Level Translation
C
uWire_CLKin0_SEL
uWire_CLKin1_SEL
uWire_Holdover
uWire_SYNC
uWire_CLKin0_SEL
R319
27k
R320
27k
9
7
5
3
1
R315
DNPC307
100pF
CLKIN0_SEL_TP
10
8
6
4
2
HEADER_2X5
uWire_DATA
CLKIN1_SEL_TP
uWire_LD
15k
DNPC306
100pF
R314
DNP
270
uWire
R312
uWire_CLK
B
6
uWire Header and Level Translation
142-0711-201
1
A
5
Holdover Status
uWire_Holdover
uWire_SYNC
Lock Detect Status
uWire_LD
Status_Hold
C
Status_LD
VccAuxPlane
D300
DNP 3.3V zener
CZRU52C3V3
R324
15k
SYNC
TESTPOINT
DNPC309
100pF
R80
15k
R81
15k
SYNC_TP
142-0711-201
Status_Hold
1
R325
27k
Holdover_TP
R82
0
DNP
TESTPOINT
LD_TP
R83
Status_LD
1
270
DNP
2
DNP
R323
DNP
2.2k
2
2
142-0711-201
SYNC
1
R86
DNP
27k
DNPC42
100pF
D4
Red
142-0711-201
R84
0
R87
DNP
27k
DNPC43
100pF
R85
TESTPOINT
270
D5
Green
An external 3.3V zener diode and 2.2k is
used to prevent SYNC input from going low
when the uWire programming cable is
disconnected while the board is in operation.
D
D
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this
specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for
any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate
and test your design implementation to confirm the system functionality for your application.
1
2
3
4
49
SNLU107
Designed for: Evaluation Customer
Mod. Date: 4/26/2012
Project: LMK04816 Evaluation Board
Sheet Title: MICROWIRE Interface
Sheet:4 of 9
Size: B
Schematic: 870600769
Rev: 1.0
Assembly Variant: LVPECL240 - 2011-07-26
File: LogicIO.SchDoc
Contact: http://www.national.com/support
5
http://www.ti.com
© Texas Instruments CopyrightYear
6
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
USB Interface
1
2
3
4
5
6
A
A
VccAuxPlane
R400
U_VCC3V3
0
USB_ID
USB_SHIELD_GND
U_VCC3V3
U_VCC3V3
R401
DNP
10k
J400
0.1µF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
B
CR401
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
U_VBus
22
USB_SHIELD_GND
C404 U_VCC3V3 R405
22
uWire_CLK
R406
DNP
33
R408
DNP
33
uWire_DATA
R409
DNP
33
uWire_LD
R410
DNP
33
C
U_VBus
USB_ID
LEUWIRE_LMK048xx
CLKUWIRE
DATAUWIRE
AT90USB1287-MU
DNP
PA3
PA4
PA5
PA6
PA7
PE2
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PE1
PE0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R403
DNP
33
uWire_SYNC
U_VCC3V3
R407
47k
C405
0.22µF
HWB
C
DNP
LD_LMK048xx
1
1µF
uWire_LE
PE6
PE7
UVcc
DD+
UGND
UCap
VBus
PE3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C403
10µF
R404
U400
2
UX60SA-MB-5ST
USB_SHIELD_GND
AVCC
GND
AREF
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
GND
VCC
PA0
PA1
PA2
0
0.1µF
DAP
PB7
PE4
PE5
RESETB
VCC
GND
XTAL2
XTAL1
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
R402
B
C401
C402
0.1µF
CR400
5
4
3
DNP
2
1
C400
U_VCC3V3
Y400
DNP
R411
8 MHz XTAL
47k
C406
18pF
2
U_VCC3V3
C407
18pF
C408
0.22µF
U_VCC3V3
RESET
DNP
C409
0.1µF
C411
1µF
C412
0.1µF
C413
0.01µF
C414
0.1µF
C415
0.01µF
1
C410
1µF
D
D
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this
specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for
any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate
and test your design implementation to confirm the system functionality for your application.
1
2
3
4
50
SNLU107
Designed for: Evaluation Customer
Mod. Date: 4/26/2012
Project: LMK04816 Evaluation Board
Sheet Title: USB Control. In development.
Sheet:9 of 9
Size: B
Schematic: 870600769
Rev: 1.0
Assembly Variant: LVPECL240 - 2011-07-26
File: onboard_usb.SchDoc
Contact: http://www.national.com/support
5
http://www.ti.com
© Texas Instruments CopyrightYear
6
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Appendix D: Bill of Materials
Table 17: Bill of Materials for LMK04816 Evaluation Boards
Item
Designator
Description
Manufacturer
PartNumber
Quantity
1
2
B2
C1, C5, C13, C20,
C22, C25, C300,
R3, R11, R12,
R19, R21, R22,
R29, R30, R37,
R46, R55, R73,
R74, R82, R84,
R229, R304, R327,
R329, R333, R337,
R340, R346, R347,
R349, R353, R354,
R358, R361, R364,
R365, R368, R371,
R373, R375, R400,
R402
ADT2-1T Balun
RES, 0 ohm, 5%, 0.1W, 0603
MiniCircuits
Vishay-Dale,
Vishey/Dale
ADT2-1T+
CRCW06030000Z0EA
1
44
3
C1_A1, C6, C14,
C19, C21, C24,
C27, C37, C38,
C44, C46, C47,
C48, C51, C52,
C53, C54, C57,
C58, C59, C60,
C63, C64, C65,
C66, C70, C71,
C72, C75, C76,
C77, C78, C81,
C82, C312, C319,
C329, C361
CAP, CERM, 0.1uF, 25V, +/-5%, X7R, 0603
Kemet
C0603C104J3RACTU
38
4
5
C1_A2
C1_B2
CAP, CERM, 47pF, 50V, +/-5%, C0G/NP0, 0603
CAP, CERM, 150pF, 50V, +/-5%, C0G/NP0, 0603
Kemet
Kemet
C0603C470J5GACTU
C0603C151J5GACTU
1
1
51
SNLU107
L M K 0 4 8 1 6
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
C2, C12, C41,
C302, C330, C346
C2pB2
C2_A1
C2_A2
C4, C69, C314,
C322, C326, C367,
C400, C401, C402,
C409, C412, C414
CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603
Kemet
C0603C104K4RACTU
6
CAP, CERM, 0.12uF, 50V, +/-10%, X7R, 0805
CAP, CERM, 0.68µF, 10V, +/-10%, X5R, 0603
CAP, CERM, 3900pF, 50V, +/-10%, X7R, 0603
CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603, CAP,
CERM, 0.1µF, 25V, +/-10%, X7R, 0603
Kemet
Kemet
MuRata
Kemet
C0805C124K5RACTU
C0603C684K8PAC
GRM188R71H392KA01D
C0603C104K3RACTU
1
1
1
12
C9
C10, C29, C32,
C341
C11
C23, C26, R104,
R112, R125, R126,
R133, R134, R213,
R215, R221, R222,
R231, R232, R338
CAP, CERM, 82pF, 50V, +/-10%, C0G/NP0, 0603
CAP, CERM, 2200pF, 50V, +/-10%, X7R, 0603
Kemet
Kemet
C0603C820K5GACTU
C0603C222K5RACTU
1
4
CAP, CERM, 10µF, 10V, +/-20%, X5R, 0805
RES, 240 ohm, 5%, 0.1W, 0603
Kemet
Vishay-Dale
C0805C106M8PACTU
CRCW0603240RJNEA
1
15
C28, C34
C35, C310, C317,
C324, Cb2pB1
C304
C311, C313, C318,
C321, C325, C331,
C342
CAP, CERM, 2pF, 50V, +/-12.5%, C0G/NP0, 0603
CAP, CERM, 10uF, 10V, +/-10%, X5R, 0805
Kemet
Kemet
C0603C209C5GACTU
C0805C106K8PACTU
2
5
CAP, CERM, 1000pF, 50V, +/-5%, C0G/NP0, 0603
CAP, CERM, 1uF, 10V, +/-10%, X5R, 0603
Kemet
Kemet
C0603C102J5GACTU
C0603C105K8PACTU
1
7
C315, C323
C340
C350, C351, C359,
C360
C368
C403
C404
C405, C408
C406, C407
C410, C411
C413, C415
CAP, CERM, 0.01uF, 100V, +/-10%, X7R, 0603
CAP, CERM, 4.7uF, 10V, +/-10%, X5R, 0603
CAP, CERM, 0.47uF, 16V, +/-10%, X7R, 0603
Kemet
Kemet
Kemet
C0603C103K1RACTU
C0603C475K8PACTU
C0603C474K4RACTU
2
1
4
CAP, CERM, 100pF, 50V, +/-5%, C0G/NP0, 0603
CAP, CERM, 10uF, 6.3V, +/-10%, X5R, 0805
CAP, TANT, 1uF, 20V, +/-10%, 8.4 ohm, 3216-18 SMD
CAP, CERM, 0.22uF, 16V, +/-10%, X7R, 0603
CAP, CERM, 18pF, 50V, +/-5%, C0G/NP0, 0603
CAP, CERM, 1uF, 16V, +/-10%, X5R, 0603
CAP, CERM, 0.01uF, 50V, +/-5%, X7R, 0603
Kemet
Kemet
Vishay-Sprague
Kemet
Kemet
Kemet
Kemet
C0603C101J5GACTU
C0805C106K9PAC
293D105X9020A2TE3
C0603C224K4RACTU
C0603C180J5GACTU
C0603C105K4PACTU
C0603C103J5RACTU
1
1
1
2
2
2
2
52
SNLU107
L M K 0 4 8 1 6
29
30
Cb1_B1
CLKin0, CLKin0*,
CLKin2, CLKin2*,
CLKout0,
CLKout0*,
CLKout2,
CLKout2*,
CLKout4,
CLKout4*,
CLKout6,
CLKout6*,
CLKout8,
CLKout8*,
CLKout10,
CLKout10*,
FBCLKin*/CLKin1*,
OSCout0,
OSCout0*
31
32
33
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
CAP, CERM, 0.33uF, 16V, +/-10%, X7R, 0603
Connector, SMT, End launch SMA 50 Ohm
Kemet
Emerson Network
Power
C0603C334K4RACTU
142-0701-851
1
19
CR400, CR401
D1
D2, D3, D4
ESD suppressor
Common Cathode Tuning Varactor
LED 2.8X3.2MM 565NM RED CLR SMD
PGB1010603MR
SMV1249-074LF
SML-LX2832IC
2
0
3
34
D5
LED 2.8X3.2MM 565NM GRN CLR SMD
SML-LX2832GC
1
35
36
J1
R2, R13, R59,
R70, R332
R2_A1
R2_A2
R2_B2
R4, R9
R18, R336, R342,
R343, R374
R24
R26, R27, R83,
R85
CONN TERM BLK PCB 5.08MM 2POS OR
RES, 0 ohm, 5%, 0.125W, 0805
Littelfuse Inc
Skyworks
Lumex
Opto/Components Inc.
Lumex
Opto/Components Inc.
Weidmuller
Vishay-Dale
1594540000
CRCW08050000Z0EA
1
5
RES, 39k ohm, 5%, 0.1W, 0603
RES, 620 ohm, 5%, 0.1W, 0603
RES, 470 ohm, 5%, 0.1W, 0603
RES, 100 ohm, 5%, 0.1W, 0603
FB, 1000 ohm, 600 mA, 0603, Ferrite
Vishay-Dale
Vishay-Dale
Vishay-Dale
Vishay-Dale
Murata
CRCW060339K0JNEA
CRCW0603620RJNEA
CRCW0603470RJNEA
CRCW0603100RJNEA
BLM18HE102SN1D
1
1
1
2
5
RES, 18 ohm, 5%, 0.1W, 0603
RES, 270 ohm, 5%, 0.1W, 0603
Vishay-Dale
Vishay-Dale
CRCW060318R0JNEA
CRCW0603270RJNEA
1
4
37
38
39
40
41
42
43
53
SNLU107
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
44
R35, R38, R41,
R43, R44, R61,
R102, R117, R124,
R138, R142, R158,
R164, R182, R190,
R206, R212, R228
RES, 51 ohm, 5%, 0.1W, 0603
Vishay-Dale
CRCW060351R0JNEA
18
45
46
R62, R67
R80, R81, R312,
R315, R317, R318,
R321, R324
RES, 4.7k ohm, 5%, 0.1W, 0603
RES, 15k ohm, 5%, 0.1W, 0603
Vishay-Dale
Vishay-Dale
CRCW06034K70JNEA
CRCW060315K0JNEA
2
8
47
R107, R108, R129,
R130, R151, R152,
R173, R174, R195,
R196, R217, R218
RES, 68 ohm, 5%, 0.1W, 0603
Vishay-Dale
CRCW060368R0JNEA
12
48
49
50
R233, R234
R307
R313, R316, R319,
R320, R322, R325
RES, 33 ohm, 5%, 0.1W, 0603
RES, 10k ohm, 5%, 0.1W, 0603
RES, 27k ohm, 5%, 0.1W, 0603
Vishay-Dale
Vishay-Dale
Vishay-Dale
CRCW060333R0JNEA
CRCW060310K0JNEA
CRCW060327K0JNEA
2
1
6
51
R331, R341, R345,
R348, R355, R359,
R362, R366, R372
FB, 120 ohm, 500 mA, 0603
Murata
BLM18AG121SN1D
9
52
53
54
55
56
57
58
59
R344
R350, R369
R351
R356
R404, R405
R407, R411
Rb2_B1
S1, S2, S3, S4, S5,
S6
U1
U2
U4, U300
RES, 392 ohm, 1%, 0.1W, 0603
RES, 51k ohm, 5%, 0.1W, 0603
RES, 2.00k ohm, 1%, 0.1W, 0603
RES, 866 ohm, 1%, 0.1W, 0603
RES, 22 ohm, 5%, 0.125W, 0805
RES, 47k ohm, 5%, 0.1W, 0603
RES, 3.9k ohm, 5%, 0.1W, 0603
0.875" Standoff
Vishay-Dale
Vishay-Dale
Vishay-Dale
Vishay-Dale
Vishay-Dale
Vishay-Dale
Vishay-Dale
VOLTREX
CRCW0603392RFKEA
CRCW060351K0JNEA
CRCW06032K00FKEA
CRCW0603866RFKEA
CRCW080522R0JNEA
CRCW060347K0JNEA
CRCW06033K90JNEA
SPCS-14
1
2
1
1
2
2
1
6
LMK04816
122.88 MHz VCXO
Precison Single Low Noise, Low 1/F corner Op Amp
Texas Instruments
Crystek
National
LMK04816BISQ
CVHD-950-122.88
LMP7731MF
1
1
2
60
61
62
54
SNLU107
L M K 0 4 8 1 6
63
U302
64
U303, U305
65
66
uWire
Vcc
67
VccVCO/Aux,
VccVCXO/Aux
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Micropower 800mA Low Noise 'Ceramic Stable'
Adjustable Voltage Regulator for 1V to 5V Applications
Ultra Low Noise, 150mA Linear Regulator for
RF/Analog Circuits Requires No Bypass Capacitor
Low Profile Vertical Header 2x5 0.100"
Connector, TH, SMA
Connector, SMA Jack, Vertical, Gold, SMD
55
Semiconductor
National
Semiconductor
National
Semiconductor
FCI
Emerson Network
Power
Emerson Network
Power Connectivity
SNLU107
LP3878SD-ADJ
1
LP5900SD-3.3
2
52601-G10-8LF
142-0701-201
1
1
142-0711-201
2
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Appendix E: PCB Layers Stackup
6-layer PCB Stackup includes:
Top Layer for high-priority high-frequency signals (2 oz.)
RO4003 Dielectric, 16 mils
RF Ground plane (1 oz.)
FR4, 4 mils
Power plane #1 (1 oz.)
FR4, 12.6 mils
Ground plane (1 oz.)
FR4, 8 mils
Power Plane #2 (1 oz.)
FR4, 12 mils
Bottom Layer copper clad for thermal relief (2 oz.)
Top Layer [LMK04816ENG.GTL]
RO4003 (Er = 3.3)
16 mil
RF Ground plane [LMK04816ENG.GP1]
FR4 (Er = 4.8)
4 mil
FR4
12.6 mil
Ground plane [LMK04816ENG.GP2]
FR4
8 mil
Power plane #2 [LMK04816ENG.G2]
FR4
12 mil
Bottom Layer [LMK04816ENG.GBL]
56
SNLU107
62.2 mil thick
Power plane #1 [LMK04816ENG.G1]
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Appendix F: PCB Layout
Layer #1 – Top
57
SNLU107
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Layer #2 – RF Ground Plane (Inverted)
58
SNLU107
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Layer #3 – Vcc Planes
59
SNLU107
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Layer #4 – Ground Plane (Inverted)
60
SNLU107
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Layer # 5 – Vcc Planes 2
61
SNLU107
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Layer #6 – Bottom
62
SNLU107
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Layers #1 and 6 – Top and Bottom (Composite)
63
SNLU107
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
64
SNLU107
L M K 0 4 8 1 6
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Appendix G: Properly Configuring LPT Port
When trying to solve any communications issue, it is most convenient to verify communication
by programming the POWERDOWN bit to confirm normal or low supply current consumption
of the evaluation board.
LPT Driver Loading
The parallel port must be configured for proper operation. To confirm that the LPT port driver is
successfully loading click “LPT/USB”  “Check LPT.” If the driver properly loads then the
following message is displayed:
Figure 18: Successfully Opened LPT Driver
Successful loading of LPT driver does not mean LPT communications in CodeLoader are setup
properly. The proper LPT port must be selected and the LPT port must not be in an improper
mode.
The PC must be rebooted after install for LPT support to work properly.
Correct LPT Port/Address
To determine the correct LPT port in Windows, open the device manager (On Windows XP,
Start  Settings  Control Panel  System  Hardware tab  Device Manager) and check
the LPT port under the Ports (COM & LPT) node of the tree. It can be helpful to confirm that
the LPT port is mapped to the expected port address, for instance to confirm that LPT1 is really
mapped to address 0x378. This can be checked by viewing the Properties of the LPT1 port and
viewing Resources tab to verify that the I/O Range starts at 0x378. CodeLoader expects the
traditional port mapping:
Port
Address
LPT1
0x378
LPT2
0x278
LPT3
0x3BC
If a non-standard address is used, use the “Other” port address in CodeLoader and type in the
port address in hexadecimal. It is possible to change the port address in the computer‟s BIOS
settings. The port address can be set in CodeLoader in the Port Setup tab as shown in Figure 19.
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Figure 19: Selecting the LPT Port Address
Correct LPT Mode
If communications are not working, then it is possible the LPT port mode is set improperly. It is
recommended to use the simple, Output-only mode of the LPT port. This can be set in the BIOS
of the computer. Common terms for this desired parallel port mode are “Normal,” “Output,” or
“AT.” It is possible to enter BIOS setup during the initial boot up sequence of the computer.
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Appendix H: Troubleshooting Information
If the evaluation board is not behaving as expected, the most likely issues are…
1) Board communication issue
2) Incorrect Programming of the device
3) Setup Error
Refer to this checklist for a practical guide on identifying/exposing possible issues.
1) Confirm Communications
Refer to Appendix G: Properly Configuring LPT Port to troubleshoot this item.
Remember to load device with Ctrl+L.
2) Confirm PLL1 operation/locking
1) Program LD_MUX = “PLL1_R/2”
2) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
i. If not, examine CLKin_SEL programming.
ii. If not, examine CLKin0_BUFTYPE / CLKin1_BUFTYPE.
iii. If not, examine PLL1 register R programming.
iv. If not, examine physical CLKin input.
3) Program LD_MUX = “PLL1_N /2”
4) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
i. If not, examine PLL1 register N programming.
ii. If not, examine physical OSCin input.
Naturally, the output frequency of the above two items, PLL 1 R Divider/2 and PLL 1 N Divider
/2, on LD pin should be the same frequency.
5) Program LD_MUX = “PLL1_DLD”
6) Confirm the LD pin output is high.
i.
If high, then PLL1 is locked, continue to PLL2 operation/locking.
7) If LD pin output is low, but the frequencies are the same, it is possible that excessive
leakage on Vtune pin is causing the digital lock detect to not activate. By default
PLL2 waits for the digital lock detect to go high before allowing PLL2 and the
integrated VCO to lock. Different VCXO models have different input leakage
specifications. High leakage, low PLL1 phase detector frequencies, and low PLL1
charge pump current settings can cause the PLL1 charge pump to operate longer than
the digital lock detect timeout which allows the device to lock, but prevents the
digital lock detect from activating.
i.
Redesign PLL1 loop filter with higher phase detector frequency
ii. Redesign PLL1 loop filter with higher charge pump current
iii. Isolate VCXO tuning input from PLL1 charge pump with an op amp.
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3) Confirm PLL2 operation/locking
1) Program LD_MUX = “PLL2_R/2”
2) Confirm that LD pin output is half the expected phase detector frequency of PLL2.
i. If not, examine PLL2_R programming.
ii. If not, examine physical OSCin input.
3) Program LD_MUX = “PLL2_N/2”
4) Confirm that LD pin output is half the expected phase detector frequency of PLL2.
i. If not, confirm OSCin_FREQ is programmed to OSCin frequency.
ii. If not, examine PLL2_N programming.
Naturally, the output frequency of the above two items should be the same frequency.
5) Program LD_MUX = “PLL2 DLD”
6) Confirm the LD pin output is high.
7) Program LD_MUX = “PLL1 & PLL2 DLD”
8) Confirm the LD pin output is high.
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EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following
conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the
user indemnifies TI from all claims arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/ kit
may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED
WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL
OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF
THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide
prior to handling the product. This notice contains important safety information about temperatures and
voltages. For additional information on TI's environmental and/or safety programs, please visit
www.ti.com/esh or contact TI.
No license is granted under any patent right or other intellectual property right of TI covering or relating to
any machine, process, or combination in which such TI products or services might be or are used. TI
currently deals with a variety of customers for products, and therefore our arrangement with the user is
not exclusive. TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2012, Texas Instruments Incorporated
REGULATORY COMPLIANCE INFORMATION
As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or
may not be subject to the Federal Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for
ENGINEERING DEVELOPMENT, DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not
considered by TI to be a finished end product fit for general consumer use. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of the equipment may cause interference with
radio communications, in which case the user at his own expense will be required to take whatever
measures may be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: This radio is intended for development/professional use only in
legally allocated frequency and power limits. Any use of radio frequencies and/or power availability of this
EVM and its development application(s) must comply with local laws governing radio spectrum allocation
and power limits for this evaluation module. It is the user’s sole responsibility to only operate this radio in
legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this
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is strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate
experimental/development licenses from local regulatory authorities, which is responsibility of user
including its acceptable authorization.
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference
received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the
user's authority to operate the equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant
to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference when the equipment is operated in a commercial environment. This equipment generates,
uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment
in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant
to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference in a residential installation. This equipment generates, uses and can radiate radio frequency
energy and, if not installed and used in accordance with the instructions, may cause harmful interference
to radio communications. However, there is no guarantee that interference will not occur in a particular
installation. If this equipment does cause harmful interference to radio or television reception, which can
be determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is
connected.
Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the
user’s authority to operate the equipment.
Concerning EVMs including radio transmitters
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This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the
following two conditions: (1) this device may not cause interference, and (2) this device must accept any
interference, including interference that may cause undesired operation of the device.
Concerning EVMs including detachable antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type
and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio
interference to other users, the antenna type and its gain should be so chosen that the equivalent
isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in
the user guide with the maximum permissible gain and required antenna impedance for each antenna
type indicated. Antenna types not included in this list, having a gain greater than the maximum gain
indicated for that type, are strictly prohibited for use with this device.
~
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la
conformité ont pu vider l’autorité de l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts
de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire
de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le
brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec
une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada.
Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut
choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne
dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne
énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour
chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au
gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
Important Notice for Users of this Product in Japan】
This development kit is NOT certified as Confirming to Technical Regulations of
Radio Law of Japan!
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below
with respect to this product:
(1) Use this product in a shielded room or any other test facility as defined in the notification #173
issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1
of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan,
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(2) Use this product only after you obtained the license of Test Radio Station as provided in Radio
Law of Japan with respect to this product, or
(3) Use of this product only after you obtained the Technical Regulations Conformity Certification
as provided in Radio Law of Japan with respect to this product.
Also, please do not transfer this product, unless you give the same notice above to the transferee.
Please note that if you could not follow the instructions above, you will be subject to penalties of Radio
Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjukku-ku, Tokyo, Japan
http://www.tij.co.jp
【ご使用にあたっての注意】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありま
すのでご注意ください。
（１）電波法施行規則第 6 条第 1 項第 1 号に基づく平成 18 年 3 月 28 日総務省告示第 173 号で
定められた電波暗室等の試験設備でご使用いただく。
（２）実験局の免許を取得後ご使用いただく。
（３）技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転
できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
http://www.tij.co.jp
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EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise
indicated, this EVM is not a finished electrical equipment and not intended for consumer use. It is
intended solely for use for preliminary feasibility evaluation in laboratory/development environments by
technically qualified electronics experts who are familiar with the dangers and application risks associated
with handling electrical mechanical components, systems and subsystems. It should not be used as all or
part of a finished end product.
Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1. You have unique knowledge concerning Federal, State and local regulatory requirements (including
but not limited to Food and Drug Administration regulations, if applicable) which relate to your
products and which relate to your use (and/or that of your employees, affiliates, contractors or
designees) of the EVM for evaluation, testing and other purposes.
2. You have full and exclusive responsibility to assure the safety and compliance of your products with
all such laws and other applicable regulatory requirements, and also to assure the safety of any
activities to be conducted by you and/or your employees, affiliates, contractors or designees, using
the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical)
between the EVM and any human body are designed with suitable isolation and means to safely limit
accessible leakage currents to minimize the risk of electrical shock hazard.
3. You will employ reasonable safeguards to ensure that your use of the EVM will not result in any
property damage, injury or death, even if the EVM should fail to perform as described or expected.
4. You will take care of proper disposal and recycling of the EVM’s electronic components and packing
materials.
Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and
environmental considerations per the user guidelines. Exceeding the specified EVM ratings (including but
not limited to input and output voltage, current, power, and environmental ranges) may cause property
damage, personal injury or death. If there are questions concerning these ratings please contact a TI field
representative prior to connecting interface electronics including input power and intended loads. Any
loads applied outside of the specified output range may result in unintended and/or inaccurate operation
and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM
User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative. During normal operation, some circuit components
o
may have case temperatures greater than 60 C as long as the input and output are maintained at a
normal ambient operating temperature. These components include but are not limited to linear regulators,
switching transistors, pass transistors, and current sense resistors which can be identified using the EVM
schematic located in the EVM User's Guide. When placing measurement probes near these devices
during normal operation, please be aware that these devices may be very warm to the touch. As with all
electronic evaluation tools, only qualified personnel knowledgeable in electronic measurement and
diagnostics normally found in development environments should use these EVMs.
Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its
licensors and their representatives harmless from and against any and all claims, damages, losses,
expenses, costs and liabilities (collectively, "Claims") arising out of or in connection with any use of the
EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether
Claims arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as
described or expected.
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Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use
in safety critical applications (such as life support) where a failure of the TI product would reasonably be
expected to cause severe personal injury or death, such as devices which are classified as FDA Class III
or similar classification, then you must specifically notify TI of such intent and enter into a separate
Assurance and Indemnity Agreement.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,
modifications, enhancements, improvements, and other changes to its products and services at any time
and to discontinue any product or service without notice. Customers should obtain the latest relevant
information before placing orders and should verify that such information is current and complete. All
products are sold subject to TI’s terms and conditions of sale supplied at the time of order
acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the
extent TI deems necessary to support this warranty. Except where mandated by government
requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are
responsible for their products and applications using TI components. To minimize the risks associated
with customer products and applications, customers should provide adequate design and operating
safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI
patent right, copyright, mask work right, or other TI intellectual property right relating to any combination,
machine, or process in which TI products or services are used. Information published by TI regarding
third-party products or services does not constitute a license from TI to use such products or services or
a warranty or endorsement thereof. Use of such information may require a license from a third party
under the patents or other intellectual property of the third party, or a license from TI under the patents or
other intellectual property of TI. Reproduction of information in TI data books or data sheets is
permissible only if reproduction is without alteration and is accompanied by all associated warranties,
conditions, limitations, and notices.
Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such
altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and
deceptive business practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure
of the TI product would reasonably be expected to cause severe personal injury or death, unless officers
of the parties have executed an agreement specifically governing such use. Buyers represent that they
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acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications,
notwithstanding any applications-related information or support that may be provided by TI. Further,
Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI
products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments
unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only
products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree
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connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless
the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers
acknowledge and agree that, if they use any non-designated products in automotive applications, TI will
not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and
application solutions:
Products
Amplifiers
Audio
Applications
amplifier.ti.com
www.ti.com/audio
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Data Converters
Automotive
DSP
Broadband
Interface
Digital Control
Logic
Military
Power Mgmt
Optical Networking
Microcontrollers
Security
RFID
Telephony
Low Power
Video & Imaging
Wireless
O P E R A T I N G
I N S T R U C T I O N S
dataconverter.ti.com
www.ti.com/automotive
dsp.ti.com
www.ti.com/broadband
interface.ti.com
www.ti.com/digitalcontrol
logic.ti.com
www.ti.com/military
power.ti.com
www.ti.com/opticalnetwork
microcontroller.ti.com
www.ti.com/security
www.ti-rfid.com
www.ti.com/telephony
www.ti.com/lpw
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
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