CDC209, CDC209–7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS SCAS108D – MARCH 1990 – REVISED MAY 1997 D D D D D D D D D D DW OR N PACKAGE (TOP VIEW) CDC209 Replaces 74AC11208 CDC209-7 Replaces 74AC11208-7 Low-Skew Propagation Delay Specifications for Clock-Driver Applications CMOS-Compatible Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Characterized for Operation at 5-V and 3.3-V VCC Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Package (DW) and Standard Plastic 300-mil DIPs (N) 1Y2 1Y3 1Y4 GND GND GND GND 2Y1 2Y2 2Y3 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1Y1 1A 1OE1 1OE2 VCC VCC 2A 2OE1 2OE2 2Y4 description The CDC209/209-7 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input. Skew parameters are specified for a reduced temperature and voltage range common to many applications. The CDC209/209-7 is characterized for operation fromTA = – 40°C to 85°C. FUNCTION TABLES INPUTS OUTPUTS 1OE1 1OE2 1A 1Y1 1Y2 1Y3 1Y4 L L L L L L L L L H H H H H L H X L L L L H L X H H H H H H X Z Z Z Z INPUTS OUTPUTS 2OE1 2OE2 2A 2Y1 2Y2 2Y3 L L L L L L 2Y4 L L L H H H H H L H X L L L L H L X H H H H H H X Z Z Z Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDC209, CDC209–7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS SCAS108D – MARCH 1990 – REVISED MAY 1997 logic symbol† X/Y 1OE1 18 17 1OE2 1 2 1 1 V4 2 G5 3 EN 4, 5 20 1 1A 4, 5 19 2 4, 5 3 4, 5 2OE1 13 8 12 9 2OE2 2A 10 11 14 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE1 18 20 1OE2 17 1 2 3 1A 2OE1 19 9 11 2 1Y3 1Y4 2Y1 12 10 2A 1Y2 13 8 2OE2 1Y1 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Y2 2Y3 2Y4 CDC209, CDC209–7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS SCAS108D – MARCH 1990 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.6 W N package . . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL Low-level input voltage VI Input voltage IOH IOL Input transition rise or fall rate Input clock frequency MAX 3 5 5.5 3.85 0.9 1.35 VCC –4 V – 24 mA VCC = 5.5 V VCC = 3 V – 24 VCC = 4.5 V VCC = 5.5 V 24 12 mA 24 – 40 • DALLAS, TEXAS 75265 V 1.65 0 POST OFFICE BOX 655303 V V 3.15 VCC = 3 V VCC = 4.5 V Operating free-air temperature UNIT 2.1 0 Low-level output current fclock TA NOM VCC = 4.5 V VCC = 5.5 V High-level output current ∆t / ∆v MIN 10 ns / V 60 MHz 85 °C 3 CDC209, CDC209–7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS SCAS108D – MARCH 1990 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC = 3 V IOH = – 50 µA VCC = 4 4.5 5V VCC = 5 5.5 5V VOH High-level output voltage IOH = – 4 mA VCC = 3 V 5V VCC = 4 4.5 IOH = – 24 mA VCC = 5 5.5 5V IOH = – 75 mA‡, VCC = 5.5 V VCC = 3 V IOL = 50 µA VCC = 4 4.5 5V VCC = 5 5.5 5V VOL Low-level output voltage IOL = 12 mA VCC = 3 V VCC = 4 4.5 5V IOL = 24 mA 5V VCC = 5 5.5 IOL = 75 mA‡, VCC = 5.5 V II Input current VI = VCC or GND VCC = 5 5.5 5V IOZ High impedance output current High-impedance VO = VCC or GND 5V VCC = 5 5.5 ICC Supply current VI = VCC or GND,, IO = 0 VCC = 5 5.5 5V Ci TA† 25°C MIN Full range 2.9 25°C 4.4 Full range 4.4 25°C 5.4 Full range 5.4 25°C 2.58 Full range 2.48 25°C 3.94 Full range 3.8 25°C 4.94 Full range 4.8 Full range POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 3.85 V 25°C 0.1 Full range 0.1 25°C 0.1 Full range 0.1 25°C 0.1 Full range 0.1 25°C 0.36 Full range 0.44 25°C 0.36 Full range 0.44 25°C 0.36 Full range 0.44 Full range 1.65 25°C ± 0.1 ±1 Full range ± 0.5 25°C ±5 Full range 25°C 8 Full range 80 Input capacitance VI = VCC or GND VCC = 5 V 25°C Co Output capacitance VO = VCC or GND VCC = 5 V 25°C † Full range is TA = – 40°C to 85°C. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. 4 TYP 2.9 V µA µA µA 4 pF 10 pF CDC209, CDC209–7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS SCAS108D – MARCH 1990 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH Propagation delay time time, low low-to-high to high level 1A and 2A Any Y tPHL Propagation delay time, time high-to-low high to low level 1A and 2A Any Y Propagation delay time, time low-to-high low to high level 1OE1,, 1OE2,, and 2OE1, 2OE2 tPHL time high-to-low high to low level Propagation delay time, 1OE1,, 1OE2,, and 2OE1, 2OE2 Any Y tPZH Enable time to the high level 1OE2 or 2OE2 Any Y tPLH tPZL tPHZ tPLZ Enable time to the low level 1OE1 or 2OE1 Disable time from the high level 1OE2 or 2OE2 Disable time from the low level 1OE1 or 2OE1 Any Y Any Y Any Y Any Y TA† MIN TYP MAX UNIT 11.1 13.1 ns 14.6 ns 14.3 ns 15.6 ns 14.2 ns 15.8 ns 15.7 ns 17.4 ns 14.2 ns 15.7 ns 19.5 ns 22.8 ns 8.6 ns 9.2 ns 9.4 ns 10.2 ns MAX UNIT 25°C 4.8 Full range 4.8 25°C 5.1 Full range 5.1 25°C 5.2 Full range 5.2 25°C 7.8 Full range 7.8 25°C 5.1 Full range 5.1 25°C 6.8 Full range 6.8 25°C 3.4 Full range 3.4 25°C 4.1 Full range 4.1 12.2 11.9 13.3 11.8 16.3 6.9 7.5 † Full range is TA = – 40°C to 85°C. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH Propagation delay time time, low low-to-high to high level 1A and 2A Any Y tPHL time high-to-low high to low level Propagation delay time, 1A and 2A Any Y tPLH Propagation delay time, time low-to-high low to high level 1OE1,, 1OE2,, and 2OE1, 2OE2 Any Y tPHL Propagation delay time, time high-to-low high to low level 1OE1,, 1OE2,, and 2OE1, 2OE2 Any Y tPZH Enable time to the high level 1OE2 or 2OE2 Any Y tPZL Enable time to the low level 1OE1 or 2OE1 Any Y tPHZ Disable time from the high level 1OE2 or 2OE2 Any Y tPLZ Disable time from the low level 1OE1 or 2OE1 Any Y TA† MIN TYP 5.5 25°C 4.2 Full range 4.2 25°C 4.2 Full range 4.2 25°C 4.6 Full range 4.6 25°C 4.8 Full range 4.8 25°C 4.3 Full range 4.3 25°C 5.3 Full range 5.3 25°C 3 Full range 3 25°C 3.7 Full range 3.7 9 9.9 7 9.3 10.1 7.3 9.6 10.7 7.7 10.2 11 7.2 9.4 4 9 12.2 13.5 5.4 7.5 8 5.7 7.5 ns ns ns ns ns ns ns ns 8.2 † Full range is TA = – 40°C to 85°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDC209, CDC209–7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS SCAS108D – MARCH 1990 – REVISED MAY 1997 switching characteristics, VCC = 5 V ± 0.25 V, TA = 25°C to 70°C (see Note 3 and Figures 1 and 2) FROM (INPUT) TO (OUTPUT) 1A and 2A Any Y 1A and 2A Any Y PARAMETER tPLH tPHL Propagation delay time, low-to-high level tsk(o) output skew time Propagation delay time, high-to-low level CDC209 CDC209-7 MIN MAX MIN MAX 6 8.5 6 8.5 6 9.3 6 9.3 1 0.7 UNIT ns ns NOTE 3: All specifications are valid only for all outputs switching simultaneously and in phase. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled Power dissipation capacitance per bank Outputs disabled CL = 50 pF, pF MIN TYP MAX 95 f = 1 MHz UNIT pF 10 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) 500 Ω VCC Output Control (low-level enabling) LOAD CIRCUIT FOR OUTPUTS 50% VCC 50% 50% 0V tPLH Output tPHL VOH 50% VCC VOL 50% VCC tPLZ ≈ VCC Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at GND (see Note C) 50% 0V tPZL Input (see Note B) S1 Open 2 × VCC GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 50% VCC tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 20% VCC VOL tPHZ 50% VCC 80% VCC VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC209, CDC209–7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS SCAS108D – MARCH 1990 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 1A, 2A 1Y1 tPLH1 tPHL1 tPLH2 tPHL2 tPLH3 tPHL3 tPLH4 tPHL4 tPLH5 tPHL5 tPLH6 tPHL6 tPLH7 tPHL7 tPLH8 tPHL8 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 NOTE D: Output skew, tsk(o), is calculated as the greater of: – The difference between the fastest and slowest of tPLHn (n = 1, 2, . . . , 8) – The difference between the fastest and slowest of tPHLn (n = 1, 2, . . . , 8) Figure 2. Waveforms for Calculation of tsk(o) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CDC209, CDC209–7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS SCAS108D – MARCH 1990 – REVISED MAY 1997 MECHANICAL INFORMATION DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN PINS ** 0.050 (1,27) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) 4040000 / B 03/95 NOTES: A. B. C. D. 8 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC209, CDC209–7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS SCAS108D – MARCH 1990 – REVISED MAY 1997 MECHANICAL INFORMATION N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PIN SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23.37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21.59) 0.940 (23,88) DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0°– 15° 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) CDC209-7DW OBSOLETE SOIC DW 20 TBD Call TI Call TI CDC209-7DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI CDC209DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI CDC209DW OBSOLETE SOIC DW 20 TBD Call TI Call TI CDC209DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI CDC209N OBSOLETE PDIP N 20 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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