LMV981-N, LMV982-N www.ti.com SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 LMV981-N Single / LMV982 Dual 1.8V, RRIO Operational Amplifiers with Shutdown Check for Samples: LMV981-N, LMV982-N FEATURES DESCRIPTION • LMV981-N/LMV982 are low voltage, low power operational amplifiers. LMV981-N/LMV982 operate from +1.8V to +5.0V supply voltages and have rail-torail input and output. LMV981-N/LMV982 input common mode voltage extends 200mV beyond the supplies which enables user enhanced functionality beyond the supply voltage range. The output can swing rail-to-rail unloaded and within 105mV from the rail with 600Ω load at 1.8V supply. LMV981N/LMV982 are optimized to work at 1.8V which make them ideal for portable two-cell battery powered systems and single cell Li-Ion systems. 1 2 • • • • • • • • • • (Typical 1.8V Supply Values; Unless Otherwise Noted) Ensured 1.8V, 2.7V and 5V Specifications Output Swing – w/600Ω load 80mV from Rail – w/2kΩ load 30mV from Rail VCM 200mV Beyond Rails Supply Current (Per Channel) 100μA Gain Bandwidth Product 1.4MHz Maximum VOS 4.0mV Gain w/600Ω Load 101dB Ultra Tiny Package DSBGA 1.0mm x 1.5mm Turn-On Time from Shutdown 19μs Temperature Range −40°C to 125°C APPLICATIONS • • • • • • • • Industrial and Automotive Consumer Communication Consumer Computing PDAs Portable audio Portable/Battery-Powered Electronic Equipment Supply Current Monitoring Battery Monitoring LMV981-N/LMV982 offer a shutdown pin that can be used to disable the device and reduce the supply current. The device is in shutdown when the SHDNpin = low. The output will be high impedance in shutdown. LMV981-N/LMV982 exhibit excellent speed-power ratio, achieving 1.4MHz gain bandwidth product at 1.8V supply voltage with very low supply current. LMV981-N/LMV982 are capable of driving a 600Ω load and up to 1000pF capacitive load with minimal ringing. LMV981-N/LMV982 have a high DC gain of 101dB, making them suitable for low frequency applications. LMV981-N is offered in space saving 6-Bump DSBGA, SC70-6 and SOT-23-6 packages. The 6Bump DSBGA package has only a 1.006mm x 1.514mm x 0.945mm footprint. LMV982 is offered in space saving VSSOP-10 package. These small packages are ideal solutions for area constrained PC boards and portable electronics such as cellular phones and PDAs. Typical Application 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2013, Texas Instruments Incorporated LMV981-N, LMV982-N SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) (3) Machine Model 200V Human Body Model 2000V Supply Voltage (V+–V −) 5.5V Differential Input Voltage ± Supply Voltage Voltage at Input/Output Pins V++0.3V, V--0.3V Storage Temperature Range −65°C to 150°C Junction Temperature (4) 150°C For soldering specifications: http://www.ti.com/lit/SNOA549f (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX) , θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX)–T A)/θJA. All numbers apply for packages soldered directly into a PC board. (2) (3) (4) Operating Ratings (1) Supply Voltage Range 1.8V to 5.0V −40°C to 125°C Temperature Range Thermal Resistance (θJA) 6-Bump DSBGA 286°C/W SC70-6 414°C/W SOT-23-6 265°C/W VSSOP-10 235°C/W (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. 1.8V DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 1.8V, V − = 0V, VCM = V+/2, VO = V+/2, RL > 1 MΩ and SHDN tied to V+. Boldface limits apply at the temperature extremes. See (1). Parameter VOS Input Offset Voltage Test Conditions Min (2) Typ (3) LMV981-N (Single) 1 4 6 LMV982 (Dual) 1 5.5 7.5 TCVOS Input Offset Voltage Average Drift 5.5 IB Input Bias Current 15 (1) (2) (3) 2 Max (2) Units mV μV/°C 35 50 nA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Application Note section for information on temperature derating of this device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N LMV981-N, LMV982-N www.ti.com SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 1.8V DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 1.8V, V − = 0V, VCM = V+/2, VO = V+/2, RL > 1 MΩ and SHDN tied to V+. Boldface limits apply at the temperature extremes. See (1). Parameter Test Conditions Min (2) Typ (3) Max (2) IOS Input Offset Current 13 25 40 IS Supply Current (per channel) 103 185 205 LMV981-N (Single) 0.156 1 2 LMV982 (Dual) 0.178 3.5 5 In Shutdown CMRR Common Mode Rejection Ratio LMV981-N, 0 ≤ VCM ≤ 0.6V 1.4V ≤ VCM ≤ 1.8V 60 55 78 LMV982, 0 ≤ VCM ≤ 0.6V 1.4V ≤ VCM ≤ 1.8V (4) 55 50 76 −0.2V ≤ VCM ≤ 0V 1.8V ≤ VCM ≤ 2.0V 50 72 75 70 100 V− −0.2 −0.2 to 2.1 (4) PSRR Power Supply Rejection Ratio 1.8V ≤ V+ ≤ 5V CMVR Input Common-Mode Voltage Range For CMRR Range ≥ 50dB TA = 25°C TA = 125°C AV Large Signal Voltage Gain LMV981-N (Single) Large Signal Voltage Gain LMV982 (Dual) VO Output Swing V −0.2 V +0.2 77 73 101 RL = 2kΩ to 0.9V, VO = 0.2V to 1.6V, VCM = 0.5V 80 75 105 RL = 600Ω to 0.9V, VO = 0.2V to 1.6V, VCM = 0.5V 75 72 90 RL = 2kΩ to 0.9V, VO = 0.2V to 1.6V, VCM = 0.5V 78 75 100 1.65 1.63 1.72 RL = 2kΩ to 0.9V VIN = ± 100mV 1.75 1.74 (5) Sourcing, VO = 0V VIN = 100mV 4 3.3 8 Sinking, VO = 1.8V VIN = −100mV 7 5 9 Ton Turn-on Time from Shutdown VSHDN Turn-on Voltage to enable part 1.0 Turn-off Voltage 0.55 (4) (5) dB dB 0.105 0.120 1.77 0.024 Output Short Circuit Current V + 0.077 IO V+ +0.2 V+ RL = 600Ω to 0.9V, VO = 0.2V to 1.6V, VCM = 0.5V RL = 600Ω to 0.9V VIN = ± 100mV μA dB V − nA dB − TA = −40°C to 85°C Units V 0.035 0.04 19 mA μs V For ensured temperature ranges, see Input Common-Mode Voltage Range specifications. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45mA over long term may adversely affect reliability. Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N Submit Documentation Feedback 3 LMV981-N, LMV982-N SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com 1.8V AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 1.8V, V − = 0V, VCM = V+/2, VO = V+/2, RL > 1 MΩ and SHDN tied to V+. Boldface limits apply at the temperature extremes. See (1). Parameter SR Slew Rate GBW Φm Test Conditions See Min (2) (3) Typ (4) Max (2) Units 0.35 V/μs Gain-Bandwidth Product 1.4 MHz Phase Margin 67 deg Gm Gain Margin 7 dB en Input-Referred Voltage Noise f = 10 kHz, VCM = 0.5V 60 nV/√Hz in Input-Referred Current Noise f = 10 kHz 0.08 pA/√Hz THD Total Harmonic Distortion f = 1kHz, AV = +1 RL = 600Ω, VIN = 1 VPP 0.023 Amp-to-Amp Isolation (1) (2) (3) (4) (5) See (5) % 123 dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Application Note section for information on temperature derating of this device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates. Input referred, RL = 100kΩ connected to V+/2. Each amp excited in turn with 1kHz to produce VO = 3VPP. (For Supply Voltages <3V, VO = V+). 2.7V DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 2.7V, V − = 0V, VCM = V+/2, VO = V+/2, RL > 1 MΩ and SHDN tied to V+. Boldface limits apply at the temperature extremes. See (1). Parameter VOS Input Offset Voltage Test Conditions Min (2) Typ (3) Max (2) Units LMV981-N (Single) 1 4 6 mV LMV982 (Dual) 1 6 7.5 mV μV/°C TCVOS Input Offset Voltage Average Drift 5.5 IB Input Bias Current 15 35 50 nA IOS Input Offset Current 8 25 40 nA IS Supply Current (per channel) 105 190 210 LMV981-N (Single) 0.061 1 2 LMV982 (Dual) 0.101 3.5 5 In Shutdown (1) (2) (3) 4 μA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Application Note section for information on temperature derating of this device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N LMV981-N, LMV982-N www.ti.com SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 2.7V DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 2.7V, V − = 0V, VCM = V+/2, VO = V+/2, RL > 1 MΩ and SHDN tied to V+. Boldface limits apply at the temperature extremes. See (1). Parameter CMRR Common Mode Rejection Ratio Test Conditions LMV982, 0 ≤ VCM ≤ 1.5V 2.3V ≤ VCM ≤ 2.7V (4) 55 50 80 −0.2V ≤ VCM ≤ 0V 2.7V ≤ VCM ≤ 2.9V 50 74 75 70 100 V− −0.2 −0.2 to 3.0 CMVR Input Common-Mode Voltage Range For CMRR Range ≥ 50dB TA = 25°C Output Swing − TA = −40°C to 85°C TA = 125°C VO (3) 81 1.8V ≤ V+ ≤ 5V VCM = 0.5V Large Signal Voltage Gain LMV982 (Dual) Typ 60 55 Power Supply Rejection Ratio Large Signal Voltage Gain LMV981-N(Single) (2) LMV981-N, 0 ≤ VCM ≤ 1.5V 2.3V ≤ VCM ≤ 2.7V (4) PSRR AV Min − RL = 600Ω to 1.35V, VO = 0.2V to 2.5V 87 86 104 RL = 2kΩ to 1.35V, VO = 0.2V to 2.5V 92 91 110 RL = 600Ω to 1.35V, VO = 0.2V to 2.5V 78 75 90 RL = 2kΩ to 1.35V, VO = 0.2V to 2.5V 81 78 100 RL = 600Ω to 1.35V VIN = ±100mV 2.55 2.53 2.62 (5) Sourcing, VO = 0V VIN = 100mV 20 15 30 Sinking, VO = 0V VIN = −100mV 18 12 25 Ton Turn-on Time from Shutdown 12.5 VSHDN Turn-on Voltage to enable part 1.9 Turn-off Voltage 0.8 (4) (5) dB V ++0.2 V dB 0.110 0.130 2.675 0.025 Output Short Circuit Current dB V −0.2 0.083 IO Units + V +0.2 2.65 2.64 (2) V+ V RL = 2kΩ to 1.35V VIN = ±100mV Max V 0.04 0.045 mA μs V For ensured temperature ranges, see Input Common-Mode Voltage Range specifications. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45mA over long term may adversely affect reliability. Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N Submit Documentation Feedback 5 LMV981-N, LMV982-N SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com 2.7V AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 2.7V, V − = 0V, VCM = 1.0V, VO = 1.35V, RL > 1 MΩ and SHDN tied to V+. Boldface limits apply at the temperature extremes. See (1). Parameter SR Slew Rate GBW Φm Test Conditions Min (2) (4) Typ (3) Max (2) Units 0.4 V/µs Gain-Bandwidth Product 1.4 MHz Phase Margin 70 deg Gm Gain Margin 7.5 dB en Input-Referred Voltage Noise f = 10 kHz, VCM = 0.5V 57 nV/√Hz in Input-Referred Current Noise f = 10 kHz 0.08 pA/√Hz THD Total Harmonic Distortion f = 1kHz, AV = +1 RL = 600Ω, VIN = 1VPP 0.022 % 123 dB Amp-to-Amp Isolation (1) (2) (3) (4) (5) (5) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Application Note section for information on temperature derating of this device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates. Input referred, RL = 100kΩ connected to V+/2. Each amp excited in turn with 1kHz to produce VO = 3VPP. (For Supply Voltages <3V, VO = V+). 5V DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 5V, V − = 0V, VCM = V+/2, VO = V+/2, RL > 1 MΩ and SHDN tied to V+. Boldface limits apply at the temperature extremes. See (1). Parameter VOS Input Offset Voltage Test Conditions Min (2) Typ (3) Max LMV981-N (Single) 1 4 6 LMV982 (Dual) 1 5.5 7.5 (2) Units mV μV/°C TCVOS Input Offset Voltage Average Drift 5.5 IB Input Bias Current 14 35 50 nA IOS Input Offset Current 9 25 40 nA IS Supply Current (per Channel) 116 210 230 μA LMV981-N (Single) 0.201 1 2 LMV982 (Dual) 0.302 3.5 5 In Shutdown CMRR Common Mode Rejection Ratio 0 ≤ VCM ≤ 3.8V 4.6V ≤ VCM ≤ 5.0V (4) −0.2V ≤ VCM ≤ 0V 5.0V ≤ VCM ≤ 5.2V (1) (2) (3) (4) 6 60 55 86 50 78 μA dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Application Note section for information on temperature derating of this device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. For ensured temperature ranges, see Input Common-Mode Voltage Range specifications. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N LMV981-N, LMV982-N www.ti.com SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 5V DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 5V, V − = 0V, VCM = V+/2, VO = V+/2, RL > 1 MΩ and SHDN tied to V+. Boldface limits apply at the temperature extremes. See (1). Parameter Test Conditions Min + PSRR Power Supply Rejection Ratio 1.8V ≤ V ≤ 5V VCM = 0.5V CMVR Input Common-Mode Voltage Range For CMRR Range ≥ 50dB TA = 25°C Large Signal Voltage Gain (LMV981-N Single) Large Signal Voltage Gain LMV982 (Dual) VO Output Swing Typ (3) 75 70 100 V− −0.2 −0.2 to 5.3 Max V+ V− +0.3 V+ −0.3 RL = 600Ω to 2.5V, VO = 0.2V to 4.8V 88 87 102 RL = 2kΩ to 2.5V, VO = 0.2V to 4.8V 94 93 113 RL = 600Ω to 2.5V, VO = 0.2V to 4.8V 81 78 90 RL = 2kΩ to 2.5V, VO = 0.2V to 4.8V 85 82 100 RL = 600Ω to 2.5V VIN = ±100mV (4) 4.855 4.835 4.890 dB 0.160 0.180 Output Short Circuit Current (5) LMV981-N, Sourcing, VO = 0V VIN = 100mV 80 68 100 Sinking, VO = 5V VIN = −100mV 58 45 65 Ton Turn-on Time from Shutdown 8.4 VSHDN Turn-on Voltage to enable part 4.2 Turn-off Voltage 0.8 (5) V 4.967 0.037 IO V dB 0.120 4.945 4.935 Units V+ +0.2 V TA = −40°C to 85°C RL = 2kΩ to 2.5V VIN = ±100mV (2) dB − TA = 125°C AV (2) 0.065 0.075 mA μs V Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45mA over long term may adversely affect reliability. 5V AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 5V, V − = 0V, VCM = V+/2, VO = 2.5V, R L > 1 MΩ and SHDN tied to V+.Boldface limits apply at the temperature extremes. See (1). Parameter SR Slew Rate GBW Φm Test Conditions Min (2) (4) Typ (3) Max (2) Units 0.42 V/µs Gain-Bandwidth Product 1.5 MHz Phase Margin 71 deg Gm Gain Margin 8 dB en Input-Referred Voltage Noise f = 10 kHz, VCM = 1V 50 nV/√Hz in Input-Referred Current Noise f = 10 kHz 0.08 pA/√Hz (1) (2) (3) (4) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Application Note section for information on temperature derating of this device. Absolute Maximum Ratings indicated junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates. Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N Submit Documentation Feedback 7 LMV981-N, LMV982-N SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com 5V AC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C. V+ = 5V, V − = 0V, VCM = V+/2, VO = 2.5V, R L > 1 MΩ and SHDN tied to V+.Boldface limits apply at the temperature extremes. See (1). Parameter THD Test Conditions Total Harmonic Distortion (2) f = 1kHz, AV = +1 RL = 600Ω, VO = 1V PP (5) Amp-to-Amp Isolation (5) Min Typ (3) Max (2) Units 0.022 % 123 dB Input referred, RL = 100kΩ connected to V+/2. Each amp excited in turn with 1kHz to produce VO = 3VPP. (For Supply Voltages <3V, VO = V+). Connection Diagrams Top View Top View A2 OUT B1 SHDN B2 GND 1 2 GND 3 C1 IN+ C2 IN- Figure 1. 6-Bump DSBGA Package See Package Number YZR0006BBA 8 Submit Documentation Feedback 6 +IN -IN TOP MARK A1 VCC Top View VDD 5 SHDN 4 OUT Figure 2. 6-Pin SC70 and SOT-23 See Package Numbers DCK0006A and DBV0006A Figure 3. 10-Pin VSSOP Package See Package Number DGS0010A Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N LMV981-N, LMV982-N www.ti.com SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise specified, VS = +5V, single supply, TA = 25°C. Supply Current vs. Supply Voltage (LMV981-N) Sourcing Current vs. Output Voltage 100 160 125°C VS = 5V 10 120 ISOURCE (mA) SUPPLY CURRENT (éA) 140 85°C 100 25°C 80 -40°C 60 VS = 2.7V 1 VS = 1.8V 0.1 40 20 1 2 3 4 0.01 0.001 5 Output Voltage Swing vs. Supply Voltage OUTPUT VOLTAGE PROXIMITY TO SUPPLY VOLTAGE (mV ABSOLUTE VALUE) Sinking Current vs. Output Voltage 10 ISINK (mA) 1 Figure 5. VS = 5V VS = 2.7V 1 VS = 1.8V 0.1 0.01 0.1 10 10 1 140 RL = 600: 130 NEGATIVE SWING 120 110 100 90 80 POSITIVE SWING 70 60 4 2 3 SUPPLY VOLTAGE (V) 1 0 OUTPUT VOLTAGE REF TO GND (V) Figure 6. Figure 7. Output Voltage Swing vs. Supply Voltage Gain and Phase vs. Frequency 5 6 135. 0 60 45 VS = 1.8V RL = 2k: CL = 1000pF 50 RL = 600: 40 PHASE 40 NEGATIVE SWING GAIN (dB) OUTPUT VOLTAGE PROXIMITY TO SUPPLY VOLTAGE (mV ABSOLUTE VALUE) 0.1 Figure 4. 100 0.01 0.001 0.01 OUTPUT VOLTAGE REFERENCED TO V+ (V) SUPPLY VOLTAGE (V) 35 30 30 20 0 POSITIVE SWING 20 0 1 2 3 5 4 6 90.0 CL = 0pF 67.5 GAIN 45. 0 22.5 10 25 112.5 CL = 300pF PHASE (°) 0 0 CL = 1000pF CL = 300pF CL = 0pF -10 10k SUPPLY VOLTAGE (V) Figure 8. 100k 0. 0 1M 10 M -22.5 FREQUENCY (Hz) Figure 9. Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N Submit Documentation Feedback 9 LMV981-N, LMV982-N SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, VS = +5V, single supply, TA = 25°C. Gain and Phase vs. Frequency Gain and Phase vs. Frequency 60 135.0 60 112.5 50 VS = 5.0V CL = 1000pF 67.5 GAIN 45.0 10 100k 1M 30 -40°C GAIN 10 0.0 0 -22.5 10 M -10 10k 125°C 100k Figure 11. Gain and Phase vs. Frequency CMRR vs. Frequency VS = 5.0V 135. 0 RL = 600: 112.5 VS = 5V 85 90.0 67.5 -40°C 25°C 85°C 20 GAIN 45. 0 125°C 10 -40°C -10 10k 100k 1M 10 M VS = 2.7V 75 VS = 1.8V 70 22.5 25°C 85°C 125°C 0 80 CMRR (dB) 30 PHASE (°) PHASE GAIN (dB) -22.5 90 CL = 150pF 0. 0 65 -22.5 60 1k 100 FREQUENCY (Hz) 10 FREQUENCY (Hz) Figure 12. Figure 13. PSRR vs. Frequency Input Voltage Noise vs. Frequency 100 1000 INPUT VOLTAGE NOISE (nV/ Hz) 90 80 70 -PSRR 60 50 40 30 10 10k VS = 5V +PSRR PSRR (dB) 10 M 1M FREQUENCY (Hz) 40 100 1k FREQUENCY (Hz) 10k 100 10 10 100 Submit Documentation Feedback 1k 10k 100k FREQUENCY (Hz) Figure 14. 10 0. 0 Figure 10. 50 45. 0 22.5 -40°C 25°C 85°C FREQUENCY (Hz) 60 67.5 25°C 85°C 125°C 20 22.5 CL = 1000pF CL = 300pF CL = 0pF -10 10k 90.0 PHASE 30 0 112.5 40 90.0 CL = 0pF 20 RL = 600: PHASE (°) GAIN (dB) 40 135. 0 CL = 150pF CL = 300pF GAIN (dB) PHASE PHASE (°) 50 RL = 600: VS = 1.8V Figure 15. Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N LMV981-N, LMV982-N www.ti.com SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified, VS = +5V, single supply, TA = 25°C. Input Current Noise vs. Frequency THD vs. Frequency 10 1 1 THD (%) INPUT CURRENT NOISE (pA/ Hz) RL = 600: AV = +1 0.1 1.8V 0.1 2.7V 5V 0.01 10 100 1k 10k 0.01 10 100k 10k 1k 100 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 16. Figure 17. THD vs. Frequency Slew Rate vs. Supply Voltage 0.5 10 RL = 600: AV = +10 SLEW RATE (V/Ps) 0.45 THD (%) 1 5V 0.1 FALLING EDGE 0.4 RISING EDGE 0.35 RL = 2k: 0.3 1.8V AV = +1 2.7V 0.01 10 VIN = 1VPP 0.25 100 1k 10k 0 100k 1 2 3 4 5 6 SUPPLY VOLTAGE (V) FREQUENCY (Hz) Figure 19. Small Signal Non-Inverting Response Small Signal Non-Inverting Response RL = 2 k: VS = 2.7V RL = 2 k: (50 mV/DIV) INPUT SIGNAL VS = 1.8V OUTPUT SIGNAL INPUT SIGNAL OUTPUT SIGNAL (50 mV/DIV) Figure 18. TIME (2.5 Ps/DIV) TIME (2.5 Ps/DIV) Figure 20. Figure 21. Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N Submit Documentation Feedback 11 LMV981-N, LMV982-N SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, VS = +5V, single supply, TA = 25°C. Large Signal Non-Inverting Response VIN VS = 5V (900 mV/div) RL = 2 k: (50 mV/DIV) OUTPUT SIGNAL INPUT SIGNAL Small Signal Non-Inverting Response VOUT VS = 1.8V RL = 2k: AV = +1 TIME (10 Ps/div) TIME (2.5 Ps/DIV) Figure 22. Figure 23. Large Signal Non-Inverting Response Large Signal Non-Inverting Response VIN (2.5 V/div) (1.35V/DIV) VIN VOUT VOUT VS = 2.7V VS = 5.0V RL = 2 k: RL = 2k: AV = +1 AV = +1 TIME (10 Ps/div) TIME (10 Ps/DIV) Figure 24. Figure 25. Short Circuit Current vs. Temperature (Sinking) Short Circuit Current vs. Temperature (Sourcing) 90 90 SHORT CIRCUIT CURRENT (mA) SHORT CIRCUIT CURRENT (mA) 5V 80 5V 70 60 50 40 2.7V 30 20 1.8V 10 0 -40 10 60 TEMPERATURE (°C) 110 80 70 60 50 40 2.7V 30 20 1.8V 10 0 -40 Figure 26. 12 Submit Documentation Feedback 10 60 TEMPERATURE (°C) 110 Figure 27. Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N LMV981-N, LMV982-N www.ti.com SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified, VS = +5V, single supply, TA = 25°C. Offset Voltage vs. Common Mode Range Offset Voltage vs. Common Mode Range 3 3 VS = 1.8V VS = 2.7V 2.5 2.5 2 2 25°C -40°C 1.5 VOS (mV) VOS (mV) 25°C 1 0.5 85°C 1 0.5 85°C 125°C 125°C 0 0 -0.5 -0.5 -1 -0.4 0 0.4 0.8 -40°C 1.5 1.2 2 1.6 -1 -0.4 2.4 VCM (V) 0.1 0.6 1.1 1.6 2.1 2.6 3.1 VCM (V) Figure 28. Figure 29. Offset Voltage vs. Common Mode Range 3 VS = 5V 2.5 2 VOS (mV) -40°C 1.5 1 0.5 25°C 125°C 85°C 0 -0.5 -1 -0.4 0.6 1.6 2.6 3.6 4.6 5.6 VCM (V) Figure 30. Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N Submit Documentation Feedback 13 LMV981-N, LMV982-N SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com APPLICATION NOTE Input and Output Stage The rail-to-rail input stage of this family provides more flexibility for the designer. The LMV981-N/LMV982 use a complimentary PNP and NPN input stage in which the PNP stage senses common mode voltage near V− and the NPN stage senses common mode voltage near V+. The transition from the PNP stage to NPN stage occurs 1V below V+. Since both input stages have their own offset voltage, the offset of the amplifier becomes a function of the input common mode voltage and has a crossover point at 1V below V+. This VOS crossover point can create problems for both DC and AC coupled signals if proper care is not taken. Large input signals that include the VOS crossover point will cause distortion in the output signal. One way to avoid such distortion is to keep the signal away from the crossover. For example, in a unity gain buffer configuration and with VS = 5V, a 5V peak-to-peak signal will contain input-crossover distortion while a 3V peakto-peak signal centered at 1.5V will not contain input-crossover distortion as it avoids the crossover point. Another way to avoid large signal distortion is to use a gain of −1 circuit which avoids any voltage excursions at the input terminals of the amplifier. In that circuit, the common mode DC voltage can be set at a level away from the VOS cross-over point. For small signals, this transition in VOS shows up as a VCM dependent spurious signal in series with the input signal and can effectively degrade small signal parameters such as gain and common mode rejection ratio. To resolve this problem, the small signal should be placed such that it avoids the VOS crossover point. In addition to the rail-to-rail performance, the output stage can provide enough output current to drive 600Ω loads. Because of the high current capability, care should be taken not to exceed the 150°C maximum junction temperature specification. Shutdown Mode The LMV981-N/LMV982 have a shutdown pin. To conserve battery life in portable applications, the LMV981N/LMV982 can be disabled when the shutdown pin voltage is pulled low. The shutdown pin can’t be left unconnected. In case shut-down operation is not needed, the shutdown pin should be connected to V+ when the LMV981-N/LMV982 are used. Leaving the shutdown pin floating will result in an undefined operation mode, either shutdown or active, or even oscillating between the two modes. Input Bias Current Consideration The LMV981-N/LMV982 family has a complementary bipolar input stage. The typical input bias current (IB) is 15nA. The input bias current can develop a significant offset voltage. This offset is primarily due to IB flowing through the negative feedback resistor, RF. For example, if IB is 50nA and RF is 100kΩ, then an offset voltage of 5mV will develop (VOS = IB x RF). Using a compensation resistor (RC), as shown in Figure 31, cancels this effect. But the input offset current (IOS) will still contribute to an offset voltage in the same manner. 14 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N LMV981-N, LMV982-N www.ti.com SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 Figure 31. Canceling the Offset Voltage due to Input Bias Current Typical Applications High Side Current Sensing The high side current sensing circuit (Figure 32) is commonly used in a battery charger to monitor charging current to prevent over charging. A sense resistor RSENSE is connected to the battery directly. This system requires an op amp with rail-to-rail input. The LMV981-N/LMV982 are ideal for this application because the common mode input range goes up to the rail. Figure 32. High Side Current Sensing Half-Wave Rectifier with Rail-to-Ground Output Swing Since the LMV981-N/LMV982 input common mode range includes both positive and negative supply rails and the output can also swing to either supply, achieving half-wave rectifier functions in either direction is an easy task. All that is needed are two external resistors; there is no need for diodes or matched resistors. The half wave rectifier can have either positive or negative going outputs, depending on the way the circuit is arranged. Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N Submit Documentation Feedback 15 LMV981-N, LMV982-N SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com In Figure 33 the circuit is referenced to ground, while in Figure 34 the circuit is biased to the positive supply. These configurations implement the half wave rectifier since the LMV981-N/LMV982 can not respond to one-half of the incoming waveform. It can not respond to one-half of the incoming because the amplifier can not swing the output beyond either rail therefore the output disengages during this half cycle. During the other half cycle, however, the amplifier achieves a half wave that can have a peak equal to the total supply voltage. RI should be large enough not to load the LMV981-N/LMV982. Figure 33. Half-Wave Rectifier with Rail-to-Ground Output Swing Referenced to Ground Figure 34. Half-Wave Rectifier with Negative-Going Output Swing Referenced to VCC Instrumentation Amplifier with Rail-to-Rail Input and Output Some manufactures make a non-“rail-to-rail”-op amp rail-to-rail by using a resistive divider on the inputs. The resistors divide the input voltage to get a rail-to-rail input range. The problem with this method is that it also divides the signal, so in order to get the obtained gain, the amplifier must have a higher closed loop gain. This raises the noise and drift by the internal gain factor and lowers the input impedance. Any mismatch in these precision resistors reduces the CMRR as well. The LMV981-N/LMV982 is rail-to-rail and therefore doesn’t have these disadvantages. Using three of the LMV981-N/LMV982 amplifiers, an instrumentation amplifier with rail-to-rail inputs and outputs can be made as shown in Figure 35. In this example, amplifiers on the left side act as buffers to the differential stage. These buffers assure that the input impedance is very high and require no precision matched resistors in the input stage. They also assure that the difference amp is driven from a voltage source. This is necessary to maintain the CMRR set by the matching R1-R2 with R3-R4. The gain is set by the ratio of R2/R1 and R3 should equal R1 and R4 equal R2. With both rail-torail input and output ranges, the input and output are only limited by the supply voltages. Remember that even with rail-to-rail outputs, the output can not swing past the supplies so the combined common mode voltages plus the signal should not be greater that the supplies or limiting will occur. For additional applications, see Texas Instruments application notes AN–29, AN–31, AN–71, and AN–127. Figure 35. Rail-to-rail instrumentation amplifier 16 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N LMV981-N, LMV982-N www.ti.com SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 Simplified Schematic Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N Submit Documentation Feedback 17 LMV981-N, LMV982-N SNOS976L – NOVEMBER 2001 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision K (March 2013) to Revision L • 18 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 17 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LMV981-N LMV982-N PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMV981MF NRND SOT-23 DBV 6 1000 TBD Call TI Call TI -40 to 125 A78A LMV981MF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A78A LMV981MFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A78A LMV981MG NRND SC70 DCK 6 1000 TBD Call TI Call TI -40 to 125 A77 LMV981MG/NOPB ACTIVE SC70 DCK 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A77 LMV981MGX/NOPB ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A77 LMV981TL/NOPB ACTIVE DSBGA YZR 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 A H LMV981TLX/NOPB ACTIVE DSBGA YZR 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 A H LMV982MM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A87A LMV982MMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A87A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LMV981MF SOT-23 DBV 6 1000 178.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 LMV981MF/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV981MFX/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV981MG SC70 DCK 6 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV981MG/NOPB SC70 DCK 6 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV981MGX/NOPB SC70 DCK 6 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV981TL/NOPB DSBGA YZR 6 250 178.0 8.4 1.12 1.63 0.76 4.0 8.0 Q1 LMV981TLX/NOPB DSBGA YZR 6 3000 178.0 8.4 1.12 1.63 0.76 4.0 8.0 Q1 LMV982MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV982MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV981MF SOT-23 DBV 6 1000 210.0 185.0 35.0 LMV981MF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LMV981MFX/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LMV981MG SC70 DCK 6 1000 210.0 185.0 35.0 LMV981MG/NOPB SC70 DCK 6 1000 210.0 185.0 35.0 LMV981MGX/NOPB SC70 DCK 6 3000 210.0 185.0 35.0 LMV981TL/NOPB DSBGA YZR 6 250 210.0 185.0 35.0 LMV981TLX/NOPB DSBGA YZR 6 3000 210.0 185.0 35.0 LMV982MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LMV982MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YZR0006xxx D 0.600±0.075 E TLA06XXX (Rev C) D: Max = 1.565 mm, Min =1.504 mm E: Max = 1.057 mm, Min =0.996 mm 4215044/A NOTES: A. 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