TI1 LM5113TME 5a, 100v half-bridge gate driver for enhancement mode gan fet Datasheet

LM5113
5A, 100V Half-Bridge Gate Driver for Enhancement Mode
GaN FETs
General Description
Features
The LM5113 is designed to drive both the high-side and the
low-side enhancement mode Gallium Nitride (GaN) FETs in
a synchronous buck or a half bridge configuration. The floating high-side driver is capable of driving a high-side enhancement mode GaN FET operating up to 100V. The high-side
bias voltage is generated using a bootstrap technique and is
internally clamped at 5.2V, which prevents the gate voltage
from exceeding the maximum gate-source voltage rating of
enhancement mode GaN FETs. The inputs of the LM5113 are
TTL logic compatible, and can withstand input voltages up to
14V regardless of the VDD voltage. The LM5113 has split
gate outputs, providing flexibility to adjust the turn-on and
turn-off strength independently.
In addition, the strong sink capability of the LM5113 maintains
the gate in the low state, preventing unintended turn-on during
switching. The LM5113 can operate up to several MHz. The
LM5113 is available in a standard LLP-10 pin package and a
12-bump micro SMD package. The LLP-10 pin package contains an exposed pad to aid power dissipation. The micro
SMD package offers a compact footprint and minimized package inductance.
■
■
■
■
■
■
■
■
■
■
Independent high-side and low-side TTL logic inputs
1.2A/5A peak source/sink current
High-side floating bias voltage rail operates up to 100VDC
Internal bootstrap supply voltage clamping
Split outputs for adjustable turn-on/turn-off strength
0.6Ω /2.1Ω pull-down/pull-up resistance
Fast propagation times (28ns typical)
Excellent propagation delay matching (1.5ns typical)
Supply rail under-voltage lockout
Low power consumption
Typical Applications
■
■
■
■
■
Current Fed Push-Pull converters
Half and Full-Bridge converters
Synchronous Buck converters
Two-switch Forward converters
Forward with Active Clamp converters
Packages
■ LLP-10 (4 mm x 4 mm)
■ micro SMD (2 mm x 2 mm)
Typical Application
30162903
FIGURE 1.
© 2012 Texas Instruments Incorporated
301629 SNVS725E
www.ti.com
LM5113 5A, 100V Half-Bridge Gate Driver for Enhancement Mode GaN FETs
January 6, 2012
LM5113
Truth Table
HI
LI
HOH
HOL
LOH
LOL
L
L
Open
L
Open
L
Open
L
H
Open
L
H
H
L
H
Open
Open
L
H
H
H
Open
H
Open
Connection Diagram
30162901
30162902
micro SMD
Ordering Information
Ordering Number
Package Type
NSC Package Drawing
Supplied As
LM5113SD
LLP-10
SDC10A
1000 units shipped in Tape & Reel
LM5113SDE
LLP-10
SDC10A
250 units shipped in Tape & Reel
LM5113SDX
LLP-10
SDC10A
4500 units shipped in Tape & Reel
LM5113TME
12–Bump micro
SMD (NOPB)
TMP12FLA
250 units shipped in Tape & Reel
LM5113TMX
12–Bump micro
SMD (NOPB)
TMP12FLA
3000 units shipped in Tape & Reel
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2
LM5113
Pin Descriptions
Pin Number
Name
micro SMD
LLP-10
A3, C4 (Note 1)
1
VDD
D3
2
HB
D2
3
D1
Description
Applications Information
5V Positive gate drive supply
Locally decouple to VSS using low ESR/ESL
capacitor located as close to the IC as possible.
High-side gate driver bootstrap
rail
Connect the positive terminal of the bootstrap
capacitor to HB and the negative terminal to HS.
The bootstrap capacitor should be placed as
close to the IC as possible.
HOH
High-side gate driver turn-on
output
Connect to the gate of high-side GaN FET with a
short, low inductance path. A gate resistor can be
used to adjust the turn-on speed.
4
HOL
High-side gate driver turn-off
output
Connect to the gate of high-side GaN FET with a
short, low inductance path. A gate resistor can be
used to adjust the turn-off speed.
C1, D4 (Note 1)
5
HS
High-side GaN FET source
connection
Connect to the bootstrap capacitor negative
terminal and the source of the high-side GaN
FET.
B4
6
HI
High-side driver control input
The LM5113 inputs have TTL type thresholds.
Unused inputs should be tied to ground and not
left open.
A4
7
LI
Low-side driver control input
The LM5113 inputs have TTL type thresholds.
Unused inputs should be tied to ground and not
left open.
A2
8
VSS
Ground return
All signals are referenced to this ground.
A1
9
LOL
Low-side gate driver sink-current Connect to the gate of the low-side GaN FET with
output
a short, low inductance path. A gate resistor can
be used to adjust the turn-off speed.
B1
10
LOH
Low-side gate driver sourcecurrent output
Connect to the gate of high-side GaN FET with a
short, low inductance path. A gate resistor can be
used to adjust the turn-on speed.
Exposed Pad
It is recommended that the exposed pad on the
bottom of the package be soldered to ground
plane on the PC board to aid thermal dissipation.
EP
Note 1: A3 and C4, C1 and D4 are internally connected.
3
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LM5113
Storage Temperature Range
ESD Rating HBM
Absolute Maximum Ratings (Note 2)
VDD to VSS
HB to HS
LI or HI Input
LOH, LOL Output
HOH, HOL Output
HS to VSS
HB to VSS
HB to VDD
Junction Temperature
−0.3V to 7V
−0.3V to 7V
−0.3V to 15V
−0.3V to VDD +0.3V
VHS −0.3V to VHB +0.3V
−5V to +100V
0 to 107V
0 to 100V
+150°C
−55°C to +150°C
2 kV
Recommended Operating
Conditions
VDD
LI or HI Input
HS
HB
HS Slew Rate
Junction Temperature
+4.5V to +5.5V
0V to +14V
−5V to 100V
VHS +4V to VHS +5.5V
<50 V/ns
−40°C to +125°C
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB =
5V, VSS = VHS = 0V, No Load on LOL and HOL or HOH and HOL (Note 3).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
LI = HI = 0V
0.07
0.1
mA
IDDO
VDD Operating Current
f = 500 kHz
2.0
3.0
mA
IHB
Total HB Quiescent Current
LI = HI = 0V
0.08
0.1
mA
IHBO
Total HB Operating Current
f = 500 kHz
1.5
2.5
mA
IHBS
HB to VSS Current, Quiescent
HS = HB = 100V
0.1
8
µA
IHBSO
HB to VSS Current, Operating
f = 500 kHz
0.4
1.0
mA
INPUT PINS
VIR
Input Voltage Threshold
Rising Edge
1.89
2.06
2.18
V
VIF
Input Voltage Threshold
Falling Edge
1.48
1.66
1.76
V
VIHYS
Input Voltage Hysteresis
RI
Input Pulldown Resistance
400
mV
100
200
300
kΩ
3.2
3.8
4.5
V
UNDER VOLTAGE PROTECTION
VDDR
VDD Rising Threshold
VDDH
VDD Threshold Hysteresis
VHBR
HB Rising Threshold
VHBH
HB Threshold Hysteresis
0.2
2.5
3.2
V
3.9
0.2
V
V
BOOTSTRAP DIODE
VDL
Low-Current Forward Voltage
IVDD-HB = 100 µA
0.45
0.65
V
VDH
High-Current Forward Voltage
IVDD-HB = 100 mA
0.90
1.00
V
RD
Dynamic Resistance
IVDD-HB = 100 mA
1.85
3.60
Ω
HB-HS Clamp
Regulation Voltage
5.2
5.45
V
4.7
LOW & HIGH SIDE GATE DRIVER
VOL
Low-Level Output Voltage
IHOL = ILOL = 100 mA
0.06
0.10
V
VOH
High-Level Output Voltage
VOH = VDD – LOH or VOH = HB – HOH
IHOH = ILOH = 100 mA
0.21
0.31
V
IOHL
Peak Source Current
HOH, LOH = 0V
1.2
IOLL
Peak Sink Current
HOL, LOL = 5V
5
IOHLK
High-Level Output Leakage Current
HOH, LOH = 0V
1.5
µA
IOLLK
Low-Level Output Leakage Current
HOL, LOL = 5V
1.5
µA
A
A
THERMAL RESISTANCE
θJA
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Junction to Ambient (Note 4)
LLP-10
40
°C/W
12-bump micro SMD
80
°C/W
4
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB =
5V, VSS = VHS = 0V, No Load on LOL and LOH or HOL and HOH (Note 3).
Typ
Max
Units
tLPHL
Symbol
LO Turn-Off Propagation Delay
Parameter
LI Falling to LOL Falling
Conditions
Min
26.5
45.0
ns
tLPLH
LO Turn-On Propagation Delay
LI Rising to LOH Rising
28.0
45.0
ns
tHPHL
HO Turn-Off Propagation Delay
HI Falling to HOL Falling
26.5
45.0
ns
tHPLH
HO Turn-On Propagation Delay
HI Rising to HOH Rising
28.0
45.0
ns
tMON
Delay Matching: LO on & HO off
1.5
8.0
ns
tMOFF
Delay Matching: LO off & HO on
1.5
8.0
ns
tHRC
HO Rise Time (0.5V - 4.5V)
CL = 1000 pF
7.0
ns
tLRC
LO Rise Time (0.5V – 4.5V)
CL = 1000 pF
7.0
ns
tHFC
HO Fall Time (0.5V - 4.5V)
CL = 1000 pF
1.5
ns
tLFC
LO Fall Time (0.5V - 4.5V)
CL = 1000 pF
1.5
ns
tPW
Minimum Input Pulse Width that Changes
the Output
10
ns
tBS
Bootstrap Diode Reverse Recovery Time IF = 100mA,
IR = 100mA
40
ns
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 4: Four layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Timing Diagram
30162904
FIGURE 2. Timing Diagram
5
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LM5113
Switching Characteristics
LM5113
Typical Performance Characteristics
(Note 5)
Peak Source Current vs Output Voltage
Peak Sink Current vs Output Voltage
30162905
30162906
IDDO vs Frequency
IHBO vs Frequency
30162908
30162907
IDD vs Temperature
IHB vs Temperature
30162909
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30162910
6
LM5113
UVLO Rising Thresholds vs Temperature
UVLO Falling Thresholds vs Temperature
30162911
30162912
Input Thresholds vs Temperature
Input Threshold Hysteresis vs Temperature
30162913
30162914
Bootstrap Diode Forward Voltage
Propagation Delay vs Temperature
30162915
30162916
7
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LM5113
LO&HO Gate Drive — High/Low Level Output Voltage
vs Temperature
HB Regulation Voltage vs Temperature
30162918
30162917
Note 5: Unless otherwise specified, VDD = VHB = 5V, VSS = VHS = 0V.
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8
The LM5113 is designed to drive both the high-side and the
low-side enhancement mode Gallium Nitride FETs in a synchronous buck or a half-bridge configuration. The outputs of
the LM5113 are independently controlled with TTL input
thresholds. The inputs of the LM5113 can withstand voltages
up to 14V regardless of the VDD voltage, and can be directly
connected to the outputs of PWM controllers.
The high side driver uses the floating bootstrap capacitor voltage to drive the high-side FET. As shown in Figure 1, the
bootstrap capacitor is recharged through an internal bootstrap diode each cycle when the HS pin is pulled below the
VDD voltage. For inductive load applications the HS node will
fall to a negative potential, clamped by the low side FET.
Due to the intrinsic feature of enhancement mode GaN FETs
the source-to-drain voltage, when the gate is pulled low, is
usually higher than a diode forward voltage drop. This can
lead to an excessive bootstrap voltage that can damage the
high-side GaN FET. The LM5113 solves this problem with an
internal clamping circuit that prevents the bootstrap voltage
from exceeding 5.2V typical.
The output pull-down and pull-up resistance of LM5113 is optimized for enhancement mode GaN FETs to achieve high
frequency, efficient operation. The 0.6Ω pull-down resistance
provides a robust low impedance turn-off path necessary to
eliminate undesired turn-on induced by high dv/dt or high di/
dt. The 2.1Ω pull-up resistance helps reduce the ringing and
over-shoot of the switch node voltage. The split outputs of the
LM5113 offer flexibility to adjust the turn-on and turn-off speed
by independently adding additional impedance in either the
turn-on path and/or the turn-off path.
The LM5113 has an Under-voltage Lockout (UVLO) on both
the VDD and bootstrap supplies. When the VDD voltage is
below the threshold voltage of 3.8V, both the HI and LI inputs
are ignored, to prevent the GaN FETs from being partially
turned on. Also if there is sufficient VDD voltage, the UVLO
will actively pull the LOL and HOL low. When the HB to HS
bootstrap voltage is below the UVLO threshold of 3.2V, only
HOL is pulled low. Both UVLO threshold voltages have
200mV of hysteresis to avoid chattering.
Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the highside switch, dc bias power for HB under-voltage lockout circuit, and the reverse recovery charge of the bootstrap diode.
The required bypass capacitance can be calculated as follows:
IHB is the quiescent current of the high-side driver. ton is the
maximum on-time period of the high-side transistor. A good
quality, ceramic capacitor should be used for the bootstrap
capacitor. It is recommended to place the bootstrap capacitor
as close to the HB and HS pins as possible.
Power Dissipation
The power consumption of the driver is an important measure
that determines the maximum achievable operating frequency of the driver. It should be kept below the maximum power
dissipation limit of the package at the operating temperature.
The total power dissipation of the LM5113 is the sum of the
gate driver losses and the bootstrap diode power loss.
The gate driver losses are incurred by charge and discharge
of the capacitive load. It can be approximated as
CLoadH and CLoadL are the high-side and the low-side capacitive loads respectively. It can also be calculated with the total
input gate charge of the high-side and the low-side transistors
as
Bypass Capacitor
The VDD bypass capacitor provides the gate charge for the
low-side and high-side transistors and to absorb the reverse
recovery charge of the bootstrap diode. The required bypass
capacitance can be calculated as follows:
There are some additional losses in the gate drivers due to
the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver
power dissipation versus frequency and load capacitance. At
higher frequencies and load capacitance values, the power
dissipation is dominated by the power losses driving the output loads and agrees well with the above equations. This plot
can be used to approximate the power losses due to the gate
drivers.
QgH and QgL are gate charge of the high-side and low-side
transistors respectively. Qrr is the reverse recovery charge of
9
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LM5113
the bootstrap diode, which is typically around 4nC. ΔV is the
maximum allowable voltage drop across the bypass capacitor. A 0.1uF or larger value, good quality, ceramic capacitor
is recommended. The bypass capacitor should be placed as
close to the pins of the IC as possible to minimize the parasitic
inductance.
Detailed Operating Description
LM5113
Reverse Recovery Power Loss of
Bootstrap Diode VIN=50V
The Load of High-Side Driver is a GaN FET
with Total Gate Charge of 10nC
Gate Driver Power Dissipation (LO+HO)
VDD=+5V, Neglecting Bootstrap Diode Losses
30162919
The bootstrap diode power loss is the sum of the forward bias
power loss that occurs while charging the bootstrap capacitor
and the reverse bias power loss that occurs during reverse
recovery. Since each of these events happens once per cycle,
the diode power loss is proportional to the operating frequency. Larger capacitive loads require more energy to recharge
the bootstrap capacitor resulting in more losses. Higher input
voltages (V IN) to the half bridge also result in higher reverse
recovery losses.
The following two plots illustrate the forward bias power loss
and the reverse bias power loss of the bootstrap diode respectively. The plots are generated based on calculations and
lab measurements of the diode reverse time and current under several operating conditions. The plots can be used to
predict the bootstrap diode power loss under different operating conditions.
30162944
The sum of the driver loss and the bootstrap diode loss is the
total power loss of the IC. For a given ambient temperature,
the maximum allowable power loss of the IC can be defined
as
Forward Bias Power Loss of
Bootstrap Diode VIN=50V
The Load of High-Side Driver is a GaN FET
with Total Gate Charge of 10nC
30162943
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10
Small gate capacitance and miller capacitance enable enhancement mode GaN FETs to operate with fast switching
speed. The induced high dv/dt and di/dt, coupled with a low
gate threshold voltage and limited headroom of enhancement
mode GaN FETs gate voltage, make the circuit layout crucial
to the optimum performance. Following are some hints.
1. The first priority in designing the layout of the driver is to
confine the high peak currents that charge and discharge
the GaN FETs gate into a minimal physical area. This will
decrease the loop inductance and minimize noise issues
on the gate terminal of the GaN FETs. The GaN FETs
should be placed close to the driver.
2. The second high current path includes the bootstrap
capacitor, the local ground referenced VDD bypass
capacitor and low-side GaN FET. The bootstrap
capacitor is recharged on a cycle-by-cycle basis through
the bootstrap diode from the ground referenced VDD
capacitor. The recharging occurs in a short time interval
and involves high peak current. Minimizing this loop
length and area on the circuit board is important to ensure
reliable operation.
3. The parasitic inductance in series with the source of the
high-side FET and the low-side FET can impose
excessive negative voltage transients on the driver. It is
recommended to connect HS pin and VSS pin to the
30162921
Without Gate Resistors
30162922
With HOH and LOH Gate Resistors
30162924
30162923
With HOH and LOH Gate Resistors
Without Gate Resistors
11
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LM5113
respective source of the high-side and low-side
transistors with a short and low-inductance path.
4. The parasitic source inductance, along with the gate
capacitor and the driver pull-down path, can form a LCR
resonant tank, resulting in gate voltage oscillations. An
optional resistor or ferrite bead can be used to damp the
ringing.
5. Low ESR/ESL capacitors must be connected close to the
IC, between VDD and VSS pins and between the HB and
HS pins to support the high peak current being drawn
from VDD during turn-on of the FETs. It is most desirable
to place the VDD decoupling capacitor and the HB to HS
bootstrap capacitor on the same side of the PC board as
the driver. The inductance of vias can impose excessive
ringing on the IC pins.
6. To prevent excessive ringing on the input power bus,
good decoupling practices are required by placing low
ESR ceramic capacitors adjacent to the GaN FETs.
The following figures show recommended layout patterns for
LLP-10 package and micro SMD package respectively. Two
cases are considered: (1) Without any gate resistors; (2) With
an optional turn-on gate resistor. It should be noted that 0402
SMD package is assumed for the passive components in the
drawings. For information on micro SMD package assembly,
refer to Application Note AN-1112.
Layout Considerations
LM5113
Physical Dimensions inches (millimeters) unless otherwise noted
LLP-10 Outline Drawing
NS Package Number SDC10A
12-Bump uSMD Outline Drawing
NS Package Number TMP12FLA
Note:
X1=1.742 mm, ±0.030 mm
X2=1.870 mm, ±0.030 mm
X3=0.600 mm, ±0.075 mm
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12
LM5113
13
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LM5113 5A, 100V Half-Bridge Gate Driver for Enhancement Mode GaN FETs
Notes
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