TI1 LMK61E07 Ultra-low jitter programmable oscillator with internal eeprom Datasheet

Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
LMK61E07
SNAS722 – DECEMBER 2017
LMK61E07 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM
1 Features
3 Description
•
The LMK61E07 family of ultra-low jitter PLLatinumTM
programmable oscillators use fractional-N frequency
synthesizers with integrated VCOs to generate
commonly used reference clocks. The output on
LMK61E07 can be configured as LVPECL, LVDS, or
HCSL. The device features self start-up from on-chip
EEPROM to generate a factory programmed default
output frequency, or the device registers and
EEPROM settings are fully programmable in-system
through I2C serial interface. The device provides fine
and coarse frequency margining control through I2C
serial interface, making it a digitally-controlled
oscillator (DCXO).
1
•
•
•
•
•
Ultra-Low Noise, High Performance
– Jitter: 90-fs RMS Typical fOUT > 100 MHz on
LMK61E07
– PSRR: –70 dBc, Robust Supply Noise
Immunity on LMK61E07
Flexible Output Format on LMK61E07
– LVPECL up to 1 GHz
– LVDS up to 900 MHz
– HCSL up to 400 MHz
Total Frequency Tolerance of ±25 ppm
System Level Features
– Glitch-Less Frequency Margining: Up to ±1000
ppm From Nominal
– Internal EEPROM: User Configurable Start-Up
Settings
Other Features
– Device Control: Fast Mode I2C up to 1000 kHz
– 3.3-V Operating Voltage
– Industrial Temperature Range (–40ºC to
+85ºC)
– 7-mm × 5-mm 8-Pin Package
Default Frequency:
– 70.656 MHz
2 Applications
•
•
•
•
•
•
The PLL feedback divider can be updated to adjust
the output frequency without spikes or glitches in
steps of <1ppb using a PFD of 12.5 MHz (R
divider=4, doubler disabled) for compatibility with
xDSL requirements, or in steps of <5.2 ppb using a
PFD of 100 MHz (R divider=1, doubler enabled) for
compatibility with broadcast video requirements. The
frequency margining features also facilitate system
design verification tests (DVT), such as standards
compliance and system timing margin testing.
Device Information(1)
PART NUMBER
LMK61E07
PACKAGE
QFM (6)
BODY SIZE (NOM)
7.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
High-Performance Replacement for Crystal, SAW,
or Silicon-Based Oscillators
Switches, Routers, Network Line Cards, Base
Band Units (BBU), Servers, Storage/SAN
Test and Measurement
Medical Imaging
FPGA, Processor Attach
xDSL, Broadcast Video
Pinout and Simplified Block Diagram
Power
Conditioning
SDA
1
6
VDD
SCL
2
5
OUTN
GND
3
4
OUTP
Integrated
Oscillator
Output
Divider
PLL
Output
Buffer
Interface
I2C/EEPROM
LMK61E0X
Ultra-high performance oscillator
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
4
4
4
4
5
5
5
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics - Power Supply .................
LVPECL Output Characteristics................................
LVDS Output Characteristics ....................................
HCSL Output Characteristics....................................
Frequency Tolerance Characteristics .......................
Frequency Margining Characteristics .....................
Power-On Reset Characteristics (VDD)..................
I2C-Compatible Interface Characteristics (SDA,
SCL) ...........................................................................
6.13 PSRR Characteristics .............................................
6.14 Other Characteristics ..............................................
6.15 PLL Clock Output Jitter Characteristics ..................
6.16 Typical 156.25-MHz Output Phase Noise
Characteristics ...........................................................
6.17 Typical 161.1328125 MHz Output Phase Noise
Characteristics ...........................................................
6.18 Additional Reliability and Qualification ....................
6.19 Typical Characteristics ............................................ 9
7
Parameter Measurement Information ................ 13
8
Detailed Description ............................................ 15
7.1 Device Output Configurations ................................. 13
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
15
15
16
20
23
27
Application and Implementation ........................ 40
9.1 Application Information............................................ 40
9.2 Typical Application .................................................. 40
10 Power Supply Recommendations ..................... 44
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 45
12 Device and Documentation Support ................. 46
6
7
7
7
12.1
12.2
12.3
12.4
12.5
12.6
7
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
46
46
13 Mechanical, Packaging, and Orderable
Information ........................................................... 46
8
8
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2017
*
Initial release.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
5 Pin Configuration and Functions
SIA Package
6-Pin QFM
Top View
SDA
1
6
VDD
SCL
2
5
OUTN
GND
3
4
OUTP
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
POWER
GND
3
Ground
Device Ground.
VDD
6
Power
3.3-V Power Supply.
4, 5
Output
Differential Output Pair (LVPECL, LVDS, or HCSL).
OUTPUT BLOCK
OUTP,
OUTN
DIGITAL CONTROL / INTERFACES
SCL
2
LVCMOS
I2C Serial Clock (open-drain). Requires an external pullup resistor to VDD.
SDA
1
LVCMOS
I2C Serial Data (bidirectional, open-drain). Requires an external pullup resistor to VDD.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
3
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD
Device supply voltage
–0.3
3.6
V
VIN
Input voltage for logic inputs
–0.3
VDD + 0.3
V
VOUT
Output voltage for clock outputs
–0.3
VDD + 0.3
V
TJ
Junction temperature
150
°C
TSTG
Storage temperature
125
°C
(1)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Device supply voltage
TA
Ambient temperature
TJ
Junction temperature
tRAMP
VDD power-up ramp time
MIN
NOM
MAX
3.135
3.3
3.465
V
–40
25
85
°C
0.1
UNIT
115
°C
100
ms
6.4 Thermal Information
(2) (3) (4)
LMK61E07
SIA (QFM)
THERMAL METRIC (1)
Airflow (LFM) 0
RθJA
UNIT
8 PINS
Junction-to-ambient thermal resistance
RθJC(top) Junction-to-case (top) thermal resistance
Airflow (LFM) 200
Airflow (LFM) 400
54
44
41.2
°C/W
34
n/a
n/a
°C/W
RθJB
Junction-to-board thermal resistance
36.7
n/a
n/a
°C/W
ψJT
Junction-to-top characterization parameter
11.2
16.9
21.9
°C/W
ψJB
Junction-to-board characterization parameter
36.7
37.8
38.9
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
(2)
(3)
(4)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal resistance is calculated on a 4-layer JEDEC board.
Connected to GND with 3 thermal vias (0.3-mm diameter).
ψJB (junction-to-board) is used when the main heat flow is from the junction to the GND pad. See Layout Guidelines for more information
on ensuring good system reliability and quality.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
6.5 Electrical Characteristics - Power Supply (1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
IDD
TEST CONDITIONS
Device current consumption
LVPECL
MIN
(2)
HCSL
IDD-PD
(1)
(2)
Device current consumption
when output is disabled
TYP
MAX
162
208
155
196
UNIT
mA
120
Refer to Parameter Measurement Information for relevant test conditions.
On-chip power dissipation should exclude 40 mW, dissipated in the 150-Ω termination resistors, from total power dissipation.
6.6 LVPECL Output Characteristics (1)
VDD = 3.3 V ± 5%, TA = –40C to 85°C
PARAMETER
TEST CONDITIONS
fOUT
Output frequency
VOD
Output voltage swing
(VOH - VOL) (2)
VOUT, DIFF, PP
Differential output peak-topeak swing
VOS
Output common-mode voltage
tR / tF
Output rise/fall time (20% to
80%) (3)
PN-Floor
Output phase noise floor
(fOFFSET > 10 MHz)
ODC
Output duty cycle (3)
(1)
(2)
(3)
MIN
(2)
TYP
10
700
800
MAX
UNIT
1000
MHz
1200
mV
2x
|VOD|
V
VDD –
1.55
V
120
200
–165
156.25 MHz
ps
dBc/Hz
45%
55%
Refer to Parameter Measurement Information for relevant test conditions.
An output frequency over fOUT maximum spec is possible, but output swing may be less than VOD minimum spec.
Ensured by characterization.
6.7 LVDS Output Characteristics (1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
fOUT
Output Frequency (1)
10
VOD
Output Voltage Swing
(VOH - VOL) (1)
300
VOUT, DIFF, PP
Differential Output Peak-toPeak Swing
VOS
TYP
390
MAX
UNIT
900
MHz
480
mV
2x
|VOD|
V
Output Common Mode
Voltage
1.2
V
tR / tF
Output Rise/Fall Time (20% to
80%) (2)
150
PN-Floor
Output Phase Noise Floor
(fOFFSET > 10 MHz)
ODC
Output Duty Cycle (2)
ROUT
Differential Output Impedance
(1)
(2)
156.25 MHz
250
ps
–162
45%
dBc/Hz
55%
125
Ω
An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
Ensured by characterization.
6.8 HCSL Output Characteristics (1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
fOUT
Output frequency
VOH
Output high voltage
(1)
TEST CONDITIONS
MIN
MAX
UNIT
10
TYP
400
MHz
600
850
mV
Refer to Parameter Measurement Information for relevant test conditions.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
5
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
HCSL Output Characteristics(1) (continued)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
VOL
Output low voltage
VCROSS
Absolute crossing voltage (2) (3)
TEST CONDITIONS
VCROSS-DELTA Variation of VCROSS (2) (3)
(4)
dV/dt
Slew rate
PN-Floor
Output phase noise floor
(fOFFSET > 10 MHz)
ODC
Output duty cycle (4)
(2)
(3)
(4)
MIN
MAX
UNIT
-100
100
mV
250
475
mV
0
140
mV
0.8
2
V/ns
100 MHz
TYP
–164
45%
dBc/Hz
55%
Measured from -150 mV to +150 mV on the differential waveform with the 300-mVpp measurement window centered on the differential
zero crossing.
Ensured by design.
Ensured by characterization.
6.9 Frequency Tolerance Characteristics (1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
fT
(1)
Total frequency tolerance
TEST CONDITIONS
All frequency bands and device junction
temperature up to 115°C; includes initial freq
tolerance, temperature & supply voltage
variation, solder reflow, and 5 year aging at
40°C ambient temperature
MIN
TYP
–25
MAX
UNIT
25
ppm
MAX
UNIT
1000
ppm
MAX
UNIT
2.95
V
0.1
V
10
ms
Ensured by characterization.
6.10 Frequency Margining Characteristics
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
Frequency margining range
from nominal
fT
MIN
TYP
–1000
6.11 Power-On Reset Characteristics (VDD)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
VTHRESH
Threshold voltage
VDROOP
Allowable voltage droop
tSTARTUP
Start-up time
TEST CONDITIONS
MIN
TYP
2.72
Time elapsed from VDD at 3.135 V to output
enabled
6.12 I2C-Compatible Interface Characteristics (SDA, SCL) (1) (2)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
VIH
Input high voltage
VIL
Input low voltage
IIH
Input leakage
CIN
Input capacitance
COUT
Input capacitance
VOL
Output low voltage
fSCL
I2C clock rate
tSU_STA
START condition setup time
(1)
(2)
6
TEST CONDITIONS
MIN
TYP
MAX
1.2
V
–40
0.6
V
40
µA
2
pF
400
IOL = 3 mA
0.6
100
SCL high before SDA low
0.6
UNIT
1000
pF
V
kHz
µs
Total capacitive load for each bus line ≤ 400 pF.
Ensured by design.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
I2C-Compatible Interface Characteristics (SDA, SCL)(1)(2) (continued)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
SCL low after SDA low
TYP
MAX
UNIT
tH_STA
START condition hold time
0.6
µs
tPH_SCL
SCL pulse width high
0.6
µs
tPL_SCL
SCL pulse width low
1.3
µs
tH_SDA
SDA hold time
tSU_SDA
SDA setup time
tR_IN / tF_IN
SCL/SDA input rise and fall
time
tF_OUT
SDA output fall time
tSU_STOP
STOP condition setup time
0.6
µs
tBUS
Bus free time between STOP
and START
1.3
µs
SDA valid after SCL low
0
0.9
µs
115
ns
CBUS = 10 pF to 400 pF
300
ns
250
ns
6.13 PSRR Characteristics (1)
VDD = 3.3 V, TA = 25°C, PLL bandwidth = 400 kHz, VCO Frequency = 5 GHz (Integer-N PLL), Output Divider = 32, Output
Type = LVPECL/LVDS/HCSL
PARAMETER
PSRR
(1)
(2)
(3)
TEST CONDITIONS
Spurs Induced by 50-mV
power supply ripple (2) (3) at
156.25-MHz output, all
output types
MIN
TYP
Sine wave at 50 kHz
–70
Sine wave at 100 kHz
–70
Sine wave at 500 kHz
–70
Sine wave at 1 MHz
–70
MAX
UNIT
dBc
Refer to Parameter Measurement Information for relevant test conditions.
Measured max spur level with 50-mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin
DJSPUR (ps, pk-pk) = [2 × 10(SPUR/20) / (π × fOUT)] × 1e6, where PSRR or SPUR in dBc and fOUT in MHz.
6.14 Other Characteristics
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
fVCO
TEST CONDITIONS
MIN
MAX
UNIT
5.6
GHz
TYP
MAX
UNIT
fOUT ≥ 100 MHz, Integer-N PLL, All output
types
100
200
fs RMS
fOUT ≥ 100 MHz, Fractional-N PLL, All output
types
150
300
fs RMS
VCO frequency range
TYP
4.6
6.15 PLL Clock Output Jitter Characteristics (1) (2)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
(3)
RMS phase jitter
(12 kHz – 20 MHz)
RJ
(3)
RMS phase jitter
(12 kHz – 20 MHz)
RJ
(1)
(2)
(3)
MIN
Refer to Parameter Measurement Information for relevant test conditions.
Phase jitter measured with Agilent E5052 signal source analyzer.
Ensured by characterization.
6.16 Typical 156.25-MHz Output Phase Noise Characteristics (1) (2)
VDD = 3.3 V, TA = 25°C, PLL bandwidth = 400 kHz, VCO Frequency = 5 GHz, Integer-N PLL, Output Divider = 32, Output
Type = LVPECL/LVDS/HCSL
PARAMETER
OUTPUT TYPE
LVPECL
LVDS
HCSL
UNIT
phn10k
Phase noise at 10-kHz offset
–143
–143
–143
dBc/Hz
Phn20k
Phase noise at 20-kHz offset
–143
–143
–143
dBc/Hz
(1)
(2)
Refer to Parameter Measurement Information for relevant test conditions.
Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
7
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Typical 156.25-MHz Output Phase Noise Characteristics(1)(2) (continued)
VDD = 3.3 V, TA = 25°C, PLL bandwidth = 400 kHz, VCO Frequency = 5 GHz, Integer-N PLL, Output Divider = 32, Output
Type = LVPECL/LVDS/HCSL
OUTPUT TYPE
PARAMETER
LVPECL
LVDS
HCSL
UNIT
phn100k
Phase noise at 100-kHz offset
–144
–144
–144
dBc/Hz
Phn200k
Phase noise at 200-kHz offset
–145
–145
–145
dBc/Hz
phn1M
Phase noise at 1-MHz offset
–150
–150
–150
dBc/Hz
phn2M
Phase noise at 2-MHz offset
–154
–154
–154
dBc/Hz
phn10M
Phase noise at 10-MHz offset
–165
–162
–164
dBc/Hz
phn20M
Phase noise at 20-MHz offset
–165
–162
–164
dBc/Hz
6.17 Typical 161.1328125 MHz Output Phase Noise Characteristics (1) (2)
VDD = 3.3 V, TA = 25°C, PLL bandwidth = 400 kHz, VCO Frequency = 5.15625 GHz, Fractional-N PLL, Output Divider = 32,
Output Type = LVPECL/LVDS/HCSL
OUTPUT TYPE
PARAMETER
LVPECL
LVDS
HCSL
UNIT
phn10k
Phase noise at 10-kHz offset
–136
–136
–136
dBc/Hz
phn20k
Phase noise at 20-kHz offset
–136
–136
–136
dBc/Hz
phn100k
Phase noise at 100-kHz offset
–140
–140
–140
dBc/Hz
phn200k
Phase noise at 200-kHz offset
–141
–141
–141
dBc/Hz
phn1M
Phase noise at 1-MHz offset
–148
–148
–148
dBc/Hz
phn2M
Phase noise at 2-MHz offset
–156
–156
–156
dBc/Hz
phn10M
Phase noise at 10-MHz offset
–161
–159
–160
dBc/Hz
phn20M
Phase noise at 20-MHz offset
–162
–160
–161
dBc/Hz
(1)
(2)
Refer to Parameter Measurement Information for relevant test conditions.
Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
6.18 Additional Reliability and Qualification
8
PARAMETER
CONDITION / TEST METHOD
Mechanical Shock
MIL-STD-202, Method 213
Mechanical Vibration
MIL-STD-202, Method 204
Moisture Sensitivity Level
J-STD-020, MSL3
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
6.19 Typical Characteristics
PLL Bandwidth = 400 kHz
Integer-N PLL
VCO Frequency = 5 GHz
Output Divider = 32
Figure 1. Closed-Loop Phase Noise of LVPECL Differential
Output at 156.25 MHz
PLL Bandwidth = 400 kHz
Integer-N PLL
VCO Frequency = 5 GHz
Output Divider = 32
Figure 3. Closed-Loop Phase Noise of HCSL Differential
Output at 156.25 MHz
PLL Bandwidth = 400 kHz
Integer-N PLL
VCO Frequency = 5 GHz
Output Divider = 32
Figure 2. Closed Loop Phase Noise of LVDS Differential
Output at 156.25 MHz
PLL Bandwidth = 400 kHz
Fractional-N PLL
VCO Frequency = 5.15625 GHz
Output Divider = 32
Figure 4. Closed-Loop Phase Noise of LVPECL Differential
Output at 161.1328125 MHz
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
9
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Typical Characteristics (continued)
VCO Frequency = 5.15625 GHz
Output Divider = 32
VCO Frequency = 5.15625 GHz
Output Divider = 32
Figure 5. Closed Loop Phase Noise of LVDS Differential
Output at 161.1328125 MHz
Figure 6. Closed-Loop Phase Noise of HCSL Differential
Output at 161.1328125 MHz
10
10
0
0
-10
-10
-20
-20
-30
-40
-50
-60
-30
-40
-50
-60
-70
-70
-80
-80
-90
78.125
109.375
140.625
171.875
Frequency (MHz)
PLL Bandwidth = 400 kHz
Integer-N PLL
203.125
234.375
-90
78.125
D007
VCO Frequency = 5 GHz
Output Divider = 32
Figure 7. 156.25 ± 78.125-MHz LVPECL Differential Output
Spectrum
10
PLL Bandwidth = 400 kHz
Fractional-N PLL
Amplitude (dBm)
Amplitude (dBm)
PLL Bandwidth = 400 kHz
Fractional-N PLL
109.375
140.625
171.875
Frequency (MHz)
PLL Bandwidth = 400 kHz
Integer-N PLL
203.125
234.375
D008
VCO Frequency = 5 GHz
Output Divider = 32
Figure 8. 156.25 ± 78.125 MHz LVDS Differential Output
Spectrum
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
Typical Characteristics (continued)
10
0
0
-10
-10
-20
-20
Amplitude (dBm)
Amplitude (dBm)
10
-30
-40
-50
-60
-30
-40
-50
-60
-70
-70
-80
-80
-90
-90
78.125
109.375
140.625
171.875
Frequency (MHz)
PLL Bandwidth = 400 kHz
Integer-N PLL
203.125
-100
80
234.375
VCO Frequency = 5 GHz
Output Divider = 32
140
160
180
Frequency (MHz)
200
220
240
D010
VCO Frequency = 5.15625 GHz
Output Divider = 32
Figure 10. 161.1328125 ± 80.56640625-MHz LVPECL
Differential Output Spectrum
10
10
0
0
-10
-10
-20
-20
Amplitude (dBm)
Amplitude (dBm)
120
PLL Bandwidth = 400 kHz
Fractional-N PLL
Figure 9. 156.25 ± 78.125-MHz HCSL Differential Output
Spectrum
-30
-40
-50
-60
-30
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
80
-100
80
100
120
140
160
180
Frequency (MHz)
PLL Bandwidth = 400 kHz
Fractional-N PLL
200
220
240
100
120
140
160
180
Frequency (MHz)
D011
VCO Frequency = 5.15625 GHz
Output Divider = 32
PLL Bandwidth = 400 kHz
Fractional-N PLL
Figure 11. 161.1328125 ± 80.56640625 MHz LVDS Output
Spectrum
200
220
240
D012
VCO Frequency = 5.15625 GHz
Output Divider = 32
Figure 12. 161.1328125 ± 80.56640625-MHz HCSL Output
Spectrum
1.8
0.9
1.7
Output Differential Swing (Vp-p)
Output Differential Swing (Vp-p)
100
D009
1.6
1.5
1.4
1.3
1.2
1.1
0.8
0.7
0.6
0.5
0
200
400
600
Output Frequency (MHz)
800
1000
0
D013
Figure 13. LVPECL Differential Output Swing vs Frequency
200
400
600
Output Frequency (MHz)
800
1000
D014
Figure 14. LVDS Differential Output Swing vs Frequency
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
11
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Typical Characteristics (continued)
Output Differential Swing (Vp-p)
1.5
1.48
1.46
1.44
1.42
1.4
0
100
200
300
Output Frequency (MHz)
400
500
D015
Figure 15. HCSL Differential Output Swing vs Frequency
12
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
7 Parameter Measurement Information
7.1 Device Output Configurations
High impedance differential probe
LMK61E0X
LVPECL
150
Oscilloscope
150
Copyright © 2016, Texas Instruments Incorporated
Figure 16. LVPECL Output DC Configuration During Device Test
High impedance differential probe
LMK61E0X
LVDS
Oscilloscope
Copyright © 2016, Texas Instruments Incorporated
Figure 17. LVDS Output DC Configuration During Device Test
High impedance differential probe
HCSL
LMK61E0X
Oscilloscope
50
50
Copyright © 2016, Texas Instruments Incorporated
Figure 18. HCSL Output DC Configuration During Device Test
LMK61E0X
Phase Noise/
Spectrum
Analyzer
LVPECL
150
150
Copyright © 2016, Texas Instruments Incorporated
Figure 19. LVPECL Output AC Configuration During Device Test
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
13
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Device Output Configurations (continued)
LMK61E0X
Phase Noise/
Spectrum
Analyzer
LVDS
Copyright © 2016, Texas Instruments Incorporated
Figure 20. LVDS Output AC Configuration During Device Test
Phase Noise/
Spectrum
Analyzer
HCSL
LMK61E0X
50
50
Copyright © 2016, Texas Instruments Incorporated
Figure 21. HCSL Output AC Configuration During Device Test
Sine wave
Modulator
Power Supply
LMK61E0X
Balun
150 (LVPECL)
Open (LVDS)
50 (HCSL)
Phase Noise/
Spectrum
Analyzer
150 (LVPECL)
Open (LVDS)
50 (HCSL)
Copyright © 2016, Texas Instruments Incorporated
Figure 22. PSRR Test Setup
OUT_P
VOD
OUT_N
80%
VOUT,DIFF,PP = 2 x VOD
0V
20%
tR
tF
Figure 23. Differential Output Voltage and Rise/Fall Time
14
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
8 Detailed Description
8.1 Overview
The LMK61E07 is a programmable oscillator family that generates commonly used reference clocks. LMK61E07
supports differential outputs with less than 200 fs, rms max random jitter in integer PLL mode and less than 300
fs, rms max random jitter in fractional PLL mode.
8.2 Functional Block Diagram
VDD
Power Conditioning
PLL
Integrated
Oscillator
10 nF
XO
R Div
/1, /4
Output
Doubler
x1, x2
OUTP
Integer Div
¥
OUTN
VCO: 4.6 GHz ~ 5.6 GHz
N Div
™û fractional
Control
SDA od
SCL od
Device
Control
Registers
od = open-drain
EEPROM
GND
Copyright © 2017, Texas Instruments Incorporated
NOTE
Control blocks are compatible with 1.8-V, 2.5-V, and 3.3-V I/O voltage levels.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
15
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
8.3 Feature Description
8.3.1 Device Block-Level Description
The LMK61E07 is an integrated oscillator that includes a 50-MHz crystal and a fractional PLL with integrated
VCO that supports a frequency range of 4.6 GHz to 5.6 GHz. The PLL block consists of a phase frequency
detector (PFD), charge pump, integrated passive loop filter, a feedback divider that can support both integer and
fractional values and a delta-sigma engine for noise suppression in fractional PLL mode. Completing the device
is the combination of an integer output divider and a differential output buffer. The PLL is powered by on-chip low
dropout (LDO) linear voltage regulators and the regulated supply network is partitioned such that the sensitive
analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs
provide isolation to the PLL from any noise in the external power supply rail. The device supports fine and coarse
frequency margining by changing the settings of the integrated oscillator and the output divider, respectively.
8.3.2 Device Configuration Control
The LMK61E07 supports I2C programming interface where an I2C host can update any device configuration after
the device enables the host interface and the host writes a sequence that updates the device registers. Once the
device configuration is set, the host can also write to the on-chip EEPROM for a new set of power-up defaults
based on the configuration pin settings in the soft pin configuration mode.
8.3.3 Register File Reference Convention
Figure 24 shows the method that this document employs to refer to an individual register bit or a grouping of
register bits. If a drawing or text references an individual bit, the format is to specify the register number first and
the bit number second. The LMK61E07 contains 38 registers that are 8 bits wide. The register addresses and the
bit positions both begin with the number zero (0). The bit address is placed in brackets or after a period. The first
bit in the register file is address R0[0] or R0.0 meaning that it is located in Register 0 and is bit position 0. The
last bit in the register file is address R72[7] or R72.7, referring to the 8th bit of register address 72 (the 73rd
register in the device). Figure 24 also lists specific bit positions as a number contained within a box. A box with
the register address encloses the group of boxes that represent the bits relevant to the specific device circuitry in
context.
Reg5
Register Number (s)
5
4
Bit Number (s)
3
2
R5.2
Figure 24. LMK61E07 Register Reference Format
8.3.4 Configuring the PLL
The PLL in LMK61E07 can be configured to accommodate various output frequencies either through I2C
programming interface or, in the absence of programming the PLL defaults stored in EEPROM are loaded on
power up. The PLL can be configured by setting the Reference Doubler, Integrated PLL Loop Filter, Feedback
Divider, and Output Divider. The corresponding register addresses and configurations are detailed in the
description section of each block below.
For the PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met.
FVCO = FREF × (D/R) × [(INT + NUM/DEN)]
where
•
•
•
•
•
•
•
16
FVCO: PLL/VCO Frequency (4.6 GHz to 5.6 GHz)
FREF: 50-MHz reference input
D: Reference input doubler, 1=Disabled, 2=Enabled
R: Reference input divider, 1=Divider bypass, 4=Divide-by-4
INT: PLL feedback divider integer value (12 bits, 1 to 4095)
NUM: PLL feedback divider fractional numerator value (22 bits, 0 to 4194303)
DEN: PLL feedback divider fractional denominator value (22 bits, 1 to 4194303)
Submit Documentation Feedback
(1)
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
Feature Description (continued)
On LMK61E07, the output frequency is related to the VCO frequency as given in Equation 2.
FOUT = FVCO / OUTDIV
where
•
OUTDIV: Output divider value (9 bits, 5 to 511)
(2)
The output frequency step size for every bit change in the numerator of the PLL fractional feedback divider is
given in Equation 3.
STEPSIZE = (FREF × D)/ (R × OUTDIV × DEN)
(3)
8.3.5 Integrated Oscillator
The integrated oscillator in LMK61E07 features programmable load capacitances that can be set for the device
to either operate at exactly its nominal oscillation frequency or operate at a fixed frequency offset from its
nominal oscillation frequency. This is done by programming R16 and R17. More details on frequency margining
are provided in Fine Frequency Margining.
8.3.6 Reference Divider and Doubler
The reference path has a divider and frequency doubler. The reference divider can be bypassed by programming
R24[0] = 0 or can be set to divide-by-4 by programming R24[0] = 1. Enabling the divider results in a lower
comparison frequency for the PLL and would result in a 6-dB increase in the in-band phase noise at the output of
the LMK61E07 but would result in a finer frequency resolution at the output for every bit change in the numerator
of fractional feedback divider. The reference doubler can be enabled by programming R34[5] = 1. Bypassing the
divider allows for a higher comparison rate and improved in-band phase noise at the output of the LMK61E07.
Enabling the doubler allows a higher comparison frequency for the PLL and would result in a 3-dB reduction in
the in-band phase noise at the output of the LMK61E07. Enabling the doubler also results in higher reference
and phase detector spurs which will be minimized by enabling the higher order components (R3, C3) of the loop
filter and programming them to appropriate values. Disabling the doubler would result in a finer frequency
resolution at the output for every bit change in the numerator of the fractional feedback divider and higher inband phase noise on the device output than when the doubler is enabled. However, the reference and phase
detector spurs would be lower on the device output than when the doubler is enabled.
8.3.7 Phase Frequency Detector
The Phase Frequency Detector (PFD) of the PLL takes inputs from the reference path and the feedback divider
output and produces an output that is dependent on the phase and frequency difference between the two inputs.
The input frequency of the PFD is equal to the 50-MHz reference frequency doubled if the reference doubler is
enabled and then divided by 4 if the reference divider is enabled. The feedback frequency to the PFD must equal
the reference path frequency to the PFD for the PLL to lock.
8.3.8 Feedback Divider (N)
The N divider of the PLL includes fractional compensation and can achieve any fractional denominator (DEN)
from 1 to 4,194,303. The integer portion, INT (valid range 1-4095), is the whole part of the N divider value and
the fractional portion, NUM / DEN, is the remaining fraction. INT, NUM, and DEN are programmed in R25/R26,
R27/R28/R29, and R30/R31/R32, respectively. The total programmed N divider value, N, is determined by: N =
INT + NUM / DEN. The output of the N divider sets the PFD frequency to the PLL. The feedback frequency to
the PFD must equal the reference path frequency to the PFD for the PLL to lock. In DCXO mode, the NUM
registers can be reprogrammed MSB first and LSB last to update the output frequency without glitches or spikes.
8.3.9 Fractional Engine
The delta signal modulator is a key component of the fractional engine and is involved in noise shaping for better
phase noise and spurs in the band of interest. The order of the delta sigma modulator is selectable between the
integer mode and third order for fractional PLL mode, and it can be programmed in R33[1:0]. Dithering can be
programmed in R33[3:2] and should be disabled for integer PLL mode and set to weak for fractional PLL mode.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
17
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Feature Description (continued)
8.3.10 Charge Pump
The PLL uses either 1.6-mA charge pump slices when the PLL is set to fractional mode, or 6.4-mA slices when
the PLL is set to integer mode. These slices can be selected by programming R34[3:0]. When the PLL is set to
fractional mode, a phase shift must be introduced to maintain a linear response and ensure consistent
performance across operating conditions and a value of 0x2 should be programmed in R35[6:4]. When the PLL
is set to integer mode, a value of 0x0 should be programmed in R35[6:4].
8.3.11 Loop Filter
The LMK61E07 features a fully integrated loop filter for the PLL that supports programmable loop bandwidth from
100 kHz to 1 MHz. The loop filter components, R2, C1, R3, and C3, can be configured by programming R36,
R37, R38, and R39, respectively. The LMK61E07 features a fixed value of C2 of 10 nF. When the PLL is
configured in fractional mode, R35[2] should be set to 1. When the reference doubler is disabled for integer
mode PLL, R35[2] should be set to 0 and R38[6:0] should be set to 0x00. When the reference doubler is enabled
for integer mode PLL, R35[2] should be set to 1 and R38 and R39 are written with the appropriate values.
Figure 25 shows the loop filter structure of the PLL. It is important to set the PLL to the best possible bandwidth
to minimize output jitter.
18
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
Feature Description (continued)
VDD
(x5)
3.3V
TCXO/
OCXO
10-54
MHz
(Optional)
VDDO
(x6)
1.8-3.3V
XO
10-100
MHz
Power
Conditioning
M div
SYNC
x2
System
x2
Clock (3.3V)
INSEL0[1:0]
0
1
2
3
4
5
Integer Div
32-b
OUT0
0
1
2
3
4
5
Integer Div
20-b
OUT1
0
1
2
3
Integer Div
20-b
Hitless
switching
with priority
IN2
/4 - /9,
/11, /13
R0 div
16-b
PLL Core 1
VCO Freq = 4.8 ~ 5.4 GHz
/4 - /9,
/11, /13
IN3
OUT2
OUT3
/[48*(2-31)]
/[48*(2-31)]
OUT4
0
1
2
3
Integer Div
20-b
Hitless
switching
with priority
/4 - /9,
/11, /13
R1 div
16-b
AC-LVDS, AC-LVPECL, AC-CML, HCSL or 2.5V LVCMOS
IN0
IN1
OUT5
PLL Core 2
VCO Freq = 5.5 ~ 6.1 GHz
/4 - /9,
/11, /13
Synthesizers (3.3V)
INSEL1[1:0]
0
1
2
3
Integer Div
20-b
OUT6
0
1
2
3
Integer Div
32-b
OUT7
Inputs (3.3V)
SDA
SCL
HW_SW_CTRL
GPIO[6:0]
STATUS[1:0]
PDN
Output (1.8-3.3V)
od
Registers
EEPROM
ROM
od
od
Device Control
and Status
1.5-3.3V Logic IOs
Control (3.3V)
od
= open-drain
CAP LF1
(x3)
LF2
*Output dividers support glitchless frequency margining
and phase synchronization
Copyright © 2017, Texas Instruments Incorporated
Figure 25. Loop Filter Structure of PLL
8.3.12 VCO Calibration
The PLL in LMK61E07 is made of LC VCO that is designed using high-Q monolithic inductors to oscillate
between 4.6 GHz and 5.6 GHz and has low phase noise characteristics. The VCO must be calibrated to ensure
that the clock outputs deliver optimal phase noise performance. Fundamentally, a VCO calibration establishes an
optimal operating point within the tuning range of the VCO. Setting R72[1] to 1 causes a VCO recalibration and is
necessary after device reconfiguration. VCO calibration automatically occurs on device power up.
8.3.13 High-Speed Output Divider
The high-speed output divider supports divide values of 5 to 511 and is programmed in R22 and R23. The output
divider also supports coarse frequency margining that can initiate as low as a 5% change in the output
frequency.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
19
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Feature Description (continued)
8.3.14 High-Speed Clock Output
The clock output on LMK61E07 can be configured as LVPECL, LVDS, or HCSL by programming R21[1:0].
Interfacing to LVPECL, LVDS, or HCSL receivers are done either with direct coupling or with AC-coupling
capacitor as shown in Figure 16 through Figure 21.
The LVDS output structure has integrated 125 Ω termination between each side (P and N) of the differential pair.
The HCSL output structure is open drain and can be DC or AC coupled to HCSL receivers with appropriate
termination scheme. The LVPECL output structure is an emitter follower requiring external termination.
8.3.15 Device Status
The PLL loss of lock and PLL calibration status can be monitored by reading R66[1:0]. These bits represent a
logic-high interrupt output and are self-cleared once the readback is complete.
8.3.15.1 Loss of Lock
The PLL loss of lock detection circuit is a digital circuit that detects any frequency error, even a single cycle slip.
Loss of lock may occur when an incorrect PLL configuration is programmed or the VCO has not been
recalibrated.
8.4 Device Functional Modes
8.4.1 Interface and Control
The host (DSP, Microcontroller, FPGA, and so forth) configures and monitors the LMK61E07 through the I2C
port. The host reads and writes to a collection of control and status bits called the register map. The device
blocks can be controlled and monitored through a specific grouping of bits located within the register file. The
host controls and monitors certain device Wide critical parameters directly through register control and status
bits. In the absence of the host, the LMK61E07 can be configured to operate from its on-chip EEPROM. The
EEPROM array is automatically copied to the device registers upon power up. The user has the flexibility to
rewrite the contents of EEPROM from the SRAM up to 100 times.
Within the device registers, there are certain bits that have read or write access. Other bits are read-only (an
attempt to write to a read-only bit will not change the state of the bit). Certain device registers and bits are
reserved meaning that they must not be changed from their default reset state. Figure 26 shows interface and
control blocks within LMK61E07 and the arrows refer to read access from and write access to the different
embedded memories (EEPROM, SRAM).
20
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
Device Functional Modes (continued)
Core 1: VCO Freq = 4.8 ~ 5.4 GHz
Core 2: VCO Freq = 5.5 ~ 6.1 GHz
From XO
x1, x2
PFD
Loop BW = 300kHz - 500kHz
N Div
™û fractional
APLL
From TCXO
TDC
Loop BW = 100Hz t 10kHz
N Div
™û fractional
TCXO-DPLL
From Input MUX
TDC
Loop BW = 1mHz t 4kHz
N Div
™û fractional
REF-DPLL
Figure 26. LMK61E07 Interface and Control Block
8.4.2 DCXO Mode and Frequency Margining
8.4.2.1 DCXO Mode
In applications that require the LMK61E07 as part of a PLL that is implemented in another device like an FPGA,
it can be used as a digitally-controlled oscillator (DCXO) where the frequency control word can be passed along
through I2C to the LMK61E07 on a regular basis, which in turn updates the numerator of its fractional feedback
divider by the required amount. In such a scenario, the entire portion of numerator for the fractional feedback
divider must be written on every attempt MSB first and LSB last to ensure that the output frequency does not
jump during the update, as described in Feedback Divider (N). In every update cycle, a total of 46 bits needs to
be updated leading to a maximum update rate of 8.7 kHz with a maximum I2C rate of 1 Mbps. The minimum step
size of 0.55 ppb (parts per billion) is achieved for the maximum VCO frequency of 5.6 GHz and when reference
input doubler is disabled and reference divider is set to 4. The minimum step size of 4.96 ppb (parts per billion) is
achieved for the maximum VCO frequency of 4.8 GHz and when reference input doubler is enabled and
reference divider is bypassed.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
21
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Device Functional Modes (continued)
8.4.2.2 Fine Frequency Margining
IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a
reference clock that is within ±100 ppm of its nominal frequency. In the worst case, an RX node with its local
reference clock at –100 ppm from its nominal frequency should be able to work seamlessly with a TX node that
has its own local reference clock at +100 ppm from its nominal frequency. Without any clock compensation on
the RX node, the read pointer will severely lag behind the write pointer and cause FIFO overflow errors. On the
contrary, when the RX node’s local clock operates at +100 ppm from its nominal frequency and the TX node’s
local clock operates at –100 ppm from its nominal frequency, FIFO underflow errors occur without any clock
compensation.
To prevent such overflow and underflow errors from occurring, modern ASICs and FPGAs include a clock
compensation scheme that introduces elastic buffers. Such a system, shown in Figure 27, is validated thoroughly
during the validation phase by interfacing slower nodes with faster ones and ensuring compliance to IEEE802.3.
The LMK61E07 provides the ability to fine tune the frequency of its outputs based on changing its load
capacitance for the integrated oscillator. This fine tuning can be done through I2C as described in Integrated
Oscillator. The change in load capacitance is implemented in a manner such that the output of LMK61E07
undergoes a smooth monotonic change in frequency.
8.4.2.3 Coarse Frequency Margining
Certain systems require the processors to be tested at clock frequencies that are slower or faster by 5% or 10%.
The LMK61E07 offers the ability to change its output divider for the desired change from its nominal output
frequency as explained in High-Speed Output Divider.
TX
RX
Serializer
Post Processing
w/ clock
compensation
Sampler
Serialized clock/data
Parallel
Data
Recovered
Clock
Parallel
Data
+/- 100 ppm
TX PLL
CDR
Ref Clk
+/- 100 ppm
Ref Clk
Deserializer
Elastic Buffer
(clock compensation)
FIFO
circular
Latency
Write
Pointer
Read
Pointer
Figure 27. System Implementation With Clock Compensation for Standards Compliance
22
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
8.5 Programming
8.5.1 I2C Serial Interface
The I2C port on the LMK61E07 works as a slave device and supports both the 100-kHz standard mode and 1MHz fast mode operations. Fast mode imposes a glitch tolerance requirement on the control signals. Therefore,
the input receivers ignore pulses of less than 50-ns duration. The I2C timing is given in I2C-Compatible Interface
Characteristics (SDA, SCL) (1) (2). The timing diagram is given in Figure 28.
STOP
START
ACK
tW(SCLL)
tW(SCLH)
STOP
tf(SM)
tr(SM)
~
~
VIH(SM)
SCL
VIL(SM)
~
~
th(START)
tr(SM)
tSU(SDATA)
th(SDATA)
tSU(START)
tSU(STOP)
tf(SM)
tBUS
~
~
~
~
VIH(SM)
SDA
VIL(SM)
~
~
Figure 28. I2C Timing Diagram
In an I2C bus system, the LMK61E07 acts as a slave device and is connected to the serial bus (data bus SDA
and lock bus SCL). These are accessed through a 7-bit slave address transmitted as part of an I2C packet. Only
the device with a matching slave address responds to subsequent I2C commands. The device slave address is
1011001 or 0x59.
During the data transfer through the I2C interface, one clock pulse is generated for each data bit transferred. The
data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can
change only when the clock signal on the SCL line is low. The start data transfer condition is characterized by a
high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is characterized by a
low-to-high transition on the SDA line while SCL is high. The start and stop conditions are always initiated by the
master. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit
and bytes are sent MSB first. The I2C register structure of the LMK61E07 is shown in Figure 29.
I2C PROTOCOL
7
1
8
8
W/R
REGISTER ADDRESS
DATA BYTE
A6 A5 A4 A3 A2 A1 A0
I2C ADDRESS
Figure 29. I2C Register Structure
The acknowledge bit (A) or non-acknowledge bit (A’) is the 9th bit attached to any 8-bit data byte and is always
generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A’
= 0). A = 0 is done by pulling the SDA line low during the 9th clock pulse and A’ = 0 is done by leaving the SDA
line high during the 9th clock pulse.
(1)
(2)
Total capacitive load for each bus line ≤ 400 pF.
Ensured by design.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
23
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Programming (continued)
The I2C master initiates the data transfer by asserting a start condition which initiates a response from all slave
devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line
(consisting of the 7-bit slave address (MSB first) and an R/W’ bit), the device whose address corresponds to the
transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the
selected device waits for data transfer with the master.
After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop
condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte
from the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low
during the 9th clock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the
slave knows the data transfer is finished and enters the idle mode. The master then takes the data line low
during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition.
A generic transaction is shown in Figure 30.
1
S
7
Slave Address
1
R/W
MSB
1
A
8
Data Byte
LSB
S
Start Condition
Sr
Repeated Start Condition
MSB
1
A
1
P
LSB
R/W 1 = Read (Rd) from slave; 0 = Write (Wr) to slave
A
Acknowledge (ACK = 0 and NACK = 1)
P
Stop Condition
Master to Slave Transmission
Slave to Master Transmission
Figure 30. Generic Programming Sequence
The LMK61E07 I2C interface supports Block Register Write/Read, Read/Write SRAM, and Read/Write EEPROM
operations. For Block Register Write/Read operations, the I2C master can individually access addressed
registers that are made of an 8-bit data byte.
8.5.2 Block Register Write
The I2C Block Register Write transaction is illustrated in Figure 31 and consists of the following sequence.
1. Master issues a Start Condition.
2. Master writes the 7-bit Slave Address following by a Write bit.
3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.
4. Master writes one or more data bytes each of which should be acknowledged by the slave. The slave
increments the internal register address after each byte.
5. Master issues a Stop Condition to terminate the transaction.
1
S
7
Slave Address
8
Data Byte 0
1
Wr
1
A
...
1
A
8
CommandCode
1
A
8
Data Byte N-1
1
A
1
P
Figure 31. Block Register Write Programming Sequence
8.5.3 Block Register Read
The I2C Block Register Read transaction is illustrated in Figure 32 and consists of the following sequence.
1. Master issues a Start Condition.
2. Master writes the 7-bit Slave Address followed by a Write bit.
3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.
4. Master issues a Repeated Start Condition.
24
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
Programming (continued)
5. Master writes the 7-bit Slave Address following by a Read bit.
6. Slave returns one or more data bytes as long as the Master continues to acknowledge them. The slave
increments the internal register address after each byte.
7. Master issues a Stop Condition to terminate the transaction.
1
S
7
Slave Address
8
Data Byte 0
1
Wr
1
A
1
A
8
CommandCode
1
A
...
1
Sr
7
Slave Address
8
Data Byte N-1
1
Rd
1
A
1
A
1
P
Figure 32. Block Register Read Programming Sequence
8.5.4 Write SRAM
The on-chip SRAM is a volatile, shadow memory array used to temporarily store register data, and is intended
only for programming the non-volatile EEPROM. The SRAM has the identical data format as the EEPROM map.
The register configuration data can be transferred to the SRAM array through special memory access registers in
the register map. To successfully program the SRAM, the complete base array and at least one page should be
written. The following details the programming sequence to transfer the device registers into the SRAM.
1. Program the device registers to match a desired setting.
2. Write a 1 to R49[6]. This ensures that the device registers are copied to the SRAM.
The SRAM can also be written with particular values according to the following programming sequence.
1. Write the SRAM address in R51.
2. Write the desired data byte in R53 in the same I2C transaction and this data byte will be written to the
address specified in the step above. Any additional access that is part of the same transaction will cause the
SRAM address to be incremented and a write will take place to the next SRAM address. Access to SRAM
will terminate at the end of current I2C transaction.
NOTE
It is possible to increment SRAM address incorrectly when 2 successive accesses are
made to R51.
8.5.5 Write EEPROM
The on-chip EEPROM is a non-volatile memory array used to permanently store register data for a custom
device start-up configuration setting to initialize registers upon power up or POR. The EEPROM is comprised of
bits shown in the EEPROM Map. The transfer must first happen to the SRAM and then to the EEPROM. During
EEPROM write, R49[2] is a 1 and the EEPROM contents cannot be accessed. The following details the
programming sequence to transfer the entire contents of SRAM to EEPROM.
1. Make sure the Write SRAM procedure (Write SRAM) was done to commit the register settings to the SRAM
with start-up configurations intended for programming to the EEPROM.
2. Write 0xBE to R56. This provides basic protection from inadvertent programming of EEPROM.
3. Write a 1 to R49[0]. This programs the entire SRAM contents to EEPROM. Once completed, the contents in
R48 will increment by 1. R48 contains the total number of EEPROM programming cycles that are
successfully completed.
4. Write 0x00 to R56 to protect against inadvertent programming of EEPROM.
8.5.6 Read SRAM
The contents of the SRAM can be read out, one word at a time, starting with that of the requested address.
Following details the programming sequence for an SRAM read by address.
1. Write the SRAM address in R51.
2. The SRAM data located at the address specified in the step above can be obtained by reading R53 in the
same I2C transaction. Any additional access that is part of the same transaction will cause the SRAM
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
25
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Programming (continued)
address to be incremented and a read will take place of the next SRAM address. Access to SRAM will
terminate at the end of current I2C transaction.
NOTE
It is possible to increment SRAM address incorrectly when 2 successive accesses are
made to R51.
8.5.7 Read EEPROM
The contents of the EEPROM can be read out, one word at a time, starting with that of the requested address.
Following details the programming sequence for an EEPROM read by address.
1. Write the EEPROM address in R51.
2. The EEPROM data located at the address specified in the step above can be obtained by reading R52 in the
same I2C transaction. Any additional access that is part of the same transaction will cause the EEPROM
address to be incremented and a read will take place of the next EEPROM address. Access to EEPROM will
terminate at the end of current I2C transaction.
NOTE
It is possible to increment EEPROM address incorrectly when 2 successive accesses are
made to R51.
26
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
8.6 Register Maps
Any bit that is labeled as RESERVED should be written with a 0.
Table 1. EEPROM Map
BYTE
NO.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
4
NVMSCRC[7]
NVMSCRC[6]
NVMSCRC[5]
NVMSCRC[4]
NVMSCRC[3]
NVMSCRC[2]
NVMSCRC[1]
NVMSCRC[0]
5
NVMCNT[7]
NVMCNT[6]
NVMCNT[5]
NVMCNT[4]
NVMCNT[3]
NVMCNT[2]
NVMCNT[1]
NVMCNT[0]
6
1
RESERVED
RESERVED
RESERVED
RESERVED
1
RESERVED
RESERVED
7
RESERVED
RESERVED
1
RESERVED
RESERVED
RESERVED
RESERVED
1
8
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
9
SLAVEADR[7]
SLAVEADR[6]
SLAVEADR[5]
SLAVEADR[4]
SLAVEADR[3]
RESERVED
RESERVED
RESERVED
10
EEREV[7]
EEREV[6]
EEREV[5]
EEREV[4]
EEREV[3]
EEREV[2]
EEREV[1]
EEREV[0]
11
RESERVED
PLL_PDN
RESERVED
RESERVED
RESERVED
RESERVED
AUTOSTRT
RESERVED
14
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
RESERVED
1
15
RESERVED
XO_CAPCTRL[1]
XO_CAPCTRL[0]
XO_CAPCTRL[9]
XO_CAPCTRL[8]
XO_CAPCTRL[7]
XO_CAPCTRL[6]
XO_CAPCTRL[5]
16
XO_CAPCTRL[4]
XO_CAPCTRL[3]
XO_CAPCTRL[2]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
19
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
20
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
21
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PLL_RDIV
22
PLL_NDIV[11]
PLL_NDIV[10]
PLL_NDIV[9]
PLL_NDIV[8]
PLL_NDIV[7]
PLL_NDIV[6]
PLL_NDIV[5]
PLL_NDIV[4]
23
PLL_NDIV[3]
PLL_NDIV[2]
PLL_NDIV[1]
PLL_NDIV[0]
PLL_NUM[21]
PLL_NUM[20]
PLL_NUM[19]
PLL_NUM[18]
24
PLL_NUM[17]
PLL_NUM[16]
PLL_NUM[15]
PLL_NUM[14]
PLL_NUM[13]
PLL_NUM[12]
PLL_NUM[11]
PLL_NUM[10]
25
PLL_NUM[9]
PLL_NUM[8]
PLL_NUM[7]
PLL_NUM[6]
PLL_NUM[5]
PLL_NUM[4]
PLL_NUM[3]
PLL_NUM[2]
26
PLL_NUM[1]
PLL_NUM[0]
PLL_DEN[21]
PLL_DEN[20]
PLL_DEN[19]
PLL_DEN[18]
PLL_DEN[17]
PLL_DEN[16]
27
PLL_DEN[15]
PLL_DEN[14]
PLL_DEN[13]
PLL_DEN[12]
PLL_DEN[11]
PLL_DEN[10]
PLL_DEN[9]
PLL_DEN[8]
28
PLL_DEN[7]
PLL_DEN[6]
PLL_DEN[5]
PLL_DEN[4]
PLL_DEN[3]
PLL_DEN[2]
PLL_DEN[1]
PLL_DEN[0]
29
PLL_
DTHRMODE[1]
PLL_DTHRMODE[0]
PLL_ORDER[1]
PLL_ORDER[0]
RESERVED
RESERVED
PLL_D
PLL_CP[3]
30
PLL_CP[2]
PLL_CP[1]
PLL_CP[0]
PLL_CP_PHASE_
SHIFT[2]
PLL_CP_PHASE_
SHIFT[1]
PLL_CP_PHASE_
SHIFT[0]
PLL_ENABLE_
C3[2]
PLL_ENABLE_
C3[1]
31
PLL_ENABLE_
C3[0]
PLL_LF_R2[7]
PLL_LF_R2[6]
PLL_LF_R2[5]
PLL_LF_R2[4]
PLL_LF_R2[3]
PLL_LF_R2[2]
PLL_LF_R2[1]
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
27
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Register Maps (continued)
Table 1. EEPROM Map (continued)
BYTE
NO.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
32
PLL_LF_R2[0]
PLL_LF_C1[2]
PLL_LF_C1[1]
PLL_LF_C1[0]
PLL_LF_R3[6]
PLL_LF_R3[5]
PLL_LF_R3[4]
PLL_LF_R3[3]
33
PLL_LF_R3[2]
PLL_LF_R3[1]
PLL_LF_R3[0]
PLL_LF_C3[2]
PLL_LF_C3[1]
PLL_LF_C3[0]
RESERVED
RESERVED
34
PRE_DIV
OUT_DIV[8]
OUT_DIV[7]
OUT_DIV[6]
OUT_DIV[5]
OUT_DIV[4]
OUT_DIV[3]
OUT_DIV[2]
35
OUT_DIV[1]
OUT_DIV[0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
28
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
The default/reset values for each register is specified for LMK61E07.
Table 2. Register Map
NAME
ADD
R
RES
ET
BIT7
BIT6
BIT5
VNDRID_BY
1
0
0x10
VNDRID[15:8]
VNDRID_BY
0
1
0x0B VNDRID[7:0]
PRODID
2
0x33
PRODID[7:0]
REVID
3
0x00
REVID[7:0]
SLAVEADR
8
0xB0 SLAVEADR[7:1]
EEREV
9
0x00
EEREV[7:0]
DEV_CTL
10
0x01
RESERVED
XO_CAPCTR 16
L_
BY1
0x00
RESERVED
XO_CAPCTR 17
L_
BY0
0x00
XO_CAPCTRL[9:2]
DIFFCTL
21
0x01
DIFF_OUT_P RESERVED
D
OUTDIV_BY1 22
0x00
RESERVED
OUTDIV_BY0 23
0x20
OUT_DIV[7:0]
RDIVCMOSC 24
TL
0x00
RESERVED
PLL_NDIV_B
Y1
25
0x00
RESERVED
PLL_NDIV_B
Y0
26
0x64
PLL_NDIV[7:0]
PLL_FRACN
UM_
BY2
27
0x00
RESERVED
PLL_FRACN
UM_
BY1
28
0x00
PLL_NUM[15:8]
PLL_FRACN
UM_
BY0
29
0x00
PLL_NUM[7:0]
PLL_FRACD
EN_
BY2
30
0x00
RESERVED
PLL_FRACD
EN_
BY1
31
0x00
PLL_DEN[15:8]
PLL_FRACD
EN_
BY0
32
0x00
PLL_DEN[7:0]
PLL_MASHC
TRL
33
0x0C RESERVED
PLL_CTRL0
34
0x24
RESERVED
PLL_CTRL1
35
0x03
RESERVED
PLL_LF_R2
36
0x28
PLL_LF_R2[7:0]
PLL_LF_C1
37
0x00
RESERVED
PLL_LF_R3
38
0x00
RESERVED
PLL_LF_C3
39
0x00
RESERVED
PLL_CALCT
RL
42
0x00
RESERVED
BIT4
BIT3
BIT2
BIT1
BIT0
RESERVED
PLL_PDN
RESERVED
ENCAL
AUTOSTRT
XO_CAPCTRL[1:0]
OUT_SEL[1:0]
OUT_DIV[8]
PLL_RDIV
PLL_NDIV[11:8]
PLL_NUM[21:16]
PLL_DEN[21:16]
PLL_DTHRMODE[1:0] PLL_ORDER[1:0]
PLL_D
RESERVED PLL_CP[3:0]
PLL_CP_PHASE_SHIFT[2:0]
RESERVED PLL_ENABLE_C3[2:0]
PLL_LF_C1[2:0]
PLL_LF_R3[6:0]
PLL_LF_C3[2:0]
PLL_CLSDWAIT[1:0]
PLL_VCOWAIT[1:0]
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
29
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
Table 2. Register Map (continued)
NAME
ADD
R
RES
ET
BIT7
BIT6
BIT5
NVMSCRC
47
0x00
NVMSCRC[7:0]
NVMCNT
48
0x00
NVMCNT[7:0]
NVMCTL
49
0x10
RESERVED
NVMLCRC
50
0x00
NVMLCRC[7:0]
MEMADR
51
0x00
RESERVED
NVMDAT
52
0x00
NVMDAT[7:0]
RAMDAT
53
0x00
RAMDAT[7:0]
NVMUNLK
56
0x00
NVMUNLK[7:0]
INT_LIVE
66
0x00
RESERVED
LOL
CAL
SWRST
72
0x00
RESERVED
SWR2PLL
RESERVED
REGCOMMI NVMCRCE
T
RR
BIT4
BIT3
BIT2
BIT1
BIT0
NVMAUTO
CRC
NVMCOMM NVMBU NVMERAS NVMPROG
IT
SY
E
MEMADR[6:0]
8.6.1 Register Descriptions
8.6.1.1 VNDRID_BY1 Register; R0
VNDRID_BY1 and VNDRID_BY0 registers are used to store the unique 16-bit Vendor Identification number
assigned to I2C vendors.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
VNDRID[15:8]
R
0x10
N
Vendor Identification Number Byte 1.
8.6.1.2 VNDRID_BY0 Register; R1
VNDRID_BY1 and VNDRID_BY0 registers are used to store the unique 16-bit Vendor Identification number
assigned to I2C vendors.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
VNDRID[7:0]
R
0x0B
N
Vendor Identification Number Byte 0.
8.6.1.3 PRODID Register; R2
The Product Identification Number is a unique 8-bit identification number used to identify the LMK61E0.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PRODID[7:0]
R
0x33
N
Product Identification Number.
8.6.1.4 REVID Register; R3
The REVID register is used to identify the LMK61E07 mask revision.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
REVID[7:0]
R
0x00
N
Device Revision Number. The Device Revision Number
is used to identify the LMK61E07 mask-set revision used
to fabricate this device.
8.6.1.5 SLAVEADR Register; R8
The SLAVEADR register reflects the 7-bit I2C Slave Address value initialized from from on-chip EEPROM.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:1]
SLAVEADR[7:1]
R
0x59
Y
I2C Slave Address. This field holds the 7-bit Slave
Address used to identify this device during I2C
transactions.
[0]
RESERVED
-
-
N
Reserved.
30
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
8.6.1.6 EEREV Register; R9
The EEREV register provides an EEPROM image revision record. EEPROM Image Revision is automatically
retrieved from EEPROM and stored in the EEREV register after a reset or after a EEPROM commit operation.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
EEREV[7:0]
R
0x00
Y
EEPROM Image Revision ID
8.6.1.7 DEV_CTL Register; R10
The DEV_CTL register holds the control functions described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
0
Y
Reserved.
[6]
PLL_PDN
RW
0
Y
PLL Powerdown. The PLL_PDN bit determines whether
PLL is automatically enabled and calibrated after a
hardware reset. If the PLL_PDN bit is set to 1 during
normal operation then PLL is disabled and the calibration
circuit is reset. When PLL_PDN is then cleared to 0 PLL
is re-enabled and the calibration sequence is
automatically restarted.
PLL_PDN
Value
0
PLL Enabled
1
PLL Disabled
[5]
CMOS_SEL
RW
0
Y
Set to 0 for LMK61E07.
[4:2]
RESERVED[5:2]
RW
0
Y
Reserved.
[1]
ENCAL
RWSC
0
N
Enable Frequency Calibration. Triggers PLL/VCO
calibration on both PLLs in parallel on 0 –> 1 transition
of ENCAL. This bit is self-clearing and set to a 0 after
PLL/VCO calibration is complete. In powerup or software
rest mode, AUTOSTRT takes precedence.
[0]
AUTOSTRT
RW
1
Y
Autostart. If AUTOSTRT is set to 1 the device will
automatically attempt to achieve lock and enable outputs
after a device reset. A device reset can be triggered by
the power-on-reset, RESETn pin or by writing to the
RESETN_SW bit. If AUTOSTRT is 0 then the device will
halt after the configuration phase, a subsequent write to
set the AUTOSTRT bit to 1 will trigger the PLL Lock
sequence.
8.6.1.8 XO_CAPCTRL_BY1 Register; R16
XO Margining Offset Value bits[9:8]
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:2]
RESERVED[5:0]
-
-
N
Reserved.
[1:0]
XO_CAPCTRL [1:0]
RW
0x0
Y
XO Offset Value bits [1:0]
8.6.1.9 XO_CAPCTRL_BY0 Register; R17
XO Margining Offset Value bits[7:0]
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
XO_CAPCTRL [9:2]
RW
0x80
Y
XO Offset Value bits[9:2]
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
31
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
8.6.1.10 DIFFCTL Register; R21
The DIFFCTL register provides control over Output for LMK61E07.
Bit #
Field
Type
Reset
EEPROM
Description
[7]
DIFF_OUT_PD
RW
0
N
Power down differential output buffer in LMK61E07.
[6:2]
RESERVED
-
-
N
Reserved.
[1:0]
OUT_SEL[1:0]
RW
0x1
Y
Channel Output Driver Select in LMK61E07. The
OUT_SEL field controls the Channel Output Driver as
shown below.
OUT_SEL
OUTPUT OPERATION
0 (0x0)
Tri-State
1 (0x1)
LVPECL
2 (0x2)
LVDS
3 (0x3)
HCSL
8.6.1.11 OUTDIV_BY1 Register; R22
The 9-bit output integer divider value is set by the OUTDIV_BY1 and OUTDIV_BY0 registers.
BIT NO.
FIELD
TYPE
RESET
EEPROM DESCRIPTION
[7:1]
RESERVED
-
-
Y
Reserved.
[0]
OUT_DIV[8]
RW
0
Y
Channel's Output Divider Byte 1 (Bit 8). The Channel
Divider, OUT_DIV, is a 9-bit divider. The valid register
values range from 5-511.
OUT_DIV
DIVIDE RATIO
0-4
RESERVED
5 (0x006)
5
6 (0x007)
6
...
...
511 (0x1FF)
511
8.6.1.12 OUTDIV_BY0 Register; R23
The 9-bit output integer divider value is set by the OUTDIV_BY1 and OUTDIV_BY0 registers.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
OUT_DIV[7:0]
RW
0x20
Y
Channel's Output Divider Byte 0 (Bits 7-0).
8.6.1.13 RDIVCMOSCTL Register; R24
Sets R divider for LMK61E07.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:1]
RESERVED
-
-
N
Reserved.
[0]
PLL_RDIV
RW
0
Y
On LMK61E07, R divider is set to divide-by-4 when set to
1 and R divider is bypassed when set to 0.
32
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
8.6.1.14 PLL_NDIV_BY1 Register; R25
The 12-bit N integer divider value for PLL is set by the PLL_NDIV_BY1 and PLL_NDIV_BY0 registers.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:4]
RESERVED
-
-
N
Reserved.
[3:0]
PLL_NDIV[11:8]
RW
0x0
Y
PLL N Divider Byte 1. PLL Integer N Divider bits [11:8].
8.6.1.15 PLL_NDIV_BY0 Register; R26
The PLL_NDIV_BY0 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_NDIV[7:0]
RW
0x32
Y
PLL N Divider Byte 0. PLL Integer N Divider bits [7:0].
8.6.1.16 PLL_FRACNUM_BY2 Register; R27
The 22-bit Fractional Divider Numerator value for PLL is set by registers PLL_FRACNUM_BY2,
PLL_FRACNUM_BY1 and PLL_FRACNUM_BY0.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:6]
RESERVED
-
-
N
Reserved.
[5:0]
PLL_NUM[21:16]
RW
0x00
Y
PLL Fractional Divider Numerator Byte 2. Bits [21:16]
8.6.1.17 PLL_FRACNUM_BY1 Register; R28
The PLL_FRACNUM_BY1 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_NUM[15:8]
RW
0x00
Y
PLL Fractional Divider Numerator Byte 1. Bits [15:8].
8.6.1.18 PLL_FRACNUM_BY0 Register; R29
The PLL_FRACNUM_BY0 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_NUM[7:0]
RW
0x00
Y
PLL Fractional Divider Numerator Byte 0. Bits [7:0]. When
using DCXO mode, the fractional numerator bits in R27,
R28, and R29 should be written in that order (MSB first
and LSB last) to avoid intermediate frequency jumps.
8.6.1.19 PLL_FRACDEN_BY2 Register; R30
The 22-bit Fractional Divider Denominator value for PLL is set by registers PLL_FRACDEN_BY2,
PLL_FRACDEN_BY1 and PLL_FRACDEN_BY0.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:6]
RESERVED
-
-
N
Reserved.
[5:0]
PLL_DEN[21:16]
RW
0x00
Y
PLL Fractional Divider Denominator Byte 2. Bits [21:16].
8.6.1.20 PLL_FRACDEN_BY1 Register; R31
The PLL_FRACDEN_BY1 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_DEN[15:8]
RW
0x00
Y
PLL Fractional Divider Denominator Byte 1. Bits [15:8].
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
33
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
8.6.1.21 PLL_FRACDEN_BY0 Register; R32
The PLL_FRACDEN_BY0 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_DEN[7:0]
RW
0x00
Y
PLL Fractional Divider Denominator Byte 0. Bits [7:0].
8.6.1.22 PLL_MASHCTRL Register; R33
The PLL_MASHCTRL register provides control of the fractional divider for PLL.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:4]
RESERVED
-
-
N
Reserved.
[3:2]
PLL_DTHRMODE[1:0]
RW
0x3
Y
Mash Engine dither mode control.
[1:0]
PLL_ORDER[1:0]
RW
0x0
Y
DITHERMODE
Dither Configuration
0 (0x0)
Weak
1 (0x1)
Reserved
2 (0x2)
Reserved
3 (0x3)
Dither Disabled
Mash Engine Order.
ORDER
Order Configuration
0 (0x0)
Integer Mode Divider
1 (0x1)
Reserved
2 (0x2)
Reserved
3 (0x3)
3rd order
8.6.1.23 PLL_CTRL0 Register; R34
The PLL_CTRL1 register provides control of PLL. The PLL_CTRL1 register fields are described in the following
table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:6]
RESERVED
RW
0x0
Y
Reserved.
[5]
PLL_D
RW
1
Y
PLL R Divider Frequency Doubler Enable. If PLL_D is 1
the R Divider Frequency Doubler is enabled.
[4]
RESERVED
-
-
N
Reserved.
[3:0]
PLL_CP[3:0]
RW
0x8
Y
PLL Charge Pump Current. Other combinations of
PLL_CP[3:0] not in table below are reserved and not
supported.
34
PLL_CP[3:0]
PLL Charge Pump Current
4 (0x4)
1.6 mA
8 (0x8)
6.4 mA
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
8.6.1.24 PLL_CTRL1 Register; R35
The PLL_CTRL3 register provides control of PLL. The PLL_CTRL3 register fields are described in the following
table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
-
N
Reserved.
[6:4]
PLL_CP_PHASE_SHIFT RW
[2:0]
0x0
Y
Program Charge Pump Phase Shift.
PLL_CP_PHASE_SHIFT[ Phase Shift
2:0]
0 (0x0)
No delay
1 (0x1)
1.3 ns for 100 MHz fPD
2 (0x2)
1 ns for 100 MHz fPD
3 (0x3)
0.9 ns for 100 MHz fPD
4 (0x4)
1.3 ns for 50 MHz fPD
5 (0x5)
1 ns for 50 MHz fPD
6 (0x6)
0.9 ns for 50 MHz fPD
7 (0x7)
0.7 ns for 50 MHz fPD
[3]
RESERVED
-
-
N
Reserved.
[2]
PLL_ENABLE_C3
RW
0
Y
Disable third order capacitor in the low pass filter.
[1:0]
RESERVED
-
0x3
Y
PLL_ENABLE_C3
MODE
0
2nd order loop filter
recommended setting
1
Enables C3, 3rd order loop
filter enabled
Reserved.
8.6.1.25 PLL_LF_R2 Register; R36
The PLL_LF_R2 register controls the value of the PLL Loop Filter R2.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_LF_R2[7:0]
RW
0x08
Y
PLL Loop Filter R2. NOTE: Table below lists commonly
used R2 values but more selections are available.
PLL_LF_R2[7:0]
R2 (Ω)
1 (0x01)
200
4 (0x04)
500
8 (0x08)
700
32 (0x20)
1600
48 (0x30)
2400
64 (0x40)
3200
8.6.1.26 PLL_LF_C1 Register; R37
The PLL_LF_C1 register controls the value of the PLL Loop Filter C1.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:3]
RESERVED
-
-
N
Reserved.
[2:0]
PLL_LF_C1[2:0]
RW
0x0
Y
PLL Loop Filter C1. The value in pF is given by 5 + 50 *
PLL_LF_C1 (in decimal).
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
35
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
8.6.1.27 PLL_LF_R3 Register; R38
The PLL_LF_R3 register controls the value of the PLL Loop Filter R3.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
-
N
Reserved.
[6:0]
PLL_LF_R3[6:0]
RW
0x00
Y
PLL Loop Filter R3. NOTE: Table below lists commonly
used R3 values but more selections are available.
PLL_LF_R3[6:0]
R3 (Ω)
0 (0x00)
18
3 (0x03)
205
8 (0x08)
854
9 (0x09)
1136
12 (0x0C)
1535
17 (0x11)
1936
20 (0x14)
2335
8.6.1.28 PLL_LF_C3 Register; R39
The PLL_LF_C3 register controls the value of the PLL Loop Filter C3.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:3]
RESERVED
-
-
N
Reserved.
[2:0]
PLL_LF_C3[2:0]
RW
0x0
Y
PLL Loop Filter C3. The value in pF is given by 5 *
PLL_LF_C3 (in decimal).
8.6.1.29 PLL_CALCTRL Register; R42
The PLL_CALCTRL register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:4]
RESERVED
-
-
N
Reserved.
[3:2]
PLL_CLSDWAIT[1:0]
RW
0x2
Y
Closed Loop Wait Period. The CLSDWAIT field sets the
closed loop wait period. Recommended value is 0x2.
[1:0]
PLL_VCOWAIT[1:0]
RW
0x1
Y
CLSDWAIT
Anlog closed loop VCO
stabilization time
0 (0x0)
150 µs
1 (0x1)
300 µs
2 (0x2)
500 µs
3 (0x3)
2000 µs
VCO Wait Period. Recommended value is 0x1.
VCOWAIT
VCO stabilization time
0 (0x0)
20 µs
1 (0x1)
400 µs
2 (0x2)
4000 µs
3 (0x3)
10000 µs
8.6.1.30 NVMSCRC Register; R47
The NVMSCRC register holds the Stored CRC (Cyclic Redundancy Check) byte that has been retreived from onchip EEPROM.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
NVMSCRC[7:0]
R
0x00
Y
EEPROM Stored CRC.
36
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
8.6.1.31 NVMCNT Register; R48
The NVMCNT register is intended to reflect the number of on-chip EEPROM Erase/Program cycles that have
taken place in EEPROM. The count is automatically incremented by hardware and stored in EEPROM.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
NVMCNT[7:0]
R
0x00
Y
EEPROM Program Count. The NVMCNT increments
automatically after every EEPROM Erase/Program Cycle.
The NVMCNT value is retreived automatically after reset,
after a EEPROM Commit operation or after a Erase/Program
cycle. The NVMCNT register will increment until it reaches its
maximum value of 255 after which no further increments will
take place.
8.6.1.32 NVMCTL Register; R49
The NVMCTL register allows control of the on-chip EEPROM Memories.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
-
N
Reserved.
[6]
REGCOMMIT
RWSC
0
N
REG Commit to EEPROM SRAM Array. The REGCOMMIT bit
is used to initiate a transfer from the on-chip registers back to
the corresponding location in the EEPROM SRAM Array. The
REGCOMMIT bit is automatically cleared to 0 when the
transfer is complete.
[5]
NVMCRCERR
R
0
N
EEPROM CRC Error Indication. The NVMCRCERR bit is set
to 1 if a CRC Error has been detected when reading back from
on-chip EEPROM during device configuration.
[4]
NVMAUTOCRC
RW
1
N
EEPROM Automatic CRC. When NVMAUTOCRC is 1 then
the EEPROM Stored CRC byte is automatically calculated
whenever a EEPROM program takes place.
[3]
NVMCOMMIT
RWSC
0
N
EEPROM Commit to Registers. The NVMCOMMIT bit is used
to initiate a transfer of the on-chip EEPROM contents to
internal registers. The transfer happens automatically after
reset or when NVMCOMMIT is set to 1. The NVMCOMMIT bit
is automatically cleared to 0. The I2C registers cannot be read
while a EEPROM Commit operation is taking place.
[2]
NVMBUSY
R
0
N
EEPROM Program Busy Indication. The NVMBUSY bit is 1
during an on-chip EEPROM Erase/Program cycle. While
NVMBUSY is 1 the on-chip EEPROM cannot be accessed.
[1]
NVMERASE
RWSC
0
N
EEPROM Erase Start. The NVMERASE bit is used to begin
an on-chip EEPROM Erase cycle. The Erase cycle is only
initiated if the immediately preceding I2C transaction was a
write to the NVMUNLK register with the appropriate code. The
NVMERASE bit is automatically cleared to 0. The EEPROM
Erase operation takes around 115ms.
[0]
NVMPROG
RWSC
0
N
EEPROM Program Start. The NVMPROG bit is used to begin
an on-chip EEPROM Program cycle. The Program cycle is
only initiated if the immediately preceding I2C transaction was
a write to the NVMUNLK register with the appropriate code.
The NVMPROG bit is automatically cleared to 0. If the
NVMERASE and NVMPROG bits are set simultaneously then
an ERASE/PROGRAM cycle will be executed The EEPROM
Program operation takes around 115ms.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
37
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
8.6.1.33 MEMADR Register; R51
The MEMADR register holds 7-bits of the starting address for on-chip SRAM or EEPROM access.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
-
N
Reserved.
[6:0]
MEMADR[6:0]
RW
0x00
N
Memory Address. The MEMADR value determines the starting
address for on-chip SRAM read/write access or on-chip
EEPROM access. The internal address to access SRAM or
EEPROM is automatically incremented; however the MEMADR
register does not reflect the internal address in this way. When
the SRAM or EEPROM arrays are accessed using the I2C
interface only bits [4:0] of MEMADR are used to form the byte
Wise address.
8.6.1.34 NVMDAT Register; R52
The NVMDAT register returns the on-chip EEPROM contents from the starting address specified by the
MEMADR register.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
NVMDAT[7:0]
R
0x00
N
EEPROM Read Data. The first time an I2C read transaction
accesses the NVMDAT register address, either because it was
explicitly targeted or because the address was autoincremented, the read transaction will return the EEPROM
data located at the address specified by the MEMADR
register. Any additional read's which are part of the same
transaction will cause the EEPROM address to be
incremented and the next EEPROM data byte will be returned.
The I2C address will no longer be auto-incremented, i.e the
I2C address will be locked to the NVMDAT register after the
first access. Access to the NVMDAT register will terminate at
the end of the current I2C transaction.
8.6.1.35 RAMDAT Register; R53
The RAMDAT register provides read and write access to the SRAM that forms part of the on-chip EEPROM
module.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
RAMDAT[7:0]
RW
0x00
N
RAM Read/Write Data. The first time an I2C read or write
transaction accesses the RAMDAT register address, either
because it was explicitly targeted or because the address was
auto-incremented, a read transaction will return the RAM data
located at the address specified by the MEMADR register and
a write transaction will cause the current I2C data to be written
to the address specified by the MEMADR register. Any
additional accesses which are part of the same transaction will
cause the RAM address to be incremented and a read or write
access will take place to the next SRAM address. The I2C
address will no longer be auto-incremented, i.e the I2C
address will be locked to the RAMDAT register after the first
access. Access to the RAMDAT register will terminate at the
end of the current I2C transaction.
38
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
8.6.1.36 NVMUNLK Register; R56
The NVMUNLK register provides a rudimentary level of protection to prevent inadvertent programming of the onchip EEPROM.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
NVMUNLK[7:0]
RW
0x00
N
EEPROM Prog Unlock. The NVMUNLK register must be
written immediately prior to setting the NVMPROG bit of
register NVMCTL, otherwise the Erase/Program cycle will not
be triggered. NVMUNLK must be written with a value of 0xBE.
8.6.1.37 INT_LIVE Register; R66
The INT_LIVE register reflects the current status of the interrupt sources.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:2]
RESERVED
-
-
N
Reserved.
[1]
LOL
R
0
N
Loss of Lock PLL.
[0]
CAL
R
0
N
Calibration Active PLL.
8.6.1.38 SWRST Register; R72
The SWRST1 register provides software reset control for specific on-chip modules. Each bit in this register is
individually self cleared after a write operation. The SWRST1 register will always return 0x00 in a read
transaction.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:2]
RESERVED
-
-
N
Reserved.
[1]
SWR2PLL
RWSC
0
N
Software Reset PLL. Setting SWR2PLL to 1 resets the PLL
calibrator and clock dividers. This bit is automatically cleared to
0.
[0]
RESERVED
-
-
N
Reserved.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
39
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMK61E07 features fine and coarse frequency margining capabilities which allow it to be used in
applications requiring the output frequency to be adjusted on the fly. In fractional PLL mode, the numerator of the
PLL fractional feedback divider can be updated over I2C to update the output frequency without glitches or
spikes, allowing the device to be used as a DCXO. The output frequency step size for every bit change in the
numerator of the PLL fractional feedback divider is given in Configuring the PLL. The Application Curves section
below illustrates the glitch-less switch in output frequency when the numerator is updated. The frequency
margining features can also aid the hardware designer during the system debug and validation phase.
9.2 Typical Application
3.3 V
3.3 V 3.3 V
VDD
4.7 kŸ
4.7 kŸ
SDA
OUTP
CMOS Clock
(DC Coupled)
SCL
OUTN
CMOS Clock
(AC Coupled)
To/From CPU
GND
Figure 33. LMK61E07 Typical Application
9.2.1 Design Requirements
Consider a typical digital subscriber line (DSL) application, in which a local modem must track the clock signal of
a network modem to ensure accurate and efficient data transfer. In such systems, a DCXO is implemented to
allow a local processor to digitally control the oscillator frequency to maintain synchronization. An example of
such a clock frequency would be 70.656 MHz.
The typical schematic above shows the I2C connection to the processor and output configurations for LVPECL
AC coupling..
The Detailed Design Procedure below describes the procedure to generate and adjust the required output
frequency for the above scenario using LMK61E07.
9.2.2 Detailed Design Procedure
This design procedure will give a quick outline of the process of configuring the LMK61E07 in the above use
case. Typically, the easiest approach to configuring the PLL is to start with the desired output frequency and
work backwards.
1. VCO Frequency Selection
– The first step is to calculate the possible VCO frequencies given the required output frequency of 70.656
MHz. The LMK61E07 output divider that can be set from /5 to /511. The VCO can output frequencies
from 4.6 GHz to 5.6 GHz. Therefore, the output frequency multiplied by the total divide value must fall
within this range.
– To determine the boundary of the total divide value, we can divide the VCO frequency limits by the output
frequency, resulting in a range of 65.1 to 79.3. Any output divider value within this range will result in a
40
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
Typical Application (continued)
valid VCO frequency. A few possible divider combinations and the resulting VCO frequencies are listed in
columns 1 and 2, respectively, of Table 3 below.
2. Input Divider and Doubler/Phase Detector Frequency Configuration
– The next step is to set the reference divider and doubler in the reference frequency path to the PLL. The
reference divider can be set to /1 or /4, and the doubler can be set to x1 or x2. The main trade-off is that
a higher phase detector frequency will result in better output phase noise performance and a lower phase
detector frequency will result in a finer output frequency step size when adjusting the feedback divider
numerator in DCXO mode.
– In the DSL application, a finer step size is desired so the reference divider will be set to /4 and the
doubler to x1 to minimize the phase detector frequency. The phase detector frequency can then be
calculated by multiplying and dividing the reference frequency of 50 MHz by those values, resulting in
12.5 MHz.
– Note that in some applications, a trade-off in step size to obtain better phase noise performance is
acceptable. In that case the design procedure can be continued, substituting the relevant reference
divider and doubler configuration and phase detector frequency.
3. Feedback Divider Selection
– The possible feedback divider values can then be calculated by dividing the VCO frequency by the phase
detector frequency. The possible values are listed in column 3 of Table 3.
– Glitch-less frequency margining in DCXO mode is achieved by adjusting the numerator of the feedback
divider without changing the integer value of the divider, which could cause a frequency glitch. Therefore,
the output frequency tuning range is limited by which VCO frequency and feedback divider we select out
of the valid combinations. To obtain as equal of a tuning range above and below the nominal output
frequency as possible, a feedback divider value with fractional portion as close to 1/2 as possible should
be chosen.
– The VCO frequency of 5369.856 MHz results in a feedback divider of 429.58848, which has a fractional
portion closest to 1/2. The decimal converted to a fraction is 429+58848/100000. To minimize step size,
the fraction can be converted to the maximum equivalent fraction of 2412768/4100000 as limited by the
maximum denominator of 4194303.
4. Frequency Margining
– With the device configured to output the nominal frequency of 70.656 MHz, the numerator can be
adjusted over I2C to tune the output frequency.
– Using equation 3 in Configuring the PLL, the step size of this configuration can be calculated to be
approximately 4x10–8 MHz or 0.58 ppb.
– The maximum and minimum tuning range limits can be determined by calculating the maximum shift in
frequency from nominal without changing the integer portion of the feedback divider (including setting the
numerator to zero or equal to the denominator). In this case, the limits are a maximum of +955 ppm and a
minimum of –1365 ppm from nominal.
Table 3. PLL Configuration Options
1. EXAMPLE OUTPUT DIVIDER
VALUES
2. POSSIBLE VCO
FREQUENCIES (MHz)
3. FEEDBACK DIVIDER WITH
PDF=12.5 MHz
4. EQUIVALENT FRACTIONAL
FEEDBACK DIVIDER VALUES
68
4804.608
384.36864
384+1511424/4100000
70
4945.92
395.6736
395+2822384/4190000
72
5087.232
406.97856
406+4012096/4100000
75
5299.2
423.936
423+3925584/4194000
76
5369.856
429.58848
429+2412768/4100000
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
41
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
9.2.2.1 PLL Loop Filter Design
The EVM software tool TICS Pro/Oscillator Programming Tool can be used to aid loop filter design. The Easy
Configuration GUI is able to generate a suggested set of loop filter values given a desired output frequency. The
tool recommends a PLL configuration that is designed to minimize jitter. As of the publication of this document, it
is not yet able to optimize for desired tuning range in DCXO mode. When configuring the device for operation in
DCXO mode, TI recommends using the software suggested loop filter settings as a starting point and then
perform the procedure described in Detailed Design Procedure to optimize the PLL configuration to suit the
application needs.
A general set of loop filter design guidelines are given below:
• There are many device configurations to achieve the desired output frequency from a device. However there
are some optimizations and trade-offs to be considered.
• The guidelines below may be followed when configuring PLL related dividers or other related registers:
– For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide value.
– For fractional divider values, keep the denominator at highest value possible to minimize spurs. It is also
best to use a higher order modulator whenever possible for the same reason.
– As a rule of thumb, keep the phase detector frequency approximately between 10 × PLL loop bandwidth
and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth may be
unstable.
– While designing the loop filter, adjusting the charge pump current or N value can help with loop filter
component selection. Lower charge pump currents and larger N values result in smaller component values
but may increase impacts of leakage and reduce PLL phase noise performance.
– A more detailed understanding of loop filter design can be found in Dean Banerjee's PLL Performance,
Simulation, and Design.
9.2.2.2 Spur Mitigation Techniques
The LMK61E07 offers several programmable features for optimizing fractional spurs. To get the best out of these
features, it makes sense to understand the different kinds of spurs as well as their behaviors, causes, and
remedies. Although optimizing spurs may involve some trial and error, there are ways to make this process more
systematic. TI offers the Clock Design Tool (SNAU082) for more information and estimation of fractional spurs.
9.2.2.2.1 Phase Detection Spur
The phase detector spur occurs at an offset from the carrier equal to the phase detector frequency, fPD. To
minimize this spur, consider a lower phase detector frequency. In some cases where the loop bandwidth is very
wide relative to the phase detector frequency, some benefit might be gained from using a narrower loop
bandwidth or adding poles to the loop filter by using R3 and C3 if previously unused, but otherwise the loop filter
has minimal impact. Bypassing at the supply pins and board layout can also have an impact on this spur,
especially at higher phase detector frequencies.
9.2.2.2.2 Integer Boundary Fractional Spur
This spur occurs at an offset equal to the difference between the VCO frequency and the closest integer channel
for the VCO. For instance, if the phase detector frequency is 100 MHz and the VCO frequency is 5003 MHz,
then the integer boundary spur would be at 3-MHz offset. This spur can be either PLL or VCO dominated. If it is
PLL dominated, decreasing the loop bandwidth and some of the programmable fractional words may impact this
spur. If the spur is VCO dominated, then reducing the loop filter will not help, but rather reducing the phase
detector and having good slew rate and signal integrity at the selected reference input will help.
9.2.2.2.3 Primary Fractional Spur
These spurs occur at multiples of fPD/DEN and are not the integer boundary spur. For instance, if the phase
detector frequency is 100 MHz and the fraction is 3/100, the primary fractional spurs would be at 1 MHz, 2 MHz,
4 MHz, 5 MHz, 6 MHz, and so forth. These are impacted by the loop filter bandwidth and modulator order. If a
small frequency error is acceptable, then a larger equivalent fraction may improve these spurs. This larger
unequivalent fraction pushes the fractional spur energy to much lower frequencies that where they are not
impactful to the system performance.
42
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
9.2.2.2.4 Sub-Fractional Spur
These spurs appear at a fraction of fPD/DEN and depend on modulator order. With the first order modulator, there
are no sub-fractional spurs. The second order modulator can produce 1/2 sub-fractional spurs if the denominator
is even. A third order modulator can produce sub-fractional spurs at 1/2, 1/3, or 1/6 of the offset, depending if it is
divisible by 2 or 3. For instance, if the phase detector frequency is 100 MHz and the fraction is 3/100, no subfractional spurs for a first order modulator or sub-fractional spurs at multiples of 1.5 MHz for a second or third
order modulator would be expected. Aside from strategically choosing the fractional denominator and using a
lower order modulator, another tactic to eliminate these spurs is to use dithering and express the fraction in
larger equivalent terms. Because dithering also adds phase noise, its level needs to be managed to achieve
acceptable phase noise and spurious performance.
Table 4 summarizes spur and mitigation techniques.
Table 4. Spur and Mitigation Techniques
SPUR TYPE
OFFSET
WAYS TO REDUCE
TRADE-OFFS
Phase Detector
fPD
Reduce Phase Detector
Frequency.
Although reducing the phase
detector frequency does improve
this spur, it also degrades phase
noise.
Integer Boundary
fVCO mod fPD
Methods for PLL Dominated
Spurs
-
Avoid the worst case VCO
frequencies if possible.
- Ensure good slew rate and
signal integrity at reference input.
Reducing the loop bandwidth
may degrade the total integrated
noise if the bandwidth is too
narrow.
- Reduce loop bandwidth or
add more filter poles to suppress
out of band spurs.
Methods for VCO Dominated
Spurs
-
Avoid the worst case VCO
frequencies if possible.
-
Reduce Phase Detector
Frequency.
Reducing the phase detector
may degrade the phase noise.
- Ensure good slew rate and
signal integrity at reference input.
Primary Fractional
Sub-Fractional
fPD/DEN
-
Decrease Loop Bandwidth.
-
Change Modulator Order.
-
Use Larger Unequivalent
Fractions.
fPD/DEN/k k=2,3, or 6
-
-
Decreasing the loop bandwidth
may degrade in-band phase
noise. Also, larger unequivalent
fractions don’t always reduce
spurs.
Use Dithering.
Use Larger Equivalent
Fractions.
-
Use Larger Unequivalent
Fractions.
-
Reduce Modulator Order.
Dithering and larger fractions
may increase phase noise.
Eliminate factors of 2 or 3 in
denominator.
9.2.2.3 Device Programming
The EVM software tool TICS Pro/Oscillator Programming Tool can be used to program the device with the
desired configuration. Simply select the Program EEPROM option and the software will automatically load the
current configuration to EEPROM. The settings will then be available upon subsequent startup without the need
to reload the registers over I2C.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
43
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
9.2.3 Application Curves
Figure 34. Increasing Output Frequency in DCXO Mode
Figure 35. Decreasing Output Frequency in DCXO Mode
10 Power Supply Recommendations
For best electrical performance of the LMK61E07 device, TI recommends using a combination of 10 µF, 1 µF,
and 0.1 µF on its power supply bypass network. TI also recommends using component side mounting of the
power supply bypass capacitors, and it is best to use 0201 or 0402 body size capacitors to facilitate signal
routing. Keep the connections between the bypass capacitors and the power supply on the device as short as
possible. Ground the other side of the capacitor using a low impedance connection to the ground plane.
Figure 36 shows the layout recommendation for power supply decoupling of LMK61E0.
11 Layout
11.1 Layout Guidelines
Ensured Thermal Reliability, Best Practices for Signal Integrity and Recommended Solder Reflow Profile provide
recommendations for board layout, solder reflow profile and power supply bypassing when using LMK61E07 to
ensure good thermal and electrical performance and overall signal integrity of entire system.
11.1.1 Ensured Thermal Reliability
The LMK61E07 is a high performance device. Therefore pay careful attention to device configuration and
printed-circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to
the ground plane of the PCB through three vias or more, as shown in Figure 36, to maximize thermal dissipation
out of the package.
Equation 4 describes the relationship between the PCB temperature around the LMK61E07 and its junction
temperature.
TB = TJ – ΨJB * P
where
•
•
•
•
TB: PCB temperature around the LMK61E07
TJ: Junction temperature of LMK61E07
ΨJB: Junction-to-board thermal resistance parameter of LMK61E07 (36.7°C/W without airflow)
P: On-chip power dissipation of LMK61E07
(4)
To ensure that the maximum junction temperature of LMK61E07 is below 115°C, it can be calculated that the
maximum PCB temperature without airflow should be at 90°C or below when the device is optimized for best
performance resulting in maximum on-chip power dissipation of 0.69 W.
11.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK61E07, TI recommends routing vias
into decoupling capacitors and then into the LMK61E07. TI also recommends increasing the via count and width
of the traces wherever possible. These steps ensure lowest impedance and shortest path for high-frequency
current flow. Figure 36 shows the layout recommendation for LMK61E07.
44
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
LMK61E07
www.ti.com
SNAS722 – DECEMBER 2017
Layout Guidelines (continued)
11.1.3 Recommended Solder Reflow Profile
TI also recommends following the solder paste supplier's recommendations to optimize flux activity and to
achieve proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferable for the
LMK61E07 to be processed with the lowest peak temperature possible while also remaining below the
components peak temperature rating as listed on the MSL label. The exact temperature profile would depend on
several factors including maximum peak temperature for the component as rated on the MSL label, Board
thickness, PCB material type, PCB geometries, component locations, sizes, densities within PCB, as well solder
manufactures recommended profile, and capability of the reflow equipment to as confirmed by the SMT
assembly operation.
11.2 Layout Example
Figure 36. LMK61E07 Layout Recommendation for Power Supply and Ground
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
45
LMK61E07
SNAS722 – DECEMBER 2017
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Clock Design Tool (SNAU082)
• PLL Performance, Simulation, and Design
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
46
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E07
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMK61E07-SIAR
ACTIVE
QFM
SIA
6
2500
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
7
LMK61E07-SIAT
ACTIVE
QFM
SIA
6
250
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
7
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMK61E07-SIAR
QFM
SIA
6
2500
330.0
16.4
5.5
7.5
1.5
8.0
16.0
Q1
LMK61E07-SIAT
QFM
SIA
6
250
178.0
16.4
5.5
7.5
1.5
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMK61E07-SIAR
QFM
SIA
6
2500
367.0
367.0
38.0
LMK61E07-SIAT
QFM
SIA
6
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
Similar pages