IDT IDT74LVC273APYG 3.3v cmos octal d-type flip-flop with reset, positive edge trigger,and 5 volt tolerant i/o Datasheet

IDT74LVC273A
3.3V CMOS OCTAL D-TYPE FLIP-FLOP WITH RESET
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS OCTAL D-TYPE
FLIP-FLOP WITH RESET,
POSITIVE EDGE TRIGGER,
AND 5 VOLT TOLERANT I/O
IDT74LVC273A
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
μ W typ. static)
• CMOS power levels (0.4μ
• Rail-to-rail output swing for increased noise margin
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
The octal D-type flip-flop with reset, positive edge trigger is built using
advanced dual metal CMOS technology. This high-speed, low power
device is ideal for driving high capacitance loads such as memory address
and data buses.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of these devices as translators in a mixed 3.3V/5V supply system.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
Dx
Q
D
CP
Ox
CP
CLR
CLR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2006
1
© 2006 Integrated Device Technology, Inc.
DSC-4595/4
IDT74LVC273A
3.3V CMOS OCTAL D-TYPE FLIP-FLOP WITH RESET
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
Continuous Clamp Current,
VI < 0 or VO < 0
–50
mA
Continuous Current through each
VCC or GND
±100
mA
CLR
1
20
VCC
O0
2
19
O7
D0
3
18
D7
IIK
IOK
D1
4
17
D6
ICC
ISS
O1
5
16
O6
O2
6
15
O5
D2
7
14
D5
D3
8
13
D4
O3
9
12
O4
10
11
CP
GND
Unit
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
SSOP/ TSSOP
TOP VIEW
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
Description
CLR
CP
Ox
Clear Input
Clock Input
Data Outputs
Dx
Data Inputs
FUNCTION TABLE (1)
Inputs
Internal
Outputs
CLR
CP
Dx
Q Value
Ox
Function
L
X
X
L
L
Clear Register
H
↑
L
L
L
Load Input Data
H
↑
H
H
H
Load Input Data
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
2
IDT74LVC273A
3.3V CMOS OCTAL D-TYPE FLIP-FLOP WITH RESET
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
µA
IOZL
(3-State Output pins)
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
±50
µA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
ΔICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
—
—
10
mV
µA
3.6 ≤ VIN ≤ 5.5V(2)
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
—
—
10
500
µA
IIH
IIL
Quiescent Power Supply Current
Variation
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Test Conditions(1)
Parameter
Output HIGH Voltage
Output LOW Voltage
Max.
Unit
VCC – 0.2
—
V
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
IOH = – 6mA
2
—
VCC = 2.3V
IOH = – 12mA
1.7
—
VCC = 2.7V
2.2
—
VCC = 3V
2.4
—
2.2
—
VCC = 3V
VOL
Min.
IOH = – 24mA
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 12mA
—
0.7
VCC = 2.7V
IOL = 12mA
—
0.4
VCC = 3V
IOL = 24mA
—
0.55
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74LVC273A
3.3V CMOS OCTAL D-TYPE FLIP-FLOP WITH RESET
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance per Transceiver Outputs enabled
CPD
Power Dissipation Capacitance per Transceiver Outputs disabled
Test Conditions
Typical
Unit
CL = 0pF, f = 10Mhz
—
—
pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V
Symbol
VCC = 3.3V ± 0.3V
Parameter
Min.
tPLH
Propagation Delay, CP to Ox
1.5
9.5
1.5
8.5
ns
tPHL
Propagation Delay, CLR to Ox
1.5
9.5
1.5
8.5
ns
tS
Data Setup Time, Dx to CP
2.5
2.5
Data Hold Time, Dx to CP
1.5
3.3
—
—
—
—
—
ns
tH
—
—
—
—
—
—
—
500
ps
tREC
CLR Recovery Time, CLR to CP
tWCLR
CLR Pulse Width, LOW
3.3
tWCP
CLK Pulse Width, HIGH or LOW
3.3
tSK(o)
Output Skew(2)
—
2
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
Max.
Min.
1.5
2
3.3
Max.
Unit
ns
ns
ns
ns
IDT74LVC273A
3.3V CMOS OCTAL D-TYPE FLIP-FLOP WITH RESET
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
tPLH
tPHL
tPLH
tPHL
OUTPUT
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
LVC Link
Propagation Delay
VLOAD
VCC
VIN
Pulse (1, 2)
Generator
tPZL
VOUT
D.U.T.
OUTPUT
SWITCH
NORMALLY
VLOAD
LOW
tPZH
OUTPUT SWITCH
NORMALLY
GND
HIGH
500Ω
RT
VIH
VT
0V
CONTROL
INPUT
GND
500Ω
DISABLE
ENABLE
Open
CL
LVC Link
Test Circuit for All Outputs
tPLZ
VLOAD/2
VT
VLOAD/2
VOL+VLZ
VOL
tPHZ
VOH
VOH-VHZ
0V
VT
0V
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Switch
DATA
INPUT
VLOAD
TIMING
INPUT
Disable High
Enable High
GND
ASYNCHRONOUS
CONTROL
All Other Tests
Open
SYNCHRONOUS
CONTROL
Test
Open Drain
Disable Low
Enable Low
INPUT
OUTPUT 1
tPLH1
VIH
VT
0V
tPHL1
tSK (x)
tSK (x)
tPLH2
tREM
tSU
tH
Set-up, Hold, and Release Times
VOH
VT
VOL
LOW-HIGH-LOW
PULSE
VT
tW
HIGH-LOW-HIGH
PULSE
tPHL2
VT
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
tH
LVC Link
VOH
VT
VOL
OUTPUT 2
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
LVC Link
IDT74LVC273A
3.3V CMOS OCTAL D-TYPE FLIP-FLOP WITH RESET
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
LVC
X
IDT
XX
Bus-Hold
Temp. Range
XX
XXXX
Device Type Package
PY
PYG
PG
PGG
Shrink Small Outline Package
SSOP - Green
Thin Shrink Small Outline Package
TSSOP - Green
273A
Octal D-Type Flip-Flop with Reset, Positive
Edge Trigger, 5V Tolerant I/O
Blank No Bus-hold
74
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6
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