AD AD7492ARUZ-5-REEL71 1.25 msps, 16 mw internal ref and clk, 12-bit parallel adc Datasheet

1.25 MSPS, 16 mW Internal REF and CLK,
12-Bit Parallel ADC
AD7492
FUNCTIONAL BLOCK DIAGRAM
Specified for VDD of 2.7 V to 5.25 V
Throughput rate of 1 MSPS (AD7492)
Throughput rate of 1.25 MSPS (AD7492-5)
Throughput rate of 400 kSPS (AD7492-4)
Low power
4 mW typ at 1 MSPS with 3 V supplies
11 mW typ at 1 MSPS with 5 V supplies
Wide input bandwidth
70 dB typ SNR at 100 kHz input frequency
2.5 V internal reference
On-chip CLK oscillator
Flexible power/throughput rate management
No pipeline delays
High speed parallel interface
Sleep mode: 50 nA typ
24-lead SOIC and TSSOP packages
AVDD
DVDD
REF OUT
4
20
5
2.5V
REF
T/H
21
CLOCK
OSCILLATOR
BUF
VIN 6
VDRIVE
CONTROL
LOGIC
CONVST 10
DB11
OUTPUT
DRIVERS
12-BIT SAR
ADC
DB0
11
PS/FS
8
CS
9
RD
AD7492
12
7
19
AGND
DGND
BUSY
01128-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The AD7492, AD7492-4, and AD7492-5 are 12-bit high speed,
low power, successive approximation ADCs. The parts operate
from a single 2.7 V to 5.25 V power supply and feature
throughput rates up to 1.25 MSPS. They contain a low noise,
wide bandwidth track/hold amplifier that can handle
bandwidths up to 10 MHz.
The conversion process and data acquisition are controlled
using standard control inputs allowing for easy interface to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CONVST and conversion is also initiated at this
point. The BUSY pin goes high at the start of conversion and
goes low 880 ns (AD7492/AD7492-4) or 680 ns (AD7492-5)
later to indicate that the conversion is complete. There are no
pipeline delays associated with the part. The conversion result is
accessed via standard CS and RD signals over a high speed
parallel interface.
The AD7492 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and 1.25 MSPS, the average current consumption
AD7492-5 is typically 2.75 mA. The part also offers flexible
power/throughput rate management.
It is also possible to operate the part in a full sleep mode and a
partial sleep mode, where the part wakes up to do a conversion
and automatically enters a sleep mode at the end of conversion.
The type of sleep mode is hardware selected by the PS/FS pin.
Using these sleep modes allows very low power dissipation
numbers at lower throughput rates.
The analog input range for the part is 0 V to REFIN. The
2.5 V reference is supplied internally and is available for
external referencing. The conversion rate is determined by the
internal clock.
PRODUCT HIGHLIGHTS
1.
High Throughput with Low Power Consumption. The
AD7492-5 offers 1.25 MSPS throughput with 16 mW
power consumption.
2.
Flexible Power/Throughput Rate Management. The
conversion time is determined by an internal clock. The
part also features two sleep modes, partial and full, to
maximize power efficiency at lower throughput rates.
3.
No Pipeline Delay. The part features a standard successive
approximation ADC with accurate control of the sampling
instant via a CONVST input and once-off conversion
control.
4.
Flexible Digital Interface. The VDRIVE feature controls the
voltage levels on the I/O digital pins.
5.
Fewer Peripheral Components. The AD7492 optimizes
PCB space by using an internal reference and internal CLK.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD7492
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Operation.................................................................. 13
Functional Block Diagram .............................................................. 1
Typical Connection Diagram ................................................... 13
General Description ......................................................................... 1
ADC Transfer Function............................................................. 13
Product Highlights ....................................................................... 1
AC Acquisition Time ................................................................. 14
Revision History ........................................................................... 2
DC Acquisition Time................................................................. 14
Specifications..................................................................................... 3
Analog Input ............................................................................... 14
AD7492-5 ...................................................................................... 3
Parallel Interface......................................................................... 14
AD7492/AD7492-4 ...................................................................... 4
Operating Modes........................................................................ 14
Timing Specifications .................................................................. 6
Power-Up..................................................................................... 16
Absolute Maximum Ratings............................................................ 7
Grounding and Layout .............................................................. 18
ESD Caution.................................................................................. 7
Power Supplies ............................................................................ 18
Pin Configuration and Function Descriptions............................. 8
Microprocessor Interfacing....................................................... 18
Typical Peformance Characteristics ............................................. 10
Outline Dimensions ....................................................................... 21
Terminology .................................................................................... 12
Ordering Guide .......................................................................... 21
Circuit Description......................................................................... 13
REVISION HISTORY
5/06—Rev. 0 to Rev. A
Added AD7492-4................................................................Universal
Changes to Table 4............................................................................ 8
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
1/01—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD7492
SPECIFICATIONS
AD7492-5
VDD = 4.75 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious-Free
Dynamic Noise (SFDR)
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE OUTPUT
REF OUT Output Voltage Range
LOGIC INPUTS
Input High Voltage, VINH 2
Input Low Voltage, VINL2
Input Current, IIN
Input Capacitance, CIN 3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
A Version 1
B Version1
Unit
69
68
70
68
−83
−87
−75
−83
69
68
70
68
−83
−87
−75
−83
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
Test Conditions/Comments
fS = 1.25 MSPS
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave
−90
−76
−90
−76
dB typ
dB max
fIN = 100 kHz sine wave
fIN = 100 kHz sine wave
−82
−90
−71
−88
5
15
10
−82
−90
−71
−88
5
15
10
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
12
±1.5
+1.5/–0.9
12
±1.25
+1.5/−0.9
Bits
LSB max
LSB max
±9
±2.5
±9
±2.5
LSB max
LSB max
0 to 2.5
±1
33
0 to 2.5
±1
33
V
μA max
pF typ
2.5
2.5
V
±1.5% for specified performance
VDRIVE × 0.7
VDRIVE × 0.3
±1
10
VDRIVE × 0.7
VDRIVE × 0.3
±1
10
V min
V max
μA max
pF max
VDD = 5 V ± 5%
VDD = 5 V ± 5%
Typically 10 nA, VIN = 0 V or VDD
VDRIVE − 0.2
0.4
±10
10
Straight (natural)
binary
VDRIVE − 0.2
0.4
±10
10
Straight (natural)
binary
V min
V max
μA max
pF max
ISOURCE = 200 μA
ISINK = 200 μA
fS = 1.25 MSPS
Rev. A | Page 3 of 24
Guaranteed no missed codes to
12 bits (A and B versions)
AD7492
Parameter
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
IDD
Normal Mode
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation 4
Normal Mode
Partial Sleep Mode
Full Sleep Mode
A Version 1
B Version1
Unit
680
120
1.25
680
120
1.25
ns max
ns min
MSPS max
4.75/5.25
4.75/5.25
V min/max
3.3
1.8
250
1
3.3
1.8
250
1
mA max
mA max
μA max
μA max
16.5
1.25
5
16.5
1.25
5
mW max
mW max
μW max
Test Conditions/Comments
Conversion time + acquisition
time
Digital I/Ps = 0 V or DVDD
fS = 1.25 MSPS, typ 2.75 mA
Static, typ 190 μA
Static, typ 200 nA
Digital I/Ps = 0 V or DVDD
1
Temperature ranges as follows: A and B Versions: −40°C to +85°C.
VINH and VINL trigger levels are set by the VDRIVE voltage. The logic interface circuitry is powered by VDRIVE.
Sample tested @ 25°C to ensure compliance.
4
See the Power vs. Throughput section.
2
3
AD7492/AD7492-4
VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted. 1
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious-Free
Dynamic Noise (SFDR)
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
A Version 2
B Version2
Unit
69
68
70
68
−85
−87
−75
−86
69
68
70
68
−85
−87
−75
−86
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
Test Conditions/Comments
fS = 1 MSPS for AD7492
fS = 400 kSPS for AD7492-4
fIN = 500 kHz sine wave 3
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave3
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave3
fIN = 100 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave3
−90
−76
−90
−76
dB typ
dB max
fIN = 100 kHz sine wave
fIN = 100 kHz sine wave
−77
−90
−69
−88
5
15
10
−77
−90
−69
−88
5
15
10
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
fIN = 500 kHz sine wave3
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave3
fIN = 100 kHz sine wave
Rev. A | Page 4 of 24
AD7492
Parameter
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE OUTPUT
REF OUT Output Voltage Range
LOGIC INPUTS
Input High Voltage, VINH 4
Input Low Voltage, VINL4
Input Current, IIN
Input Capacitance, CIN3, 5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
A Version 2
B Version2
Unit
12
±1.5
12
+1.5/−0.9
±0.6
±1
+1.5/−0.9
Bits
LSB max
LSB typ
LSB max
LSB max
±9
±2.5
±9
±2.5
LSB max
LSB max
0 to 2.5
±1
33
0 to 2.5
±1
33
V
μA max
pF typ
2.5
2.5
V
±1.5% for specified performance
VDRIVE × 0.7
VDRIVE × 0.3
±1
10
VDRIVE × 0.7
VDRIVE × 0.3
±1
10
V min
V max
μA max
pF max
VDD = 5 V ± 5%
VDD = 5 V ± 5%
Typically 10 nA, VIN = 0 V or VDD
VDRIVE − 0.2
0.4
±10
10
Straight (Natural)
Binary
VDRIVE − 0.2
0.4
±10
10
Straight (Natural)
Binary
V min
V max
μA max
pF max
ISOURCE = 200 μA
ISINK = 200 μA
880
120
1
880
120
1
ns max
ns min
MSPS max
kSPS max
400
POWER REQUIREMENTS
VDD
IDD
Normal Mode
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation4, 6
Normal Mode
Partial Sleep Mode
Full Sleep Mode
2.7/5.25
2.7/5.25
V min/max
3
3
mA max
1.8
250
1
1.8
250
1
mA max
μA max
μA max
15
1.25
5
15
1.25
5
mW max
mW max
μW max
1
Only A version specification applies to the AD7492-4.
Temperature ranges as follows: A and B versions: −40°C to +85°C.
3
500 kHz sine wave specifications do not apply for the AD7492-4.
4
VINH and VINL trigger levels are set by the VDRIVE voltage. The logic interface circuitry is powered by VDRIVE.
5
Sample tested @ 25°C to ensure compliance.
6
See the Power vs. Throughput section.
2
Rev. A | Page 5 of 24
Test Conditions/Comments
fS = 1 MSPS for AD7492
fS = 400 kSPS for AD7492-4
VDD = 5 V
VDD = 3 V
Guaranteed no missed codes to
12 bits (A and B versions)
Conversion time + acquisition
time for AD7492
Conversion time + acquisition
time for AD7492-4
Digital I/Ps = 0 V or DVDD.
fS = 1 MSPS, typ 2.2 mA
fS = 400 kSPS, Typ 2.2 mA
(AD7492-4)
Static, typ 190 μA
Static, typ 200 nA
Digital I/Ps = 0 V or DVDD
VDD = 5 V
VDD = 5 V
VDD = 5 V
AD7492
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted. 1
Table 3.
Parameter
tCONVERT
tWAKEUP
t1
t2
t3
t4 4
t5
t64
t7 5
t8
t9
t10
Limit at TMIN, TMAX
AD7492/AD7492-4
AD7492-5 2
880
680
20 3
203
500
500
10
10
10
10
40
N/A
0
0
0
0
20
20
15
15
8
8
0
0
120
120
100
100
Unit
ns max
μs max
μs max
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
Description
Partial Sleep Wake-Up Time
Full Sleep Wake-Up Time
CONVST Pulse Width
CONVST to BUSY Delay, VDD = 5 V
CONVST to BUSY Delay, VDD = 3 V
BUSY to CS Setup Time
CS to RD Setup Time
RD Pulse Width
Data Access Time after Falling Edge of RD
Bus Relinquish Time after Rising Edge of RD
CS to RD Hold Time
Acquisition Time
Quiet Time
1
Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2).
The AD7492-5 is specified with VDD = 4.75 V to 5.25 V.
This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 μs, but there is no guarantee that the part
samples within 0.5 LSB of the true analog input value. Therefore, the user should not start conversion until after the specified time.
4
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V
5
t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
2
3
200µA
1.6V
CL
50pF
200µA
IOH
01128-002
TO OUTPUT
PIN
IOL
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. A | Page 6 of 24
AD7492
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
AVDD to AGND/DGND
DVDD to AGND/DGND
VDRIVE to AGND/DGND
AVDD to DVDD
VDRIVE to DVDD
AGND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Input Current to Any Pin Except
Supplies1
Operating Temperature Range
Commercial (A and B Versions)
Storage Temperature Range
Junction Temperature
SOIC, TSSOP Package Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
1
Ratings
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
±10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +85°C
−65°C to +150°C
150°C
450 mW
75°C/W (SOIC)
115°C/W (TSSOP)
25°C/W (SOIC)
35°C/W (TSSOP)
215°C
220°C
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 24
AD7492
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DB9
1
24 DB8
DB10
2
23 DB7
(MSB) DB11
3
22 DB6
AVDD
4
21 V
DRIVE
REF OUT
5
VIN
6
AGND
7
CS
8
17 DB4
RD
9
16 DB3
CONVST 10
15 DB2
PS/FS 11
14 DB1
BUSY 12
13 DB0 (LSB)
AD7492
20 DV
DD
01128-003
TOP VIEW 19 DGND
(Not to Scale) 18 DB5
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin
1 to 3,
13 to 18,
22 to 24
4
Mnemonic
DB11 to DB0
5
6
REF OUT
VIN
7
AGND
8
CS
9
RD
10
CONVST
11
PS/FS
12
BUSY
19
DGND
AVDD
Function
Data Bit 11 to Data Bit 0. Parallel digital outputs that provide the conversion result for the part. These are
three-state outputs that are controlled by CS and RD. The output high voltage level for these outputs is
determined by the VDRIVE input.
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7492.
The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart,
even on a transient basis. This supply should be decoupled to AGND.
Reference Out. The output voltage from this pin is 2.5 V ± 1%.
Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents
a high dc input impedance.
Analog Ground. Ground reference point for all analog circuitry on the AD7492. All analog input signals
should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The
conversion result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both
connected to the same AND gate on the input so the signals are interchangeable. CS can be hardwired
permanently low.
Read Input. Logic input used in conjunction with CS to access the conversion result. The conversion result is
placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to the
same AND gate on the input so the signals are interchangeable. CS and RD can be hardwired permanently
low, in which case the data bus is always active and the result of the new conversion is clocked out slightly
before to the BUSY line going low.
Conversion Start Input. Logic input used to initiate conversion. The input track/hold amplifier goes from track
mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. The
conversion input can be as narrow as 10 ns. If the CONVST input is kept low for the duration of conversion
and is still low at the end of conversion, the part automatically enters a sleep mode. The type of sleep mode is
determined by the PS/FS pin. If the part enters a sleep mode, the next rising edge of CONVST wakes up the
part. Wake-up time depends on the type of sleep mode.
Partial Sleep/Full Sleep Mode. This pin determines the type of sleep mode the part enters if the CONVST pin is
kept low for the duration of the conversion and is still low at the end of conversion. In partial sleep mode the
internal reference circuit and oscillator circuit are not powered down and draws 250 μA maximum. In full
sleep mode all of the analog circuitry are powered down and the current drawn is negligible. This pin is
hardwired either high (DVDD) or low (GND).
BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal goes high after
the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is
complete and the conversion result is in the output register, the BUSY line returns low. The track/hold returns
to track mode just prior to the falling edge of BUSY and the acquisition time for the part begins when BUSY
goes low. If the CONVST input is still low when BUSY goes low, the part automatically enters its sleep mode
on the falling edge of BUSY.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7492. The DGND and AGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
Rev. A | Page 8 of 24
AD7492
Pin
20
Mnemonic
DVDD
21
VDRIVE
Function
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7492 apart
from the output drivers and input circuitry. The DVDD and AVDD voltages should ideally be at the same
potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled
to DGND.
Supply Voltage for the Output Drivers and Digital Input Circuitry, 2.7 V to 5.25 V. This voltage determines the
output high voltage for the data output pins and the trigger levels for the digital inputs. It allows the AVDD
and DVDD to operate at 5 V (and maximize the dynamic performance of the ADC) while the digital input and
output pins can interface to 3 V logic.
Rev. A | Page 9 of 24
AD7492
TYPICAL PEFORMANCE CHARACTERISTICS
71
0
70
–20
69
5V
–40
67
66
(dB)
SNR+D (dB)
68
3V
65
64
–60
–80
63
62
–100
61
500
1000
1500
2000
2500
INPUT FREQUENCY (kHz)
–120
0
100000
Figure 4. Typical SNR + D vs. Input Tone
500000
600000
Figure 7. Typical SNR @ 500 kHz Input Tone
95
0
90
–0.5
85
5V
5V
–1.0
80
–1.5
75
(dB)
THD (dB)
200000
300000
400000
FREQUENCY (Hz)
01128-007
0
01128-004
60
3V
70
–2.0
65
–2.5
60
–3.0
55
200
350
500
1000
2000
–3.5
INPUT FREQUENCY (kHz)
1
10
100
1000
10000
01128-008
100
01128-005
50
100000
FREQUENCY (Hz)
Figure 5. Typical THD vs. Input Tone
Figure 8. Typical Bandwidth
70.60
0
70.4
–40°C
–20
VCC = 5V
100mV p-p SINEWAVE ON VCC
fSAMPLE = 1MHz, fIN = 100kHz
70.2
–40
–55°C
PSSR (dB)
69.8
+25°C
+125°C
69.6
–60
–80
+85°C
69.4
–100
69.2
3.0
3.5
4.0
4.5
SUPPLY (Volts)
5.0
5.5
Figure 6. Typical SNR vs. Supply
–120
0 5 10 16 20 26 31 36 41 46 51 57 61 67 72 77 82 88 92 97
3 8 13 18 23 28 34 39 44 49 54 59 64 69 74 80 84 89 94 100
VCC RIPPLE FREQUENCY (kHz)
Figure 9. Typical Power Supply Rejection Ratio (PSRR)
Rev. A | Page 10 of 24
01128-009
69.0
2.50
01128-006
SNR (dB)
70.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
0
512
1023
1534
2045
2556
3067
CODE
3578
4089
Figure 10. Typical INL for 2.75 V @ 25°C
–1.0
0
512
1023
1534
2045
2556
3067
CODE
Figure 11. Typical DNL for 2.75 V @ 25°C
Rev. A | Page 11 of 24
3578
4089
01128-011
(DNL)
1.0
01128-010
(INL)
AD7492
AD7492
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition, and full scale, a point
1/2 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 1 LSB.
Gain Error
The last transition should occur at the analog value 1 1/2 LSB
below the nominal full scale. The first transition is a 1/2 LSB
above the low end of the scale (zero in the case of AD7492). The
gain error is the deviation of the actual difference between the
first and last code transitions from the ideal difference between
the first and last code transitions with offset errors removed.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode after the end
of the conversion. Track/Hold acquisition time is the time
required for the output of the track/hold amplifier to reach its
final value, within ±0.5 LSB, after the end of conversion.
Signal-to-Noise and Distortion Ratio
This is the measured ratio of signal-to-noise and distortion at
the output of the A/D converter. The signal is the rms
amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent on the number of
quantization levels in the digitization process; the more levels,
the smaller the quantization noise. The theoretical signal to
(noise + distortion) ratio for an ideal N-bit converter with a sine
wave input is given by:
Signal-to-Noise and Distortion = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB and for a 10-bit
converter is 62 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7492 it is defined as:
THD (dB) = 20 log
(V22 + V32 + V4 2 + V52 + V62 )
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n is equal to zero. For example, the
second order terms include (fa + fb) and (fa − fb), while the
third order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
The AD7492 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
Aperture Delay
In a sample/hold, the time required after the hold command for
the switch to open fully is the aperture delay. The sample is, in
effect, delayed by this interval, and the hold command would
have to be advanced by this amount for precise timing.
Aperture Jitter
Aperture jitter is the range of variation in the aperture delay. In
other words, it is the uncertainty about when the sample is
taken. Jitter is the result of noise that modulates the phase of the
hold command. This specification establishes the ultimate
timing error, hence the maximum sampling frequency for a
given resolution. This error increases as the input dV/dt
increases.
V1
Rev. A | Page 12 of 24
AD7492
CIRCUIT DESCRIPTION
CONVERTER OPERATION
TYPICAL CONNECTION DIAGRAM
The AD7492 is a 12-bit successive approximation analog-todigital converter based around a capacitive DAC. The AD7492
can convert analog input signals in the range 0 V to VREF. Figure
12 shows a very simplified schematic of the ADC. The control
logic, SAR register, and capacitive DAC are used to add and
subtract fixed amounts of charge from the sampling capacitor to
bring the comparator back into a balanced condition.
Figure 15 shows a typical connection diagram for the AD7492.
Conversion is initiated by a falling edge on CONVST. Once
CONVST goes low the BUSY signal goes high, and at the end of
the conversion, the falling edge of BUSY is used to activate an
interrupt service routine. The CS and RD lines are then activated
in parallel to read the 12 data bits. The internal band gap
reference voltage is 2.5 V, providing an analog input range of 0 V
to 2.5 V, making the AD7492 a unipolar A/D. A capacitor with a
minimum capacitance of 100 nF is needed at the output of the
REF OUT pin as it stabilizes the internal reference value. It is
recommended to perform a dummy conversion after power-up as
the first conversion result could be incorrect. This also ensures
that the part is in the correct mode of operation. The CONVST
pin should not be floating when power is applied, as a rising edge
on CONVST might not wake up the part.
CAPACITIVE
DAC
VREF
SWITCHES
VIN
CONTROL
INPUTS
CONTROL LOGIC
OUTPUT DATA
12-BIT PARALLEL
01128-012
SAR
Figure 12. Simplified Block Diagram of AD7492
Figure 13 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A. The comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on VIN.
In Figure 15 the VDRIVE pin is tied to DVDD, which results in
logic output voltage values being either 0 V or DVDD. The
voltage applied to VDRIVE controls the voltage value of the output
logic signals and the input logic signals. For example, if DVDD is
supplied by a 5 V supply and VDRIVE by a 3 V supply, the logic
output voltage levels would be either 0 V or 3 V. This feature
allows the AD7492 to interface to 3 V parts while still enabling
the A/D to process signals at 5 V supply.
10µF
CAPACITIVE
DAC
1nF
VIN
2kΩ
A
SW1
B
CONTROL LOGIC
01128-013
SW2
COMPARATOR
AGND
µC/µP
Figure 14 shows the ADC during conversion. When conversion
starts, SW2 opens and SW1 moves to Position B, causing the
comparator to become unbalanced. The ADC then runs
through its successive approximation routine and brings the
comparator back into a balanced condition. When the
comparator is rebalanced, the conversion result is available in
the SAR register.
CAPACITIVE
DAC
2kΩ
A
SW1
B
AGND
COMPARATOR
AD7492
100nF
VIN
0V TO 2.5V
DB0 TO
DB9 (DB11)
PS/FS
Figure 15. Typical Connection Diagram
ADC TRANSFER FUNCTION
The output coding of the AD7492 is straight binary. The
designed code transitions occur at successive integer LSB values
(that is, 1 LSB, 2 LSB, etc.). The LSB size equals 2.5/4096 for the
AD7492. The ideal transfer characteristic for the AD7492 is
shown in Figure 16.
CONTROL LOGIC
SW2
47µF
ANALOG
SUPPLY
2.7V TO 5.25V
VDRIVE AVDD
DVDD
CS
CONVST
RD
BUSY
01128-014
VIN
0.1µF
+
REF OUT
2.5V
PARALLELED
INTERFACE
Figure 13. ADC Acquisition Phase
+
01128-015
COMPARATOR
Figure 14. ADC Conversion Phase
Rev. A | Page 13 of 24
AD7492
ANALOG INPUT
111...000
Figure 18 shows the equivalent circuit of the analog input
structure of the AD7492. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. The Capacitor C3 is
typically about 4 pF and can be primarily attributed to pin
capacitance. The Resistor R1 is an internal switch resistance.
This resistor is typically about 125 Ω. The Capacitor C1 is the
sampling capacitor while R2 is used for bandwidth control.
1LSB = VREF /4096
011...111
01128-016
000...010
000...001
000...000
+VREF –1LSB
0V 1/2LSB
ANALOG INPUT
VDD
Figure 16. Transfer Characteristic for 12 Bits
D1
VIN
AC ACQUISITION TIME
In ac applications, it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of impedance at the VIN pin of the ADC
cause the THD to degrade at high input frequencies.
Table 6. Dynamic Performance Specifications
Input
Buffers
AD9631
AD797
SNR
500 kHz
69.5
69.6
THD
500 kHz
80
81.6
Typical Amplifier Current
Consumption
17 mA
8.2 mA
DC ACQUISITION TIME
The ADC starts a new acquisition phase at the end of a
conversion and ends it on the falling edge of the CONVST
signal. At the end of the conversion, there is a settling time
associated with the sampling circuit. This settling time lasts
120 ns. The analog signal on VIN is also acquired during this
settling time; therefore, the minimum acquisition time needed
is 120 ns.
Figure 17 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R3
represents the source impedance of a buffer amplifier or
resistive network, R1 is an internal switch resistance, R2 is for
bandwidth control, and C1 is the sampling capacitor. C2 is
back-plate capacitance and switch parasitic capacitance.
During the acquisition phase the sampling capacitor must be
charged to within 0.5 LSB of its final value.
VIN
R1
125Ω
C2
8pF
C1
22pF
R2
636Ω
Figure 17. Equivalent Analog Input Circuit
01128-017
R3
C3
4pF
D2
R1
125Ω
C1
22pF
R2
636Ω
C2
8pF
01128-018
ADC CODE
111...111
111...110
Figure 18. Equivalent Analog Input Circuit
PARALLEL INTERFACE
The parallel interface of the AD7492 is 12 bits wide. The output
data buffers are activated when both CS and RD are logic low. At
this point the contents of the data register are placed onto the data
bus. Figure 19 shows the timing diagram for the parallel port.
Figure 20 shows the timing diagram for the parallel port when
CS and RD are tied permanently low. In this setup, once the
BUSY line goes from high to low, the conversion process is
completed. The data is available on the output bus slightly
before the falling edge of BUSY.
Note that the data bus cannot change state while the A/D is
doing a conversion, as this would have a detrimental effect on
the conversion in progress. The data out lines go three-state
again when either the RD or CS line goes high. Thus the CS can
be tied low permanently, leaving the RD line to control
conversion result access. Please reference the VDRIVE section for
output voltage levels.
OPERATING MODES
The AD7492 has two possible modes of operation depending
on the state of the CONVST pulse at the end of a conversion,
Mode 1 and Mode 2.
Mode 1 (High-Speed Sampling)
In this mode of operation the CONVST pulse is brought high
before the end of conversion, that is, before BUSY goes low (see
Figure 20). If the CONVST pin is brought from high-to-low
while BUSY is high, the conversion is restarted. When
operating in this mode a new conversion should not be initiated
until 140 ns after BUSY goes low. This acquisition time allows
the track/hold circuit to accurately acquire the input signal. As
mentioned earlier, a read should not be done during a
conversion. This mode facilitates the fastest throughput times
for the AD7492.
Rev. A | Page 14 of 24
AD7492
tCONVERT
CONVST
t9
t2
t10
BUSY
t3
CS
t8
t4
RD
t6
t7
DBx
01128-019
t5
Figure 19. Parallel Port Timing
tCONVERT
CONVST
t9
t2
DBx
DATA N
DATA N+1
01128-020
BUSY
Figure 20. Parallel Port Timing with CS and RD Tied Low
Mode 2 (Partial or Full Sleep Mode)
Figure 21 shows the AD7492 in Mode 2 operation where the
ADC goes into either partial or full sleep mode after
conversion. The CONVST line is brought low to initiate a
conversion and remains low until after the end of the
conversion. If CONVST goes high and low again while BUSY is
high, the conversion is restarted. Once the BUSY line goes from
high-to-low, the CONVST line has its status checked and, if low,
the part enters a sleep mode. The type of sleep mode the
AD7492 enters depends on what way the PS/FS pin is
hardwired. If the PS/FS pin is tied high, the AD7492 enters
partial sleep mode. If the PS/FS pin is tied low, the AD7492
enters full sleep mode.
The device wakes up again on the rising edge of the CONVST
signal. From partial sleep the AD7492 is capable of starting
conversions typically 1 μs after the rising edge of CONVST. The
CONVST line can go from high-to-low during the wake-up time,
but the conversion is still not initiated until after 1 μs. It is
recommended that the conversion should not be initiated until at
least 20 μs of the wake-up time has elapsed. This ensures that the
AD7492 has stabilized to within 0.5 LSB of the analog input value.
After 1 μs, the AD7492 has only stabilized to within approximately 3 LSB of the input value. From full sleep, this wake-up
time is typically 500 μs. In all cases the BUSY line only goes high
once CONVST goes low. Superior power performance can be
achieved in these modes of operation by waking up the AD7492
only to carry out a conversion. The optimum power performance
is obtained when using full sleep mode as the ADC comparator,
reference buffer, and reference circuit are powered down. While
in partial sleep mode, only the ADC comparator is powered
down and the reference buffer is put into a low power mode. The
100 nF capacitor on the REF OUT pin is kept charged up by the
reference buffer in partial sleep mode while in full sleep mode
this capacitor slowly discharges. This explains why the wake-up
time is shorter in partial sleep mode. In both sleep modes the
clock oscillator circuit is powered down.
Rev. A | Page 15 of 24
AD7492
tCONVERT
CONVST
tWAKEUP
BUSY
CS
01128-021
RD
DBx
Figure 21. Mode 2 Operation
VDRIVE
Power vs. Throughput
The VDRIVE pin is used as the voltage supply to the digital output
drivers and the digital input circuitry. It is a separate supply
from AVDD and DVDD. The purpose of using a separate supply
for the digital input/output interface is that the user can vary
the output high voltage, VOH, and the logic input levels, VINH
and VINL, from the VDD supply to the AD7492. For example, if
AVDD and DVDD are using a 5 V supply, the VDRIVE pin can be
powered from a 3 V supply. The ADC has better dynamic
performance at 5 V than at 3 V, so operating the part at 5 V,
while still being able to interface to 3 V parts, pushes the
AD7492 to the top bracket of high performance 12-bit ADCs.
Of course, the ADC can have its VDRIVE and DVDD pins
connected together and be powered from a 3 V or 5 V supply.
The trigger levels are VDRIVE × 0.7 and VDRIVE × 0.3 for the digital
inputs. The pins that are powered from VDRIVE are DB11 to DB0,
CS, RD, CONVST, and BUSY.
The two modes of operation for the AD7492 produces different
power vs. throughput performances, Mode 1 and Mode 2; see
the Operating Modes section of the data sheet for more detailed
descriptions of these modes. Mode 2 is the sleep mode
(partial/full) of the part and it achieves the optimum power
performance.
Mode 1
Figure 22 shows the AD7492 conversion sequence in Mode 1
using a throughput rate of 500 kSPS. At 5 V supply, the current
consumption for the part when converting is 3 mA and the
quiescent current is 1.8 mA. The conversion time of 880 ns
contributes 6.6 mW to the overall power dissipation in the
following way:
(880 ns/2 μs) × (5 × 3 mA) = 6.6 mW
The contribution to the total power dissipated by the remaining
1.12 μs of the cycle is 5.04 mW
As previously mentioned, the PS/FS pin is used to control the
type of power-down mode that the AD7492 can enter into if
operated in Mode 2. This pin can be hardwired either high or
low, or even controlled by another device. It is important to
note that toggling the PS/FS pin while in power-down mode
does not switch the part between partial sleep and full sleep
modes. To switch from one sleep mode to another, the AD7492
has to be powered up and the polarity of the PS/FS pin changed.
It can then be powered down to the required sleep mode.
(1.12 μs/2 μs) × (5 × 1.8 mA) = 5.04 mW
Thus the power dissipated during each cycle is
6.6 mW + 5.04 mW = 11.64 mW
CONVST
tCONVERT
POWER-UP
It is recommended that the user performs a dummy conversion
after power-up, as the first conversion result could be incorrect.
This also ensures that the part is in the correct mode of
operation. The recommended power-up sequence is as follows:
1. GND
tQUIESCENT
BUSY
1.12µs
880ns
2µs
Figure 22. Mode 1 Power Dissipation
2. VDD
3. VDRIVE
4. Digital Inputs
5. VIN
Rev. A | Page 16 of 24
01128-022
PS/FS PIN
AD7492
Mode 2 (Full Sleep Mode)
Figure 25, Figure 26, and Figure 27 show a typical graphical
representation of power vs. throughput for the AD7492 when in
Mode 1 @ 5 V and 3 V, Mode 2 in full sleep mode @ 5 V and 3
V, and Mode 2 in partial sleep mode @ 5 V and 3 V.
Figure 23 shows the AD7492 conversion sequence in Mode 2,
full sleep mode, using a throughput rate of approximately
100 kSPS. At 5 V supply the current consumption for the part
when converting is 3 mA, while the full sleep current is 1 μA
maximum. The power dissipated during this power-down is
negligible and thus not worth considering in the total power
figure. During the wake-up phase, the AD7492 draws typically
1.8 mA. Overall power dissipated is
12
10
tCONVERT
6
4
3V
500µs
tQUIESCENT
BUSY
0
0
9.5ms
200
01128-023
880ns
100
10ms
300
900
1000
90
100
90
100
3.5
Mode 2 (Partial Sleep Mode)
3.0
2.5
POWER (mV)
Figure 24 shows the AD7492 conversion sequence in Mode 2,
partial sleep mode, using a throughput rate of 1 kSPS. At 5 V
supply, the current consumption for the part when converting is
3 mA, while the partial sleep current is 250 μA maximum.
During the wake-up phase, the AD7492 typically draws 1.8 mA.
Power dissipated during wake-up and conversion is
2.0
5V
1.5
3V
1.0
(880 ns/1 ms) × (5 × 3 mA) + (20 μs/1 ms) × (5 × 1.8 mA) =
193.2 mW
0.5
Power dissipated during power-down is
0
0
10
20
30
(979 μs/1 ms) × (5 × 250 μA) = 1.22 mW
70
50
60
40
THROUGHPUT (kHz)
80
Figure 26. Power vs. Throughput
(Mode 2 in Full Sleep Mode @ 5 V and 3 V)
Overall power dissipated is
2.5
193.2 μW + 1.22 mW = 1.41 mW
tWAKEUP
800
Figure 25. Power vs. Throughput
(Mode 1 @ 5 V and 3 V)
Figure 23. Full Sleep Power Dissipation
CONVST
400 500 600 700
THROUGHPUT (kHz)
01128-025
2
01128-026
tWAKEUP
POWER (mV)
8
(880 ns/10 ms) × (5 × 3 mA) + (500 μs/10 ms) × (5 × 1.8 mA)
= 451.32 μW
CONVST
5V
tCONVERT
5V
2.0
979µs
1ms
1.5
3V
1.0
0.5
Figure 24. Partial Sleep Power Dissipation
0
0
10
20
30
70
40
50
60
THROUGHPUT (kHz)
80
Figure 27. Power vs. Throughput
(Mode 2 in Partial Sleep Mode @ 5 V and 3 V)
Rev. A | Page 17 of 24
01128-027
880ns
01128-024
tQUIESCENT
BUSY
POWER (mV)
20µs
AD7492
GROUNDING AND LAYOUT
The analog and digital power supplies are independent and
separately pinned out to minimize coupling between analog and
digital sections within the device. To complement the excellent
noise performance of the AD7492, it is imperative that care be
given to the PCB layout. Figure 28 shows a recommended
connection diagram for the AD7492.
All of the AD7492 ground pins should be soldered directly to a
ground plane to minimize series inductance. The AVDD pin,
DVDD pin, and VDRIVE pin should be decoupled to both the
analog and digital ground planes. The REF OUT pin should be
decoupled to the analog ground plane with a minimum
capacitor value of 100 nF. This capacitor helps to stabilize the
internal reference circuit. The large value capacitors decouple
low frequency noise to analog ground, the small value
capacitors decouple high frequency noise to digital ground. All
digital circuitry power pins should be decoupled to the digital
ground plane. The use of ground planes can physically separate
sensitive analog components from the noisy digital system. The
two ground planes should be joined in only one place and
should not overlap so as to minimize capacitive coupling
between them. If the AD7492 is in a system where multiple
devices require AGND-to-DGND connections, the connection
should still be made at one point only, a star ground point,
established as close as possible to the AD7492.
10µF
0.1µF
47µF
+
ANALOG
SUPPLY
5V
AVDD
AGND
DGND
2.5V
100nF
+
+
Separate power supplies for AVDD and DVDD are desirable, but if
necessary, DVDD can share its power connection to AVDD. The
digital supply (DVDD) must not exceed the analog supply (AVDD)
by more than 0.3 V in normal operation.
MICROPROCESSOR INTERFACING
ADSP-2185 to AD7492 Interface
Figure 29 shows a typical interface between the AD7492 and the
ADSP-2185. The ADSP-2185 processor can be used in one of
two memory modes, full memory mode and host mode. The
Mode C pin determines in which mode the processor works.
The interface in Figure 29 is set up to have the processor
working in full memory mode, allowing full external addressing
capabilities.
AD7492
VDRIVE
OPTIONAL
REF OUT
01128-028
10µF
1nF
POWER SUPPLIES
When the AD7492 has finished converting, the BUSY line
requests an interrupt through the IRQ2 pin. The IRQ2 interrupt
has to be set up in the interrupt control register as edgesensitive. The data memory select (DMS) pin latches in the
address of the ADC into the address decoder. The read
operation is started.
DVDD
1nF
Noise to the analog power line can be further reduced by use of
multiple decoupling capacitors as shown in Figure 28.
Decoupling capacitors should be placed directly at the power
inlet to the PCB and also as close as possible to the power pins
of the AD7492. The same decoupling method should be used
on other ICs on the PCB, with the capacitor leads as short as
possible to minimize lead inductance.
Figure 28. Typical Decoupling Circuit
A0 TO A15
ADSP-21851
DMS
Noise can be minimized by applying the following simple rules
to the PCB layout:
• Analog signals should be kept away from digital signals.
• Fast switching signals like clocks should be shielded with
digital ground to avoid radiating noise to other sections of
the board and clock signals should never be run near the
analog inputs.
• Avoid running digital lines under the device as this couples
noise onto the die.
• The power supply lines to the AD7492 should use as large a
trace as possible to provide a low impedance path and reduce
the effects of glitches on the power supply line.
Rev. A | Page 18 of 24
AD7492
ADDRESS
DECODER
RD
D0 TO D23
CS
BUSY
IRQ2
MODE C
CONVST
ADDRESS BUS
RD
100kΩ
DB0 TO DB9
(DB11)
DATA BUS
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 29. ADSP-2185 to AD7492 Interface
01128-029
+
• Avoid crossover of digital and analog signals and place
traces that are on opposite sides of the board at right angles
to each other.
AD7492
OPTIONAL
ADSP-21065Lto AD7492 Interface
Figure 30 shows a typical interface between the AD7492 and the
ADSP-21065L SHARC® processor. This interface is an example
of one of three DMA handshake modes. The MSX control line is
actually three memory select lines. Internal ADDR25–24 are
decoded into MS3-0, these lines are then asserted as chip selects.
The DMAR1 (DMA Request 1) is used in this setup as the
interrupt to signal end of conversion. The rest of the interface is
standard handshaking operation.
A0 TO A15
CONVST
ADDRESS BUS
AD7492
TMS320C251
IS
ADDRESS
DECODER
CS
BUSY
STRB
RD
R/W
READY
OPTIONAL
MSC
ADDRESS
LATCH
AD7492
DMD0 TO DMD15
ADDRESS
DECODER
DMAR1
RD
Figure 31. TMS320C25 to AD7492 Interface
CS
PIC17C4x to AD7492 Interface
BUSY
Figure 32 shows a typical parallel interface between the AD7492
and PIC17C4x. The microcontroller sees the ADC as another
memory device with its own specific memory address on the
memory map. The CONVST signal can be controlled by either
the microcontroller or an external source. The BUSY signal
provides an interrupt request to the microcontroller when a
conversion ends. The INT pin on the PIC17C4x must be
configured to be active on the negative edge. Port C and Port D
of the microcontroller are bidirectional and used to address the
AD7492 and to read in the 12-bit data. The OE pin on the PIC
can be used to enable the output buffers on the AD7492 and
perform a read operation.
RD
DB0 TO DB9
(DB11)
DATA BUS
1ADDITIONAL
DATA BUS
1ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS
BUS
ADSP-21065L1
D0 TO 31
DB0 TO DB9
(DB11)
01128-031
CONVST
PINS OMITTED FOR CLARITY.
Figure 30. ADSP-21065L to AD7492 Interface
TMS320C25 to AD7492 Interface
Figure 31 shows an interface between the AD7492 and the
TMS320C25. The CONVST signal can be applied from the
TMS320C25 or from an external source. The BUSY line
interrupts the digital signal processor when conversion is
completed. The TMS320C25 does not have a separate RD
output to drive the AD7492 RD input directly. This has to be
generated from the processor STRB and R/W outputs with the
addition of some glue logic. The RD signal is OR-gated with the
MSC signal to provide the WAIT state required in the read cycle
for correct interface timing. The following instruction is used to
read the conversion from the AD7492:
OPTIONAL
CONVST
PIC17C4x1
DB0 TO DB9
(DB11)
AD0 TO AD15
AD7492
ADDRESS
LATCH
ALE
ADDRESS
DECODER
RD
BUSY
OE
INT
IN D,ADC
1ADDITIONAL
where:
D is the data memory address.
ADC is the AD7492 address.
CS
PINS OMITTED FOR CLARITY.
Figure 32. PIC17C4x to AD7492 Interface
The read operation must not be attempted during conversion.
Rev. A | Page 19 of 24
01128-032
MSX
ADDRESS BUS
01128-030
ADDR 0 TO
ADDR 23
AD7492
OPTIONAL
Figure 33 shows the AD7492 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. (The AD7492 occupies
one of these I/O spaces.) Each data transfer consumes two bus
cycles, one cycle to fetch data and the other to store data.
AD0 TO AD15
A16 TO A19
ALE
Rev. A | Page 20 of 24
CONVST
ADDRESS
LATCH
AD7492
ADDRESS
BUS
80C1861
After the AD7492 has finished the conversion, the BUSY line
generates a DMA request to Channel 1 (DRQ1). Because of the
interrupt, the processor performs a DMA read operation that
resets the interrupt latch. Sufficient priority must be assigned to
the DMA channel to ensure that the DMA request is serviced
before the completion of the next conversion. This
configuration can be used with 6 MHz and 8 MHz 80C186
processors.
ADDRESS/DATA BUS
ADDRESS
DECODER
DRQ1
Q
CS
R
BUSY
S
RD
RD
DATA BUS
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. 80C186 to AD7492 Interface
DB0 TO DB9
(DB11)
01128-033
80C186 to AD7492 Interface
AD7492
OUTLINE DIMENSIONS
15.60 (0.6142)
15.20 (0.5984)
24
13
7.60 (0.2992)
7.40 (0.2913)
1
10.65 (0.4193)
10.00 (0.3937)
12
2.65 (0.1043)
2.35 (0.0925)
0.75 (0.0295)
× 45°
0.25 (0.0098)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY 1.27 (0.0500)
BSC
0.10
8°
SEATING
0.33 (0.0130) 0°
PLANE
0.20 (0.0079)
0.51 (0.020)
0.31 (0.012)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 34. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
7.90
7.80
7.70
24
13
4.50
4.40
4.30
1
6.40 BSC
12
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.30
0.19
SEATING
PLANE
0.10 COPLANARITY
0.20
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 35. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7492AR
AD7492AR–REEL
AD7492AR–REEL7
AD7492ARZ 1
AD7492ARZ–REEL1
AD7492ARZ–REEL71
AD7492BR
AD7492BR-REEL
AD7492BR–REEL7
AD7492BRZ1
AD7492AR-5
AD7492AR-5–REEL
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Resolution (Bits)
12
12
12
12
12
12
12
12
12
12
12
12
Throughput Rate
(MSPS)
1
1
1
1
1
1
1
1
1
1
1.25
1.25
Rev. A | Page 21 of 24
Package
Description
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
Package Option
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
AD7492
Model
AD7492AR-5–REEL7
AD7492ARZ-51
AD7492BR-5
AD7492BR-5–REEL
AD7492BR-5–REEL7
AD7492BRZ-51
AD7492ARU
AD7492ARU–REEL
AD7492ARU–REEL7
AD7492ARUZ1
AD7492ARUZ–REEL1
AD7492ARUZ–REEL71
AD7492ARU-5
AD7492ARU-5–REEL
AD7492ARU-5–REEL7
AD7492ARUZ-51
AD7492ARUZ-5–REEL1
AD7492ARUZ-5–REEL71
AD7492ARUZ-41
AD7492ARUZ-4REEL1
AD7492ARUZ-4REEL71
AD7492BRU
AD7492BRU–REEL
AD7492BRU–REEL7
AD7492BRUZ1
AD7492BRU-5
AD7492BRU-5–REEL
AD7492BRU-5–REEL7
AD7492BRUZ-51
EVAL-AD7492CB 2
EVAL-CONTROL BRD2 3
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Resolution (Bits)
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
Throughput Rate
(MSPS)
1.25
1.25
1.25
1.25
1.25
1.25
1
1
1
1
1
1
1.25
1 .25
1.25
1.25
1.25
1.25
0.4
0.4
0.4
1
1
1
1
1.25
1.25
1.25
1.25
1
Package
Description
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
Z = Pb–free part.
This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
3
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
2
Rev. A | Page 22 of 24
Package Option
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
Evaluation Board
Controller Board
AD7492
NOTES
Rev. A | Page 23 of 24
AD7492
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01128-0-5/06(A)
Rev. A | Page 24 of 24
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