NXP Semiconductors Data Sheet: Technical Data Kinetis K27F MCU Sub-Family K27P169M150SF5 Rev. 1, 03/2017 MK27FN2M0VMI15 High performance ARM® Cortex®-M4 MCU with 2 MB Flash, 1 MB SRAM, 2 USB Controllers (High-Speed and FullSpeed), SDRAM controller, QuadSPI interface and integrated Power Management Controller . K27F extends the Kinetis Micontroller portfolio with large embedded memory, advanced external memory interfaces, performance, and peripheral integration while maintaining a high level of software compatibility with previous Kinetis devices: • The extended memory resources include a total of 2 MB of programmable flash and 1 MB of embedded SRAM which can be used to support application needs for data logging 169 MAPBGA (MI) and rich human to machine interfaces with displays 9 x 9 x 1.28 mm Pitch 0.65 mm • K27F enables memory expansion leveraging the SDRAM controller and QuadSPI interface for eXecution-In-Place (XIP) from an external Serial NOR flash • Both the USB High-Speed and Crystal-less Full-Speed Controllers integrate a PHY to reduce BOM cost • The integrated smart peripherals such as Low-power UARTs and Timers operate in very low-power modes to optimize battery life of the system • K27F leverages a standard MCU topology with a single input supply voltage ranging from 1.71V to 3.6V and an independant VBAT domain Performance Human-machine interface • Up to 150 MHz ARM Cortex-M4 based core with DSP • Up to 120 General-purpose input/output (GPIOs) instructions and Single Precision Floating Point unit Analog modules (FPU) • Integrated Power Management Control (PMC) Memories and memory expansion • One 16-bit SAR ADCs, two 6-bit DAC and one 12-bit • 2 MB dual bank program flash and 1 MB SRAM DAC • 8 KB I/D + 8 KB System cache • Two analog comparators (CMP) containing a 6-bit • 32-bit external bus interface (FlexBus) DAC and programmable reference input • 32-bit SDRAM controller • 1.2 V Voltage reference • Dual QuadSPI interface with eXecution-In-Place (XIP) Timers • supports SDR and DDR serial flash and octal • One 4-ch 32-bit Periodic interrupt timer configurations • Two 16-bit low-power timer PWM modules • 32 KB Boot ROM with built-in bootloader • Two 8-ch motor control/general purpose/PWM timers System and Clocks • Two 2-ch quadrature decoder/general purpose timers • 32-ch Asynchronous DMA • Real-time clock with independent 3.6 V power domain • Multiple low-power modes • Programmable delay block • Memory protection unit with multi-master protection Operating Characteristics • 3 to 32 MHz main crystal oscillator • Temperature range (ambient): -40 to 105°C (BGA) • 32 kHz low power crystal oscillator • Main VDD Voltage and Flash write voltage range:1.71 • 48 MHz internal reference V–3.6 V • Hardware and Software Watchdogs • Independent VDDIO_E (QuadSPI):1.71 V–3.6 V NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Security • Hardware random-number generator • Memory Mapped Crypto Acceleration Unit(MMCAU): DES, 3-DES, AES, SHA-1, SHA-256 and MD5 accelerator • Cyclic Redundancy Check (CRC) Target Applications • Wearables • Low-end graphic display system • Cost-optimized multi-standard wireless smart home hubs • Home Automation devices • Consumer accessories • Independent VBAT (RTC): 1.71 V–3.6 V • I/O Voltage range (VDD): 1.71 V–3.6 V Communication interfaces • Two USB controllers:Crystal-less Full-/low-speed + transceiver Host and Device; High-/Full-/low-speed + PHY Host and Device • Secure Digital Host Controller (SDHC) • Two I2S modules, four I2C modules and five LowPower UART modules • Four SPI modules (SPI3 supports more than 40 Mbps) • 32-ch Programmable module (FlexIO) to emulate various serial, parallel or custom interfaces Ordering Information 1 Part Number MK27FN2M0VMI15 Embedded Memory Flash SRAM 2 MB 1 MB Package Type Maximum number of I\O's 169 MAPBGA 120 1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search. Device Revision Number Device Mask Set Number SIM_SDID[REVID] JTAG ID Register[PRN] 2N96T 0010 0010 Related Resources Type Description Resource Fact Sheet The Fact Sheet gives overview of the product key features and its uses. K2x Fact Sheet Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K27P169M150SF5RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document Chip Errata The chip mask set Errata provides additional or corrective information for Kinetis_K_2N96T1 a particular device mask set. Package drawing Package dimensions are provided in package drawings. • MAPBGA 169-pin: 98ASA00628D1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Cryptographic accelerator (CAU) Trace Port TPIU JTAG & Serial Wire SWJ-DP ARM Cortex M4 ETM PPB AHB-AP NVIC PIT ITM WIC FPU DWT IRC 48 MHz OSC DMA Mux x2 DCD USB/ FS/LS USB Vreg MUX 256 KByte MCG PLL HS DCD FPB USB HS/FS/ LS DSP System ICODE DCODE 256 KByte RTC OSC eDMA eSDHC Cache SRAM 8 Kbyte M0 8 Kbyte M1 M5 M3 Crossbar Switch (XBS) M2 M4 S2 System Memory Protection Unit (MPU) S1 IRC 4 MHz FLL PLL S5 QSPI S6 S0 BOOT ROM Flash Controller S3 BME2 SDRAMC AHB to IPS 0 FlexBus RGPIO AHB to IPS 1 x128 512 KByte OCRAM 4 KByte EERAM Flash 6-bit DAC & CMP x2 SPI x4 FlexIO PDB PIT 16-bit ADC I2C x4 LPUART x5 FlexTimer x4 TRNG CMT TPM x2 CRC RTC Low-power timer x2 512 KByte 512 KByte 512 KByte 512 KByte Vref I2S x2 12-bit DAC PMC Figure 1. K27F Block Diagram Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 3 NXP Semiconductors Table of Contents 1 Ratings.................................................................................... 5 1.1 Thermal handling ratings................................................. 5 1.2 Moisture handling ratings................................................ 5 1.3 ESD handling ratings....................................................... 5 1.4 Voltage and current maximum ratings............................. 5 2 General................................................................................... 6 2.1 AC electrical characteristics.............................................6 2.2 Nonswitching electrical specifications..............................7 2.2.1 Voltage and current operating requirements....... 7 2.2.2 HVD, LVD and POR operating requirements...... 8 2.2.3 Voltage and current operating behaviors.............9 2.2.4 Power mode transition operating behaviors........ 10 2.2.5 2.2.6 Power consumption operating behaviors............ 11 Electromagnetic Compatibility (EMC) specifications....................................................... 19 2.2.7 Designing with radiated emissions in mind..........19 2.2.8 Capacitance attributes.........................................19 2.3 Switching specifications...................................................19 2.3.1 Device clock specifications..................................20 2.3.2 General switching specifications......................... 20 2.4 Thermal specifications..................................................... 22 2.4.1 Thermal operating requirements......................... 22 2.4.2 Thermal attributes................................................22 3 Peripheral operating requirements and behaviors.................. 23 3.1 Core modules.................................................................. 23 3.1.1 Debug trace timing specifications........................23 3.1.2 JTAG electricals.................................................. 23 3.2 Clock modules................................................................. 26 3.2.1 MCG specifications..............................................26 3.2.2 IRC48M specifications.........................................29 3.2.3 Oscillator electrical specifications........................30 3.2.4 32 kHz oscillator electrical characteristics........... 32 3.3 Memories and memory interfaces................................... 33 3.3.1 QuadSPI AC specifications................................. 33 3.3.2 Flash electrical specifications.............................. 38 3.3.3 Flexbus switching specifications..........................40 3.3.4 SDRAM controller specifications......................... 43 3.4 Analog............................................................................. 46 3.4.1 ADC electrical specifications............................... 46 4 NXP Semiconductors 4 5 6 7 8 3.4.2 CMP and 6-bit DAC electrical specifications....... 50 3.4.3 12-bit DAC electrical characteristics....................52 3.4.4 Voltage reference electrical specifications.......... 55 3.5 Timers..............................................................................56 3.6 Communication interfaces............................................... 56 3.6.1 USB Voltage Regulator electrical specifications..57 3.6.2 USB Full Speed Transceiver and High Speed PHY specifications...............................................58 3.6.3 USB DCD electrical specifications.......................58 3.6.4 DSPI switching specifications (limited voltage range).................................................................. 59 3.6.5 DSPI switching specifications (full voltage range).................................................................. 62 3.6.6 Inter-Integrated Circuit Interface (I2C) timing...... 64 3.6.7 LPUART switching specifications........................ 66 3.6.8 SDHC specifications............................................66 3.6.9 I2S switching specifications.................................68 Dimensions............................................................................. 74 4.1 Obtaining package dimensions....................................... 74 Pinout...................................................................................... 74 5.1 K27F Signal Multiplexing and Pin Assignments.............. 74 5.2 Recommended connection for unused analog and digital pins........................................................................75 5.3 K27F Pinouts................................................................... 76 Ordering parts......................................................................... 76 6.1 Determining valid orderable parts....................................76 Part identification.....................................................................77 7.1 Description.......................................................................77 7.2 Format............................................................................. 77 7.3 Fields............................................................................... 77 7.4 Example...........................................................................78 Terminology and guidelines.................................................... 78 8.1 Definitions........................................................................ 78 8.2 Examples......................................................................... 79 8.3 Typical-value conditions.................................................. 79 8.4 Relationship between ratings and operating requirements....................................................................80 8.5 Guidelines for ratings and operating requirements..........80 9 Revision History...................................................................... 80 Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Ratings 1 Ratings 1.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level (for V-temp variant) Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105°C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 1.4 Voltage and current maximum ratings Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 5 NXP Semiconductors General Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V VDDA Analog supply voltage – 0.3 3.8 V –0.3 3.8 V –0.3 3.8 V VDDIO_E VBAT VDDIO_E is an independent voltage supply for PORTE 1 RTC supply voltage IDD Digital supply current — 300 mA ID Maximum current single pin limit (digital output pins) –25 25 mA USB regulator input –0.3 6.0 V VUSB0_Dx USB0_DP and USB_DM input voltage –0.3 3.63 V VUSB1_DPx USB1_DP and USB1_DM input voltage –0.3 3.63 V VREGIN 1. VDDIO_E is independent of the VDD domain and can operate at a voltage independent of VDD. 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal High Low 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 2. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins • have CL=15 pF loads, • are slew rate disabled, and • are normal drive strength 2. input pins • have their passive filter disabled (PORTx_PCRn[PFE]=0) 6 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 General 2.2 Nonswitching electrical specifications 2.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V Digital Supply voltage for Port E 1.71 3.6 V Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V 1.71 3.6 V 0.7 × VDD — V 0.75 × VDD — V — 0.35 × VDD V — 0.3 × VDD V 0.7 × VDDIO_E — V — V 0.35 × VDDIO_E V VDDIO_E VDDA VBAT VIH RTC battery supply voltage Input high voltage • 2.7 V ≤ VDD ≤ 3.6 V • 1.7 V ≤ VDD ≤ 2.7 V VIL Notes Input low voltage • 2.7 V ≤ VDD ≤ 3.6 V • 1.7 V ≤ VDD ≤ 2.7 V VIH_E Input high voltage • 2.7 V ≤ VDDIO_E ≤ 3.6 V • 1.7 V ≤ VDDIO_E ≤ 2.7 V VIL_E Input low voltage • 2.7 V ≤ VDDIO_E ≤ 3.6 V 0.75 × VDDIO_E — — V 0.3 × VDDIO_E • 1.7 V ≤ VDDIO_E ≤ 2.7 V VHYS Input hysteresis 0.06 × VDD — V VHYS_E Input hysteresis 0.06 × VDDIO_E — V -5 — mA -25 — mA IICIO I/O pin negative DC injection current — single pin • VIN < VSS-0.3V IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Negative current injection 1 VODPU Pseudo Open drain pullup voltage level VDD VDD V VRAM VDD voltage required to retain RAM 1.2 — V VPOR_VBAT — V VRFVBAT VBAT voltage required to retain the VBAT register file Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 2 7 NXP Semiconductors General 1. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD or VDDIO_E. If VIN is less than -0.3V, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(-0.3-VIN)/|IICIO|. The actual resistor value should be an order of magnitude higher to tolerate transient voltages. 2. Open drain outputs must be pulled to VDD. 2.2.2 HVD, LVD and POR operating requirements Table 2. VDD supply HVD, LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VHVDH High Voltage Detect (High Trip Point) — 3.72 — V VHVDL High Voltage Detect (Low Trip Point) — 3.46 — V VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V 2.62 2.70 2.78 V 2.72 2.80 2.88 V 2.82 2.90 2.98 V 2.92 3.00 3.08 V — 60 — mV 1.54 1.60 1.66 V 1.74 1.80 1.86 V 1.84 1.90 1.96 V 1.94 2.00 2.06 V 2.04 2.10 2.16 V — 40 — mV VLVW1H VLVW2H VLVW3H VLVW4H Low-voltage warning thresholds — high range • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) VLVW2L VLVW3L VLVW4L VHYSL 1 • Level 4 falling (LVWV=11) VHYSH VLVW1L Notes Low-voltage warning thresholds — low range • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) 1 • Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis — low range VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage 8 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 General NOTE There is no LVD circuit for VDDIO_E domain. Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes 2.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Min. Typ.1 Max. Unit Output high voltage — normal drive strength IO Group 1 • 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -5 mA • 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -2.5 mA IO Groups 2 and 3 • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -5 mA IO Group 4 • 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOH = -5 mA • 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOH = -2.5 mA 2, 3 VBAT – 0.5 — — V VBAT – 0.5 — — V — — V — — V — — V — — V VDD – 0.5 VDD – 0.5 VDDIO_E – 0.5 VDDIO_E – 0.5 Output high voltage — High drive strength IO Group 3 • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA IO Group 4 • 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOH = -15 mA • 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOH = -7.5 mA IOHT Output high current total for all ports VOL Output low voltage — normal drive strength Notes 2 VDD – 0.5 — — V VDD – 0.5 — — V VDDIO_E – 0.5 — — V VDDIO_E – 0.5 — — V — — 100 mA 2, 4, 5 IO Group 1 • 2.7 V ≤ VBAT ≤ 3.6 V, IOL = -5 mA • 1.71 V ≤ VBAT ≤ 2.7 V, IOL = -2.5 mA IO Groups 2 and 3 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = -10 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOL = -5 mA IO Group 4 — — 0.5 V — — 0.5 V — — 0.5 V — — 0.5 V — — 0.5 V Table continues on the next page... Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 9 NXP Semiconductors General Table 4. Voltage and current operating behaviors (continued) Symbol Description • 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOL = -5 mA • 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOL = -2.5 mA Min. Typ.1 Max. Unit — — 0.5 V Output low voltage — High drive strength Notes 2, 4 IO Group 3 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = -20 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOL = -10 mA IO Group 4 • 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOL = -15 mA • 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOL = -7.5 mA IOLT IIN Output low current total for all ports — — 0.5 V — — 0.5 V — — 0.5 V — — 0.5 V — — 100 mA Input leakage current VDD domain pins • VSS ≤ VIN ≤ VDD PORTE pins • VSS ≤ VIN ≤ VDDIO_E 6, 7, 8 — 0.002 0.5 µA — 0.002 0.5 µA — 0.002 0.5 µA VBAT domain pins • VSS ≤ VIN ≤ VBAT RPU Internal pullup resistors(except RTC_WAKEUP pins) 20 — 50 kΩ 9 RPD Internal pulldown resistors (except RTC_WAKEUP pins) 20 — 50 kΩ 10 1. Typical values characterized at 25°C and VDD = 3.6V unless otherwise noted. 2. IO Group 1 includes VBAT domain pins: RTC_WAKEUP_b. IO Group 2 includes VDD domain pins: PORTA, PORTB, PORTC, and PORTD, except PTA4. IO Group 3 includes VDD domain pins: PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7. IO Group 4 includes VDDIO_E domain pins: PORTE. 3. PTA4 has lower drive strength: IOH = -5 mA for high VDD range; IOH = -2.5 mA for low VDD range. 4. Open drain outputs must be pulled to VDD. 5. PTA4 has lower drive strength: IOL = 5mA for high VDD range; IOL = 2.5mA for low VDD range. 6. VDD domain pins include ADC, CMP, and RESET_b inputs. Measured at VDD = 3.6V. 7. PORTE analog input voltages cannot exceed VDDIO_E supply when VDD ≥ VDDIO_E. PORTE analog input voltages cannot exceed VDD supply when VDD ˂ VDDIO_E. 8. VBAT domain pins include EXTAL32, XTAL32, and RTC_WAKEUP_b pins. 9. Measured at minimum supply voltage and VIN = VSS 10. Measured at minimum supply voltage and VIN = VDD 2.2.4 Power mode transition operating behaviors For detailed description of the power modes, please refer to the Power Management chapter of the K27F Reference Manual. All specifications except tPOR, and VLLSx –> RUN recovery times in the following table assume this clock configuration: 10 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 General • • • • • CPU and system clocks = 100 MHz Bus clock = 50 MHz FlexBus clock = 50 MHz Flash clock = 25 MHz MCG mode=FEI Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VLLS0 –> RUN • VLLS1 –> RUN • VLLS2 –> RUN • VLLS3 –> RUN • LLS2 –> RUN • LLS3 –> RUN • VLPS –> RUN • STOP –> RUN Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Min. Max. Unit — 300 µs — 171 µs — 171 µs — 103 µs — 103 µs — 6.3 µs — 6.3 µs — 5.4 µs — 5.4 µs Notes 11 NXP Semiconductors General 2.2.5 Power consumption operating behaviors Figure 3. Power Supplies of K27F The K27F device has several power supplies and the total current consumption of the device is the accumulative result of each individual power supplies’ current consumption, dependent on the power mode of operation. (RUN, HSRUN, VLPR, Stop, VLLS3 etc.) IDD_MCU_total = IDD + IDDIO_E + IDD_VBAT + IDDA + IDD_USB When calculating the total MCU current consumption considerations to external loads on the following should be made: • On top of the device’s IDD current consumption, external loads applied to Ports A,B,C and D need to be considered • IDDIO_E current consumption is significantly dependent on external loads applied to Port E pins, and the internal current consumption in the device is negligible compared to IDD. • The USB_VREG provides a 3.3V output which can drive loads of upto 150 mA need to be considered. The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 6 details the IDD values observed through the VDD supply. Table 6. Power consumption operating behaviors (through VDD) Symbol IDDA Description Analog supply current Min. Typ. Max. Unit Notes — — See Note mA 1 Table continues on the next page... 12 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 General Table 6. Power consumption operating behaviors (through VDD) (continued) Symbol Description Min. IDD_RUN Run mode current — all peripheral clocks disabled, code of while(1) loop executing from internal flash @ 3.0 V • @ 25°C • @ 70°C • @ 85°C • @ 105°C IDD_RUN Run mode current — all peripheral clocks enabled, code of while(1) loop executing from internal flash @ 3.0 V • @ 25°C • @ 70°C • @ 85°C • @ 105°C IDD_RUNCO Run mode current in compute operation - 120 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from internal flash at 3.0 V • @ 25°C • @ 70°C • @ 85°C • @ 105°C IDD_HSRUN High_speed Run mode current — all peripheral clocks disabled, code of while(1) loop executing from internal flash @ 3.0 V • @ 25°C • @ 70°C • @ 85°C • @ 105°C IDD_HSRUN High-speed Run mode current — all peripheral clocks enabled, code of while(1) loop executing from internal flash @ 3.0 V • @ 25°C • @ 70°C • @ 85°C • @ 105°C Typ. Max. Unit Notes 2 — 36.3 41.2 — 43.4 61.3 — 48.8 75.5 — 59.9 98.4 mA 2 — 49.7 56.4 mA — 57.0 80.5 — 62.5 96.6 — 73.6 120.9 3 — 33.4 37.9 — 40.4 57.0 — 45.7 70.7 — 56.7 93.2 mA 4 — 48.2 57.5 mA — 58.2 86.5 — 64.8 102.3 — 78.7 134.5 4 — 64.7 77.1 — 74.8 111.1 — 81.5 128.8 — 95.6 163.3 IDD_HSRUNCO High-speed Run mode current in compute operation – 150 MHz core/ 25 MHz flash / bus clock disabled, code of while(1) loop executing from internal flash at 3.0 V mA 3 mA Table continues on the next page... Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 13 NXP Semiconductors General Table 6. Power consumption operating behaviors (through VDD) (continued) Symbol Description • @ 25°C • @ 70°C Min. Typ. Max. — 45.4 54.1 — 55.0 81.8 — 61.8 97.6 — 75.6 129.1 Unit Notes • @ 85°C • @ 105°C IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled, code of while(1) loop executing from internal flash • @ 25°C • @ 70°C • @ 85°C • @ 105°C IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled, code of while(1) loop executing from internal flash at 3.0 V • @ 25°C 2 — 18.7 21.2 — 27.1 38.2 — 32.8 50.7 — 43.4 71.3 mA 5 — 9.6 10.9 — 18.5 26.1 — 24.4 37.7 — 35.5 58.4 mA • @ 70°C • @ 85°C • @ 105°C IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled • @ 25°C • @ 70°C • @ 85°C • @ 105°C IDD_VLPR 6 — 1.3 3.9 — 3.0 8.0 — 4.2 11.0 — 7.0 17.2 mA Very-low-power run mode current at 3.0 V — all peripheral clocks enabled • @ 25°C • @ 70°C • @ 85°C • @ 105°C IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 1 MHz flash / bus clock disabled, while(1) code executing from internal flash at 3.0 V • @ 25°C • @ 70°C 6 — 1.9 5.7 — 3.5 9.3 — 4.8 12.5 — 7.5 18.4 mA 7 — 1.2 3.6 — 2.8 7.5 mA Table continues on the next page... 14 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 General Table 6. Power consumption operating behaviors (through VDD) (continued) Symbol Description • @ 85°C • @ 105°C IDD_PSTOP2 Stop mode current with partial stop 2 clocking option core and system disabled / 10.5 MHz bus at 3.0 V • @ 25°C • @ 70°C • @ 85°C Min. Typ. Max. — 4.1 10.7 — 6.9 16.9 — 6.6 19.8 — 12.4 33.1 15.9 41.5 19.0 46.6 — IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled • @ 25°C • @ 70°C • @ 85°C • @ 105°C IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks enabled • @ 25°C • @ 70°C • @ 85°C • @ 105°C IDD_STOP Notes 3 — • @ 105°C Unit mA 6 — 0.9 2.7 — 2.5 6.7 — 3.8 9.9 — 6.5 16.0 mA 6 — 1.4 4.2 — 3.0 8.0 — 4.3 11.2 — 7.0 17.2 — 1.0 2.8 — 3.9 9.9 — 6.0 15.0 — 10.0 24.4 — 0.5 1.4 — 2.4 5.8 — 3.7 8.7 — 6.3 14.1 — 19.5 30.0 mA Stop mode current at 3.0 V • @ 25°C • @ 70°C mA • @ 85°C • @ 105°C IDD_VLPS Very-low-power stop mode current at 3.0 V • @ 25°C • @ 70°C mA • @ 85°C • @ 105°C IDD_LLS3 Low leakage stop mode current at 3.0 V • @ 25°C μA Table continues on the next page... Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 15 NXP Semiconductors General Table 6. Power consumption operating behaviors (through VDD) (continued) Symbol Description • @ 70°C • @ 85°C Min. Typ. Max. — 140.8 210.8 — 265.6 386.8 — 579.4 807.4 Unit Notes • @ 105°C IDD_LLS2 IDD_VLLS3 Low leakage stop mode current at 3.0 V 8 • @ 25°C — 7.5 13.0 • @ 70°C — 42.7 72.7 • @ 85°C — 79.6 126.6 • @ 105°C — 176.3 256.3 — 16.1 24.1 — 120.5 175.5 — 227.4 321.9 — 481.9 665.4 μA Very low-leakage stop mode 3 current at 3.0 V • @ 25°C • @ 70°C μA • @ 85°C • @ 105°C IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V • @ 25°C 8 — 3.5 6.5 — 12.0 16.0 — 21.0 27.5 — 56.6 68.1 — 1.9 5.4 — 5.7 8.7 — 10.5 14.5 — 28.0 34.1 μA • @ 70°C • @ 85°C • @ 105°C IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V • @ 25°C • @ 70°C μA • @ 85°C • @ 105°C IDD_VLLS0 Very low-leakage stop mode 0 current with POR detect circuit enabled 8 — 0.726 1.7 — 5.7 7.2 — 10.7 13.2 — 26.1 30.6 μA • @ 25°C • @ 105°C • @ 85°C • @ 105°C IDD_VBAT Average current with RTC and 32 kHz disabled @ 3.0 V • @ 25°C μA — 0.255 0.319 Table continues on the next page... 16 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 General Table 6. Power consumption operating behaviors (through VDD) (continued) Symbol Description Min. Typ. Max. — 0.595 0.750 — 0.989 1.30 — 2.2 2.8 • @ 70°C • @ 85°C Unit Notes • @ 105°C IDD_VBAT Average current when CPU is not accessing RTC registers @ 1.8 V 9 μA • @ 25°C — 0.436 0.489 • @ 70°C — 0.724 0.897 — 1.1 1.4 — 2.0 2.6 • @ 85°C • @ 105°C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. 2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. 3. MCG configured for PEE mode. 4. 150 MHz core and system clock, 50 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. 5. 25 MHz core and system clock, 25 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. Code executing from flash. 7. MCG configured for BLPE mode. 8. By default, this mode has only 32 KB of SRAM enabled. 9. Includes 32 kHz oscillator current and RTC operation. Below table list the current consumption adders for different SRAM configurations from the LLS2/VLLS2 (TYP) IDD values using a 32 KB SRAM retention referenced in Table 6. Table 7. LLS2/VLLS2 additional Typical IDD current consumption Adders RAM array retained LLS2 VLLS2 @ 25°C @ 85°C @ 105°C Unit RAM2: 32 KB 0.5 10.8 21.3 µA RAM3: 32 KB 0.5 11.0 21.5 µA RAM4: 32 KB 0.4 10.7 21.0 µA RAM5: 128 KB 1.4 28.1 57.6 µA RAM6: 64 KB 0.6 15.2 30.5 µA RAM7: 192 KB 2.1 41.1 85.1 µA RAM8: 256 KB 2.8 53.0 109.9 µA RAM9: 256 KB 2.3 53.5 110.9 µA RAM2: 32 KB 0.5 9.1 19.7 µA RAM3: 32 KB 0.5 8.5 18.0 µA RAM4: 32 KB 0.5 8.1 16.8 µA Table continues on the next page... Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 17 NXP Semiconductors General Table 7. LLS2/VLLS2 additional Typical IDD current consumption Adders (continued) RAM array retained @ 25°C @ 85°C @ 105°C Unit RAM5: 128 KB 1.5 26.6 57.1 µA RAM6: 64KB 0.8 12.9 27.1 µA RAM7: 192KB 2.3 40.2 86.6 µA RAM8: 256 KB 3.0 52.9 114.3 µA RAM9: 256 KB 3.0 53.1 114.8 µA Table 8. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 µA IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. 52 52 52 52 52 52 µA IEREFSTEN4MHz External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 228 237 245 251 258 uA IIREFSTEN4MHz IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. nA VLLS1 440 490 540 560 570 580 VLLS3 440 490 540 560 570 580 LLS2 490 490 540 560 570 680 LLS3 490 490 540 560 570 680 VLPS 510 560 560 560 610 680 STOP 510 560 560 560 610 680 ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 µA IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 432 357 388 475 532 810 nA ILPUART LPUART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX µA Table continues on the next page... 18 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 General Table 8. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 data at 115200 baud rate. Includes selected clock source power consumption. 66 66 66 66 66 66 MCGIRCLK (4 MHz internal reference clock) 214 234 246 254 260 268 OSCERCLK (4 MHz external crystal) IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 µA 2.2.6 Electromagnetic Compatibility (EMC) specifications EMC measurements to IC-level IEC standards are available from NXP on request. 2.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions. 1. Go to nxp.com 2. Perform a keyword search for “EMC design.” 2.2.8 Capacitance attributes Table 9. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF 2.3 Switching specifications Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 19 NXP Semiconductors General 2.3.1 Device clock specifications Table 10. Device clock specifications Symbol Description Min. Max. Unit — 150 MHz Notes High Speed run mode fSYS System and core clock Normal run mode (and High Speed run mode unless otherwise specified above) fSYS System and core clock — 120 MHz System and core clock when Full Speed USB in operation 20 — MHz System and core clock when High Speed USB in operation 100 — MHz Bus clock — 75 MHz fB_CLK FlexBus clock — 75 MHz fFLASH Flash clock — 28 MHz fLPTMR LPTMR clock — 25 MHz fSYS_USBHS fBUS VLPR mode1 fSYS System and core clock — 4 MHz fBUS Bus clock — 4 MHz fB_CLK FlexBus clock — 4 MHz fFLASH Flash clock — 1 MHz fERCLK External reference clock — 16 MHz fLPTMR_pin LPTMR clock — 25 MHz fI2S_MCLK I2S master clock — 12.5 MHz fI2S_BCLK I2S bit clock — 4 MHz 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, LPUART, CMT, timers, and I2C signals. Table 11. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1, 2 NMI_b pin interrupt pulse width (analog filter enabled) — Asynchronous path 100 — ns Table continues on the next page... 20 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 General Table 11. General switching specifications (continued) Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) — Asynchronous path 50 — ns 3 External RESET_b input pulse width (digital glitch filter disabled) 100 — ns Port rise and fall time (high drive strength) • Slew enabled • 1.71 ≤ VDD ≤ 2.7V 4, 5 — 34 — 16 — 10 — 8 ns ns • 2.7 ≤ VDD ≤ 3.6V • Slew disabled • 1.71 ≤ VDD ≤ 2.7 V ns ns • 2.7 ≤ VDD ≤ 3.6 V Port rise and fall time (low drive strength) • Slew enabled • 1.71 ≤ VDD ≤ 2.7 V 6, 7 — 34 — 16 — 7 — 5 ns ns • 2.7 ≤ VDD ≤ 3.6 V • Slew disabled • 1.71 ≤ VDD ≤ 2.7 V ns ns • 2.7 ≤ VDD ≤ 3.6 V Port rise and fall time (high drive strength) • Slew enabled • 1.71 ≤ VDDIO_E ≤ 2.7 V 5, 8 — 34 — 16 — 7 — 5 ns ns • 2.7 ≤ VDDIO_E ≤ 3.6 V • Slew disabled • 1.71 ≤ VDDIO_E ≤ 2.7 V ns ns • 2.7 ≤ VDDIO_E ≤ 3.6 V Port rise and fall time (low drive strength) • Slew enabled • 1.71 ≤ VDDIO_E ≤ 2.7 V 7, 8 — 34 — 16 — 7 — 5 ns ns • 2.7 ≤ VDDIO_E ≤ 3.6 V • Slew disabled • 1.71 ≤ VDDIO_E ≤ 2.7 V ns ns • 2.7 ≤ VDDIO_E ≤ 3. 6V 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 21 NXP Semiconductors General 5. 6. 7. 8. 75 pF load. Ports A, B, C, and D. 25 pF load. Port E pins only. 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 12. Thermal operating requirements (for V-Temp range) Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C Notes 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + RθJA x chip power dissipation 2.4.2 Thermal attributes Table 13. Thermal attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) Description 169 MAPBGA Unit Notes Thermal resistance, junction to ambient (natural convection) 56.8 °C/W 1 RθJA Thermal resistance, junction to ambient (natural convection) 27.1 °C/W 1 Single-layer (1S) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 41 °C/W 1 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 22.4 °C/W 1 — RθJB Thermal resistance, junction to board 10.4 °C/W 2 — RθJC Thermal resistance, junction to case 7.1 °C/W 3 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 0.2 °C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification. 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 22 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 Debug trace timing specifications Table 14. Debug trace operating behaviors Symbol Description Min. Max. Unit Tcyc Clock period Frequency dependent MHz Twl Low pulse width 2 — ns Twh High pulse width 2 — ns Tr Clock and data rise time — 3 ns Tf Clock and data fall time — 3 ns Ts Data setup 1.5 — ns Th Data hold 1.0 — ns TRACECLK Tr Tf Twh Twl Tcyc Figure 4. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 5. Trace data specifications Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 23 NXP Semiconductors Peripheral operating requirements and behaviors 3.1.2 JTAG electricals Table 15. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 25 • Serial Wire Debug 0 50 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 20 — ns • Serial Wire Debug 10 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.0 — ns J7 TCLK low to boundary scan output data valid — 28 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 19 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns Unit J2 TCLK cycle period J3 TCLK clock pulse width Table 16. JTAG full voltage range electricals Symbol J1 Description Min. Max. Operating voltage 1.71 3.6 TCLK frequency of operation V MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 20 • Serial Wire Debug 0 40 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.5 — ns J2 TCLK cycle period J3 TCLK clock pulse width Table continues on the next page... 24 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 16. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.0 — ns J7 TCLK low to boundary scan output data valid — 30.6 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.0 — ns J11 TCLK low to TDO data valid — 19.0 ns J12 TCLK low to TDO high-Z — 17.0 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J2 J3 J3 TCLK (input) J4 J4 Figure 6. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 7. Boundary scan (JTAG) timing Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 25 NXP Semiconductors Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 8. Test Access Port timing TCLK J14 J13 TRST Figure 9. TRST timing 3.2 Clock modules 3.2.1 MCG specifications Table 17. MCG specifications Symbol Description Min. Typ. Max. Unit fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C — 32.768 — kHz fints_t Internal reference frequency (slow clock) — user trimmed 31.25 — 39.0625 kHz Notes Table continues on the next page... 26 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 17. MCG specifications (continued) Symbol Min. Typ. Max. Unit Internal reference (slow clock) current — 20 — µA [O: ] Internal reference (slow clock) startup time — 32 — µs Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM — ± 0.3 ± 0.6 %fdco 1 Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM only — ± 0.2 ± 0.5 %fdco 1 Iints tirefsts Description Notes Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — ±1 ±2 %fdco 1 Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C — ± 0.5 ±1 %fdco 1 fintf_ft Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25°C — 4 — MHz fintf_t Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C 3 — 5 MHz Internal reference (fast clock) current — 25 — µA tirefsts Iintf [L: ] Internal reference startup time (fast clock) — 10 15 µs floc_low Loss of external clock minimum frequency — RANGE = 00 (3/5) x fints_t — — kHz (16/5) x fints_t — — kHz ext clk freq: above (3/5)fint never reset ext clk freq: between (2/5)fint and (3/5)fint maybe reset (phase dependency) ext clk freq: below (2/5)fint always reset floc_high Loss of external clock minimum frequency — RANGE = 01, 10, or 11 ext clk freq: above (16/5)fint never reset ext clk freq: between (15/5)fint and (16/5)fint maybe reset (phase dependency) ext clk freq: below (15/5)fint always reset FLL ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz fdco_ut DCO output frequency range — untrimmed 16.0 23.04 26.66 MHz 32.0 46.08 53.32 48.0 69.12 79.99 Low range 2 (DRS=00, DMX32=0) 640 × fints_ut Mid range (DRS=01, DMX32=0) 1280 × fints_ut Mid-high range (DRS=10, DMX32=0) Table continues on the next page... Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 27 NXP Semiconductors Peripheral operating requirements and behaviors Table 17. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes 64.0 92.16 106.65 18.3 26.35 30.50 36.6 52.70 60.99 54.93 79.09 91.53 73.23 105.44 122.02 20 20.97 25 MHz 3, 4 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.98 — MHz — 180 — — 150 — — — 1 1920 × fints_ut High range (DRS=11, DMX32=0) 2560 × fints_ut Low range (DRS=00, DMX32=1) 732 × fints_ut Mid range (DRS=01, DMX32=1) 1464 × fints_ut Mid-high range (DRS=10, DMX32=1) 2197 × fints_ut High range (DRS=11, DMX32=1) 2929 × fints_ut fdco DCO output frequency range Low range (DRS=00) 640 × ffll_ref Mid range (DRS=01) 1280 × ffll_ref Mid-high range (DRS=10) 1920 × ffll_ref High range (DRS=11) 2560 × ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS=00) 5, 6 732 × ffll_ref Mid range (DRS=01) 1464 × ffll_ref Mid-high range (DRS=10) 2197 × ffll_ref High range (DRS=11) 2929 × ffll_ref Jcyc_fll FLL period jitter • fDCO = 48 MHz • fDCO = 98 MHz tfll_acquire FLL target frequency acquisition time ps ms 7 PLL Table continues on the next page... 28 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 17. MCG specifications (continued) Symbol fpll_ref Description PLL reference frequency range fvcoclk_2x VCO output frequency fvcoclk PLL output frequency fvcoclk_90 PLL quadrature output frequency Ipll PLL operating current • VCO @ 176 MHz (fpll_ref = 8 MHz, VDIV multiplier = 22, PRDIV divide=1) Ipll PLL operating current • VCO @ 360 MHz (fpll_ref = 8 MHz, VDIV multiplier = 45, PRDIV divide=1) Jcyc_pll Jacc_pll Dunl tpll_lock Min. Typ. Max. Unit 8 — 16 MHz 180 90 90 — — — 360 180 180 MHz MHz MHz — 1.1 — mA — 2 — mA PLL period jitter (RMS) — 100 — ps • fvco = 360 MHz — 75 — ps PLL accumulated jitter over 1µs (RMS) 8 9 • fvco = 180 MHz — 600 — ps • fvco = 360 MHz — 300 — ps ± 4.47 — ± 5.97 Lock detector detection time 8 9 • fvco = 180 MHz Lock exit frequency tolerance Notes — — 10-6 150 × + 1075(1/ fpll_ref) % s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0). 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 29 NXP Semiconductors Peripheral operating requirements and behaviors 3.2.2 IRC48M specifications Table 18. IRC48M specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDD48M Supply current — 520 — μA firc48m Internal reference frequency — 48 — MHz — ± 0.5 ± 1.0 %firc48m — ± 0.5 ± 1.5 — ± 0.5 ± 1.0 %firc48m Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at low voltage (VDD=1.71 V-1.89 V) over temperature • Regulator disable (USB_CLK_RECOVER_IRC_EN[REG_EN]=0) • Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89 V-3.6 V) over temperature • Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) Δfirc48m_cl Closed loop total deviation of IRC48M frequency over voltage and temperature — — ± 0.1 %fhost Jcyc_irc48m Period Jitter (RMS) — 35 150 ps Startup time — 2 3 μs tirc48mst Notes 1 2 1. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). 2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by one of the following settings: • USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or • MCG_C7[OSCSEL]=10, or • SIM_SOPT2[PLLFLLSEL]=11 3.2.3 Oscillator electrical specifications 3.2.3.1 Oscillator DC electrical specifications Table 19. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC Supply current — low-power mode (HGO=0) Notes 1 • 32 kHz — 600 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA — 1.2 — mA Table continues on the next page... 30 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 19. Oscillator DC electrical specifications (continued) Symbol Description • 24 MHz Min. Typ. Max. Unit — 1.5 — mA Notes • 32 MHz IDDOSC Supply current — high gain mode (HGO=1) 1 • 32 kHz — 7.5 — μA • 4 MHz — 500 — μA • 8 MHz (RANGE=01) — 650 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3.25 — mA • 32 MHz — 4 — mA Cx EXTAL load capacitance — — — Cy XTAL load capacitance — — — RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ — 0 — kΩ Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V RS 2, 3 2, 3 2, 4 Series resistor — high-frequency, high-gain mode (HGO=1) 5 Vpp 1. VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf 2. See crystal or resonator manufacturer's recommendation Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 31 NXP Semiconductors Peripheral operating requirements and behaviors 3. Cx,Cy can be provided by using either the integrated capacitors or by using external components. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.2.3.2 Symbol Oscillator frequency specifications Table 20. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency — highfrequency mode (low range) (MCG_C2[RANGE]=01) 3 — 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 — 32 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 750 — ms Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — 250 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.6 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) — 1 — ms tcst Notes 1, 2 1. Proper PC board layout procedures must be followed to achieve specifications. 2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.2.4 32 kHz oscillator electrical characteristics 3.2.4.1 32 kHz oscillator DC electrical specifications Table 21. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VBAT Supply voltage 1.71 — 3.6 V Table continues on the next page... 32 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 21. 32kHz oscillator DC electrical specifications (continued) Symbol Min. Typ. Max. Unit Internal feedback resistor — 100 — MΩ Cpara Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation — 0.6 — V RF Description 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.2.4.2 Symbol 32 kHz oscillator frequency specifications Table 22. 32 kHz oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal — 32.768 — kHz Crystal start-up time — 1000 — ms 1 fec_extal32 Externally provided input clock frequency — 32.768 — kHz 2 vec_extal32 Externally provided input clock amplitude 700 — VBAT mV 2, 3 fosc_lo tstart Description Notes 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 3.3 Memories and memory interfaces 3.3.1 QuadSPI AC specifications • All data is based on a negative edge data launch from the device and a positive edge data capture, as shown in the timing diagrams in this section. • Measurements are with a load of 15 pf (1.8 V) and 35 pf (3 V) on output pins. Input slew: 1 ns • Timings assume a setting of 0x0000_000x for QuadSPI _SMPR register (see the reference manual for details). Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 33 NXP Semiconductors Peripheral operating requirements and behaviors The following table lists the QuadSPI delay chain read/write settings. Refer the device reference manual for register and bit descriptions. Table 23. QuadSPI delay chain read/write settings Mode QuadSPI registers Notes QuadSPI_MCR[DQ S_EN] QuadSPI_SOCCR[ SOCCFG] QuadSPI_MCR[SC LKCFG] QuadSPI_FLSHCR[ TDH] SDR Yes 3Fh 5 No Delay of 63 buffer and 64 mux DDR Yes 3Fh 1 2 Delay of 63 buffer and 64 mux Hyperflash RDS driven from Flash 0h No 2 Delay of 1 mux SDR mode 1 2 3 Clock Tck SFCK Tcss Tcsh CS Tis Tih Data in Figure 10. QuadSPI input timing (SDR mode) diagram NOTE • The below timing values are with default settings for sampling registers like QuadSPI_SMPR. • A negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad. • The below timing are for a load of 15 pf (1.8 V) and 35 pf (3 V) or output pads 34 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors • All board delays need to be added appropriately • Input hold time being negative does not have any implication or max achievable frequency Table 24. QuadSPI input timing (SDR mode) specifications Symbol Parameter Value Min Unit Max Tis Setup time for incoming data 4 - ns Tih Hold time requirement for incoming data 1.5 - ns 1 2 3 Clock Tck SFCK Tcss Tcsh CS Toh Tov Data out Figure 11. QuadSPI output timing (SDR mode) diagram Table 25. QuadSPI output timing (SDR mode) specifications Symbol Parameter Value Min Unit Max Tov Output Data Valid - 2.8 ns Toh Output Data Hold -1.4 - ns Tck SCK clock period - 100 MHz Tcss Chip select output setup time 2 - ns Tcsh Chip select output hold time -1 - ns NOTE For any frequency setup and hold specifications of the memory should be met. DDR Mode Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 35 NXP Semiconductors Peripheral operating requirements and behaviors 1 2 3 Clock Tck SFCK Tcss Tcsh CS Tih Tis Data in Figure 12. QuadSPI input timing (DDR mode) diagram NOTE • Numbers are for a load of 15 pf (1.8 V) and 35 pf (3 V) • The numbers are for setting of hold condition in register QuadSPI_SMPR[DDRSNP] Table 26. QuadSPI input timing (DDR mode) specifications Symbol Parameter Value Min Tis Setup time for incoming data Unit Max 4 (Without learning) ns 1 (With learning) Tih Hold time requirement for incoming data 1 1.5 - ns 2 3 Clock Tck SFCK Tcss Tcsh CS Tov Toh Data out Figure 13. QuadSPI output timing (DDR mode) diagram 36 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 27. QuadSPI output timing (DDR mode) specifications Symbol Parameter Value Min Unit Max Tov Output Data Valid - 4.5 ns Toh Output Data Hold 1.5 - ns Tck SCK clock period - 75 (with learning) MHz - 45 (without learning) Tcss Chip select output setup time 2 - Clk(sck) Tcsh Chip select output hold time -1 - Clk(sck) Hyperflash mode RDS TsMIN ThMIN DI[7:0] Figure 14. QuadSPI input timing (Hyperflash mode) diagram Table 28. QuadSPI input timing (Hyperflash mode) specifications Symbol Parameter Value Min Unit Max TsMIN Setup time for incoming data 2 - ns ThMIN Hold time requirement for incoming data 2 - ns Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 37 NXP Semiconductors Peripheral operating requirements and behaviors CK CK 2 Tclk SKMAX Tclk SKMIN THO TDVO Output Invalid Data Figure 15. QuadSPI output timing (Hyperflash mode) diagram Table 29. QuadSPI output timing (Hyperflash mode) specifications Symbol Parameter Value Min Unit Max TdvMAX Output Data Valid - 4.3 ns Tho Output Data Hold 1.3 - ns TclkSKMAX Ck to Ck2 skew max - T/4 + 0.5 ns TclkSKMIN Ck to Ck2 skew min T/4 - 0.5 - ns NOTE Maximum clock frequency = 75 MHz. 3.3.2 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 3.3.2.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. 38 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 30. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm8 thversscr Program Phrase high-voltage time — 7.5 18 μs Erase Flash Sector high-voltage time — 13 113 ms 1 — 413 3616 ms 1 Notes thversblk512k Erase Flash Block high-voltage time for 512 KB Notes 1. Maximum time based on expectations at cycling end-of-life. 3.3.2.2 Symbol Flash timing specifications — commands Table 31. Flash command timing specifications Description Min. Typ. Max. Unit — — 1.8 ms Read 1s Block execution time trd1blk512k • 512 KB program flash trd1sec4k Read 1s Section execution time (4 KB flash) — — 100 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs Erase Flash Block execution time tersblk512k — 435 3700 ms Erase Flash Sector execution time — 15 115 ms Program Section execution time (1 KB flash) — 5 — ms trd1all Read 1s All Blocks execution time — — 6.7 ms trdonce Read Once execution time — — 30 μs Program Once execution time — 90 — μs tersall Erase All Blocks execution time — 1750 14,800 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 1750 14,800 ms 2 tersscr tpgmsec1k tpgmonce • 512 KB program flash 2 2 1 Swap Control execution time tswapx01 • control code 0x01 — 200 — μs tswapx02 • control code 0x02 — 90 150 μs tswapx04 • control code 0x04 — 90 150 μs tswapx08 • control code 0x08 — — 30 μs tswapx10 • control code 0x10 — 90 150 μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 39 NXP Semiconductors Peripheral operating requirements and behaviors 3.3.2.3 Flash high voltage current behaviors Table 32. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 3.3.2.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 3.5 7.5 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 33. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3.3.3 Flexbus switching specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 34. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation — FB_CLK MHz 1/FB_CLK — ns Address, data, and control output valid — 11.8 ns Address, data, and control output hold 1.0 — ns FB1 Clock period FB2 FB3 Notes 1 Table continues on the next page... 40 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 34. Flexbus limited voltage range switching specifications (continued) Num Description Min. Max. Unit FB4 Data and FB_TA input setup 11.9 — ns FB5 Data and FB_TA input hold 0.0 — ns Notes 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 35. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Frequency of operation — FB_CLK MHz 1/FB_CLK — ns Address, data, and control output valid — 12.6 ns FB3 Address, data, and control output hold 1.0 — ns FB4 Data and FB_TA input setup 12.5 — ns FB5 Data and FB_TA input hold 0 — ns FB1 Clock period FB2 Notes 1 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 41 NXP Semiconductors Peripheral operating requirements and behaviors Read Timing Parameters S0 S1 S2 S3 S0 FB1 FB_CLK FB5 FB_A[Y] Address FB4 FB2 FB_D[X] FB3 Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn electricals_read.svg FB4 FB_BEn FB5 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ S0 S1 S2 S3 S0 Figure 16. FlexBus read timing diagram 42 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Write Timing Parameters FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 electricals_write.svg FB4 TSIZ Figure 17. FlexBus write timing diagram 3.3.4 SDRAM controller specifications Following figure shows SDRAM read cycle. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 43 NXP Semiconductors Peripheral operating requirements and behaviors 0 1 D0 2 3 4 5 6 7 8 9 10 11 12 13 CLKOUT D3 D1 Row A[23:0] Column D4 SRAS D2 SCAS 1 D4 DRAMW D5 D[31:0] D6 SDRAM_CS[1:0] D4 BS[3:0] ACTV 1DACR[CASL] NOP READ NOP PRE =2 Figure 18. SDRAM read timing diagram Table 36. SDRAM Timing (Full voltage range) NUM Characteristic 1 Symbol Min Max Operating voltage 1.71 3.6 V Frequency of operation Unit — CLKOUT MHz 1/CLKOUT — ns 2 CLKOUT high to SDRAM address valid tCHDAV - 11.2 ns D2 CLKOUT high to SDRAM control valid tCHDCV 11.1 ns D3 CLKOUT high to SDRAM address invalid tCHDAI 1.0 - ns D4 CLKOUT high to SDRAM control invalid tCHDCI 1.0 - ns D5 SDRAM data valid to CLKOUT high tDDVCH 12.0 - ns D6 CLKOUT high to SDRAM data invalid tCHDDI 1.0 - ns D73 CLKOUT high to SDRAM data valid tCHDDVW - 12.0 ns D83 CLKOUT high to SDRAM data invalid tCHDDIW 1.0 - ns D0 Clock period D1 1. All timing specifications are based on taking into account, a 25 pF load on the SDRAM output pins. 2. CLKOUT is same as FB_CLK, maximum frequency can be 75 MHz 44 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors 3. D7 and D8 are for write cycles only. Table 37. SDRAM Timing (Limited voltage range) NUM Characteristic 1 Symbol Min Max Operating voltage 2.7 3.6 V Frequency of operation — CLKOUT MHz 1/CLKOUT — ns 2 - 11.1 ns 11.1 ns Unit D0 Clock period D1 CLKOUT high to SDRAM address valid tCHDAV D2 CLKOUT high to SDRAM control valid tCHDCV D3 CLKOUT high to SDRAM address invalid tCHDAI 1.0 - ns D4 CLKOUT high to SDRAM control invalid tCHDCI 1.0 - ns D5 SDRAM data valid to CLKOUT high tDDVCH 11.3 - ns D6 CLKOUT high to SDRAM data invalid tCHDDI 1.0 - ns D73 CLKOUT high to SDRAM data valid tCHDDVW - 11.1 ns D83 CLKOUT high to SDRAM data invalid tCHDDIW 1.0 - ns 1. All timing specifications are based on taking into account, a 25 pF load on the SDRAM output pins. 2. CLKOUT is same as FB_CLK, maximum frequency can be 75 MHz 3. D7 and D8 are for write cycles only. Following figure shows an SDRAM write cycle. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 45 NXP Semiconductors Peripheral operating requirements and behaviors 0 D0 1 2 3 4 5 6 7 8 9 10 11 12 CLKOUT D3 D1 Row A[23:0] Column SRAS D2 SCAS1 D4 DRAMW D7 D[31:0] D8 SDRAM_CS[1:0] D2 D4 D4 BS[3:0] D4 ACTV 1 NOP WRITE NOP PALL DACR[CASL] = 2 Figure 19. SDRAM write timing diagram 3.4 Analog 3.4.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 38 and Table 39 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 46 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors 3.4.1.1 ADC operating conditions Table 38. ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.6 V ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage • 16-bit differential mode VREFL — 31/32 × VREFH V • All other modes VREFL — — 4 5 pF — 2 5 kΩ CADIN Input capacitance RADIN Input series resistance RAS Analog source resistance (external) • 8-bit / 10-bit / 12-bit modes Notes VREFH 13-bit / 12-bit modes 3 fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion ≤ 13-bit mode clock frequency 1.0 — 18.0 MHz Crate ADC conversion ≤ 13-bit modes rate No ADC hardware averaging 4 5 20.000 — 818.330 kS/s Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 47 NXP Semiconductors Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 20. ADC input impedance equivalency diagram 3.4.1.2 ADC electrical characteristics Table 39. ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description Conditions1 IDDA_ADC Supply current ADC asynchronous clock source fADACK Sample Time TUE DNL INL Min. Typ.2 Max. Notes 0.215 — 1.7 mA 3 • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 • <12-bit modes — ±1.4 ±2.1 Differential nonlinearity • 12-bit modes — ±0.7 –1.1 to +1.9 • <12-bit modes — ±0.2 • 12-bit modes — ±1.0 Integral non-linearity Unit –0.3 to 0.5 –2.7 to +1.9 Table continues on the next page... 48 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 39. ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description Conditions1 Min. Typ.2 Max. — ±0.5 –0.7 to +0.5 • 12-bit modes — –4 –5.4 • <12-bit modes — –1.4 –1.8 • ≤13-bit modes — — ±0.5 • <12-bit modes EFS EQ ENOB Full-scale error Quantization error Effective number of bits Unit Notes LSB4 VADIN = VDDA5 LSB4 16-bit differential mode 6 • Avg = 32 12.8 14.5 • Avg = 4 11.9 13.8 — — bits bits 16-bit single-ended mode • Avg = 32 • Avg = 4 THD Total harmonic distortion 12.2 13.9 11.4 13.1 — — 16-bit differential mode • Avg = 32 bits bits dB — -94 7 — dB 16-bit single-ended mode • Avg = 32 SFDR Spurious free dynamic range — -85 82 95 16-bit differential mode • Avg = 32 16-bit single-ended mode 78 — — dB — dB 7 90 • Avg = 32 EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device VTEMP25 Temp sensor voltage 25 °C 1.55 1.62 1.69 mV/°C 8 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 49 NXP Semiconductors Peripheral operating requirements and behaviors 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 15.00 14.70 14.40 14.10 ENOB 13.80 13.50 13.20 12.90 12.60 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 12.30 12.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 21. Typical ENOB vs. ADC_CLK for 16-bit differential mode 3.4.2 CMP and 6-bit DAC electrical specifications Table 40. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA VAIN Analog input voltage VSS – 0.3 — VDD V VAIO Analog input offset voltage — — 20 mV • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV VH Analog comparator hysteresis1 VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns — — 40 μs — 7 — μA Analog comparator initialization IDAC6b delay2 6-bit DAC current adder (enabled) Table continues on the next page... 50 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 40. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 0.08 0.07 CMP Hystereris (V) 0.06 HYSTCTR Setting 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 22. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 51 NXP Semiconductors Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP Hysteresis (V) 0.12 HYSTCTR Setting 0.1 00 01 10 11 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 23. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.4.3 12-bit DAC electrical characteristics 3.4.3.1 Symbol 12-bit DAC operating requirements Table 41. 12-bit DAC operating requirements Desciption VDDA Supply voltage VDACR Reference voltage Min. Max. Unit Notes 3.6 V 1.13 3.6 V 1 2 CL Output load capacitance — 100 pF IL Output load current — 1 mA 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. 52 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors 3.4.3.2 Symbol 12-bit DAC operating behaviors Table 42. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.7 1 μs 1 tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) — low-power mode and highspeed mode Vdacoutl DAC output voltage range low — highspeed mode, no load, DAC set to 0x000 — — 100 mV Vdacouth DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF VDACR −100 — VDACR mV INL Integral non-linearity error — high speed mode — — ±8 LSB 2 DNL Differential non-linearity error — VDACR > 2 V — — ±1 LSB 3 DNL Differential non-linearity error — VDACR = VREF_OUT — — ±1 LSB 4 — ±0.4 ±0.8 %FSR 5 Gain error — ±0.1 ±0.6 %FSR 5 Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB TCO Temperature coefficient offset voltage — 3.7 — μV/C TGE Temperature coefficient gain error — 0.000421 — %FSR/C AC Offset aging coefficient — — 100 μV/yr Rop Output resistance (load = 3 kΩ) — — 250 Ω SR Slew rate -80h→ F7Fh→ 80h VOFFSET Offset error EG PSRR 1. 2. 3. 4. 5. V/μs • High power (SPHP) 1.2 1.7 — • Low power (SPLP) 0.05 0.12 — — — -80 CT Channel to channel cross talk BW 3dB bandwidth 6 dB kHz • High power (SPHP) 550 — — • Low power (SPLP) 40 — — Settling within ±1 LSB The INL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 53 NXP Semiconductors Peripheral operating requirements and behaviors 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 24. Typical INL error vs. digital code 54 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 25 -40 55 85 105 125 Temperature °C Figure 25. Offset at half scale vs. temperature 3.4.4 Voltage reference electrical specifications Table 43. VREF full-range operating requirements Symbol Description VDDA Supply voltage TA Temperature CL Output load capacitance Min. Max. Unit 3.6 V Operating temperature range of the device °C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference. 2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 55 NXP Semiconductors Peripheral operating requirements and behaviors Table 44. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes V 1 Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.190 1.195 1.200 Vout Voltage reference output — user trim 1.1945 1.195 1.1955 V 1 Vstep Voltage reference trim step — 0.5 — mV 1 Vtdrift Temperature drift (Vmax -Vmin across the full temperature range) — 2 15 mV 1 Ibg Bandgap only current — 60 80 µA 1 Ilp Low-power buffer current — 180 360 uA 1 Ihp High-power buffer current — 480 960 mA 1 µV 1, 2 ΔVLOAD Load regulation • current = ± 1.0 mA Tstup Buffer startup time Tchop_osc_st Internal bandgap start-up delay with chop oscillator enabled up Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 200 — — — 100 µs — — 35 ms — — 0.5 2 mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load. Table 45. VREF limited-range operating requirements Symbol Description Min. Max. Unit TA Temperature 0 50 °C Notes Table 46. VREF limited-range operating behaviors Symbol Vout Description Voltage reference output with factory trim Min. Max. Unit 1.173 1.225 V Notes 3.5 Timers See General switching specifications. 3.6 Communication interfaces 56 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors 3.6.1 USB Voltage Regulator electrical specifications Table 47. USB VREG electrical specifications Symbol VREG_IN0 Description Min. Typ.1 Max. Unit Notes Regulator selectable input supply voltages 2.7 — 5.5 V 2 Quiescent current — Run mode, load current equal zero, input supply (VREG_IN*) > 3.6 V — VREG_IN1 IDDon VREG_IN0 μA — VREG_IN1 — 157 — 157 IDDstby VREG_IN0 Quiescent current — Standby mode, load current equal zero 2 — 2 — — 680 — — 920 — — — μA VREG_IN1 IDDoff VREG_IN0 VREG_IN1 Quiescent current — Shutdown mode • VREG_IN*= 5.0 V and temperature=25 °C nA ILOADrun Maximum load current — Run mode — — 150 mA ILOADstby Maximum load current — Standby mode — — 1 mA 300 — — mV 3 3.3 3.6 V 2.1 2.8 3.6 V 1.76 2.2 8.16 μF 1 — 100 mΩ VDROPOUT Regulator drop-out voltage — Run mode at maximum load current with inrush current limit disabled VREG_OUT Regulator programmable output target voltage — Selected input supply > programmed output target voltage + VDROPOUT 3 4 • Run mode • Standby mode COUT External output capacitor ESR External output capacitor equivalent series resistance ILIM Short circuit current — 350 — mA 5 IINRUSH Inrush current limit 40 — 100 mA 6, 7, 8, 9 1. Typical values assume the selected input supply is 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operation range is 2.7 V to 5.5 V; tolerance voltage is up to 6 V. 3. 150mA is inclusive of the run mode current of the on-chip USB modules. Available load outside of the chip depends on USB operation and device power dissipation limits. 4. The target voltage for the regulator is programmable, accounting for the range of the max and min values. 5. Current limit disabled. 6. Current limit should be disabled after the powers have stabilized to allow full functionality of the regulator. 7. Limited Characterization 8. IINRUSH with VREGINx=4.0 V to 5.5 V 9. Total current load on startup should be less than IINRUSH min over full input voltage range of the regulator. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 57 NXP Semiconductors Peripheral operating requirements and behaviors 3.6.2 USB Full Speed Transceiver and High Speed PHY specifications This section describes the USB0 port Full Speed/Low Speed transceiver and USB1 port USB-PHY High Speed Phy parameters. The high speed phy is capable of full and low speed as well. The USB0 (FS/LS Transceiver) and USB1 ((USB HS/FS/LS) meet the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 Specification with the amendments below. • USB ENGINEERING CHANGE NOTICE • Title: 5V Short Circuit Withstand Requirement Change • Applies to: Universal Serial Bus Specification, Revision 2.0 • Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000 • USB ENGINEERING CHANGE NOTICE • Title: Pull-up/Pull-down resistors • Applies to: Universal Serial Bus Specification, Revision 2.0 • USB ENGINEERING CHANGE NOTICE • Title: Suspend Current Limit Changes • Applies to: Universal Serial Bus Specification, Revision 2.0 • On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification • Revision 2.0 version 1.1a July 27, 2012 • Battery Charging Specification (available from USB-IF) • Revision 1.2 (including errata and ECNs through March 15, 2012), March 15, 2012 USB1_VBUS pin is a detector function which is 5v tolerant and complies with the above specifications without needing any external voltage division components. 3.6.3 USB DCD electrical specifications Table 48. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC, VDM_SRC USB_DP and USB_DM source voltages (up to 250 μA) 0.5 — 0.7 V Threshold voltage for logic high 0.8 — 2.0 V 7 10 13 μA VLGC IDP_SRC USB_DP source current Table continues on the next page... 58 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 48. USB DCD electrical specifications (continued) Symbol Description Min. Typ. Max. Unit IDM_SINK, IDP_SINK USB_DM and USB_DP sink currents 50 100 150 μA RDM_DWN D- pulldown resistance for data pin contact detect 14.25 — 24.8 kΩ VDAT_REF Data detect voltage 0.25 0.33 0.4 V 3.6.4 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 49. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation — 30 MHz 2 x tBUS — ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 2 — ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 2 — ns 2 DS5 DSPI_SCK to DSPI_SOUT valid — 15.0 ns DS6 DSPI_SCK to DSPI_SOUT invalid 1.0 — ns DS7 DSPI_SIN to DSPI_SCK input setup 15.8 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 59 NXP Semiconductors Peripheral operating requirements and behaviors DSPI_PCSn DS3 DSPI_SCK DS7 (CPOL=0) DSPI_SIN DS1 DS2 DS4 DS8 First data DSPI_SOUT Data Last data DS5 First data DS6 Data Last data Figure 26. DSPI classic SPI timing — master mode Table 50. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DS12 DS13 Min. Max. Unit 2.7 3.6 V — 1 15 MHz 4 x tBUS — ns (tSCK/2) − 2 (tSCK/2) + 2 ns DSPI_SCK to DSPI_SOUT valid — 23.0 ns DSPI_SCK to DSPI_SOUT invalid 0 — ns DSPI_SIN to DSPI_SCK input setup 2.7 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7.0 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 13 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 13 ns 1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example, when bus clock is 60MHz, SPI clock should not be greater than 10MHz. 60 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DS12 DSPI_SOUT First data DS13 DS16 DS11 Last data Data DS14 DSPI_SIN First data Data Last data Figure 27. DSPI classic SPI timing — slave mode Table 51. Master mode DSPI3 timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation — 60 MHz 2 x tBUS — ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 2 — ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 2 — ns 2 DS5 DSPI_SCK to DSPI_SOUT valid — 9.1 ns DS6 DSPI_SCK to DSPI_SOUT invalid 1.0 — ns DS7 DSPI_SIN to DSPI_SCK input setup 7.8 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. Table 52. Slave mode DSPI3 timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation — 30 1 MHz 4 x tBUS — ns (tSCK/2) − 2 (tSCK/2) + 2 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid — 16.0 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2.7 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7.0 — ns Table continues on the next page... Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 61 NXP Semiconductors Peripheral operating requirements and behaviors Table 52. Slave mode DSPI3 timing (limited voltage range) (continued) Num Description Min. Max. Unit DS15 DSPI_SS active to DSPI_SOUT driven — 13 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 13 ns 1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example, when bus clock is 60MHz, SPI clock should not be greater than 10MHz. 3.6.5 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 53. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit Notes 1.71 3.6 V 1 — 15 MHz 4 x tBUS — ns DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 4 — ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 4 — ns 3 DS5 DSPI_SCK to DSPI_SOUT valid — 16 ns DS6 DSPI_SCK to DSPI_SOUT invalid 1.0 — ns DS7 DSPI_SIN to DSPI_SCK input setup 19.1 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. 62 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors DSPI_PCSn DS3 DS4 DS8 DS7 (CPOL=0) DS1 DS2 DSPI_SCK DSPI_SIN Data First data DSPI_SOUT Last data DS5 DS6 First data Data Last data Figure 28. DSPI classic SPI timing — master mode Table 54. Slave mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V — 7.5 MHz 8 x tBUS — ns (tSCK/2) - 4 (tSCK/2) + 4 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid — 23.1 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2.6 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7.0 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 13.0 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 13.0 ns DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Data Last data DS14 First data Data Last data Figure 29. DSPI classic SPI timing — slave mode Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 63 NXP Semiconductors Peripheral operating requirements and behaviors Table 55. Master mode DSPI3 timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V — 40 MHz 2 x tBUS — ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 2 — ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 2 — ns 2 DS5 DSPI_SCK to DSPI_SOUT valid — 9.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid 1.0 — ns DS7 DSPI_SIN to DSPI_SCK input setup 10.5 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0.0 — ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. Table 56. Slave mode DSPI3 timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V — 20 MHz 4 x tBUS — ns (tSCK/2) - 2 (tSCK/2) + 2 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid — 18.2 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0.0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2.7 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7.0 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 13.0 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 13.0 ns Notes> 1 1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,when bus clock is 60MHz, SPI clock should not be greater than 10MHz. 3.6.6 Inter-Integrated Circuit Interface (I2C) timing Table 57. I 2C timing Characteristic SCL Clock Frequency Symbol fSCL Standard Mode Fast Mode Minimum Maximum Minimum Maximum 0 100 0 400 Unit kHz Table continues on the next page... 64 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 57. I 2C timing (continued) Characteristic Symbol Standard Mode Fast Mode Minimum Maximum Minimum Maximum Unit Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 — 0.6 — µs LOW period of the SCL clock tLOW 4.7 — 1.25 — µs HIGH period of the SCL clock tHIGH 4 — 0.6 — µs Set-up time for a repeated START condition tSU; STA 4.7 — 0.6 — µs Data hold time for I2C bus devices tHD; DAT 01 3.452 03 0.91 µs Data set-up time tSU; DAT 2504 — 1002, 5 — ns Rise time of SDA and SCL signals tr — 1000 20 +0.1Cb6 300 ns Fall time of SDA and SCL signals tf — 300 20 +0.1Cb5 300 ns Set-up time for STOP condition tSU; STO 4 — 0.6 — µs Bus free time between STOP and START condition tBUF 4.7 — 1.3 — µs Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. Input signal Slew = 10 ns and Output Load = 50 pF 4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 6. Cb = total capacitance of the one bus line in pF. Table 58. I 2C 1 Mbps timing Characteristic Symbol Minimum Maximum Unit MHz SCL Clock Frequency fSCL 0 11 Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 0.26 — µs LOW period of the SCL clock tLOW 0.5 — µs HIGH period of the SCL clock tHIGH 0.26 — µs Set-up time for a repeated START condition tSU; STA 0.26 — µs Data hold time for I2C bus devices tHD; DAT 0 — µs Data set-up time tSU; DAT 50 Rise time of SDA and SCL signals Fall time of SDA and SCL signals tr tf — ns ,2 120 ns 2 120 ns 20 +0.1Cb 20 +0.1Cb Table continues on the next page... Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 65 NXP Semiconductors Peripheral operating requirements and behaviors Table 58. I 2C 1 Mbps timing (continued) Characteristic Symbol Minimum Maximum Unit Set-up time for STOP condition tSU; STO 0.26 — µs Bus free time between STOP and START condition tBUF 0.5 — µs Pulse width of spikes that must be suppressed by the input filter tSP 0 50 ns 1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across the full voltage range. 2. Cb = total capacitance of the one bus line in pF. SDA tf tSU; DAT tr tLOW tf tHD; STA tr tSP tBUF SCL S HD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 30. Timing definition for devices on the I2C bus 3.6.7 LPUART switching specifications See General switching specifications. 3.6.8 SDHC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 59. SDHC full voltage range switching specifications Num Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25/45 MHz fpp Clock frequency (MMC full speed\high speed) 0 25/45 MHz fOD Clock frequency (identification mode) 0 400 kHz Table continues on the next page... 66 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors Table 59. SDHC full voltage range switching specifications (continued) Num Symbol Description Min. Max. Unit SD2 tWL Clock low time 7 — ns SD3 tWH Clock high time 7 — ns SD4 tTLH Clock rise time — 3 ns SD5 tTHL Clock fall time — 3 ns SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) 0 8.1 ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 tISU SDHC input setup time 5 — ns SD8 tIH SDHC input hold time 0 — ns Table 60. SDHC limited voltage range switching specifications Num Symbol Description Min. Max. Unit Operating voltage 2.7 3.6 V Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz fOD Clock frequency (identification mode) 0 400 kHz SD2 tWL Clock low time 7 — ns SD3 tWH Clock high time 7 — ns SD4 tTLH Clock rise time — 3 ns SD5 tTHL Clock fall time — 3 ns SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) 0 7 ns SD7 tISU SDHC input setup time 5 — ns SD8 tIH SDHC input hold time 0 — ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 67 NXP Semiconductors Peripheral operating requirements and behaviors SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 31. SDHC timing 3.6.9 I2S switching specifications This section provides the AC timings for the I2S in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync (I2S_FS) shown in the figures below. Table 61. I2S master mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_BCLK cycle time S4 I2S_BCLK pulse width high/low S5 80 — ns 45% 55% BCLK period I2S_BCLK to I2S_FS output valid — 15 ns S6 I2S_BCLK to I2S_FS output invalid 0 — ns S7 I2S_BCLK to I2S_TXD valid — 15 ns S8 I2S_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 15 — ns S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 — ns 68 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_BCLK (output) S4 S4 S6 S5 I2S_FS (output) S10 S9 I2S_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 32. I2S timing — master mode Table 62. I2S slave mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V S11 I2S_BCLK cycle time (input) 80 — ns S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_FS input setup before I2S_BCLK 4.5 — ns S14 I2S_FS input hold after I2S_BCLK 2 — ns S15 I2S_BCLK to I2S_TXD/I2S_FS output valid — 20 ns S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_BCLK 4.5 — ns S18 I2S_RXD hold after I2S_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 69 NXP Semiconductors Peripheral operating requirements and behaviors S11 S12 I2S_BCLK (input) S12 S15 S16 I2S_FS (output) S13 I2S_FS (input) S14 S15 S19 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 33. I2S timing — slave modes 3.6.9.1 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 63. I2S/SAI master mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK (as an input) pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid — 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 — ns S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 15 — ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns 70 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 34. I2S/SAI timing — master modes Table 64. I2S/SAI slave mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 4.5 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 — ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 23.1 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 4.5 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 71 NXP Semiconductors Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 35. I2S/SAI timing — slave modes 3.6.9.2 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 65. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid — 45 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 — ns S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 45 — ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns 72 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 36. I2S/SAI timing — master modes Table 66. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 30 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 5 — ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 56.5 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns S18 I2S_RXD hold after I2S_RX_BCLK 5 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 72 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 73 NXP Semiconductors Dimensions S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 37. I2S/SAI timing — slave modes 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package 169-pin MAPBGA Then use this document number 98ASA00628D For additional packaging assembly information on MAPBGA, refer to applications note AN4982. 5 Pinout 5.1 K27F Signal Multiplexing and Pin Assignments The signal multiplexing and pin assignments are provided in an Excel file attached to this document: 1. Click the paperclip symbol on the left side of the PDF window. 74 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Pinout 2. Double-click on the Excel file to open it. 3. Select the “Pinout” tab. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 5.2 Recommended connection for unused analog and digital pins Table 67 shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application Table 67. Recommended connection for unused analog interfaces Pin Type K27F Short recommendation Detailed recommendation Analog/non GPIO ADCx/CMPx Float Analog input - Float Analog/non GPIO VREF_OUT Float Analog output - Float Analog/non GPIO DAC0_OUT, DAC1_OUT Float Analog output - Float Analog/non GPIO RTC_WAKEUP_B Float Analog output - Float Analog/non GPIO XTAL32 Float Analog output - Float Analog/non GPIO EXTAL32 Float Analog input - Float GPIO/Analog PTA18/EXTAL0 Float Analog input - Float GPIO/Analog PTA19/XTAL0 Float Analog output - Float GPIO/Analog PTx/ADCx Float Float (default is analog input) GPIO/Analog PTx/CMPx Float Float (default is analog input) GPIO/Digital PTA0/JTAG_TCLK Float Float (default is JTAG with pulldown) GPIO/Digital PTA1/JTAG_TDI Float Float (default is JTAG with pullup) GPIO/Digital PTA2/JTAG_TDO Float Float (default is JTAG with pullup) GPIO/Digital PTA3/JTAG_TMS Float Float (default is JTAG with pullup) GPIO/Digital PTA4/NMI_b 10kΩ pullup or disable and float Pull high or disable in PCR & FOPT and float GPIO/Digital PTx Float Float (default is disabled) USB USB0_DP Float Float USB USB0_DM Float Float USB VREG_OUT Tie to input and ground through 10 kΩ Tie to input and ground through 10 kΩ USB VREG_IN0 Tie to output and ground through 10 kΩ Tie to output and ground through 10 kΩ Table continues on the next page... Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 75 NXP Semiconductors Ordering parts Table 67. Recommended connection for unused analog interfaces (continued) Pin Type K27F Short recommendation Detailed recommendation USB VREG_IN1 Tie to output and ground through 10 kΩ Tie to output and ground through 10 kΩ USB USB1VSS Always connect to VSS Always connect to VSS USB USB1_DP Float Float USB USB1_DM Float Float USB USB_VBUS Float Float VBAT VBAT Float Float VDDA VDDA Always connect to VDD potential Always connect to VDD potential VREFH VREFH Always connect to VDD potential Always connect to VDD potential VREFL VREFL Always connect to VSS potential Always connect to VSS potential VSSA VSSA Always connect to VSS potential Always connect to VSS potential 5.3 K27F Pinouts The pinout diagrams are provided in an Excel file attached to this document: 1. Click the paperclip symbol on the left side of the PDF window. 2. Double-click on the Excel file to open it. 3. Select the respective package tab. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. 6 Ordering parts 6.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: MK27 . 76 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Part identification 7 Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification K## Kinetis family • K27 A Key attribute • D = Cortex-M4 w/ DSP • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only • X = Program flash and FlexMemory FFF Program flash memory size • • • • • • • R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • FM = 32 QFN (5 mm x 5 mm) • FT = 48 QFN (7 mm x 7 mm) 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB 2M0 = 2 MB Table continues on the next page... Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 77 NXP Semiconductors Terminology and guidelines Field Description Values • • • • • • • • • • LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK = 80 LQFP (12 mm x 12 mm) LL = 100 LQFP (14 mm x 14 mm) MC = 121 MAPBGA (8 mm x 8 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) MI = 169 MAPBGA (9 mm x 9 mm) AU = 210 WLCSP (6.9 mm x 6.9 mm) 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz 18 = 180 MHz CC Maximum CPU frequency (MHz) • • • • • • N Packaging type • R = Tape and reel • (Blank) = Trays 7.4 Example This is an example part number: MK27FN2M0VMI15 8 Terminology and guidelines 8.1 Definitions Key terms are defined in the following table: Term Rating Definition A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Table continues on the next page... 78 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Terminology and guidelines Term Definition Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. 8.2 Examples EX AM PL E Operating rating: EX AM PL E Operating requirement: EX AM PL E Operating behavior that includes a typical value: 8.3 Typical-value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 79 NXP Semiconductors Revision History 8.4 Relationship between ratings and operating requirements g( g tin era Op in rat ) in. ) in. m t (m en m g tin era Op e uir req g tin era Op t en em uir q re ax (m .) x ma g( g tin era in rat .) Op Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure –∞ ∞ Operating (power on) dli n Ha ng x.) n.) mi g( in rat li nd Ha ng a (m ing rat Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 8.5 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 9 Revision History The following table provides a revision history for this document. Table 68. Revision History Rev. No. Date 0 05/2016 Substantial Changes Initial internal release Table continues on the next page... 80 NXP Semiconductors Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 Revision History Table 68. Revision History (continued) Rev. No. Date 1 03/2017 Substantial Changes • • • • • • • • • • • • • Updated Flash electrical Specifications section Updated Device Mask Set number in Device Revision Number Updated the Operating Characteristics and Communication Interfaces in Front matter Updated FB4 value in Flexbus limited voltage range switching specifications table in Flexbus switching specifications Updated D5 value in SDRAM Timing (Limited voltage range) table in SDRAM controller specifications Added DSPI3 timing specifications in DSPI switching specifications (limited voltage range) and DSPI switching specifications (full voltage range) Updated I2C section Removed TSI block from K27F block diagram and TSI section Updated maximum value of VBAT from 4.25 V to 3.8 V in Voltage and current maximum ratings section Removed the footnote associated with Die junction Temperature in Thermal operating requirements (for V-Temp range) table in Thermal operating requirements section Removed the row that had entry of TSI0x in Recommended connection for unused analog interfaces table Added statement about the package assembly information in Obtaining package dimensions section Updated Power consumption operating behaviors section Kinetis K27F MCU Sub-Family, Rev. 1, 03/2017 81 NXP Semiconductors How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM, the ARM powered logo, Thumb, and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2016–2017 NXP B.V. Document Number K27P169M150SF5 Revision 1, 03/2017