Lyontek LY62W2568RL-70LLT 256k x 8 bit low power cmos sram Datasheet


LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Rev. 1.5
Rev. 1.6
Rev. 1.7
Description
Initial Issue
Revised VIH to TTL compatible
Revised IDR (TYP.)
Revised VIH to 0.7*Vcc
Revised VDR
Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package available
Added packing type in ORDERING INFORMATION
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Revised PACKAGE OUTLINE DIMENSION in page9/10/12/13
Revised ORDERING INFORMATION in page 14
Added SL Grade
Deleted E Grade
Revised ISB1/IDR
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
Issue Date
Aug.1.2007
Jan.9.2008
Feb.22.2008
May.6.2008
Mar.3.2009
May.6.2010
Aug.30.2010
Aug.9.2011

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
FEATURES
GENERAL DESCRIPTION
 Fast access time : 55/70ns
 Low power consumption:
Operating current : 20/18mA (TYP.)
Standby current : 1A (TYP.)
 Single 2.7V ~ 5.5V power supply
 All outputs TTL compatible
 Fully static operation
 Tri-state output
 Data retention voltage : 1.5V (MIN.)
 Green package available
 Package : 32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
32-pin 450 mil SOP
32-pin 600 mil P-DIP
36-ball 6mm x 8mm TFBGA
The LY62W2568 is a 2,097,152-bit low power
CMOS static random access memory organized as
262,144 words by 8 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The LY62W2568 is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
The LY62W2568 operates from a single power
supply of 2.7V ~ 5.5V and all outputs are fully TTL
compatible
PRODUCT FAMILY
Product
Family
LY62W2568
LY62W2568(I)
Operating
Temperature
0 ~ 70℃
-40 ~ 85℃
Vcc Range
Speed
2.7 ~ 5.5V
2.7 ~ 5.5V
55/70ns
55/70ns
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Vcc
Vss
A0-A17
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
1µA
20/18mA
1µA
20/18mA
256Kx8
MEMORY ARRAY
SYMBOL
DESCRIPTION
A0 - A17
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#, CE2
Chip Enable Inputs
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No Connection
COLUMN I/O
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
PIN CONFIGURATION
1
32
Vcc
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE#
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
A3
9
A2
10
A1
11
A0
12
DQ0
LY62W2568
A17
25
A11
24
OE#
23
A10
22
CE#
21
DQ7
13
20
DQ6
DQ1
14
19
DQ5
DQ2
15
18
DQ4
Vss
16
17
DQ3
A11
A9
A8
A13
WE#
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LY62W2568
T S O P-I/S T S O P
SOP/P-DIP
A
A0
A1
CE2
A3
A6
A8
B
DQ4
A2
WE#
A4
A7
DQ0
C
DQ5
NC
A5
D
Vss
Vcc
E
Vcc
Vss
F
DQ6
A17
DQ2
G
DQ7 OE# CE# A16
A15 DQ3
H
NC
A9
A10
1
2
A11
A12
3
4
TFBGA
DQ1
A13
A14
5
6
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
SYMBOL
VT1
VT2
Operating Temperature
TA
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
IOUT
RATING
-0.5 to 6.5
-0.5 to VCC+0.5
0 to 70(C grade)
-40 to 85(I grade)
-65 to 150
1
50
UNIT
V
V
℃
℃
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
CE#
CE2
OE#
WE#
H
X
X
X
I/O OPERATION
High-Z
SUPPLY CURRENT
ISB1
X
L
X
X
High-Z
ISB1
Output Disable
L
H
H
H
High-Z
ICC,ICC1
Read
L
H
L
H
DOUT
ICC,ICC1
L
H
X
L
DIN
ICC,ICC1
Write
Note:
H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
PARAMETER
Supply Voltage
VCC
2.7
*1
Input High Voltage
VIH
0.7*VCC
*2
Input Low Voltage
VIL
- 0.2
Input Leakage Current
ILI
VCC ≧ VIN ≧ VSS
-1
Output Leakage
VCC ≧ VOUT ≧ VSS,
ILO
-1
Current
Output Disabled
Output High Voltage
VOH IOH = -1mA
2.4
Output Low Voltage
VOL
IOL = 2mA
Cycle time = Min.
- 55
CE# = VIL and CE2 = VIH ,
ICC
II/O = 0mA
- 70
Other pins at VIL or VIH
Average Operating
Power supply Current
Cycle time = 1µ s
CE# = 0.2V and CE2≧VCC-0.2V,
ICC1
II/O = 0mA
Other pins at 0.2V or VCC - 0.2V
LL/LLI
CE# ≧VCC-0.2V
*5
25℃
SL
Standby Power
*5
or CE2≦0.2V
SLI
ISB1
40℃
Supply Current
Others at 0.2V or
SL
VCC - 0.2V
SLI
-
TYP.
3.0
-
*4
MAX.
5.5
VCC+0.3
0.6
1
UNIT
V
V
V
µA
-
1
µA
2.7
-
0.4
V
V
20
60
mA
18
50
mA
4
10
mA
1
1
1
1
1
50
5
5
20
25
µA
µA
µA
µA
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical values are measured at VCC = VCC(TYP.) and TA = 25℃
5. This parameter is measured at VCC = 3.0V
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
-
MAX
6
8
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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UNIT
pF
pF

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM.
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
SYM.
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW *
tWHZ*
LY62W2568-55
MIN.
MAX.
55
55
55
30
10
5
20
20
10
-
LY62W2568-70
MIN.
MAX.
70
70
70
35
10
5
25
25
10
-
UNIT
LY62W2568-55
MIN.
MAX.
55
50
50
0
45
0
25
0
5
20
LY62W2568-70
MIN.
MAX.
70
60
60
0
55
0
30
0
5
25
UNIT
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
CE2
OE#
tOE
tOH
tOHZ
tCHZ
tOLZ
tCLZ
Dout
High-Z
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
CE2
tAS
tWP
tWR
WE#
tWHZ
Dout
TOW
High-Z
(4)
tDW
Din
(4)
tDH
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
CE2
tWP
WE#
tWHZ
Dout
High-Z
(4)
tDW
Din
tDH
Data Valid
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL
TEST CONDITION
MIN.
VDR
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
1.5
LL/LLI
VCC = 1.5V
CE# ≧ VCC - 0.2V
SL 25℃
IDR
or CE2 ≦ 0.2V
SLI 40℃
Other pins at 0.2V or VCC-0.2V SL/SLI
See Data Retention
tCDR
0
Waveforms (below)
tR
tRC*
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
tR
CE# ≧ Vcc-0.2V
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE2
tR
CE2 ≦ 0.2V
VIL
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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TYP.
0.5
0.5
0.5
0.5
MAX.
5.5
20
4
4
15
UNIT
V
µA
µA
µA
µA
-
-
ns
-
-
ns

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
PACKAGE OUTLINE DIMENSION
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
Θ
INCH(BASE)
0.047 (MAX)
0.004 ±0.002
0.039 ±0.002
0.009 ±0.002
0.006 ±0.002
0.724 ±0.008
0.315 ±0.008
0.020 (TYP)
0.787 ±0.008
0.024 ±0.004
0.0315 ±0.004
0.003 (MAX)
o
o
0 ~5
MM(REF)
1.20 (MAX)
0.10 ±0.05
1.00 ±0.05
0.22 ±0.05
0.155 ±0.055
18.40 ±0.20
8.00 ±0.20
0.50 (TYP)
20.00 ±0.20
0.60 ±0.10
0.08 ±0.10
0.08 (MAX)
o
o
0 ~5
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
HD
cL
12° (2x)
32
16
17
12° (2x)
b
E
e
1
"A"
Seating Plane
D
y
12° (2X)
16
17
0.254
A2
c
A
GAUGE PLANE
A1
0
SEATING PLANE
L
12° (2X)
L1
"A" DATAIL VIEW
32
1
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
Θ
INCH(BASE)
0.049 (MAX)
0.004 ±0.002
0.039 ±0.002
0.009 ±0.002
0.006 ±0.002
0.465 ±0.008
0.315 ±0.008
0.020 (TYP)
0.528±0.008
0.02 ±0.008
0.031 ±0.005
0.003 (MAX)
o
o
0 ~5
MM(REF)
1.25 (MAX)
0.10 ±0.05
1.00 ±0.05
0.22 ±0.05
0.155 ±0.055
11.80 ±0.20
8.00 ±0.20
0.50 (TYP)
13.40 ±0.20.
0.50 ±0.20
0.8 ±0.125
0.076 (MAX)
o
o
0 ~5
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
32 pin 450 mil SOP Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
E1
e
L
L1
S
y
Θ
INCH.(BASE)
0.120(MAX)
0.004(MIN)
0.116(MAX)
0.016(TYP)
0.008(TYP)
0.817(MAX)
0.445±0.006
0.555±0.025
0.050(TYP)
0.033±0.017
0.055±0.008
0.026(MAX)
0.004(MAX)
o
o
0 -10
MM(REF)
3.048(MAX)
0.102(MIN)
2.946(MAX)
0.406(TYP)
0.203(TYP)
20.75(MAX)
11.303±0.152
14.097±0.635
1.270(TYP)
0.838±0.432
1.397±0.203
0.660(MAX)
0.101(MAX)
o
o
0 -10
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
32 pin 600 mil P-DIP Package Outline Dimension
UNIT
SYM.
A1
A2
B
D
E
E1
e
eB
L
S
Q1
INCH(BASE)
MM(REF)
0.015(MIN)
0.155±0.005
0.018±0.005
1.650±0.01
0.600±0.010
0.545±0.005
0.100(TYP)
0.650±0.020
0.158±0.043
0.075±0.010
0.070±0.005
0.381(MIN)
3.937±0.127
0.457±0.127
41.910±0.254
15.240±0.254
13.843±0.127
2.540(TYP)
16.510±0.508.
4.013±1.092
1.905±0.254
1.778±0.127
Note : D/E1/S dimension do not include mold flash.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12

LY62W2568
Rev. 1.7
256K X 8 BIT LOW POWER CMOS SRAM
36 ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
13

LY62W2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
ORDERING INFORMATION
LY62W2568 U V - WW XX Y Z
Z : Packing Type
Blank : Tube or Tray
Tube : 32-pin 450 mil SOP
32-pin 600 mil P-DIP
Tray : 32-pin 8 mm x 20 mm TSOP-I
32-pin 8 mm x 13.4 mm STSOP
36-ball 6 mm x 8 mm TFBGA
T : Tape Reel
Y : Temperature Range
Blank : (Commercial) 0°C ~ 70°C
I : (Industrial) -40°C ~ +85°C
XX : Power Type
LL : Ultra Low Power
SL : Special Ultra Low Power
WW : Access Time(Speed)
V : Lead Information
L : Green Package
U : Package Type
S : 32-pin 450 mil SOP
P : 32-pin 600 mil P-DIP
L : 32-pin 8 mm x 20 mm TSOP-I
R : 32-pin 8 mm x 13.4 mm STSOP
G : 36-ball 6 mm x 8 mm TFBGA
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
14

LY62W2568
Rev. 1.7
256K X 8 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
15
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