Fairchild FAN7391 High-current, high & low-side, gate-drive ic Datasheet

FAN7391
High-Current, High & Low-Side, Gate-Drive IC
Features
Description
 Floating Channels for Bootstrap Operation to +600 V
The FAN7391 is a monolithic high- and low-side gatedrive IC, which can drive high-speed MOSFETs and
IGBTs that operate up to +600 V. It has a buffered output
stage with all NMOS transistors designed for high pulse
current driving capability and minimum cross-conduction.
 Typically 4.5 A / 4.5 A Sourcing / Sinking Current
Driving Capability
 Common-Mode dv/dt Noise-Canceling Circuit
 Built-in Under-Voltage Lockout for Both Channels
 Built-in Advanced Input Filter
 Matched Propagation Delay for Both Channels
 Logic (VSS) and Power (COM) Ground ±5 V Offset
 3.3 V and 5 V Input Logic Compatible
 Output In-Phase with Input
Fairchild’s high-voltage process and common-mode
noise-canceling techniques provide stable operation of
the high-side driver under high-dv/dt noise circumstances. An advanced level-shift circuit offers high-side
gate driver operation up to VS=-9.8 V (typical) for
VBS=15 V.
The advanced input filter of HIN provides protection
against short-pulsed input signals caused by noise.
Applications
 Plasma Display Panel (PDP) Sustain Driver
The UVLO circuit prevents malfunction when VDD and
VBS are lower than the specified threshold voltage.
 High-Intensity Discharge (HID) Lamp Ballast
 Switching Mode Power Supply (SMPS)
The high-current and low-output voltage-drop feature
makes this device suitable for the PDP sustain pulse
driver, motor driver, switching mode power supply, and
high-power DC-DC converter applications.
 Motor Driver
Related Resources
 AN-6076 — Design and Application Guide of Boot-
14-SOP
strap Circuit for High-Voltage Gate-Drive IC
 AN-9052 — Design Guide for Selection of Bootstrap
Components
 AN-8102 — Recommendations to Avoid Short Pulse
Width Issues in HVIC Gate Driver Applications
Ordering Information
Part Number
Package
Operating Temperature Range
Packing Method
FAN7391MX
14-SOP
-40C ~ 125C
Tape & Reel
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
www.fairchildsemi.com
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
June 2014
15V
RBOOT
DBOOT
FAN7391
Up to 600V
HIN
1
HIN
NC 14
LIN
2
LIN
VB
3
VSS
HO 12
4
NC
VS
5
COM
NC 10
6
LO
NC
9
7
VDD
NC
8
Controller
VSS
13
Q1
R1
R2
CBOOT
11
OUTPUT
Load
C1
R3
Q2
R4
FAN7391 Rev.01
Figure 1. Application Circuit for Half-Bridge
Internal Block Diagram
FAN7391
13
VB
12
HO
11
VS
7
VDD
6
LO
5
COM
UVLO
NOISE
CANCELLER
R
S
DRIVER
200K
PULSE
GENERATOR
Advanced
Input Filter
HIN 1
R
Q
UVLO
VSS/COM
LEVEL
SHIFT
DRIVER
DELAY
LIN 2
200K
VSS 3
Pin 4, 8, 9, 10 and 14 are no connection
FAN7391 Rev.01
Figure 2. Functional Block Diagram
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
www.fairchildsemi.com
2
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Typical Application Circuit
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Pin Configurations
HIN
1
14
NC
LIN
2
13
VB
VSS
3
12
HO
NC
4
11
VS
COM
5
10
NC
LO
6
9
NC
VDD
7
8
NC
FAN7391
FAN7391 Rev.01
Figure 3. Pin Assignments (Top View)
Pin Definitions
14-Pin
Name
Description
1
HIN
Logic Input for High-Side Gate Driver Output
2
LIN
Logic Input for Low-Side Gate Driver Output
3
VSS
Logic Ground
5
COM
Low-Side Driver Return
6
LO
Low-Side Driver Output
7
VDD
Low-Side and Logic Part Supply Voltage
11
VS
High-Voltage Floating Supply Return
12
HO
High-Side Driver Output
13
VB
High-Side Floating Supply
4, 8, 9, 10, 14
NC
No Connect
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
Characteristics
VS
High-Side Floating Supply Offset Voltage
VB
High-Side Floating Supply Voltage
Min.
Max.
Unit
VB-VSHUNT
VB+0.3
V
-0.3
625.0
V
VS-0.3
VB+0.3
V
VHO
High-Side Floating Output Voltage, HO Pin
VDD
Low-Side and Logic Fixed Supply Voltage
-0.3
VSHUNT
V
VLO
Low-Side Output Voltage, LO Pin
-0.3
VDD+0.3
V
VIN
Logic Input Voltage (HIN and LIN)
VSS-0.3
VDD+0.3
V
VSS
Logic Ground
VDD-25
VDD+0.3
V
Allowable Offset Voltage Slew Rate
50
V/ns
Power Dissipation
1.0
W
JA
Thermal Resistance, Junction-to-Ambient
110
C/W
TJ
Junction Temperature
+150
C
TSTG
Storage Temperature
+150
C
dVS/dt
PD(1)(2)(3)
Notes:
1. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material).
2. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection; and
JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.
3. Do not exceed PD maximum under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
VB
High-Side Floating Supply Voltage
VS+10
VS+20
V
VS
High-Side Floating Supply Offset Voltage
6-VDD
600
V
VHO
High-Side Output Voltage
VS
VB
V
VDD
Low-Side and Logic Supply Voltage
10
20
V
VLO
Low-Side Output Voltage
COM
VDD
V
VIN
Logic Input Voltage (HIN and LIN)
VSS
VDD
V
TA
Operating Ambient Temperature
-40
+125
C
Pulse Width of Logic Input for High-Side Gate Driver
100
PWHIN
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
ns
www.fairchildsemi.com
4
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Absolute Maximum Ratings
VBIAS (VDD, VBS)=15.0 V, VS=VSS=COM, TA=25C, unless otherwise specified. The VIL, VIH, and IIN parameters are
referenced to VSS/COM and are applicable to the respective input signals HIN and LIN. The VO and IO parameters are
referenced to COM and VS is applicable to the respective output signals HO and LO.
Symbol
Characteristics
Condition
Min.
Typ.
Max. Unit
POWER SUPPLY SECTION (VDD AND VBS)
VDDUV+
VBSUV+
VDD and VBS Supply Under-Voltage
Positive-Going Threshold
8.0
8.8
9.8
VDDUVVBSUV-
VDD and VBS Supply Under-Voltage
Negative-Going Threshold
7.4
8.3
9.0
VDDUVH VDD and VBS Supply Under-Voltage
VBSUVH Lockout Hysteresis Voltage
V
0.5
ILK
Offset Supply Leakage Current
VB=VS=600 V
50
IQBS
Quiescent VBS Supply Current
VIN=0 V or 5 V
45
80
IQDD
Quiescent VDD Supply Current
VIN=0 V or 5 V
75
110
IPBS
Operating VBS Supply Current
fIN=20 kHz, rms value
530
640
IPDD
Operating VDD Supply Current
fIN=20 kHz, rms value
530
640
23
25
µA
µA
SHUNT REGULATOR SECTION
VSHUNT
VDD=Sweep or VBS=Sweep,
ISHUNT=5 mA
VDDand VBS Shunt Regulator Clamping
Voltage
21
V
LOGIC INPUT SECTION (HIN, LIN)
VIH
Logic "1" Input Voltage
VIL
Logic "0" Input Voltage
2.5
IIN+
Logic "1" Input Bias Current
VIN=5 V
25
50
IIN-
Logic "0" Input Bias Current
VIN=0 V
1.0
2.0
RIN
Input Pull-Down Resistance
1.2
100
200
V
µA
k
GATE DRIVER OUTPUT SECTION (HO, LO)
VOH
High-Level Output Voltage, VBIAS-VO
No Load
1.0
V
VOL
Low-Level Output Voltage, VO
No Load
35
mV
IO+
Output High, Short-Circuit Pulsed Current(4)
VO=0 V, VIN=5 V,PW<10 µs
3.5
4.5
IO-
Output Low, Short-Circuit Pulsed Current(4)
VO=15 V, VIN=0 V,PW<10 µs
3.5
4.5
VS
Allowable Negative VS Pin Voltage for HIN
Signal Propagation to HO
VSSCOM
VSS-COM/COM-VSS Voltage Endurability
-9.8
A
-7.0
V
5
V
-5
Note:
4. This parameter guaranteed by design.
Dynamic Electrical Characteristics
VBIAS (VDD, VBS)=15.0 V, VS=VSS=COM=0 V, CL=1000 pF, and TA=25C unless otherwise specified.
Symbol
Characteristics
Test Condition
Min.
Typ.
Max.
ton
Turn-On Propagation Delay
VS=0 V
150
220
toff
Turn-Off Propagation Delay
VS=0 V
150
220
MT
Delay Matching, HS & LS Turn-On/Off
15
50
tr
Turn-On Rise Time
25
50
tf
Turn-Off Fall Time
20
45
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
Unit
ns
www.fairchildsemi.com
5
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Electrical Characteristics
240
240
220
220
200
tOFF [ns]
tON [ns]
200
180
160
140
180
160
140
120
120
100
100
80
80
-40
-20
0
20
40
60
80
100
60
-40
120
-20
0
Temperature [°C]
40
40
30
30
20
60
80
100
120
20
10
10
-20
0
20
40
60
80
100
0
-40
120
-20
0
20
40
60
80
100
120
100
120
Temperature [°C]
Temperature [°C]
Figure 6. Turn-On Rise Time
vs. Temperature
Figure 7. Turn-Off Fall Time
vs. Temperature
50
50
40
MTOFF [ns]
40
MTON [ns]
40
Figure 5. Turn-Off Propagation Delay
vs. Temperature
tF [ns]
tR [ns]
Figure 4. Turn-On Propagation Delay
vs. Temperature
0
-40
20
Temperature [°C]
30
20
30
20
10
10
0
-40
0
-20
0
20
40
60
80
100
-10
-40
120
Temperature [°C]
0
20
40
60
80
Temperature [°C]
Figure 8. Turn-On Delay Matching vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
-20
Figure 9. Turn-Off Delay Matching vs. Temperature
www.fairchildsemi.com
6
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Typical Characteristics
120
120
100
100
IQBS [A]
IQDD [A]
140
80
80
60
60
40
40
20
20
0
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
Temperature [°C]
40
60
80
100
120
Figure 11. Quiescent VBS Supply Current
vs. Temperature
1.2
1.2
1.0
1.0
[A]
IPBS [mA]
IPDD [mA]
[A]
Figure 10. Quiescent VDD Supply Current
vs. Temperature
0.8
0.6
0.8
0.6
0.4
0.4
0.2
-40
-20
0
20
40
60
80
100
0.2
-40
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 12. Operating VDD Supply Current
vs. Temperature
Figure 13. Operating VBS Supply Current
vs. Temperature
9.5
9.5
9.0
9.0
VDDUV- [V]
VDDUV+ [V]
20
Temperature [°C]
8.5
8.5
8.0
8.0
7.5
-40
-20
0
20
40
60
80
100
7.5
-40
120
Figure 14. VDD UVLO+ vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 15. VDD UVLO- vs. Temperature
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7
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Typical Characteristics (Continued)
9.5
9.0
9.0
VBSUV- [V]
VBSUV+ [V]
9.5
8.5
8.0
8.5
8.0
7.5
-40
-20
0
20
40
60
80
100
7.5
-40
120
-20
0
Temperature [°C]
Figure 16. VBS UVLO+ vs. Temperature
40
60
80
100
120
Figure 17. VBS UVLO- vs. Temperature
1200
1.0
1000
0.8
800
VOL [mV]
VOH [mV]
20
Temperature [°C]
600
0.6
0.4
400
0.2
200
0
-40
-20
0
20
40
60
80
100
0.0
-40
120
-20
0
Temperature [°C]
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
-20
0
20
40
60
80
100
0.5
-40
120
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 20. Logic HIGH Input Voltage
vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
40
Figure 19. Low-Level Output Voltage
vs. Temperature
VIL [V]
VIH [V]
Figure 18. High-Level Output Voltage
vs. Temperature
0.5
-40
20
Temperature [°C]
Figure 21. Logic LOW Input Voltage
vs. Temperature
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8
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Typical Characteristics (Continued)
-7
60
-8
50
VS [V]
IIN+ [A]
40
30
-9
-10
20
-11
10
0
-40
-20
0
20
40
60
80
100
-12
-40
120
Temperature [°C]
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 22. Logic Input High Bias Current
vs. Temperature
Figure 23. Allowable Negative VS Voltage
vs. Temperature
100
90
TFLTHIN [ns]
80
70
60
50
40
30
20
10
0
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 24. Input Filtering Time of HIN
vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
www.fairchildsemi.com
9
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Typical Characteristics (Continued)
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Switching Time Definitions
15V
HIN
1 HIN
VB 13
LIN
2
LIN
HO 12
10µF
100nF
1nF
VS 11
3 VSS
15V
VDD 7
5 COM
6
10µF
LO
1nF
100nF
FAN7391 Rev.01
Figure 25. Switching Time Test Circuit (Referenced 14-SOP)
HIN
LIN
HO
LO
FAN7390 Rev.01
Figure 26. Input / Output Timing Diagram
HIN
50%
50%
LIN
ton
tr
toff
tf
90%
90%
HO
LO
10%
10%
FAN7390 Rev.01
Figure 27. Switching Time Waveform Definitions
HIN
LIN
50%
LO
10%
50%
MT
HO
10%
90%
LO
90%
HO
MT
FAN7390 Rev.01
Figure 28. Delay Matching Waveform Definitions
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
www.fairchildsemi.com
10
1. Advanced Input Noise Filter
Figure 29 shows the input noise filter method, which has
symmetry duration between the input signal (tINPUT) and
the output signal (tOUTPUT) and helps to reject noise
spikes and short pulses. This input filter is applied to the
HIN. The upper pair of waveforms (Example A) shows
an input signal duration (tINPUT) much longer than input
filter time (tFLTHIN); it is approximately the same duration
between the input signal time (tINPUT) and the output
signal time (tOUTPUT). The lower pair of waveforms
(Example B) shows an input signal time (tINPUT) slightly
longer than input filter time (tFLTHIN); it is approximately
the same duration between input signal time (tINPUT) and
the output signal time (tOUTPUT).
tFLTHIN
t FLTHIN
t FLTHIN
tFLTHIN
t FLTHIN
t FLTHIN
HO
(LOW)
Example B
Example A
HIN
HIN
HIN
HO
(HIGH)
Figure 30. Noise Rejecting Input Filter Definition
Figure 31 shows the characteristics of the input filters
while receiving narrow ON and OFF pulses. If input
signal pulse duration, PWHIN, is less than input filter
time, tFLTHIN; the output pulse, PWHO, is zero. The input
signal is rejected by input filter. Once the input signal
pulse duration, PWHIN, exceeds input filter time, tFLTHIN,
the output pulse durations, PWHO, matches the input
pulse durations, PWHIN. FAN7391 input filter time,
tFLTHIN, is about 50ns for the high-side outputs.
t FLTHIN
t INPUT
tOUTPUT
HO
1000
Input Pulse
Output Pulse
900
t FLTHIN
Output Pulse Width [ns]
Example B
HIN
tINPUT
tOUTPUT
Output duration is
same as input duration
HO
Figure 29. Input Noise Filter Definition
800
700
600
500
400
300
200
2. Short-Pulsed Input Noise Rejection
Method
100
The Advanced input filter circuitry provides protection
against short-pulsed input signals caused by noise.
If the input signal duration is less than input filter time
(tFLTHIN), the output does not change states.
Example A and B of the Figure 30 show the input and
output waveforms with short-pulsed noise spikes with a
duration less than input filter time; the output does not
change states.
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
0
100
200 300 400 500 600 700 800 900 1000
Input Pulse Width [ns]
Figure 31. Input Filter Characteristic of Narrow ON
www.fairchildsemi.com
11
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Example A
Applications Information
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
Package Dimensions
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
PIN ONE
INDICATOR
1
1.70
7
0.51
0.35
1.27
0.25
1.27
LAND PATTERN RECOMMENDATION
M
C B A
(0.33)
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.10
C
0.25
0.19
0.10 C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50
0.25 X 45°
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 32. 14-Lead, Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/M1/M14A.pdf
Always visit Fairchild Semiconductor’s online packaging area for the most recent packing drawings:
http://www.fairchildsemi.com/packing_dwg/PKG-M14A.pdf.
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
www.fairchildsemi.com
12
FAN7391 — High-Current, High & Low Side, Gate-Drive IC
© 2014 Fairchild Semiconductor Corporation
FAN7391 Rev. 1.0.0
www.fairchildsemi.com
13
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