ACPL-P481 and ACPL-W481 Inverted Logic, High CMR Optocoupler for Intelligent Power Modules and IGBT/MOSFET Gate Drive Data Sheet Description Features The high-speed ACPL-P481/W481 optocoupler contains a GaAsP LED, photo detector and a Schmitt trigger that eliminates the need for external waveform conditioning circuits. • Inverted output type (totem pole output) • Performance Specified for Common IPM Applications Over Industrial Temperature Range. • Short Maximum Propagation Delays • Minimized Pulse Width Distortion (PWD) • Very High Common Mode Rejection (CMR) • Hysteresis • Available in Stretched SO-6 Package. • Package Clearance/Creepage at 8 mm (ACPL-W481) • Safety Approval: (pending) – UL Recognized with 3750 Vrms (5000 Vrms for ACPL-W481) for 1 minute per UL1577. – CSA Approved. – IEC/EN/DIN EN 60747-5-5 Approved with VIORM = 891 Vpeak for ACPL-P481 and VIORM = 1140 Vpeak for ACPL-W481, under option 060. The totem pole output eliminates the need for a pull-up resistor. An Intelligent Power Module, Power MOSFET or IGBT can be driven directly. Propagation delay difference between devices has been minimized to maximize inverter efficiency through reduced switching dead time. Applications • • • • • IPM Interface Isolation Isolated IGBT/MOSFET Gate Drive AC and Brushless DC Motor Drives Industrial Inverters General Digital Isolation Functional Diagram Anode 1 6 VCC N.C. 2 5 VO Cathode 3 SHIELD 4 Ground Note: A 0.1 µF bypass capacitor must be connected between pins 4 and 6. Specifications • • • • • • Wide Operating Temperature Range: –40°C to 100°C. Maximum Propagation Delay tPHL / tPLH = 350 ns Maximum Pulse Width Distortion (PWD) = 250 ns. Propagation Delay Difference: Min. –100 ns, Max. 250 ns Wide Operating VCC Range: 4.5 V to 20 V 20 kV/µs Minimum Common Mode Rejection (CMR) at VCM = 1000 V. Truth Table (Positive Logic) LED VO ON LOW OFF HIGH CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information ACPL-P481/W481 is UL recognized with 3750/5000 Vrms for 1 minute respectively per UL 1577. Both are approved under CSA Component Acceptance Notice #5, File CA 88324. Option Part number ACPL-P481 ACPL-W481 RoHS Compliant Surface Mount Package -000E X -500E X Stretched SO-6 -060E Tape & Reel IEC/EN/DIN EN 60747-5-5 100 per tube X 1000 per reel X -560E Quantity X X X 100 per tube X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an ordering part number. Example 1: ACPL-P481-560E: Stretched SO-6 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and RoHS compliant. Example 2: ACPL-P481-000E: Stretched SO-6 Surface Mount package in tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Package Outline Drawings ACPL-P481 Stretched SO-6 Package, 7 mm clearance 1.27 BSG 0.050 0.381 ±0.127 0.015 ±0.005 0.45 0.018 10.7 0.421 1.27 0.050 7.62 0.300 6.81 0.268 45° +0.254 0 +0.010 0.180 - 0.000 4.580 1.590 ±0.127 0.063 ±0.005 0.76 0.030 2.16 0.085 3.180 ±0.127 0.125 ±0.005 7° 7° 7° 0.20 ±0.10 0.008 ±0.004 1±0.250 0.040 ±0.010 2 7° 5 NOM. 9.7 ±0.250 0.382 ±0.010 0.254 ±0.050 0.010 ±0.002 Floating Lead Protusions max. 0.25 [0.01] Dimensions in Millimeters [ Inches ] Lead Coplanarity= 0.1mm [0.004 Inches ] ACPL-W481 Stretched SO-6 Package, 8 mm clearance 0.381 ±0.127 0.015 ±0.005 1 0.760 0.030 5 3 4 7.62 [0.300] +0.127 -0.000 +0.005 0.268 - 0.000 6.807 7° 45° 1.905 0.075 1.270 0.050 1.590 ±0.127 0.063 ±0.005 0.20 ±0.10 0.008 ±0.004 7° 0.750 ±0.250 [0.0295 ±0.010] 12.650 0.498 6 2 0.45 0.018 +0.254 0 +0.010 0.180 - 0.000 4.580 1.27 BSG 0.050 0.254 ±0.050 0.010 ±0.002 35° NOM. 3.180 ±0.127 0.125 ±0.005 7° 7° Floating Lead protusion max. 0.25[0.01] 11.500 ±0.25 0.453 ±0.010 Dimensions in millimeters [inches] Lead Coplanarity=0.1mm [0.004 inches] Recommended Pb-Free IR Profile The recommended reflow profile is per JEDEC Standard, J-STD-020 (latest revision). Non-halide flux should be used. Regulatory Information The ACPL-P481/W481 is approved by the following organizations: IEC/EN/DIN EN 60747-5-5 (Option 060 only) UL Approved with Maximum Working Insulation Voltage VIORM = 891 Vpeak for ACPL-P481 and VIORM = 1140 Vpeak for ACPL-W481 Approval under UL 1577, component recognition program up to VISO = 3750 VRMS (5000 Vrms for ACPL-W481). File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. 3 Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (ACPL-P481/W481 Option 060) Description Symbol ACPL-P481 ACPL-W481 Installation Classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms I – IV I – IV I – III I – IV I – IV I – IV Climatic Classification 55/100/21 55/100/21 Pollution Degree (DIN VDE 0110/39) 2 2 Unit Maximum Working Insulation Voltage VIORM 891 1140 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC VPR 1670 2137 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6=VPR, Type and Sample Test, tm = 10 sec, Partial Discharge < 5 pC VPR 1426 1824 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 6000 8000 Vpeak Case Temperature TS 175 175 °C Input Current IS, INPUT 230 230 mA Output Power PS, OUTPUT 600 600 mW Insulation Resistance at TS, VIO = 500 V RS >109 >109 Ω Safety-limiting Values – maximum values allowed in the event of a failure. * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under the Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-5), for a detailed description of Method a and Method b partial discharge test profiles. Table 2. Insulation and Safety Related Specifications Parameter Symbol ACPL-P481 ACPL-W481 Units Conditions Minimum External Air Gap (External Clearance) L(101) 7.0 8.0 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 8.0 8.0 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. >175 >175 V DIN IEC 112/VDE 0303 Part 1 IIIa IIIa Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group 4 CTI Material Group (DIN VDE 0110, 1/89, Table 1) Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature TS -55 125 °C Operating Temperature TA -40 100 °C Average Input Current IF(avg) 10 mA Peak Transient Input Current (< 1 µs pulse width, 300 pps) (< 200 µs pulse width, < 1% duty cycle) IF(tran) 1.0 40 A mA Reverse Input Voltage VR 5 V Average Output Current IO 25 mA Supply Voltage VCC 0 25 V Output Voltage VO -0.5 25 V Total Package Power Dissipation PT 210 mW 1 Table 4. Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Power Supply Voltage VCC 4.5 20 V 2 Forward Input Current (OFF) IF(OFF) 6 10 mA Forward Input Voltage (ON) VF(ON) – 0.8 V Operating Temperature TA -40 100 °C 5 Table 5. Electrical Specifications Over recommended operating conditions TA = -40 °C to 100 °C, VCC = +4.5 V to 20 V, IF(ON) = 6 mA to 10 mA, VF(OFF) = 0 V to 0.8 V, unless otherwise specified. All typicals at TA = 25 °C. Parameter Symbol Logic Low Output Voltage VOL Min. Typ. Max. Units Test Conditions Fig. 0.3 V IOL = 3.5 mA 1, 3 0.5 Logic High Output Voltage VOH Output Leakage Current (VO = VCC + 0.5 V) IOHH Logic Low Supply Current ICCL Logic High Supply Current VCC-1.8 VCC - 0.9 VCC-2.5 VCC - 1.2 ICCH Logic Low Short Circuit Output Current IOSL Logic High Short Circuit Output Current IOSH Input Forward Voltage VF Input Reverse Breakdown Voltage BVR Input Diode Temperature Coefficient ∆VF/∆TA Input Capacitance CIN IOL = 6.5 mA V IOH = -3.5 mA 2, 3, 7 IOH = -6.5 mA 100 µA VCC = 5 V, VF = 0 V 500 µA VCC = 20 V, VF = 0 V 1.9 3.0 mA VCC = 5.5 V, IF = 10 mA, IO = 0mA 2.0 3.0 mA VCC = 20 V, IF = 10 mA, IO = 0mA 1.5 2.5 mA VCC = 5.5 V, VF = 0 V, IO = 0mA 1.6 2.5 mA VCC = 20 V, VF = 0 V, IO = 0mA mA VO = VCC = 5.5 V, IF = 10 mA 25 50 mA VO = VCC = 20 V, IF = 10 mA -25 mA VCC = 5.5 V, VF = 0 V, VO = GND -50 mA VCC = 20 V, VF = 0 V, VO = GND 1.7 V TA = 25°C, IF = 6 mA 1.85 V IF = 6 mA V IR = 10 µA 1.7 mV/°C IF = 6 mA 60 pF f = 1 MHz, VF = 0 V 1.5 Note 5 3 3 4 4 Table 6. Switching Specifications Over recommended operating conditions TA = -40 °C to 100 °C, VCC = +4.5 V to 20 V, IF(ON) = 6 mA to 10 mA, VF(OFF) = 0 V to 0.8 V, unless otherwise specified. All typicals at TA = 25 °C. Parameter Symbol Propagation Delay Time to Logic Low Output Level Typ. Max. Units Test Conditions Fig. Note tPHL 110 350 ns With Peaking Capacitor 5, 6 6 Propagation Delay Time to Logic High Output Level tPLH 140 350 ns With Peaking Capacitor 5, 6 6 Pulse Width Distortion |tPHL - tPLH| = PWD 250 ns 9 Propagation Delay Difference Between Any Two Parts PDD 250 ns 11 Output Rise Time (10-90%) tr 16 ns 5, 8 Output Fall Time (90-10%) tf 20 ns 5, 8 Logic High Common Mode Transient Immunity |CMH| 20 kV/µs |VCM| = 1000 V, VF = 0 V, VCC = 5 V, TA = 25°C 9 7 Logic Low Common Mode Transient Immunity |CML| 20 kV/µs |VCM| = 1000 V, IF = 6.0 mA, VCC = 5 V, TA = 25°C 9 7 6 Min. -100 Table 7. Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage* VISO 3750 (ACPL-P481) 5000 (ACPL-W481) Input-Output Resistance RI-O Input-Output Capacitance CI-O * Typ. Max. Units Vrms Test Conditions Fig. Note RH < 50%, t = 1 min. TA = 25°C 5, 8 1012 VI-O = 500 Vdc 5 0.6 f = 1 MHz, VI-O = 0 Vdc 5 The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable). Notes: 1. Derate total package power dissipation, PT, linearly above 70°C free-air temperature at a rate of 4.5 mW/°C. 2. Detector requires a VCC of 4.5V or higher for stable operation as output might be unstable if VCC is lower than 4.5V. Be sure to check the power ON/OFF operation other than the supply current. 3. Duration of output short circuit time should not exceed 10 ms. 4. Input capacitance is measured between pin 1 and pin 3. 5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together. 6. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the trailing edge of the output pulse. The tPHL propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the leading edge of the output pulse. 7. CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, VO > 2.0 V. CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, VO < 0.8 V. 8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS (6000 VRMS for ACPL-W481) for one second (leakage detection current limit, II-O <= 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable. 9. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH | for any given device. 10. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 is recommended. 11. The difference between tPLH and tPHL between any two devices under the same test condition. 7 IOH - HIGH LEVEL OUTPUT CURRENT - mA VOL - LOW LEVEL OUTPUT VOLTAGE - V 0.15 IF = 6mA 0.14 0.13 Vcc = 4.5V Vcc = 20V 0.12 0.11 0.1 -50 0 50 100 TA - TEMPERATURE - °C 150 Figure 1. Typical Logic Low Output Voltage vs. Temperature Vo-OUTPUT VOLTAGE-V 3 2.5 2 1.5 1 0.5 Io = 6.4mA 0 1 2 3 IF - INPUT CURRENT - mA 4 Vo = 2.7V -15 Vo = 2.4V -20 -25 -50 0 100 TA = 25°C 10 1.0 0.1 0.01 1.2 1.4 1.3 VF - FORWARD VOLTAGE - V 1.5 THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C1 AND C2. VCC 1 6 2 OUTPUT VO MONITORING NODE * 5V D1 SHIELD C1 = 120 pF 4 C2 = 15 pF 5 kΩ 660 Ω 330 Ω 6 mA 10 mA 619 Ω IF(ON) D2 3 R1 IF(ON) ALL DIODES ARE EITHER 1N916 OR 1N3064 5 INPUT IF 50% IF(ON) tPHL tPLH 0 mA D3 D4 * 0.1 µF BYPASS - SEE NOTE 10 OUTPUT V VOL (OV) Figure 5. Test Circuit for tPLH, tPHL, tr, and tf 8 150 Figure 4. Typical Input Diode Forward Characteristic PULSE GEN. tr = tf = 5ns f = 100 kHz 10% DUTY CYCLE VO = 5 V ZO = 50 R1 50 100 TA - TEMPERATURE - °C + VF - 0.001 1.1 5 Figure 3. Typical Output Voltage vs. Forward Input Current INPUT MONITORING NODE -10 IF TA = 25°C Vcc=4.5V 3.5 0 -5 1000 Io = -2.6mA 4 VCC = 4.5V VF = 0V Figure 2. Typical Logic High Output Current vs. Temperature IF - FORWARD CURRENT - mA 4.5 0 VOH 1.3 V 230 25 TA = 25°C VF = 0V 190 Vcc = 20V IF = 10mA TPLH 170 Vo-OUTPUT VOLTAGE-V Tp-PROPAGATION DELAY-ns 210 150 130 Vcc = 10V IF = 6mA TPHL 110 90 20 15 10 5 70 50 -50 0 50 TA - TEMPERATURE - C 100 Tp-PROPAGTION DELAY-ns Figure 6. Typical Propagation Delays vs. Temperature. 200 TA = 25°C 180 160 TPLH 140 120 100 80 TPHL 60 40 20 0 0 5 0 150 0 5 10 15 Vcc-SUPPLY VOLTAGE-V Figure 7. Typical Logic High Output Voltage vs. Supply Voltage IF (mA) 10 6 IF (mA) 6 10 10 15 Vcc-SUPPLY VOLTAGE-V 20 25 Figure 8. Typical Propagation Delay vs. Supply Voltage VCC RIN CMH A CML VCM (PEAK) 1 6 + |VCM| 0.1 µF B VFF 2 5 3 4 SHIELD 0V OUTPUT VO MONITORING NODE VOH SWITCH AT B:VF = 0V VO (MIN.)* OUTPUT VO VCM + 20 SWITCH AT A:IF = 6 mA VOL Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-2122EN - December 21, 2012 VO (MAX.)* * SEE NOTE 6 25