TI1 LMV934-N Single, dual, quad 1.8-v, rrio operational amplifier Datasheet

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LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
LMV93x-N/-N-Q1 Single, Dual, Quad 1.8-V, RRIO Operational Amplifiers
1 Features
•
1
•
•
•
•
•
•
•
•
•
Typical 1.8-V Supply Values; Unless Otherwise
Noted
Available in Automotive AEC-Q100 Grade 1
Specified at 1.8-V, 2.7-V and 5-V
Output Swing
– With 600-Ω Load 80 mV from Rail
– With 2-kΩ Load 30 mV from Rail
VCM 200 mV Beyond Rails
Supply Current (per Channel) 100 μA
Gain Bandwidth Product 1.4 MHz
Maximum VOS 4.0 mV
Ultra Tiny Packages
Temperature Range −40°C to 125°C
LMV93x-N devices exhibit an excellent speed-power
ratio, achieving 1.4-MHz gain bandwidth product at
1.8-V supply voltage with very low supply current.
The LMV93x-N devices can drive a 600-Ω load and
up to 1000-pF capacitive load with minimal ringing.
These devices also have a high DC gain of 101 dB,
making them suitable for low-frequency applications.
The single LMV93x-N is offered in space-saving 5-pin
SC70 and SOT-23 packages. The dual LMV932-N
are in 8-pin VSSOP and SOIC packages and the
quad LMV934-N are in 14-pin TSSOP and SOIC
packages. These small packages are ideal solutions
for area constrained PC boards and portable
electronics such as mobile phones and tablets.
The LMV93x-N-Q1 family retains all the LMV93x-N
family features while adding AEC-Q100 Grade 1
qualification for automotive applications.
Device Information(1)
2 Applications
•
•
•
•
•
•
Mobile Phones
Tablets
Wearables
Health Monitoring
Portable and Battery-Powered Electronic
Equipment
Battery Monitoring
3 Description
The LMV93x-N family (LMV931-N single, LMV932-N
dual and LMV934-N quad) are low-voltage, lowpower operational amplifiers. The LMV93x-N family
operates from 1.8-V to 5.5-V supply voltages and
have rail-to-rail input and output. The input commonmode voltage extends 200 mV beyond the supplies
which enables user enhanced functionality beyond
the supply voltage range. The output can swing railto-rail unloaded and within 105 mV from the rail with
600-Ω load at 1.8-V supply. The LMV93x-N devices
are optimized to work at 1.8 V, which make them
ideal for portable two-cell, battery-powered systems
and single-cell Li-Ion systems.
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMV931-N
SOT-23 (5)
2.90 mm × 1.60 mm
LMV931-N-Q1
SC-70 (5)
2.00 mm × 1.25 mm
LMV932-N
VSSOP (8)
3.00 mm × 3.00 mm
LMV932-N-Q1
SOIC (8)
4.90 mm × 3.91 mm
LMV934-N
TSSOP (8)
5.00 mm × 4.40 mm
LMV934-N-Q1
SOIC (14)
8.60 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
High-Side Current Sense Amplifier
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
Handling Ratings - Commercial ................................ 4
Handling Ratings - Automotive ................................. 4
Recommended Operating Ratings............................ 4
Thermal Information .................................................. 4
DC Electrical Characteristics 1.8 V .......................... 5
AC Electrical Characteristics 1.8 V ........................... 6
DC Electrical Characteristics 2.7 V .......................... 7
AC Electrical Characteristics 2.7 V ........................... 8
Electrical Characteristics 5 V DC ............................ 9
AC Electrical Characteristics 5 V ......................... 10
Typical Characteristics .......................................... 11
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ............................................... 18
8.3 Dos and Don'ts ....................................................... 21
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (June 2014) to Revision O
•
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision M (November 2013) to Revision N
Page
•
Complete rewrite for GDS standard. ...................................................................................................................................... 1
•
Added LMV934-N-Q1. The other Q grades were added in previous revision........................................................................ 1
Changes from Revision L (March 2013) to Revision M
Page
•
Added Automotive Q Grade. ................................................................................................................................................. 1
•
Added Output Swing for Q-Grade in all Electrical Tables ...................................................................................................... 6
2
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Product Folder Links: LMV931-N LMV931-N-Q1 LMV932-N LMV932-N-Q1 LMV934-N LMV934-N-Q1
LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
www.ti.com
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
DBV and DCK Package
5-Pin SC-70 and SOT-23
LMV931-N, LMV931-N-Q1 Top View
DGK and D Package
8-Pin VSSOP and SOIC
LMV932-N, LMV932-N-Q1 Top View
1
8
+
V
OUT A
A
2
-
+
7
-IN A
OUT B
3
6
+IN A
V
-
-IN B
B
+
4
5
+IN B
DGK and D Package
14-Pin TSSOP and SOIC
LMV934-N, LMV934-N-Q1 Top View
Pin Functions: LMV931
PIN
NAME
LMV931
I/O
DESCRIPTION
DBV, DCK NO.
+IN
1
I
Noninverting Input
-IN
3
I
Inverting Input
OUT
4
O
Output
V-
2
P
Negative Supply
V+
5
P
Positive Supply
Pin Functions: LMV932 and LMV934
PIN
NAME
+IN A
LMV932
LMV934
D, DGK NO.
D, PW NO.
I/O
DESCRIPTION
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
+IN C
—
10
I
Noninverting input, channel C
+IN D
—
12
I
Noninverting input, channel D
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
–IN C
—
9
I
Inverting input, channel C
–IN D
—
13
I
Inverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
—
8
O
Output, channel C
OUT D
—
14
O
Output, channel D
V+
8
4
P
Positive (highest) power supply
V–
4
11
P
Negative (lowest) power supply
Copyright © 2001–2014, Texas Instruments Incorporated
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LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
See
.
Supply voltage ( V+– V− )
MIN
MAX
–0.3
6
V-
Differential input voltage
(2)
(3)
V
+
(V ) - 0.3
(V ) + 0.3
–40
150
Junction temperature (3)
(1)
V+
-
Voltage at input/output pins
UNIT
°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but specific performance is not specified. For specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
The maximum power dissipation is a function of TJ(max) , RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max)–TA)/RθJA. All numbers apply for packages soldered directly into a PC board.
6.2 Handling Ratings - Commercial
Tstg
Electrostatic
discharge
V(ESD)
(1)
(2)
(3)
(4)
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS001, all pins (1) (2)
–2000
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (3)
–750
750
Machine Model (MM) (4)
–200
200
Storage temperature range
V
JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
Machine model, 200 Ω in series with 100-pF.
6.3 Handling Ratings - Automotive
MIN
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
UNIT
°C
–65
150
Human body model (HBM), per AEC Q100-002 (1)
–2000
2000
Charged device model (CDM), per AEC Q100-011
–750
750
–200
200
Machine Model (MM)
(1)
(2)
MAX
(2)
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Machine model, 200 Ω in series with 100-pF.
6.4 Recommended Operating Ratings
(1)
See
.
MIN
MAX
Supply Voltage Range ( V+– V− )
1.8
5.5
V
Temperature Range
−40
125
°C
(1)
UNIT
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but specific performance is not specified. For specifications and the test
conditions, see the Electrical Characteristics.
6.5 Thermal Information
LMV921
THERMAL METRIC (1)
DCK
LMV922
DBV
DGK
265
235
5 PINS
RθJA
(1)
4
Junction-to-ambient thermal resistance
414
LMV924
D
DGK
175
155
8 PINS
D
UNIT
127
°C/W
14 PINS
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
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SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
6.6 DC Electrical Characteristics 1.8 V
Unless otherwise specified, all limits specified for TJ = 25°C. V+ = 1.8 V, V − = 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
LMV931 (Single)
VOS
Input Offset Voltage
MIN
25°C
TYP
MAX
1
4
(1)
Full Range
LMV932 (Dual),
LMV934 (Quad)
25°C
1
5.5
Full Range
Full Range
5.5
IB
Input Bias Current
25°C
15
μV/°C
35
Full Range
50
25°C
13
25
Full Range
IS
Supply Current (per channel)
40
25°C
103
185
Full Range
CMRR
PSRR
CMVR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Common-Mode Voltage
Range
25°C
60
Full Range
55
LMV932 and LMV934
0 ≤ VCM ≤ 0.6 V
1.4 V ≤ VCM ≤ 1.8 V (2)
25°C
55
Full Range
50
−0.2 V ≤ VCM ≤ 0 V
1.8 V ≤ VCM ≤ 2.0 V
25°C
50
72
+
25°C
75
100
Full Range
70
For CMRR Range ≥ 50dB
25°C
−40°C to 85°C
125°C
Large Signal Voltage Gain
LMV931-N (Single)
LMV931-N-Q1 (Single)
AV
Large Signal Voltage Gain
LMV932-N (Dual)
LMV932-N-Q1 (Dual)
LMV934-N (Quad)
LMV934-N-Q1 (Quad)
VO
(1)
(2)
Output Swing
205
LMV931, 0 ≤ VCM ≤ 0.6 V
1.4 V ≤ VCM ≤ 1.8 V (2)
1.8 V ≤ V ≤ 5 V
V− − 0.2
−
V
V− + 0.2
RL = 600 Ω to 0.9 V,
VO = 0.2 V to 1.6 V,
VCM = 0.5 V
25°C
77
Full Range
73
RL = 2 kΩ to 0.9 V,
VO = 0.2 V to 1.6 V,
VCM = 0.5 V
25°C
80
Full Range
75
RL = 600 Ω to 0.9 V,
VO = 0.2 V to 1.6 V,
VCM = 0.5 V
25°C
75
Full Range
72
RL = 2 kΩ to 0.9 V,
VO = 0.2 V to 1.6 V,
VCM = 0.5 V
25°C
78
Full Range
75
RL = 600 Ω to 0.9 V
VIN = ±100 mV
25°C
RL = 2 kΩ to 0.9 V
VIN = ±100 mV
mV
7.5
Input Offset Voltage
Average Drift
Input Offset Current
mV
6
TCVOS
IOS
UNIT
1.65
78
1.63
25°C
1.75
Full Range
1.74
nA
μA
dB
76
dB
−0.2
to
2.1
dB
dB
V+ + 0.2
V+
V
V+ − 0.2
101
dB
105
dB
90
dB
100
dB
1.72
0.077
Full Range
nA
0.105
V
0.120
1.77
0.024
0.035
V
0.04
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration.
For specified temperature ranges, see the CMVR parameter in DC Electrical Characteristics 1.8 V for the input common-mode voltage
specifications.
Copyright © 2001–2014, Texas Instruments Incorporated
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LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
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DC Electrical Characteristics 1.8 V (continued)
Unless otherwise specified, all limits specified for TJ = 25°C. V+ = 1.8 V, V − = 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
RL = 600 Ω to 0.9 V
VIN = ±100 mV
Output Swing
LMV932-N-Q1 (Dual)
LMV934-N-Q1 (Quad)
VO
RL = 2 kΩ to 0.9 V
VIN = ±100 mV
25°C
(3)
Output Short Circuit Current
1.65
Full Range
1.63
25°C
1.75
(1)
Sinking, VO = 1.8 V
VIN = −100 mV
25°C
7
Full Range
5
Full Range
4
UNIT
0.105
V
0.173
1.77
1.74
25°C
MAX
1.72
0.024
Sourcing, VO = 0 V
VIN = 100 mV
(3)
TYP
0.077
Full Range
IO
MIN
0.035
V
0.055
8
mA
3.3
9
mA
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely
affect reliability.
6.7 AC Electrical Characteristics 1.8 V
Unless otherwise specified, all limits specified for TJ = 25°C. V+ = 1.8 V, V − = 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
Slew Rate
GBW
Φm
Gm
Gain Margin
en
Input-Referred Voltage Noise
f = 10 kHz, VCM = 0.5 V
in
Input-Referred Current Noise
f = 10 kHz
Total Harmonic Distortion
f = 1 kHz, AV = +1
RL = 600 Ω, VIN = 1 VPP
Amplifier-to-Amplifier Isolation
See (3)
THD
(1)
(2)
(3)
6
See
(2)
SR
.
MIN
TYP
(1)
MAX
UNIT
0.35
V/μs
Gain-Bandwidth Product
1.4
MHz
Phase Margin
67
deg
7
dB
60
nV/√Hz
0.08
pA/√Hz
0.023%
123
dB
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration.
Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates.
Input referred, RL = 100 kΩ connected to V+/2. Each amplifier excited in turn with 1 kHz to produce VO = 3 VPP (For Supply Voltages <3
V, VO = V+).
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LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
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SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
6.8 DC Electrical Characteristics 2.7 V
Unless otherwise specified, all limits specified for TJ = 25°C. V+ = 2.7 V, V − = 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
LMV931 (Single)
VOS
Input Offset Voltage
MIN
25°C
TYP
MAX
1
4
(1)
Full Range
LMV932 (Dual)
LMV934 (Quad)
1
5.5
Full Range
Input Offset Voltage Average
Drift
Full Range
IB
Input Bias Current
25°C
Input Offset Current
5.5
μV/°C
15
35
50
25°C
8
25
Full Range
IS
Supply Current (per channel)
40
25°C
105
190
Full Range
CMRR
Common-Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
VCM
Input Common-Mode Voltage
Range
25°C
60
Full Range
55
LMV932 and LMV934
0 ≤ VCM ≤ 1.5 V
2.3 V ≤ VCM ≤ 2.7 V (2)
25°C
55
Full Range
50
25°C
+
1.8 V ≤ V ≤ 5 V
VCM = 0.5 V
For CMRR Range ≥ 50 dB
25°C
AV
VO
Large Signal Voltage Gain
LMV932-N (Dual)
LMV932-N-Q1 (Dual)
LMV934-N (Quad)
LMV934-N-Q1 (Quad)
Output Swing
75
100
Full Range
70
VO
(1)
(2)
V
V− + 0.2
RL = 600 Ω to 1.35 V,
VO = 0.2 V to 2.5 V
25°C
87
Full Range
86
RL = 2 kΩ to 1.35 V,
VO = 0.2 V to 2.5 V
25°C
92
Full Range
91
RL = 600 Ω to 1.35 V,
VO = 0.2 V to 2.5 V
25°C
78
Full Range
75
RL = 2 kΩ to 1.35 V,
VO = 0.2 V to 2.5 V
25°C
81
Full Range
78
RL = 600 Ω to 1.35 V
VIN = ±100 mV
25°C
RL = 600 Ω to 1.35 V
VIN = ±100 mV
Output Swing
LMV932-N-Q1 (Dual)
LMV934-N-Q1 (Quad)
−
RL = 2 kΩ to 1.35 V
VIN = ±100 mV
2.55
2.53
25°C
2.65
−0.2
to
3.0
dB
dB
V+ + 0.2
V+
2.64
25°C
2.55
104
2.53
25°C
2.65
Full Range
2.64
dB
110
dB
90
dB
100
dB
2.62
0.110
V
0.130
2.675
0.04
V
0.045
2.62
0.083
Full Range
V
V+ − 0.2
0.025
Full Range
μA
dB
0.083
Full Range
nA
dB
25°C
V− − 0.2
nA
80
74
−40°C to 85°C
RL = 2 kΩ to 1.35 V
VIN = ±100 mV
81
50
125°C
Large Signal Voltage Gain
LMV931-N (Single)
LMV931-N-Q1 (Single)
210
LMV931, 0 ≤ VCM ≤ 1.5 V
2.3 V ≤ VCM ≤ 2.7 V (2)
−0.2 V ≤ VCM ≤ 0 V
2.7 V ≤ VCM ≤ 2.9 V
mV
7.5
Full Range
IOS
mV
6
25°C
TCVOS
UNIT
0.110
V
0.187
2.675
0.025
0.04
V
0.059
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration.
For specified temperature ranges, see the CMVR parameter in DC Electrical Characteristics 1.8 V for the input common-mode voltage
specifications.
Copyright © 2001–2014, Texas Instruments Incorporated
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LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
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DC Electrical Characteristics 2.7 V (continued)
Unless otherwise specified, all limits specified for TJ = 25°C. V+ = 2.7 V, V − = 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MΩ.
PARAMETER
Output Short Circuit Current (3)
IO
(3)
TEST CONDITIONS
MIN
TYP
30
Sourcing, VO = 0 V
VIN = +100 mV
25°C
20
Full Range
15
Sinking,
VO = 2.7 V
VIN = −100 mV
25°C
18
Full Range
12
(1)
MAX
UNIT
mA
25
mA
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely
affect reliability.
6.9 AC Electrical Characteristics 2.7 V
Unless otherwise specified, all limits specified for TJ = 25°C. V+ = 2.7 V, V − = 0 V, VCM = 1.0 V, VO = 1.35 V and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
See (2)
MIN
TYP
(1)
MAX
UNIT
SR
Slew Rate
0.4
V/µs
GBW
Gain-Bandwidth Product
1.4
MHz
Φm
Phase Margin
70
deg
Gm
Gain Margin
en
Input-Referred Voltage Noise
f = 10 kHz, VCM = 0.5 V
in
Input-Referred Current Noise
f = 10 kHz
THD
Total Harmonic Distortion
f = 1 kHz, AV = +1
RL = 600 Ω, VIN = 1 VPP
Amp-to-Amp Isolation
(1)
(2)
(3)
8
See
(3)
7.5
dB
57
nV√Hz
0.08
pA/√Hz
0.022%
123
dB
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration.
Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates.
Input referred, RL = 100 kΩ connected to V+/2. Each amplifier excited in turn with 1 kHz to produce VO = 3 VPP (For Supply Voltages <3
V, VO = V+).
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6.10 Electrical Characteristics 5 V DC
Unless otherwise specified, all limits specified for TJ = 25°C. V+ = 5 V, V − = 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
LMV931 (Single)
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Average
Drift
IB
Input Bias Current
MIN
25°C
TYP
MAX
1
4
(1)
Full Range
LMV932 (Dual)
LMV934 (Quad)
25°C
1
5.5
Full Range
μV/°C
25°C
14
35
50
25°C
9
25
Full Range
IS
Supply Current (per channel)
40
25°C
116
210
Full Range
CMRR
PSRR
Power Supply Rejection Ratio
CMVR
Input Common-Mode Voltage
Range
25°C
60
Full Range
55
−0.2 V ≤ VCM ≤ 0 V
5.0 V ≤ VCM ≤ 5.2 V
25°C
1.8 V ≤ V+ ≤ 5 V
VCM = 0.5 V
For CMRR Range ≥ 50 dB
25°C
AV
VO
Large Signal Voltage Gain
LMV932-N (Dual)
LMV932-N-Q1 (Dual)
LMV934-N (Quad)
LMV934-N-Q1 (Quad)
Output Swing
78
25°C
75
100
Full Range
70
VO
(2)
V + 0.3
25°C
88
Full Range
87
RL = 2 kΩ to 2.5 V,
VO = 0.2 V to 4.8 V
25°C
94
Full Range
93
RL = 600 Ω to 2.5 V,
VO = 0.2 V to 4.8 V
25°C
81
Full Range
78
RL = 2 kΩ to 2.5 V,
VO = 0.2 V to 4.8 V
25°C
85
Full Range
82
RL = 600 Ω to 2.5 V
VIN = ±100 mV
25°C
4.855
Full Range
4.835
25°C
4.945
Full Range
4.935
25°C
4.855
RL = 2 kΩ to 2.5 V
VIN = ±100 mV
−0.2
to
5.3
4.807
4.945
μA
dB
V+ + 0.2
V+
V
+
V − 0.3
102
dB
113
dB
90
dB
100
dB
4.890
0.160
V
0.180
4.967
0.065
V
0.075
4.890
0.120
25°C
nA
dB
0.037
Full Range
nA
dB
0.120
0.160
V
0.218
4.967
0.037
Full Range
(1)
V−
−
RL = 600 Ω to 2.5 V,
VO = 0.2 V to 4.8 V
RL = 600 Ω to 2.5 V
VIN = ±100 mV
Output Swing
LMV932-N-Q1 (Dual)
LMV934-N-Q1 (Quad)
V− − 0.2
−40°C to 85°C
RL = 2 kΩ to 2.5 V
VIN = ±100 mV
86
50
125°C
Large Signal Voltage Gain
LMV931-N (Single)
LMV931-N-Q1 (Single)
230
0 ≤ VCM ≤ 3.8 V
4.6 V ≤ VCM ≤ 5.0 V (2)
Common-Mode Rejection Ratio
mV
7.5
5.5
Input Offset Current
mV
6
Full Range
IOS
UNIT
4.935
0.065
V
0.075
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration.
For specified temperature ranges, see the CMVR parameter in DC Electrical Characteristics 1.8 V for the input common-mode voltage
specifications.
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Electrical Characteristics 5 V DC (continued)
Unless otherwise specified, all limits specified for TJ = 25°C. V+ = 5 V, V − = 0 V, VCM = V+/2, VO = V+/2 and RL > 1 MΩ.
PARAMETER
Output Short Circuit Current (3)
IO
(3)
TEST CONDITIONS
MIN
TYP
100
LMV931, Sourcing, VO = 0
V
VIN = +100 mV
25°C
80
Full Range
68
Sinking, VO = 5 V
VIN = −100 mV
25°C
58
Full Range
45
(1)
MAX
UNIT
mA
65
mA
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely
affect reliability.
6.11 AC Electrical Characteristics 5 V
Unless otherwise specified, all limits specified for TJ = 25°C. V+ = 5 V, V − = 0 V, VCM = V+/2, VO = 2.5 V and R L > 1 MΩ.
PARAMETER
TEST CONDITIONS
See . (2)
MIN
TYP
(1)
MAX
UNIT
SR
Slew Rate
0.42
V/µs
GBW
Gain-Bandwidth Product
1.5
MHz
Φm
Phase Margin
71
deg
Gm
Gain Margin
en
Input-Referred Voltage Noise
f = 10 kHz, VCM = 1 V
in
Input-Referred Current Noise
f = 10 kHz
THD
Total Harmonic Distortion
f = 1 kHz, AV = 1
RL = 600 Ω, VO = 1 VPP
Amplifier-to-Amplifier Isolation
See (3)
(1)
(2)
(3)
10
8
dB
50
nV/√Hz
0.08
pA/√Hz
0.022%
123
dB
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration.
Connected as voltage follower with input step from V− to V+. Number specified is the slower of the positive and negative slew rates.
Input referred, RL = 100 kΩ connected to V+/2. Each amplifier excited in turn with 1 kHz to produce VO = 3 VPP (For Supply Voltages <3
V, VO = V+).
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6.12 Typical Characteristics
Unless otherwise specified, VS = 5 V, single-supply, TA = 25°C.
160
100
125°C
SUPPLY CURRENT (éA)
140
VS = 5V
85°C
10
ISOURCE (mA)
120
100
25°C
80
-40°C
60
VS = 2.7V
1
VS = 1.8V
0.1
40
20
0
0
1
2
3
4
5
6
0.01
0.001
100
VS = 5V
ISINK (mA)
10
VS = 2.7V
1
VS = 1.8V
0.01
0.001
0.01
0.1
10
1
OUTPUT VOLTAGE REF TO GND (V)
Figure 3. Sinking Current vs. Output Voltage
OUTPUT VOLTAGE PROXIMITY TO
SUPPLY VOLTAGE (mV ABSOLUTE VALUE)
0.1
1
10
Figure 2. Sourcing Current vs. Output Voltage
OUTPUT VOLTAGE PROXIMITY TO SUPPLY
VOLTAGE (mV ABSOLUTE VALUE)
Figure 1. Supply Current vs. Supply Voltage (LMV931-N)
0.1
0.01
OUTPUT VOLTAGE REFERENCED TO V+ (V)
SUPPLY VOLTAGE (V)
140
RL = 600:
130
NEGATIVE SWING
120
110
100
90
80
POSITIVE SWING
70
60
0
1
4
2
3
SUPPLY VOLTAGE (V)
5
6
Figure 4. Output Voltage Swing vs. Supply Voltage
45
RL = 2k:
40
NEGATIVE SWING
35
30
25
POSITIVE SWING
20
0
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
Figure 5. Output Voltage Swing vs. Supply Voltage
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Figure 6. Gain and Phase vs. Frequency
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Typical Characteristics (continued)
Unless otherwise specified, VS = 5 V, single-supply, TA = 25°C.
Figure 7. Gain and Phase vs. Frequency
Figure 8. Gain and Phase vs. Frequency
90
VS = 5V
85
CMRR (dB)
80
VS = 2.7V
75
VS = 1.8V
70
65
60
1k
100
FREQUENCY (Hz)
10
Figure 10. CMRR vs. Frequency
Figure 9. Gain and Phase vs. Frequency
100
90
PSRR (dB)
80
70
-PSRR
60
50
40
30
10
100
1k
FREQUENCY (Hz)
Figure 11. PSRR vs. Frequency
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10k
INPUT VOLTAGE NOISE (nV/ Hz)
1000
VS = 5V
+PSRR
12
10k
100
10
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 12. Input Voltage Noise vs. Frequency
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Typical Characteristics (continued)
Unless otherwise specified, VS = 5 V, single-supply, TA = 25°C.
10
1
INPUT CURRENT NOISE (pA/ Hz)
RL = 600:
AV = +1
THD (%)
1
0.1
1.8V
0.1
2.7V
5V
0.01
10
100
1k
10k
0.01
10
100k
1k
100
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Input Current Noise vs. Frequency
Figure 14. THD vs. Frequency
10
0.5
RL = 600:
AV = +10
SLEW RATE (V/Ps)
0.45
THD (%)
1
5V
0.1
FALLING EDGE
0.4
RISING EDGE
0.35
RL = 2k:
0.3
1.8V
AV = +1
2.7V
0.01
10
VIN = 1VPP
0.25
100
1k
10k
0
100k
1
2
5
6
VS = 2.7V
RL = 2 k:
(50 mV/DIV)
INPUT SIGNAL
OUTPUT SIGNAL
INPUT SIGNAL
OUTPUT SIGNAL
(50 mV/DIV)
RL = 2 k:
4
Figure 16. Slew Rate vs. Supply Voltage
Figure 15. THD vs. Frequency
VS = 1.8V
3
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
TIME (2.5 Ps/DIV)
TIME (2.5 Ps/DIV)
Figure 17. Small Signal Noninverting Response
Figure 18. Small Signal Noninverting Response
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Typical Characteristics (continued)
Unless otherwise specified, VS = 5 V, single-supply, TA = 25°C.
VIN
INPUT SIGNAL
VS = 5V
OUTPUT SIGNAL
(50 mV/DIV)
(900 mV/div)
RL = 2 k:
VOUT
VS = 1.8V
RL = 2k:
AV = +1
TIME (10 Ps/div)
TIME (2.5 Ps/DIV)
Figure 19. Small Signal Noninverting Response
Figure 20. Large Signal Noninverting Response
VIN
(2.5 V/div)
(1.35V/DIV)
VIN
VOUT
VOUT
VS = 2.7V
VS = 5.0V
RL = 2 k:
RL = 2k:
AV = +1
AV = +1
TIME (10 Ps/div)
TIME (10 Ps/DIV)
Figure 21. Large Signal Noninverting Response
Figure 22. Large Signal Noninverting Response
90
90
SHORT CIRCUIT CURRENT (mA)
SHORT CIRCUIT CURRENT (mA)
5V
80
5V
70
60
50
40
2.7V
30
20
1.8V
10
0
-40
10
60
TEMPERATURE
(°C)
110
Figure 23. Short Circuit Current vs. Temperature (Sinking)
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80
70
60
50
40
2.7V
30
20
1.8V
10
0
-40
10
60
TEMPERATURE
(°C)
110
Figure 24. Short Circuit Current vs. Temperature (Sourcing)
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Typical Characteristics (continued)
Unless otherwise specified, VS = 5 V, single-supply, TA = 25°C.
3
3
VS = 1.8V
VS = 2.7V
2.5
2.5
2
2
25°C
-40°C
1.5
VOS (mV)
VOS (mV)
25°C
1
0.5
85°C
1
0.5
85°C
125°C
125°C
0
0
-0.5
-0.5
-1
-0.4
0
0.4
0.8
-40°C
1.5
1.2
2
1.6
-1
-0.4
2.4
0.1
0.6
VCM (V)
1.1
1.6
2.1
2.6
3.1
VCM (V)
Figure 25. Offset Voltage vs. Common-Mode Range
Figure 26. Offset Voltage vs. Common-Mode Range
3
VS = 5V
2.5
2
-40°C
VOS (mV)
1.5
1
0.5
125°C
25°C
85°C
0
-0.5
-1
-0.4
0.6
1.6
2.6
3.6
4.6
5.6
VCM (V)
Figure 27. Offset Voltage vs. Common-Mode Range
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7 Detailed Description
7.1 Overview
The LMV93x-N are low-voltage, low-power operational amplifiers (op-amp) operating from 1.8-V to 5.5-V
supply voltages and have rail-to-rail input and output. LMV93x-N input common-mode voltage extends 200
mV beyond the supplies which enables user enhanced functionality beyond the supply voltage range.
7.2 Functional Block Diagram
(Each Amplifier)
7.3 Feature Description
The differential inputs of the amplifier consist of a noninverting input (+IN) and an inverting input (–IN). The
amplifer amplifies only the difference in voltage between the two inputs, which is called the differential input
voltage. The output voltage of the op-amp VOUT is given by Equation 1:
VOUT = AOL (IN+ - IN-)
where
•
AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 10 uV per volt).
(1)
7.4 Device Functional Modes
7.4.1 Input and Output Stage
The rail-to-rail input stage of this family provides more flexibility for the designer. The LMV93x-N use a
complimentary PNP and NPN input stage in which the PNP stage senses common-mode voltage near V− and
the NPN stage senses common-mode voltage near V+. The transition from the PNP stage to NPN stage occurs 1
V below V+. Because both input stages have their own offset voltage, the offset of the amplifier becomes a
function of the input common-mode voltage and has a crossover point at 1 V below V+.
Figure 28. Simplified Schematic Diagram
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Device Functional Modes (continued)
This VOS crossover point can create problems for both DC− and AC-coupled signals if proper care is not taken.
Large input signals that include the VOS crossover point will cause distortion in the output signal. One way to
avoid such distortion is to keep the signal away from the crossover. For example, in a unity gain buffer
configuration with VS = 5 V, a 5-V peak-to-peak signal will contain input-crossover distortion while a 3-V peak-topeak signal centered at 1.5 V will not contain input-crossover distortion as it avoids the crossover point. Another
way to avoid large signal distortion is to use a gain of −1 circuit which avoids any voltage excursions at the input
terminals of the amplifier. In that circuit, the common-mode DC voltage can be set at a level away from the VOS
cross-over point. For small signals, this transition in VOS shows up as a VCM dependent spurious signal in series
with the input signal and can effectively degrade small signal parameters such as gain and common-mode
rejection ratio. To resolve this problem, the small signal should be placed such that it avoids the VOS crossover
point. In addition to the rail-to-rail performance, the output stage can provide enough output current to drive 600Ω loads. Because of the high-current capability, take care not to exceed the 150°C maximum junction
temperature specification.
7.4.2 Input Bias Current Consideration
The LMV93x-N family has a complementary bipolar input stage. The typical input bias current (IB) is 15 nA. The
input bias current can develop a significant offset voltage. This offset is primarily due to IB flowing through the
negative feedback resistor, RF. For example, if IB is 50 nA and RF is 100 kΩ, then an offset voltage of 5 mV will
develop (VOS = IB x RF). Using a compensation resistor (RC), as shown in Figure 29, cancels this effect. But the
input offset current (IOS) will still contribute to an offset voltage in the same manner.
Figure 29. Canceling the Offset Voltage due to Input Bias Current
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV93x-N devices bring performance, economy and ease-of-use to low-voltage, low-power systems. They
provide rail-to-rail input and rail-to-rail output swings into heavy loads.
8.2 Typical Applications
8.2.1 High-Side Current-Sensing Application
Figure 30. High-Side Current Sensing
8.2.1.1 Design Requirements
The high-side current-sensing circuit (Figure 30) is commonly used in a battery charger to monitor charging
current to prevent overcharging. A sense resistor RSENSE is connected to the battery directly. This system
requires an op amp with rail-to-rail input. The LMV93x-N are ideal for this application because its common-mode
input range extends up to the positive supply.
8.2.1.2 Detailed Design Procedure
As seen in Figure 30, the ICHARGE current flowing through sense resistor RSENSE develops a voltage drop equal to
VSENSE. The voltage at the negative sense point will now be less than the positive sense point by an amount
proportional to the VSENSE voltage.
The low-bias currents of the LMV93x cause little voltage drop through R2, so the negative input of the LMV93x
amplifier is at essentially the same potential as the negative sense input.
The LMV93x will detect this voltage error between its inputs and servo the transistor base to conduct more
current through Q1, increasing the voltage drop across R1 until the LMV93x inverting input matches the
noninverting input. At this point, the voltage drop across R1 now matches VSENSE.
IG, a current proportional to ICHARGE, will flow according to the following relation:
IG = VRSENSE / R1 = ( RSENSE * ICHARGE ) / R1
(2)
IG also flows through the gain resistor R3 developing a voltage drop equal to:
V3 = IG * R3 = ( VRSENSE / R1 ) * R3 = ( ( RSENSE * ICHARGE ) / R2 ) * R3
18
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(3)
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Typical Applications (continued)
VOUT = (RSENSE * ICHARGE ) * G
where
•
G = R3 / R1
(4)
The other channel of the LMV93x may be used to buffer the voltage across R3 to drive the following stages.
8.2.1.3 Application Curve
Figure 31 shows the results of the example current sense circuit.
5
VOUT (V)
4
3
2
1
0
0
1
2
3
4
5
ICHARGE (A)
C001
NOTE: the error after 4 V where transistor Q1 runs out of headroom and saturates, limiting the upper output swing.
Figure 31. Current Sense Amplifier Results
8.2.2 Half-Wave Rectifier Applications
RI
VIN
VOUT
RI
VIN
VCC
3
VOUT
LMV931
4
+
0
t
1
t
Figure 32. Half-Wave Rectifier With Rail-To-Ground Output Swing Referenced to Ground
VCC
VIN
VOUT
3
+
VCC
4
VIN
VCC
t
VOUT
LMV931
RI
1
t
RI
Figure 33. Half-Wave Rectifier With Negative-Going Output Referenced to VCC
Copyright © 2001–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LMV931-N LMV931-N-Q1 LMV932-N LMV932-N-Q1 LMV934-N LMV934-N-Q1
19
LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
www.ti.com
Typical Applications (continued)
8.2.2.1 Design Requirements
Because the LMV931-N, LMV932-N, LMV934-N input common-mode range includes both positive and negative
supply rails and the output can also swing to either supply, achieving half-wave rectifier functions in either
direction is an easy task. All that is needed are two external resistors; there is no need for diodes or matched
resistors. The half-wave rectifier can have either positive or negative going outputs, depending on the way the
circuit is arranged.
8.2.2.2 Detailed Design Procedure
In Figure 32 the circuit is referenced to ground, while in Figure 33 the circuit is biased to the positive supply.
These configurations implement the half-wave rectifier because the LMV93x-N can not respond to one-half of the
incoming waveform. It can not respond to one-half of the incoming because the amplifier cannot swing the output
beyond either rail therefore the output disengages during this half cycle. During the other half cycle, however, the
amplifier achieves a half wave that can have a peak equal to the total supply voltage. RI should be large enough
not to load the LMV93x-N.
8.2.2.3 Application Curve
Figure 34. Output of Ground-to-Rail Circuit
Figure 35. Output of Rail-to-Ground Circuit
8.2.3 Instrumentation Amplifier With Rail-to-Rail Input and Output Application
Figure 36. Rail-to-Rail Instrumentation Amplifier
8.2.3.1 Design Requirements
Using three of the LMV93x-N amplifiers, an instrumentation amplifier with rail-to-rail inputs and outputs can be
made as shown in Figure 36.
8.2.3.2 Detailed Design Procedure
In this example, amplifiers on the left side act as buffers to the differential stage. These buffers assure that the
input impedance is very high. They also assure that the difference amp is driven from a voltage source. This is
necessary to maintain the CMRR set by the matching R1-R2 with R3-R4. The gain is set by the ratio of R2/R1 and
R3 should equal R1 and R4 equal R2. With both rail-to-rail input and output ranges, the input and output are only
limited by the supply voltages. Remember that even with rail-to-rail outputs, the output can not swing past the
supplies so the combined common-mode voltages plus the signal should not be greater that the supplies or
limiting will occur.
8.2.3.3 Application Curve
Figure 37 shows the results of the instrumentation amplifier with R1 and R3 = 1 K, and R2 and R4 = 100 kΩ, for a
gain of 100, running on a single 5-V supply with a input of VCM = VS/2. The combined effects of the individual
offset voltages can be seen as a shift in the offset of the curve.
20
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Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMV931-N LMV931-N-Q1 LMV932-N LMV932-N-Q1 LMV934-N LMV934-N-Q1
LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
www.ti.com
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
Typical Applications (continued)
5
VOUT (V)
4
3
2
1
0
0
10
20
30
VDIFF (mV)
40
50
C001
Figure 37. Instrumentation Amplifier Output Results
8.3 Dos and Don'ts
Do properly bypass the power supplies.
Do add series resistence to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.
Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 kΩ per volt).
9 Power Supply Recommendations
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI
recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For singlesupply, place a capacitor between V+ and V− supply leads. For dual supplies, place one capacitor between V+
and ground, and one capacitor between V- and ground.
10 Layout
10.1 Layout Guidelines
The V+ pin should be bypassed to ground with a low-ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Take care to minimize the loop area formed by the bypass capacitor connection between V+ and ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible minimizing strays.
Copyright © 2001–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LMV931-N LMV931-N-Q1 LMV932-N LMV932-N-Q1 LMV934-N LMV934-N-Q1
21
LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
www.ti.com
10.2 Layout Example
Figure 38. SOT-23 Layout Example
22
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Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMV931-N LMV931-N-Q1 LMV932-N LMV932-N-Q1 LMV934-N LMV934-N-Q1
LMV931-N, LMV931-N-Q1
LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1
www.ti.com
SNOS993O – NOVEMBER 2001 – REVISED DECEMBER 2014
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMV931 PSPICE Model (also applicable to the LMV932 and LMV934), http://www.ti.com/lit/zip/snom028
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
TI Filterpro Software, http://www.ti.com/tool/filterpro
11.2 Documentation Support
11.2.1 Related Documentation
For additional applications, see the following: AN-31 Op Amp Circuit Collection, SNLA140
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMV931-N
Click here
Click here
Click here
Click here
Click here
LMV931-N-Q1
Click here
Click here
Click here
Click here
Click here
LMV932-N
Click here
Click here
Click here
Click here
Click here
LMV932-N-Q1
Click here
Click here
Click here
Click here
Click here
LMV934-N
Click here
Click here
Click here
Click here
Click here
LMV934-N-Q1
Click here
Click here
Click here
Click here
Click here
11.4 Trademarks
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2001–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LMV931-N LMV931-N-Q1 LMV932-N LMV932-N-Q1 LMV934-N LMV934-N-Q1
23
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMV931MF
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
A79A
LMV931MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
A79A
LMV931MFX
NRND
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
A79A
LMV931MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
A79A
LMV931MG
NRND
SC70
DCK
5
1000
TBD
Call TI
Call TI
-40 to 125
A74
LMV931MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
A74
LMV931MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
A74
LMV931Q1MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
ALAA
LMV931Q1MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
ALAA
LMV931Q1MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
BBA
LMV931Q1MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
BBA
LMV932MA
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 125
LMV9
32MA
LMV932MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV9
32MA
LMV932MAX
NRND
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 125
LMV9
32MA
LMV932MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV9
32MA
TBD
Call TI
Call TI
LMV932MM
NRND
VSSOP
DGK
8
1000
-40 to 125
A86A
LMV932MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM
& no Sb/Br)
-40 to 125
A86A
LMV932MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM
& no Sb/Br)
-40 to 125
A86A
LMV932Q1MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
-40 to 125
LMV93
2Q1MA
Addendum-Page 1
CU SN
Level-1-260C-UNLIM
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2015
Orderable Device
Status
(1)
LMV932Q1MAX/NOPB
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV93
2Q1MA
(4/5)
ACTIVE
SOIC
D
8
2500
LMV934MA
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
-40 to 125
LMV934MA
LMV934MA/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV934MA
LMV934MAX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
-40 to 125
LMV934MA
LMV934MAX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV934MA
LMV934MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LMV93
4MT
LMV934MTX
NRND
TSSOP
PW
14
2500
TBD
Call TI
Call TI
-40 to 125
LMV93
4MT
LMV934MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LMV93
4MT
LMV934Q1MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV934
Q1MT
LMV934Q1MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV934
Q1MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
27-Jun-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMV931-N, LMV931-N-Q1, LMV932-N, LMV932-N-Q1, LMV934-N, LMV934-N-Q1 :
• Catalog: LMV931-N, LMV932-N, LMV934-N
• Automotive: LMV931-N-Q1, LMV932-N-Q1, LMV934-N-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LMV931MF
SOT-23
DBV
5
1000
178.0
8.4
LMV931MF/NOPB
SOT-23
DBV
5
1000
178.0
LMV931MFX
SOT-23
DBV
5
3000
178.0
LMV931MFX/NOPB
SOT-23
DBV
5
3000
LMV931MG
SC70
DCK
5
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV931MG/NOPB
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV931MGX/NOPB
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV931Q1MF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV931Q1MFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV931Q1MG/NOPB
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV931Q1MGX/NOPB
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV932MAX
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMV932MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMV932MM
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV932MM/NOPB
VSSOP
DGK
8
1000
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV932MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV932Q1MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMV934MAX
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMV934MAX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LMV934MTX
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
LMV934MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
LMV934MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
LMV934Q1MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV931MF
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV931MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV931MFX
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV931MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV931MG
SC70
DCK
5
1000
210.0
185.0
35.0
LMV931MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV931MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
LMV931Q1MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV931Q1MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV931Q1MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV931Q1MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
LMV932MAX
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV932MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMV932MM
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMV932MM/NOPB
VSSOP
DGK
8
1000
364.0
364.0
27.0
LMV932MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMV932Q1MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMV934MAX
SOIC
D
14
2500
367.0
367.0
35.0
LMV934MAX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LMV934MTX
TSSOP
PW
14
2500
367.0
367.0
35.0
LMV934MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
LMV934MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
LMV934Q1MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
Pack Materials-Page 3
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