STMicroelectronics M65KG256AB 256mbit (4 banks x 4m x 16) 1.8v supply, 133mhz clock rate, ddr low power sdram Datasheet

M65KG256AB
256Mbit (4 Banks x 4M x 16)
1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM
PRELIMINARY DATA
Features summary
■
256Mbit SYNCHRONOUS DYNAMIC RAM
– Organized as 4 Banks of 4MWords, each
16 bits wide
■
DOUBLE DATA RATE (DDR)
– 2 Data Transfers/Clock Cycle
– Data Rate: 266Mbit/s (max.)
■
SUPPLY VOLTAGE
– VDD = 1.7 to 1.9V (1.8V typical in
accordance with JEDEC standard)
– VDDQ = 1.7 to 1.9V for Inputs/Outputs
■
SYNCHRONOUS BURST READ AND WRITE
– Fixed Burst Lengths: 2, 4, 8, 16 Words
– Burst Types: Sequential and Interleaved.
– Clock Frequency: 133MHz (7.5ns speed
class)
– Clock Valid to Output Delay (CAS Latency):
3 at 133MHz
– Burst Read Control by Burst Read
Terminate and Precharge Commands
■
AUTOMATIC PRECHARGE
■
BYTE WRITE CONTROLLED BY LDQM AND
UDQM
■
LOW-POWER FEATURES:
– Partial Array Self Refresh (PASR)
– Automatic Temperature Compensated Self
Refresh (ATCSR)
– Driver Strength (DS)
– Deep Power-Down Mode
– Auto Refresh and Self Refresh
■
LVCMOS Interface Compatible with
Multiplexed Addressing
■
OPERATING TEMPERATURE
– - 30 to 85°C
Wafer
The M65KG256AB is only available as part of a multi-chip package Product.
February 2006
Rev 1.0
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/51
www.st.com
1
M65KG256AB
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2/51
2.1
Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Clock Inputs (K, K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9
Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10
Lower/Upper Data Input Mask (LDQM, UDQM) . . . . . . . . . . . . . . . . . . . . . . 10
2.11
Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS) . . . . . . 10
2.12
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.13
VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15
VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Mode Register Set command (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Extended Mode Register Set command (EMRS) . . . . . . . . . . . . . . . . . . . . . 12
3.3
Bank(Row) Activate command (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Read command (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Read with Auto Precharge (READA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6
Burst Read Terminate command (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7
Write command (WRIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8
Write with Auto Precharge command (WRITA) . . . . . . . . . . . . . . . . . . . . . . . 14
3.9
Precharge Selected Bank/Precharge All Banks command (PRE/PALL) . . . . 14
3.10
Self Refresh Entry command (SELF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.11
Self Refresh Exit command (SELFX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
M65KG256AB
4
5
3.12
Auto Refresh command (REF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.13
Power-Down Entry command (PDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.14
Power-Down Exit command (PDEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.15
Deep Power-Down Entry command (DPDEN) . . . . . . . . . . . . . . . . . . . . . . . 16
3.16
Device Deselect command (DESL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.17
No Operation command (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3
Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7
Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
Extended Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/51
M65KG256AB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
4/51
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bank Selection using BA0-BA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Minimum Delay Between two Commands in Concurrent Auto Precharge Mode . . . . . . . . 18
Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Self Refresh Current (IDD6) in Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC Characteristics Measured in Clock Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
M65KG256AB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Simplified Command State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Consecutive Bank(Row) Activate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read followed by Read in Same Bank and Row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read followed by Read in a Different Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Read with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Read with Auto Precharge AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Read Operation (Burst Lengths = 2, 4 and 8, CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . 34
Burst Terminate During Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Write followed by Write in Same Bank and Row. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Write followed by Write in a Different Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Write operation with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Write with Auto Precharge AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Write Operation (Burst Lengths = 2, 4 and 8, CAS Latency = 1) . . . . . . . . . . . . . . . . . . . . 38
Byte Write AC Waveforms (Data Masking using LDQM/UDQM) . . . . . . . . . . . . . . . . . . . . 39
Mode Register/Extended Mode Register Set Commands AC Waveforms . . . . . . . . . . . . . 40
Read followed by Write using the Burst Read Terminate Command (BST) . . . . . . . . . . . 41
Write followed by Read (Write Completed). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Write followed by Read in the same Bank and Row (Write Interrupted). . . . . . . . . . . . . . . 43
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Auto Refresh Command AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Self Refresh Entry and Exit Commands AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Deep Power-Down Entry Command AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Deep Power-Down Exit AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5/51
1 Summary description
1
M65KG256AB
Summary description
The M65KG256AB is a 256Mbit Double Data Rate (DDR) Low Power Synchronous DRAM
(LPSDRAM). The memory array is organized as 4 Banks of 4,194,304 Words of 16 bits each.
The device achieves low power consumption and very high-speed data transfer using the 2-bit
prefetch pipeline architecture that allows doubling the data input/output rate. Command and
address inputs are synchronized with the rising edge of the clock while data inputs/outputs are
transferred on both edges of the system clock. The M65KG256AB is well suited for handheld
battery powered applications like PDAs, 2.5 and 3G mobile phones and handheld computers.
The device architecture is illustrated in Figure 2: Functional Block Diagram. It uses Burst mode
to read and write data. It is capable of two, four, eight or sixteen-Word, sequential and
interleaved burst.
To minimize current consumption during self refresh operations, the M65KG256AB includes
three mechanisms configured via the Extended Mode Register:
●
Automatic Temperature Compensated Self Refresh (ATCSR) adapts the refresh frequency
according to the operating temperature provided by a built-in temperature sensor.
●
Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of
bank, one bank, two banks or all banks.
●
The Deep Power-Down (DPD) mode completely halts the refresh operation and achieves
minimum current consumption by cutting off the supply voltage from the whole memory
array.
The device is programmable through two registers, the Mode Register and the Extended Mode
Register:
6/51
●
The Mode Register is used to select the CAS Latency, the Burst Type (sequential,
interleaved) and the Burst Length. For more details, refer to Table 7: Mode Register
Definition, and to 3.1: Mode Register Set command (MRS) in Section 3: Commands.
●
Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of
bank, one bank, two banks or all banks.
●
The Extended Mode Register is used to configure the low-power features (PASR, ATCSR
and Driver Strength) to reduce the current consumption during the Self Refresh
operations. For more details, refer to Table 8: Extended Mode Register Definition, and to
Section 3.2: Extended Mode Register Set command (EMRS) in Section 3: Commands.
M65KG256AB
Figure 1.
1 Summary description
Logic Diagram
VDD VDDQ
13
16
A0-A12
DQ0-DQ15
2
BA0-BA1
E
UDQS
RAS
LDQS
CAS
M65KG256AB
K
K
KE
W
UDQM
LDQM
VSS
Table 1.
VSSQ
AI10243
Signal Names
A0-A12
Address Inputs
BA0-BA1
Bank Select Inputs
DQ0-DQ15
Data Inputs/Outputs
K, K
Clock Inputs
KE
Clock Enable Input
E
Chip Enable Input
W
Write Enable Input
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
UDQM
Upper Data Input Mask
LDQM
Lower Data Input Mask
UDQS
Upper Data Read/ Write Strobe I/O
LDQS
Lower Data Read/Write Strobe I/O
VDD
Supply Voltage
VDDQ
Input/Output Supply Voltage
VSS
Ground
VSSQ
Input/Output Ground
7/51
M65KG256AB
1 Summary description
Figure 2.
Functional Block Diagram
Clock Generator
K
K
KE
TCSR, PASR
Extended
Mode
Register
Self Refresh
Logic & Timer
Internal Row
Counter
...
Burst Length
Address Buffers
...
...
BA0
DQ15
UDQM/LDQM
UDQS/LDQS
Address
Registers
A0
BA1
DQ0
Column Add
Counter
Bank Select
A12
I/O Buffer & Logic
Column Decoders
...
Column
PreDecoders
Memory
Cell
Array
Sense AMP & I/O Gate
Column
Active
4 Mb x 16 Bank A
...
W
4 Mb x 16 Bank B
Row Decoders
CAS
Refresh
4 Mb x 16 Bank C
Row Decoders
RAS
4 Mb x 16 Bank D
Row Decoders
StateMachine
E
Row
PreDecoders
Row Decoders
Row
Active
Mode
Register
Burst
Counter
CAS Latency
Data Out
Control
ai10242
8/51
M65KG256AB
2
2 Signal descriptions
Signal descriptions
See Figure 1: Logic Diagram, and Table 1: Signal Names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A12)
The A0-A12 Address Inputs are used to select the row or column to be made active. If a row is
selected, all thirteen, A0-A12 Address Inputs are used. If a column is selected, only the nine
least significant Address Inputs, A0-A8, are used. In this latter case, A10 determines whether
Auto Precharge is used:
●
●
During a Read or Write operation:
–
If A10 is High (set to ‘1’), the Read or Write operation includes an Auto Precharge
cycle.
–
If A10 is Low (set to ‘0’), the Read or Write cycle does not include an Auto Precharge
cycle.
When issuing a Precharge command:
–
If A10 is Low, only the bank selected by BA1-BA0 will be precharged.
–
If A10 is High, all the banks will be precharged.
The address inputs are latched at the cross point of K rising edge and K falling edge.
2.2
Bank Select Address Inputs (BA0-BA1)
The Banks Select Address Inputs, BA0 and BA1, are used to select the bank to be made active
(see Table 2: Bank Selection using BA0-BA1).
When selecting the addresses, the device must be enabled, the Row Address Strobe, RAS,
must be Low, VIL, the Column Address Strobe, CAS, and W must be High, VIH.
2.3
Data Inputs/Outputs (DQ0-DQ15)
The Data Inputs/Outputs output the data stored at the selected address during a Read
operation, or to input the data during a write operation.
2.4
Chip Enable (E)
The Chip Enable input, E, activates the memory state machine, address buffers and decoders
when driven Low, VIL. When E is High, VIH, the device is not selected.
2.5
Column Address Strobe (CAS)
The Column Address Strobe, CAS, is used in conjunction with Address Inputs A8-A0 and BA1BA0, to select the starting column location prior to a read or write operation.
9/51
2 Signal descriptions
2.6
M65KG256AB
Row Address Strobe (RAS)
The Row Address Strobe, RAS, is used in conjunction with Address Inputs A11-A0 and BA1BA0, to select the starting address location prior to a Read or Write.
2.7
Write Enable (W)
The Write Enable input, W, controls writing.
2.8
Clock Inputs (K, K)
The Clock signals, K and K, are the master clock inputs. All input signals except UDQM/LDQM,
UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising edge and K falling edge.
During read operations, UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising
edge and K falling edge. During write operations, UDQM/LDQM and DQ0-DQ15 are referred to
the cross point of UDQS/LDQS and VREF, and UDQS/LDQS to the cross point of K rising edge
and K falling edge.
2.9
Clock Enable (KE)
When driven Low, VIL, the Clock Enable input, KE, is used to suspend the Clock K, to switch the
device to Self Refresh, Power-Down or Deep Power-Down mode.
The Clock Enable, KE, must be stable for at least one clock cycle. This means that, if KE level
changes on K rising edge and K falling edge with a setup time of tAS, it must be at the same
level by the next K rising edge with a hold time of tAH.
2.10
Lower/Upper Data Input Mask (LDQM, UDQM)
Lower Data Input Mask and Upper Data Input Mask are input signals used to mask the written
data. UDQM and LDQM are sampled when UDQS/LDQS level crosses VREF. When LDQM is
Low, VIL, DQ0 to DQ7 Inputs/Outputs are selected. When UDQM is Low, VIL, DQ8 to DQ15
Inputs/Outputs are selected.
2.11
Lower/Upper Data Read/Write Strobe Input/Output (LDQS,
UDQS)
LDQS and UDQS can be either input or output signals and act as write data strobe and read
data strobe respectively. LDQS and UDQS are the strobe signals for DQ0 to DQ7 and DQ8 to
DQ15, respectively.
2.12
VDD Supply Voltage
VDD provides the power supply to the internal core of the memory device. It is the main power
supply for all operations (Read and Write).
10/51
M65KG256AB
2.13
2 Signal descriptions
VDDQ Supply Voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered
independently of VDD. VDDQ can be tied to VDD or can use a separate supply. It is
recommended to power-up and power-down VDD and VDDQ together to avoid certain conditions
that would result in data corruption.
2.14
VSS Ground
Ground, VSS, is the reference for the core power supply. It must be connected to the system
ground.
2.15
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS.
Note: Each device in a system should have VDD and VDDQ decoupled with a 0.1µF ceramic
capacitor close to the pin (high frequency, inherently low inductance capacitors should be as
close as possible to the package).
Table 2.
Bank Selection using BA0-BA1
Selected Bank
BA0
BA1
Bank A
VIL
VIL
Bank B
VIH
VIL
Bank C
VIL
VIH
Bank D
VIH
VIH
11/51
M65KG256AB
3 Commands
3
Commands
The M65KG256AB recognizes a set of commands that are obtained by specific statuses of
Chip Enable, E, Column Address Strobe, CAS, Row Address Strobe, RAS, Write Enable, W,
and address inputs. Refer to Table 3: Commands, in conjunction with the text descriptions
below.
Figure 3: Simplified Command State Diagram shows the operations that are performed when
each command is issued at each state of the DDR LPSDRAM.
3.1
Mode Register Set command (MRS)
The Mode Register Set command is used to configure the Burst Length, Burst Type and CAS
Latency of the device by programming the Mode Register.
The command is issued with KE held High, with BA0, BA1 and A10 set to ‘0’, and E, RAS, CAS
and W driven Low, VIL. The value of address inputs A0 to A7 determines the Burst Length,
Burst Type and CAS Latency of the device (see Table 7: Mode Register Definition and
Figure 19: Mode Register/Extended Mode Register Set Commands AC Waveforms):
●
The Burst Length (2, 4, 8, 16 Words) is programmed using the address inputs A2-A0
●
The Burst Type (sequential or interleaved) is programmed using A3.
●
The CAS Latency (3 Clock cycles) is programmed using A6-A4.
It is required to execute a Mode Register Set command at the end of the Power-up sequence.
Once the command has been issued, it is necessary to wait for at least two clock cycles before
issuing another command.
3.2
Extended Mode Register Set command (EMRS)
The Extended Mode Register Set command is used to configure the low-power features of the
device by programming the Extended Mode Register.
The command is issued with KE held High, BA0 at ‘0’, BA1 at ‘1’, A10 at ‘0’, by driving E, RAS,
CAS and W, Low, VIL. The value of address inputs A0 to A9 determines the Driver Strength, the
part of the array that is refreshed during Self Refresh and the Automatic Temperature
Compensated Self Refresh feature (see Table 8: Extended Mode Register Definition and
Figure 19: Mode Register/Extended Mode Register Set Commands AC Waveforms):
●
The part of the array to be refreshed (all banks, Bank A and B, Bank A only) during Self
Refresh is set using A2-A0.
●
The Driver Strength (full, 1/2 strength, 1/4 strength, 1/8 strength) is set using bits A6-A5
●
The Automatic temperature Compensated Self Refresh feature is always enabled (A9 set
to ‘0’).
It is required to execute an Extended Mode Register Set command at the end of the Power-up
sequence. Once the command has been issued, it is necessary to wait for at least two clock
cycles before issuing another command.
12/51
M65KG256AB
3.3
3 Commands
Bank(Row) Activate command (ACT)
The Bank(Row) Activate command is used to switch a row in a specific bank of the device from
the Idle to the active mode. The bank is selected by BA0 and BA1 and the row by A0 to A12
(see Table 2: Bank Selection using BA0-BA1).
This command is initiated by driving KE High, VIH, with E and RAS Low, VIL, and CAS and W
High.
A minimum delay of tRC is required after issuing the Bank (Row) Activate command prior to
initiating Read and Write operations from and to the active bank.
A minimum time of tRC is required between two Bank(Row) Activate commands to the same
bank (see Figure 6: Consecutive Bank(Row) Activate Command).
3.4
Read command (READ)
The Read command is used to read from the memory array in Burst Read mode. In this mode,
data is output in bursts synchronized with the cross points of the clock signals, K and K.
The start address of the Burst Read is determined by the column address, A0 to A12, and the
bank address, BA0-BA1, at the beginning of the Burst Read operation. A valid Read command
is initiated by driving E and CAS Low, VIL, and W and RAS High, VIH.
3.5
Read with Auto Precharge (READA)
This command is identical to the Read command except that a precharge is automatically
performed at the end of the Read operation. The precharge starts tRPD (Burst Length/2 clock
periods) after the Read with Auto Precharge command is input.
A tRAS(min) delay elapses between the Bank (Row) Activate and the Auto Precharge
commands. This lock-out mechanism allows a Read with auto Precharge command to be
issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min)
requirement.
The DDR LPSDRAM supports the Concurrent Auto Precharge mode: a Read with autoprecharge can be followed by any command to another active bank, as long as that command
does not interrupt the read data transfer, and that all other related limitations apply (e.g.
contention between read data and written data must be avoided). Table 4: Minimum Delay
Between two Commands in Concurrent Auto Precharge Mode shows the minimum delays
between a Read with Auto Precharge command to one bank and a command to a different
bank.
Refer to Figure 10 for a description of Read operation with Auto Precharge.
3.6
Burst Read Terminate command (BST)
The Burst Read Terminate command is used to terminate a Burst Read operation.
It is issued with KE held High, by driving E and W Low and CAS and RAS High. tBSTZ after
issuing the Burst Read Terminate command, DQ0-DQ15 and LDQS, UDQS revert to the high
impedance state (see Figure 12: Burst Terminate During Read Operation).
There is no such command for Burst Write operations.
13/51
M65KG256AB
3 Commands
3.7
Write command (WRIT)
This Write command is used to write to the memory array in Burst Write mode. In this mode,
data is input synchronized with the cross points of the clock signals, K and K.
The start address of the Burst Write is determined by the column address, A0 to A12, and the
address of the selected bank, BA0-BA1, at the beginning of the Burst Read operation. A valid
Write command is initiated by driving E, CAS and W Low, VIL, and RAS High, VIH.
3.8
Write with Auto Precharge command (WRITA)
This command is identical to the Write command except that a precharge is automatically
performed at the end of the Write operation. The precharge starts tWPD (Burst Length/2 +3
clock periods) after the Write with Auto Precharge command is input.
Refer to Figure 16 for a description of Write operation with Auto Precharge.
3.9
Precharge Selected Bank/Precharge All Banks command (PRE/
PALL)
The Precharge Selected Bank and Precharge All Banks are used to place the bank selected by
BA0 and BA1 (see Table 2: Bank Selection using BA0-BA1) and all banks in idle mode,
respectively.
The precharge commands are issued by driving E, RAS and W Low, with CAS and KE held
High. The value on A10 determines whether either the selected bank or all the banks will be
precharged:
●
If A10 is High, BA0-BA1 are Don’t Care and all the banks are precharged.
●
If A10 is Low when, only the bank selected by BA0-BA1 is precharged.
The bank(s) is/are placed in the Idle mode tRP after issuing the Precharge command. Once the
bank is in Idle mode, the Bank (Row) Activate command has to be issued to switch the bank
back to active mode.
The precharge commands can be issued during Burst Read or Burst Write in which case the
Burst Read or Write operation is terminated and the selected bank placed in Idle mode.
The device needs to be in Idle mode before entering Self Refresh, Auto Refresh, Power-Down
and Deep Power-Down.
3.10
Self Refresh Entry command (SELF)
The Self Refresh Entry command is used to start a Self Refresh operation. Before starting a
Self Refresh, the device must be idle. The Self Refresh Entry command is issued by driving KE
Low, with E, RAS, and CAS Low, and W High (see Figure 25: Self Refresh Entry and Exit
Commands AC Waveforms).
During the Self Refresh operation, the internal memory controller generated the addresses of
the row to be refreshed.
The Self Refresh operation goes on as long as the Clock Enable signal, KE, is held Low.
14/51
M65KG256AB
3.11
3 Commands
Self Refresh Exit command (SELFX)
The Self Refresh Exit command is used to exit from Self Refresh mode.
There are two ways to exit from Self Refresh mode:
●
Driving KE Low to High, with E High, RAS, CAS and W Don’t Care,
●
Driving E Low and RAS, CAS and W High.
Non-read commands can be executed 3tCK + tRC after the end of the Self Refresh operation,
where tCK is the Clock period and tRC the RAS Cycle time.
See Figure 25 for a description of Self Refresh Exit AC waveforms.
3.12
Auto Refresh command (REF)
This command performs an Auto Refresh. The device is placed in Auto refresh mode from Idle
by holding KE High, VIH, driving E, RAS and CAS Low and driving W High. The address bits
are “Don’t Care” because the addresses of the bank and row to be refreshed are internally
determined by the internal refresh controller. The output buffer becomes High-Z after the Auto
Refresh has started. Precharge operations are automatically completed after the Auto Refresh.
A Bank(Row) Activate, a Mode Register Set or an Extended Mode Register Set command can
be issued tRFC after the last Auto Refresh command (see Figure 24: Auto Refresh Command
AC Waveforms).
The average refresh cycle is tREF (see Table 15: AC Characteristics). To optimize the operation
scheduling, a flexibility in the absolute refresh interval is provided.
A maximum of eight Auto Refresh commands can be issued to the DDR LPSDRAM and the
maximum absolute interval between two Auto Refresh commands 9tREF.
3.13
Power-Down Entry command (PDEN)
The DDR LPSDRAM is caused to enter Power-Down mode from Idle by driving either:
●
KE Low and E High (other signals are Don’t Care),
●
KE Low and RAS, CAS and W High with E Low.
The Power-Down mode continues as long as KE remains Low.
3.14
Power-Down Exit command (PDEX)
The DDR LPSDRAM exits from Power-Down mode by driving KE High.
15/51
M65KG256AB
3 Commands
3.15
Deep Power-Down Entry command (DPDEN)
The device is placed in Deep Power-Down mode by driving KE Low, with E and W Low and
RAS and CAS High (see Figure 26: Deep Power-Down Entry Command AC Waveforms). All
banks must be precharged or in idle state before entering the Deep Power-Down mode.
After the command execution, the device remains in Deep Power-Down mode while KE is low.
Deep Power-Down Exit (DPDEX)
The M65KG256AB exits Deep Power-Down mode by asserting KE High. A special sequence is
then required before the device can take any new command into account:
1.
Maintain No Operation status conditions for a minimum of 200µs,
2.
Issue a Precharge All Banks command (see Section 3.9: Precharge Selected Bank/
Precharge All Banks command (PRE/PALL) for details),
3.
Once all banks are precharged and after the minimum tRP delay is satisfied, issue 2 or
more Auto Refresh commands,
4.
Issue a Mode Register Set command to initialize the Mode Register bits,
5.
Issue an Extended Mode Register Set command to initialize the Extended Mode Register
bits.
The Deep Power-Down mode exit sequence is illustrated in Figure 27: Deep Power-Down Exit
AC Waveforms.
3.16
Device Deselect command (DESL)
When the Chip Enable, E, is High at the cross point of the Clock K rising edge with VREF, all
input signals are ignored and the device internal status is held.
3.17
No Operation command (NOP)
The device is placed in the No Operation mode, by driving CAS, RAS and W High, with E Low
and KE High.
As long as this command is input at the cross point of the Clock K rising edge with the VREF
level, address and data input are ignored and the device internal status is held.
16/51
M65KG256AB
Table 3.
3 Commands
Commands
Command(1)
Mode Register Set
Symbol KEn-1(2)
KEn
E
(2)
RAS
CAS
W
VIL
MRS
VIH
Extended Mode Register
Set
EMRS
Bank (Row) Activate
ACT
Read
READ
Read with Auto Precharge
READA
Burst Read Terminate
BST
Write
WRIT
Write with Auto Precharge
WRITA
Precharge Selected Bank
PRE
BA1 BA0
VIH
VIL
VIL
VIL
VIL
VIL
VIH
A0-A9,
A11-A12
MR/EMR
Data(3)
MR/EMR
Data(3)
VIH
VIH
VIL
VIL
VIH
VIH
V
V
VIH
VIH
VIL
VIH
VIL
VIH
V
V
VIH
VIH
VIL
VIH
VIH
VIL
X
X
X
VIH
VIH
VIL
VIH
VIL
VIL
V
V
Column
Address
VIH
VIH
VIL
VIL
VIH
VIL
Precharge All Banks
PALL
Self-Refresh Entry(8)
SELF
VIH
VIL
Self Refresh Exit
SELFX
VIL
VIH
Auto Refresh(8)
REF
VIH
VIH
Power-Down Entry(8)
PDEN
VIH
VIL
Power-Down Exit
PDEX
VIL
VIH
VIL
VIL
VIL
VIH
VIH
X
X
X
VIL
VIH
VIH
VIH
VIL
VIL
VIL
VIH
VIH
X
X
X
VIL
VIH
VIH
VIH
VIH
X
X
X
VIL
VIH
VIH
VIH
A10
VIL
Row Address
Column
Address
VIL(4)
VIH(5)
VIL(4)
VIH(5)
V(6)
V(6)
X
VIL(6)
X(7)
X(7)
X
VIH(7)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Deep Power-down Entry(8)
DPDEN
VIH
VIL
VIL
VIH
VIH
VIL
X
X
X
Deep Power-down Exit
DPDEX
VIL
VIH
X
X
X
X
X
X
X
1. X = Don’t Care (VIL or VIH); V = Valid Address Input.
2. Clock Enable KE must be stable at least for one clock cycle.
3. MR and EMR data is the value to be written in the Mode Register and Extended Mode Register, respectively.
4. If A10 is Low, VIL, when issuing the command, the row remains active at the end of the operation.
5. If A10 is High, VIH, when issuing the command, an automatic precharge cycle is performed at the end of the operation and
the row reverts to the Idle mode.
6. If A10 is Low, VIL, when issuing the command, only the bank selected by BA0-BA1 is precharged (BA0-BA1 should be
valid).
7. If A10 is High, VIH, when issuing the command, all the banks are precharged and BA0-BA1 are Don’t Care.
8. All the banks must be idle before executing this command.
17/51
M65KG256AB
3 Commands
Table 4.
Minimum Delay Between two Commands in Concurrent Auto Precharge Mode
From Command
READA
WRITEA
To Command(1)
Minimum Delay Between the 2 Commands in
Concurrent auto Precharge Mode(2)
Unit
READ or READA
BL/2
tCK
WRITE or WRITEA
CAS Latency (rounded up) + BL/2
tCK
PRE, PALL or ACT
1
tCK
READ or READA
1 + BL/2 + tWTR
tCK
WRITE or WRITEA
BL/2
tCK
PRE, PALL or ACT
1
tCK
1. This command must be issued to a different Bank from the initial command and must not interrupt it.
2. BL = Burst Length.
Table 5.
Burst Type Definition
Burst Length = 2 Burst Length = 4
Words
Words
Start
Addr.
(A0-A3) Sequen Inter- Sequen- Inter-tial
leaved
leaved
tial
Burst Length = 8 Words
Sequential
Interleaved
Burst Length = 16 Words
Sequential
Interleaved
00h
0-1
0-1
0-1-2-3
0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0-1-2-..D-E-F
0-1-2-..D-E-F
01h
1-0
1-0
1-2-3-0
1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3..D-E-F-0
1-0-3-..C-F-E
02h
2-3-0-1
2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
2-3-4..E-F-0-1 2-3-0- ..F-C-D
03h
3-0-1-2
3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
3-4-5..F-0-1-2
3-2-1-..E-D-C
04h
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
4-5-6..0-1-2-3
4-5-6-..9-A-B
05h
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
5-6-7..1-2-3-4
5-4-7..8-B-A
06h
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
6-7-8..2-3-4-5
6-7-4-..B-8-9
07h
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
7-8-9..3-4-5-6
7-6-5-..A-9-8
08h
8-9-A..4-5-6-7
8-9-A..5-6-7
09h
9-A-B..5-6-7-8
9-8-A..4-7-6
0Ah
A-B-C..6-7-8-9
A-B-8..7-4-5
0Bh
B-C-D..7-8-9-A
B-A-9..6-5-4
0Ch
C-D-E..8-9-A-B C-D-E..1-2-3
0Dh
D-E-F..9-A-B-C
D-C-F..0-3-2
0Eh
E-F-0..A-B-CD
E-F-C..3-0-1
0Fh
F-0-1..B-C-D-E
F-E-D..2-1-0
18/51
M65KG256AB
Simplified Command State Diagram
Extended
Mode Register
Set
Self
Refresh
SE
LF
Ex
it
SE
LF
S
R
EM
MRS
Mode Register
Set
REF
IDLE
Auto Refresh
CK
CK
E
Power-Down
ACT
Deep
Power-Down
E
D
PD
D
EN
ee
Ex p P
it ow
Se e
qu r-D
en ow
ce n
CKE
CKE
T
BS
d
ea
R
ith
d w rge
Rea recha
oP
aut
PRE
Ter
h
rec
E (P
READA
PR
n)
atio
in
erm
Precharge
rec
har
ge
eT
arg
POWER-ON
READ
min
E (P
PR
WRITEA
Read
n)
Read
WRITE
Active
Power-Down
atio
Write
W
Aut rite wit
oP
rech h
arge
ROW
ACTIVE
W
rite
Figure 3.
3 Commands
Precharge
Automatic Sequence
Manual Input
Deep Power-Down Exit Sequence
ai11204
19/51
4 Operating modes
4
M65KG256AB
Operating modes
There are 7 operating modes that control the memory. Each of these is composed by a
sequence of commands (see Table 6: Operating Modes for a summary).
4.1
Power-Up
The DDR LPSDRAM has to be powered up and initialized in a well determined manner:
1.
After applying power to VDD and VDDQ an initial pause of at least 200µs is required before
the signals can be toggled.
2.
The Precharge command must then be issued to all banks. Until the command is issued
KE and UDQM/LDQM must be held High to make sure that DQ0-DQ15 remain high
impedance.
3.
tRP after precharging all the banks, the Mode Register and the Extended Mode Register
must be set by issuing a Mode Register Set command and an Extended Mode Register
Set command, respectively. A minimum pause of tMRD must be respected after each
register set command.
4.
After the two registers are configured, two or more auto Refresh cycles must be executed
before the device is ready for normal operation.
The third and fourth steps can be swapped.
Refer to Figure 23 for a detailed description of the Power-Up AC waveforms.
4.2
Burst Read
The M65KG256AB is switched in Burst Read mode by issuing a Bank (Row) Activate command
to set the bank and column addresses to be read from, followed by a Read command (see
sections 3.3: Bank(Row) Activate command (ACT) and 3.4: Read command (READ) for
details).
Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the A10
Address Input. If A10 is High (set to ‘1’) when the Burst Read command is issued, the Burst
Read operation will be followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’), the row
will remain active for subsequent accesses.
Burst Read operations are performed at Word level only. Different Burst Types (sequential or
interleaved), Burst Lengths (2, 4, 8 or 16 Words) can be programmed using the Mode Register
bits. Only a CAS Latency of 3 clock cycles is available. Refer to Section 5.1: Mode Register
description, and to Section 3.1: Mode Register Set command (MRS), for details on the Mode
Register bits and how to program them.
The Burst Read starts 3tCK + tAC after the Clock K rising edge where the Read command is
latched, where tCK is the Clock period and tAC is the access time from K or K. Data Strobe,
UDQS/LDQS, are output simultaneously with data. tRPRE prior to the first rising edge of the
data strobe, the UDQS/LDQS signals go from High-Z to Low state. This Low pulse is referred to
as the Read Preamble. The burst data are then output synchronized with the rising and falling
edge of the data strobe. UDQS/LDQS become High-Z on the next clock cycle after the Burst
20/51
M65KG256AB
4 Operating modes
Read is completed. tRPST from the last falling edge of the data strobe, the DQS pins become
High-Z. This low period of DQS is referred as Read Postamble.
See Table 5: Burst Type Definition, Table 15: AC Characteristics, Table 16: AC Characteristics
Measured in Clock Period, and Figures 9 and 11, for a detailed description of Burst Read
operation and characteristics.
Burst Read can be terminated by issuing a Burst Read Terminate command (see Section 3.6:
Burst Read Terminate command (BST) and Figure 12: Burst Terminate During Read
Operation).
The interval between Burst Read to Burst Read and Burst Read to Burst Write commands are
described in Figures 7, 8 and 20.
4.3
Burst Write
The M65KG256AB is switched in Burst Write mode by issuing a Bank (Row) Activate command
to set the bank and column addresses to be written to, followed by a Write command (see
sections 3.3: Bank(Row) Activate command (ACT) and 3.7: Write command (WRIT) for details).
Burst Write can be accompanied by an Auto Precharge cycle depending on the state of the A10
Address Input. If A10 is High (set to ‘1’) when the Write command is issued, the Write operation
will be followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’), Auto Precharge is not
selected and the row will remain active for subsequent accesses.
Burst Write operations can be performed either at Byte or at Word level. The CAS Latency for
Burst Write operations is fixed to 1 clock cycle.
UDQS/LDQS input act as the strobe for the input data and UDQM/LDQM select the Byte to be
written. UDQS/LDQS must be Low tWPRE prior to their first rising edge; and can be changed to
High-Z tWPST after their last falling edge. These two periods of time are referred to as Write
Preamble and Write Postamble, respectively.
See Table 15: AC Characteristics, Table 16: AC Characteristics Measured in Clock Period, and
Figures 15, 17, and 18, for a detailed description of Burst Write AC waveforms and
characteristics.
The interval between Burst Write to Burst Write commands are described in Figures 13, 14, 21
and 22.
4.4
Self Refresh
In the Self Refresh mode, the data contained in the DDR LPSDRAM memory array is retained
and refreshed. The size of the memory array to be refreshed is programmed in the Extended
Mode Register. Only the data contained in the part of the array selected for Self Refresh will be
retained and refreshed. In this respect, this is a power saving feature.
The Self Refresh mode is entered and exited by issuing a Self Refresh Entry and Self Refresh
Exit command, respectively (see Section 3: Commands). When in this mode, the device is not
clocked any more.
21/51
M65KG256AB
4 Operating modes
4.5
Auto Refresh
The Automatic Temperature Compensated Self Refresh mode (ATCSR) is used to refresh the
whole DDR RAM array in normal operation mode whenever needed.
The device is placed in the Auto Refresh mode by issuing an Auto Refresh command (see
Section 3: Commands).
4.6
Power-Down
In Power-Down mode, the current is reduced to the active standby current (IDD3P).
The Power-Down mode is initiated by issuing a Power-Down Entry command. tPDEN (1 clock
cycle) after the cycle when this command was issued, the DDR LPSDRAM enters into PowerDown mode. In Power-Down mode, power consumption is reduced by deactivating the input
initial circuit. There is no internal refresh when the device is in the Power-Down mode.
The device can exit from Power-Down tPDEX (1 cycle minimum) after issuing a Power-Down Exit
command.
See Section 3: Commands for details on the Power-Down Entry and Exit commands.
4.7
Deep Power-Down
In Deep Power-Down mode, the power consumption is reduced to the standby current (IDD7).
Before putting the device in the Deep Power-Down mode all the banks must be Idle or have
been precharged.
The Deep Power-Down mode is entered and exited by issuing a Deep Power-Down Entry and a
Deep Power-Down Exit command.
See Section 3: Commands for details on the Power-Down Entry and Exit commands.
Table 6.
Operating Modes
Operating Mode(1)
KEn-1
KEn
E
RAS
CAS
W
A10
A9, A11
A0-A8
BA0-BA1
Burst Read
VIH
VIH
VIL
VIH
VIL
VIH
VIL(2)
X
Start Column
Address
Bank
Select
Burst Write
VIH
VIH
VIL
VIH
VIL
VIL
VIL(2)
X
Start Column
Address
Bank
Select
Self Refresh
VIH
VIL
VIL
VIL
VIL
VIH
X
X
Auto Refresh
VIH
VIH
VIL
VIL
VIL
VIH
X
X
Power-Down
VIH
VIL
VIL
VIH
VIH
VIH
X
X
VIH
X
X
X
VIH
VIL
VIL
VIH
VIH
VIL
X
X
Deep Power-Down
1. X = Don’t Care VIL or VIH.
2. If A10 = VIL the Burst Read or Write operation is not followed by an Auto Precharge cycle. If A10 = VIH, the Burst Read or
Write operation is followed by an Auto Precharge cycle to the bank selected by BA0-BA1.
22/51
M65KG256AB
5
5 Registers description
Registers description
The DDR Mobile RAM has the two mode registers, the Mode Register and the Extended Mode
register.
5.1
Mode Register description
The Mode Register is used to select the CAS Latency, Burst Type, and Burst Length of the
device:
●
The CAS Latency defines the number of clock cycles after which the first data will be
output during a Burst Read operation.
●
The Burst Type specifies the order in which the burst data will be addressed. This order is
programmable either to sequential or interleaved (see Table 5: Burst Type Definition).
●
The Burst Length is the number of Words that will be output or input during a Burst Read
or Write operation. It can be configured as 2, 4, 8 or 16 Words.
The Mode Register must be programmed at the end of the Power-Up sequence prior to issuing
any command. It is loaded by issuing a Mode Register Set command (MRS), with BA0-BA1 are
set to ‘00’ to select the Mode Register.
Table 7: Mode Register Definition, shows the available Mode Register configurations.
Table 7.
Mode Register Definition
Address
Bits
Mode
Register Bit
Register Description
A12-A7
-
-
A6-A4
MR6-MR4
CAS Latency Bits
(Read Operations)
A3
A2-A0
MR3
MR2-MR0
Value
Description
000000
011
3 Clock Cycles
Other configurations reserved
0
Sequential
1
Interleaved
001
2 Words
010
4 Words
011
8 Words
100
16 Words
Burst Type Bit
Burst Length Bit
Other configurations reserved
BA1-BA0
-
-
00
23/51
M65KG256AB
5 Registers description
5.2
Extended Mode Register description
The Extended Mode Register is used to program the low-power Self Refresh operation of the
device:
●
Partial Array Self Refresh
●
Driver Strength
●
Automatic Temperature Compensated Self Refresh.
It is loaded by issuing a Extended Mode Register Set command (EMRS) with BA0-BA1 set to
‘01’ to select the Extended Mode Register.
Table 8: Extended Mode Register Definition, shows the available Extended Mode Register
configurations.
Table 8.
Extended Mode Register Definition
Address
Bits
Mode Register
Bit
Description
A12-A10
-
-
A9
EMR9
A8-A7
A6-A5
A4-A3
A2-A0
-
EMR6-EMR5
-
EMR2-EMR0
Value
000
0
Automatic Temperature
Compensated Self Refresh Bits 1
-
Description
Enabled
Reserved
00
00
Full Strength
01
1/2 Strength
10
1/4 Strength
11
1/8 Strength
Driver Strength Bits
-
00
000
All Banks
001
Bank A and Bank B (BA1=0)
010
Bank A (BA0 and BA1 =0)
Partial Array Self Refresh Bits
Other configurations reserved
BA1-BA0
24/51
-
-
10
M65KG256AB
6
6 Maximum rating
Maximum rating
Stressing the device above the ratings listed in Table 9: Absolute Maximum Ratings, may cause
permanent damage to the device. These are stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
Table 9.
Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
TJ
Junction Temperature
-30
85
°C
TSTG
Storage Temperature
-55
125
°C
VIO
Input or Output Voltage
-0.5
2.3
V
VDD, VDDQ
Supply Voltage
-0.5
2.3
V
IOS
Short Circuit Output Current
50
mA
PD
Power Dissipation
1.0
W
25/51
M65KG256AB
7 DC and AC parameters
7
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 10. AC characteristics are measured with driver strength set to “Full Strength” (EMR5EMR6 set to ‘00’). Designers should check that the operating conditions in their circuit match
the measurement conditions when relying on the quoted parameters.
Table 10.
Operating and AC Measurement Conditions
M65KG256AB
Parameter(1)
Symbol
Units
Min
Typ
Max
Supply Voltage
1.7
1.8
1.9
V
Input/Output Supply Voltage
1.7
1.8
1.9
V
TJ
Ambient Temperature
-30
85
°C
CL
Load Capacitance
15
pF
VIL
Input Pulses Voltages
0.2
V
VIH
Input Pulses Voltages
1.6
V
Input and Output Timing Ref. Voltages
0.9
V
VID
Input Differential Voltage (K and K)
1.4
V
VIX
Input differential Cross Point Voltage (K and K)
VDDQ/2(2)
V
1
V/ns
VDD
VDDQ(2)
VREF
∆VI/∆ tR
Input Signal Slew Rate
1. All voltages are referenced to VSS.
2. VDD must be equal to VDDQ.
Figure 4.
AC Measurement I/O Waveform
Clock Timing Reference Voltage
K
VIX
VREF
K
Output Transition Timing Reference Voltage
VDDQ
VREF
0V
Input Transition Timing Voltage
VIH
VIL
Dt
Input Signal Slew Rate = VIH - VIL
Dt
26/51
AI10238
M65KG256AB
Figure 5.
7 DC and AC parameters
AC Measurement Load Circuit
DEVICE
UNDER
TEST
Output
CL
AI11353
Table 11.
Capacitance
M65KG256AB
Symbol
Parameter
Signal
Unit
Min
Max
K, K
2.0
3.0
pF
All other input pins
2.0
3.0
pF
DQ0-DQ15, UDQS/LDQS, LDQM/UDQM
3.0
4.0
pF
CI1(1)
Input Capacitance
CI2(1)
CIO(1)(2)
Data I/O Capacitance
1. TJ = 25°C; VDD and VDDQ = 1.7 to 1.9V; f = 133MHz; VOUT = VDDQ/2; VOUT = 0.2V.
2. Data Output are disabled.
Table 12.
DC Characteristics 1
M65KG256AB
Symbol
Parameter
Unit
Test Condition
Min
ILI
Input Leakage Current
ILO
Output Leakage Current
Typ.
Max
0V≤VIN ≤VDDQ
-1.0
1.0
µA
0V≤VOUT ≤VDDQ,
DQ0-DQ15
disabled.
-1.5
1.5
µA
VIH(1)
Input High Voltage
VIN = 0V
0.8VDDQ
VDDQ+0.3
V
VIL(2)
Input Low Voltage
VIN = 0V
−0.3
0.3
V
0.2
V
VOL
Output Low Voltage
IOUT = 100µA
VOH
Output High Voltage
IOUT = −100µA
VIN
Input Voltage Level for K/K inputs
VIX
Input Differential Cross Point Voltage
for K / K inputs
VID
Input Differential Voltage for K/ K
inputs
VDDQ-0.2
-0.3
V
VDDQ+0.3
0.5VDDQ-0.2 0.5VDDQ 0.5VDDQ+0.2
1.0
VDDQ+0.6
V
V
1. VIH maximum value = 2.6V (pulse width 5ns).
2. VIL minimum value = 1.0V (pulse width 5ns).
27/51
M65KG256AB
7 DC and AC parameters
Table 13.
DC Characteristics 2
Symbol
IDD1(2)
IDD2P
IDD2PS
Test Condition(1)(2)
Parameter
Operating Current
M65KG256AB Unit
Burst length = 4, one bank active
tRC ≥ tRC(min), IOL = 0mA
60
KE ≤VIL(max), tCK = 15ns
0.8
KE ≤VIL(max), tCK = ∞
0.6
Precharge Standby Current in PowerDown Mode
mA
mA
KE ≥ VIH (min), E ≥ VIH (min),
IDD2N
Precharge Standby Current in Non
Power-Down Mode
IDD3PS
mA
KE ≥ VIH (min), tCK = ∞
IDD2NS
IDD3P
3
tCK = 15ns, Input signals changed
once in 2 clock cycles.
2
Input signals are stable
Active Standby Current in Power-Down
Mode
KE ≤VIL(max), tCK = 15ns
1.5
KE ≤VIL(max), tCK = ∞
1.2
mA
KE ≥ VIH (min), E ≥ VIH (min),
IDD3N
Active Standby Current in Non PowerDown Mode
10
tCK = 15ns, Input signals are changed
once in 2 clock cycles.
mA
KE ≥ VIH (min), tCK = ∞
IDD3NS
7
Input signals are stable
tCK ≥ tCK (min), IOL = 0mA
All banks active
Burst Length = 4
130
mA
Auto Refresh Current
tRRC ≥ tRRC (min)
60
mA
IDD6
Self Refresh Current
KE ≤0.2V
See Table 14
µA
IDD7
Standby Current in Deep Power-down
Mode
KE ≤0.2V (see Deep Power-Down
mode description)
10
µA
IDD4(2)
Burst Mode Current
IDD5(3)
1. VDD and VDDQ = 1.7 to 1.9V, VSS = VSSQ = 0V.
2. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
3. Addresses change only once during tCK.
Table 14.
Self Refresh Current (IDD6) in Normal Operating Mode
Memory Array(1)
Temperature in °C
All Banks
Typ
Max
2 Banks
Typ
Max
Typ
Max
-30 ≤TJ ≤40
200
160
160
µA
40 ≤TJ ≤65
350
270
220
µA
65 ≤TJ ≤85
550
400
320
µA
1. TJ = –30 to 85°C, VDD and VDDQ = 1.7 to 1.9V, VSS = VSSQ = 0V; KE ≤0.2V.
28/51
Unit
1 Bank
M65KG256AB
Table 15.
7 DC and AC parameters
AC Characteristics
M65KG256AB(1)
Symbol
Alt
tAC(2)
Parameter
Unit
Min
Max
Data Output Access Time from K and K
1.5
6.0
ns
tAS(3)
tIS
Address and Control Input Setup Time
1.4
ns
tAH(3)
tIH
Address Control Input Hold Time
1.4
ns
Clock Cycle Time
7.5
ns
tDQSCK(2)
UDQS/LDQS Access Time from K and K
1.5
6.0
ns
tDQSHZ(5)
UDQS/LDQS High-Z Time from K and K
1.5
6.0
ns
tDQSLZ(6)
UDQS/LDQS Low-Z Time from K and K
1.5
6.0
ns
tDQSQ(3)
UDQS/LDQS to Data Output Skew
0.65
ns
tCK
tDV(4)
Data Output Valid to Data Output Transition Time
tDS(3)
tDH(3)
2
ns
Data Input and UDQM/LDQM Setup Time
0.9
ns
Data Input and UDQM/LDQM Hold Time
0.9
ns
tOHZ(5)
tHZ
Data Output High-Z Time from K and K
1.5
6.0
ns
tOLZ(6)
tLZ
Data Output Low-Z Time from K and K
1.5
6.0
ns
tRAS
RAS Active Time (Bank (Row) Activate to Bank Precharge)
45
120000
ns
tRC
RAS Cycle Time (Bank (Row) Activate to Bank Activate in Auto
Refresh mode)
75
ns
tRCD
Delay Time, from RAS Active to CAS Active
30
ns
tRRD
Delay Time, from RAS Active to RAS Bank Active
15
ns
22.5
ns
tSRE
tRP
RAS Precharge Time
tREF
Average Periodic Refresh Time
tSREX
tWPRES
7.8
µs
Self Refresh Exit Time
16
ns
Write Preamble Setup Time
0
ns
1. The above timings are measured according to the test conditions shown in Table 10: Operating and AC Measurement
Conditions.
2. These timings define the signal transition delays from K or K cross point, that is when K or K signal crosses VREF.
3. The timing reference level is VREF.
4. tDV defines the delay between two successive transitions of the data output signals, that is when DQ0-DQ15
cross VREF.
5. tOHZ and tDQSHZ define the transition time from Low-Z to High-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read
operation, respectively. They specify when data outputs stop being driven.
6. tOLZ and tDQSLZ define the transition time from High-Z to Low-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read
operation. They specify when data outputs begin to be driven.
29/51
M65KG256AB
7 DC and AC parameters
Table 16.
AC Characteristics Measured in Clock Period
M65KG256AB
Symbol
Alt
Parameter
Unit
Min
Max
tBSTW(1)
Burst Read Terminate Command to Write Command Delay Time
3
tCK
tBSTZ(1)
Burst Read Terminate Command to Data Output Hi-Z
3
tCK
tCHW
tCH
Clock High Pulse Width
0.45
0.55
tCK
tCLW
tCL
Clock Low Pulse Width
0.45
0.55
tCK
tDAL
Autoprecharge write recovery and precharge time
2tCK + 22.5
ns
tDMD
UDQM/LDQM to Data Input Latency
0
tCK
tDQSS
Write Command to First UDQS/LDQS Latching Transition
0.75
tDSS(2)
UDQS/LDQS Falling Edge to K Setup Time
0.2
tCK
tDSH(2)
UDQS/LDQS Falling Edge Hold Time from K
0.2
tCK
tDQSH
UDQS/LDQS High Pulse Width
0.35
tCK
tDQSL
UDQS/LDQS Low Pulse Width
0.35
tCK
1.25
tCK
tDPE
tPDEN
Power-Down Entry Time
1
tCK
tDPX
tPDEX
Power-Down Exit Time
1
tCK
Mode Register Set Cycle Time
2
tCK
Precharge Command to Data Output High-Z
3
tCK
tMRD
tPROZ(1)
tHZP
tRPRE
Read Preamble Time
0.9
1.1
tCK
tRPST
Read Postamble Time
0.4
0.6
tCK
tRFC
RAS Cycle Time (Auto Refresh to Bank Active in Auto Refresh mode)
15
tCK
tRPD
Delay Time from Read to Precharge Command (same Bank)
BL/2(3)
tCK
tRWD
Delay Time from Read to Write Command (all data output)
3+BL/2(3)
tCK
tWTR
Write to Read command Delay
1
tCK
tWPRE
Write Preamble
0.25
tCK
Data Strobe Low Pulse Width (Write Postamble)
0.4
tWPST(2)
0.6
tCK
tWRD
Delay Time from Write to Read Command (all data input)
2+BL/2(3)
tCK
tWPD
Delay Time from Write to Precharge Command (same Bank)
3+BL/2(3)
tCK
tWCD
Write Command to Data Input Latency
1
tCK
tWR
Write Recovery Time
2
tCK
1. CAS Latency equals 3 clock cycles.
2. The transition for Low-Z to High-Z occur when the device outputs become floating. No specific reference voltage is given in
this document.
3. BL stands for Burst Length.
30/51
M65KG256AB
Figure 6.
7 DC and AC parameters
Consecutive Bank(Row) Activate Command
K
K
tRRD
Command
ACT
A CT
Address
Row 0
Row 1
NOP
NOP
PRE
ACT
NOP
Row 0
tRC
BA0-BA1
Bank A
Active
Bank D
Active
Bank A
Active
Precharge
Bank A
ai11210
1. The above figure shows consecutive Bank(Row) Activate commands issued to different banks. A tRRD delay must be
respected between two consecutive Bank(Row) Activate commands (ACT) to different banks. If the destination row is
already active, the bank must be precharged to close the row; the ACT command can then be issued tRP after the PRE
command.
2. Consecutive ACT commands to the same bank must be issued at a tRC interval and separated by a Precharge command
(PRE).
Figure 7.
Read followed by Read in Same Bank and Row
K
K
Command
Address
ACT
NOP
Row
READ
NOP
READ
Column A Column B
BA0-BA1
Read from
Column A
Read from
Column B
DOA0 DOA1 DOB0 DOB1 DOB2 DOB3
DQ0-DQ15
UDQS, LDQS
tRCD
Bank A
Active
Note: 1. Burst Length = 4
2. CAS Latency = 3
3. Bank = Bank A
Data Read from
Column A
Data Read from
Column B
ai11205
1. The consecutive READ command must be issued after a minimum delay of tCK to interrupt the previous Read operation.
2. To issue the consecutive READ to a different row, precharge the bank (PRE) to interrupt the previous Read operation. tRP
after the PRE command, issue the ACT command. The consecutive READ command can be issued tRCD after the ACT
command.
31/51
M65KG256AB
7 DC and AC parameters
Figure 8.
Read followed by Read in a Different Bank
K
K
Command
ACT
Address
Row 0
NOP
ACT
NOP
READ
NOP
READ
Column A Column B
Row 1
BA0-BA1
Read from Read from
Column A Column B
DOA0 DOA1 DOB0 DOB1 DOB2 DOB3
DQ0-DQ15
UDQS/
LDQS
tRCD
Bank A
Active
Data Read from Data Read from
Bank D
Bank A
Read from Read from
Bank D
Bank A
Bank D
Active
Note: 1. Burst Length = 4
2. CAS Latency = 3
ai11206
1. If the consecutive Read operation targets an active row, the second READ command must be issued after a minimum
delay of tCK to interrupt the previous Read operation.
2. If the consecutive Read operation targets an idle row, precharge the bank (PRE) without interrupting the previous Read
operation. tRP after the PRE command, issue the ACT command. The consecutive READ command can be issued tRCD
after the ACT command.
Figure 9.
Read with Auto Precharge
K
K
tRP (min)
tRAS
tRPD
tRCD
Command
ACT
READA
NOP
ACT
UDQS, LDQS
tAC
tDQSCK
DO0 DO1 DO2 DO3
DQ0-DQ15
Note: Burst Length = 2
32/51
Start of
Internal
Auto Precharge cycle
ai10586
M65KG256AB
7 DC and AC parameters
Figure 10. Read with Auto Precharge AC Waveforms
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
tCK
K
K
tCLW
tCHW
tRP
KE
tRC
E
tRAS
RAS
CAS
W
BA0
BA1
A10
Address
tAS
tAS
tAH
tAS
tAH
tAS
tAH
tAH
LDQM/
UDQM
tDQSLZ
tRPRE
tRPST
LDQS/
UDQS
tDQSQ
DQ0-DQ15
Hi-Z
DO0 DO1 DO2 DO3
tRCD
tDV
tDQSHZ
tAC,
tDQSCK
Bank(Row) Activate
in Bank A
Read
from Bank A
Precharge
in Bank A
AI11212
1. Burst Length = 4 Words, CAS Latency = 3 clock cycles.
33/51
M65KG256AB
7 DC and AC parameters
Figure 11. Read Operation (Burst Lengths = 2, 4 and 8, CAS Latency = 3)
t0
t1
t2
t3
t4
t5
t6
K
K
tRCD
Command
NOP
ACT
A0-A12
BA0-BA1
NOP
Row
Address
READ
NOP
Column
Address
tRPST
tRPRE
UDQS,
LDQS(1)
tAC
tDQSCK
DO0 DO1
DQ0-DQ15(1)
UDQS,
LDQS(2)
DO0 DO1 DO2 DO3
DQ0-DQ15(2)
UDQS,
LDQS(2)
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
DQ0-DQ15(2)
Notes: 1. Burst Length = 2
2. Burst Length = 4
3. Burst Length = 8.
4. In all cases, CAS Latency = 3.
ai10552
Figure 12. Burst Terminate During Read Operation
t0 t0.5
t1 t1.5
t2 t2.5
t3 t3.5
t4
t4.5
t5
t5.5
K
K
Command
READ
BST
NOP
tBSTZ
UDQS,
LDQS
DQ0-DQ15
DO0 DO1
ai10585
34/51
M65KG256AB
7 DC and AC parameters
Figure 13. Write followed by Write in Same Bank and Row
K
K
Command
Address
ACT
Row
NOP
WRIT
WRIT
NOP
Column A Column B
BA0-BA1
tRCD
DIA0 DIA1 DIB0 DIB1 DIB2 DIB3
DQ0-DQ15
UDQS, LDQS
Bank A
Active
Note: 1. Burst Length = 4
2. Bank = Bank A
Data Written to
Column A
Data Written to
Column B
ai11207
1. The consecutive WRIT command must be issued after a minimum delay of tCK to interrupt the previous Write operation.
2. To issue the consecutive WRITE to a different row, precharge the bank (PRE) to interrupt the previous Write operation. tRP
after the PRE command, issue the ACT command. The consecutive WRIT command can be issued tRCD after the ACT
command.
35/51
M65KG256AB
7 DC and AC parameters
Figure 14. Write followed by Write in a Different Bank
K
K
Command
ACT
NOP
ACT
NOP
WRIT
NOP
WRIT
tRCD
Address
Row 0
Column A Column B
Row 1
BA0-BA1
DIA0 DIA1
DQ0-DQ15
DIB0 DIB1 DIB2 DIB3
UDQS/
LDQS
Bank A
Active
Data Read from
Bank A
Bank D
Active
Data Read from
Bank D
ai11208b
Note: 1. Burst Length = 4
1. If the consecutive Write operation targets an active row, the second WRIT command must be issued after a minimum delay
of tCK to interrupt the previous Write operation.
2. If the consecutive Write operation targets an idle row, precharge the bank (PRE) without interrupting the previous Write
operation. tRP after the PRE command, issue the ACT command. The consecutive WRIT command can be issued tRCD
after the ACT command.
Figure 15. Write operation with Auto Precharge
K
K
tRAS(min)
tRP
tRCD
Command
ACT
NOP
WRITEA
NOP
ACT
UDQM, LDQM
tWPD
UDQS, LDQS
DQ0-DQ15
Note: Burst Length = 4
36/51
DI0
DI1
DI2
DI3
Start of
Internal
Auto Precharge cycle
ai10587
M65KG256AB
7 DC and AC parameters
Figure 16. Write with Auto Precharge AC Waveforms
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
tCK
K
K
tCLW
tCHW
tRP
KE
tRC
E
tRAS
RAS
CAS
W
BA0
BA1
A10
Address
tAS
tAS
tAH
tAS
tAH
tAS
tAH
tAH
LDQM/
UDQM
tDQSL
tDQSS
LDQS/
UDQS
tWPST
tWPRE
tDS
DQ0-DQ15
tDSH
Hi-Z
DIN
tRCD
DIN+2
DIN+3
tDH
tDQSH
tWR
Bank A
Active
Write
to Bank A
Precharge
in Bank A
AI11213b
1. Burst Length = 4 Words, CAS Latency = 1 clock cycle.
37/51
M65KG256AB
7 DC and AC parameters
Figure 17. Write Operation (Burst Lengths = 2, 4 and 8, CAS Latency = 1)
t0
t1
t2
t3
t4
t5
t6
K
K
tRCD
Command
A0-A12
BA0-BA1
NOP
ACT
NOP
Row
Address
WRITE
NOP
Column
Address
tWPRE
UDQS,
LDQS(1)
tWPRES
DQ0-DQ15(1)
DI0
DI1
tWPST
UDQS,
LDQS(2)
DQ0-DQ15(2)
DI0
DI1
DI2
DI3
DI0
DI1
DI2
DI3
UDQS,
LDQS(2)
DQ0-DQ15(2)
Notes: 1. Burst Length = 2
2. Burst Length = 4
3. Burst Length = 8.
4. In all cases, CAS Latency = 1.
38/51
DI4
DI5
DI6
DI7
ai10553
UDQM
LDQM
Hi-Z
Hi-Z
t2
tCLW
tAH
tAS
t1
Bank/Row Activate
Read
in Bank D
from Bank D
DQ8-DQ15
DQ0-DQ7
t0
High
tAH
tAS
LDQS/
UDQS
tCK
tCHW
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
K
t3
tWPRE
t4
Lower Byte
Read
t5
t6
t7
Upper Byte
Read
tWPST
t8
tAH
t10
tDQSS
tAS
t9
tDQSL
t14
Read from
Bank D
tAH
tAS
t13
Upper Byte
Write
t12
Lower Byte
Write
Upper Byte
Write
t11
t15
t16
t18
Upper Byte
Read
t17
t19
Upper Byte
Read
t20
AI11218
M65KG256AB
7 DC and AC parameters
Figure 18. Byte Write AC Waveforms (Data Masking using LDQM/UDQM)
1. Burst Length = 4 Words.
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M65KG256AB
7 DC and AC parameters
Figure 19. Mode Register/Extended Mode Register Set Commands AC Waveforms
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
K
K
High
KE
tMRD
E
RAS
CAS
W
BA0-BA1
A10
MR
Address
Data (2)
LDQM/
UDQM
LDQS/ Hi-Z
UDQS
DQ0-DQ15
(OUT)
Hi-Z
tRP
Precharge
(optionnal)
Mode Register
Set
Bank D
Active
Read to
Bank D
Precharge
Bank D
1. To program the Extended Mode Register, BA0 and BA1 must be set to ‘0’ and ‘1’ respectively, and A0 to A11 to the
Extended Mode Register Data.
2. MR Data is the value to be written to the Mode Register.
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AI11214
M65KG256AB
7 DC and AC parameters
Figure 20. Read followed by Write using the Burst Read Terminate Command (BST)
t0
t1
READ
BST
t2
t3
t4
t6
t5
t7
t8
K
K
Command
WRIT
NOP
NOP
tBSTZ ( ≥tBSTZ)
UDQM,
LDQM
tBSTZ ( = CL)
DQ0-DQ15
DO0 DO1
DI0
DI1
DI2
DI3
UDQS,
LDQS
Data Output
Note: 1. Burst Length = 4
2. CAS Latency = 3 (CL)
Data Input
ai11209
1. If the Write operation is performed to the same bank and row than the Read operation, the Burst Read Terminate command
(BST) must be issued to terminate the Read operation.The WRIT command can then be issued tBSTW (ŠtBSTW) after the
BST command.
2. If the Write operation is performed to the same bank but to a different row, the bank must be precharged to interrupt the
Read operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued tRCD
after the ACT command.
3. If the Write operation is performed to a different bank and to an active row, the sequence is identical to the one described in
Note 1
4. If the Write operation is performed to a different bank and to an idle row, the bank must be precharged independently from
the Read operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued
tRCD after the ACT command.
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M65KG256AB
7 DC and AC parameters
Figure 21. Write followed by Read (Write Completed)
t0
t1
t2
t3
t4
t5
t6
t7
t8
K
K
Command
WRIT
NOP
READ
NOP
tWRDmin (3)
UDQM,
LDQM
DQ0-DQ15
DI0
DI1
DI2
DI3
DO0 DO1 DO2
UDQS,
LDQS
Data Input
Note: 1. Burst Length = 4
2. CAS Latency = 3 (CL)
3. tWRD = BL/2 + 2 clock cycles
Data Output
ai10838
1. If the Read operation is performed to the same bank and row than the Write operation, the READ command should be
performed tWRD after the WRIT command to complete the Write operation.
2. If the Read operation is performed to the same bank but to a different row, the bank must be precharged tWPD after the
Write operation. tRP after the Precharge command, issue the ACT command. The READ command can then be issued
tRCD after the ACT command.
3. If the Read operation is performed to a different bank and to an active row, the sequence is identical to the one described in
Note 1
4. If the Read operation is performed to a different bank and to an idle row, the bank must be precharged independently from
the Write operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued
tRCD after the ACT command.
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M65KG256AB
7 DC and AC parameters
Figure 22. Write followed by Read in the same Bank and Row (Write Interrupted)
t0
t1
WRIT
READ
t2
t3
t4
t5
t6
t7
t8
K
K
Command
NOP
UDQM,
LDQM
DQ0-DQ15
DI0
DI1
DI2
DO0 DO1 DO2 DO3
UDQS,
LDQS
Data Input Masked
Data Output
Note: 1. Burst Length = 4
2. CAS Latency = 3 (CL)
ai10839
1. UDQM/LDQM must be input 1 clock cycle prior to the READ command to prevent invalid data from being written. If the
READ command is input on the next cycle after the WRIT command, UDQM/LDQM are not necessary.
2. If the Read operation is issued to a different row in the same bank, or to an idle row in a different bank, a Precharge
command (PRE) must be issued before the READ command. In this case, the Read operation does not interrupt the Write
operation.
3. If the Read operation is issued to a different bank, and to an active row, the sequence is identical to the one described in
Note 1
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High
Precharge
All Banks
High 1 Clock Cycle needed
DQ0-DQ15 Hi-Z
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
K
EMR
Data (1)
tMRD
Mode
Extended Mode
CBR
Register Set Register Set Auto Refresh
tRP
MR
Data (1)
tMRD
tRFC
CBR
Auto Refresh
tRFC
2 Refresh Cycles needed
Bank(Row)
Activate
AI11211
7 DC and AC parameters
M65KG256AB
Figure 23. Power-Up Sequence
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
M65KG256AB
7 DC and AC parameters
Figure 24. Auto Refresh Command AC Waveforms
t0
t1
t2
t3
t4
t5
t6
tm
tm+1
tm+2
tm+3
tm+4
tm+5
tm+6
tm+7
tm+8
tm+9
K
K
High
KE
E
RAS
CAS
W
BA0
BA1
A10
Address
LDQM/
UDQM
LDQS/
UDQS
Hi-Z
DQ0-DQ15
(OUT)
Hi-Z
DQ0-DQ15
(IN)
Hi-Z
tRP
Precharge
(optional)
tRFC
Auto Refresh
Bank A
Active
Read from
Bank A
AI11215
1. Burst Length = 4 Words, CAS Latency = 3 clock cycles.
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M65KG256AB
7 DC and AC parameters
Figure 25. Self Refresh Entry and Exit Commands AC Waveforms
t0
t1
t2
t3
t4
t5
tn
tn+1
tn+2
tm
tm+1 tm+2
tm+3 tm+4
tm+5
K
K
tAS
tAH
KE
E
RAS
CAS
W
BA0
BA1
A10
Address
LDQM/
UDQM
UDQS/
LDQS
DQ0-DQ15
(OUT)
DQ0-DQ15
(IN)
Hi-Z
Hi-Z
Hi-Z
tRP
Precharge
(optional)
1. Burst Length = 4 Words.
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tSREX
Self Refresh
Entry
Self Refresh
Exit
Bank A
Active
Read to
Bank A
ai11216
M65KG256AB
7 DC and AC parameters
Figure 26. Deep Power-Down Entry Command AC Waveforms
t0
t1
t2
t3
t4
t5
K
K
KE
E
RAS
CAS
W
A10
UDQM/ Low
LDQM
DQ0-DQ15
Hi-Z
tRP
Precharge
All Banks
Deep Power-Down
Entry
ai10847
1. BA0, BA1 and address bits A0 to A11 (except A10) are ‘Don’t Care’. Upper and Lower Data Input Mask signals, UDQM and
LDQM are Low, VIL.
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High
t1
t2
Precharge
All Banks
200µs
High Level nedeed
1 Clock Cycle needed
t0
Deep
Power-Down
Exit
DQ0-DQ15 Hi-Z
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
K
t5
EMR
Data (1)
t6
t7
tMRD
t8
Mode
Extended Mode Auto Refresh
Register Set Register Set
tRP
t4
MR
Data (1)
tMRD
t3
t9
tRFC
t10
t11
t13
Auto Refresh
t12
t14
t15
t17
t18
tRFC
t19
t20
t21
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
AI11217
Bank/Row Activate
2 Refresh Cycles needed
t16
7 DC and AC parameters
M65KG256AB
Figure 27. Deep Power-Down Exit AC Waveforms
M65KG256AB
8
8 Part numbering
Part numbering
Table 17.
Ordering Information Scheme
Example:
M65KG256AB
8
W
8
Device Type
M65 = Low-Power SDRAM
Mode
K = Wafer Form
Operating Voltage
G = VDD = VDDQ = 1.8V, DDR LPSDRAM, x16
Array Organization
256 = 4 Banks x 4Mbit x 16
Number of Chip Enable Inputs
A = One Chip Enable
Die Version
B = B-Die
Speed
8 = 7.5ns
Delivery Form
W = Wafer Form
Temperature Range
8 = 30 to 85°C
For a list of available options (Speed, Package, etc.) or for further information on any aspect of
this device, please contact the ST Sales Office nearest to you.
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M65KG256AB
9 Revision history
9
50/51
Revision history
Date
Revision
09-Feb-2006
1.0
Changes
First Issue.
M65KG256AB
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