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MSP430FR2422
SLASEE5 – JANUARY 2018
MSP430FR2422 Mixed-Signal Microcontroller
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture
– Clock Supports Frequencies up to 16 MHz
– Wide Supply Voltage Range: 2.0 V to 3.6 V (1)
• Optimized Ultra-Low-Power Modes
– Active Mode: 120 µA/MHz (Typical)
– Standby: LPM3.5, Real-Time Clock (RTC)
Counter With 32768-Hz Crystal: 710 nA
(Typical)
– Shutdown (LPM4.5): 36 nA without SVS
• Low-Power Ferroelectric RAM (FRAM)
– Up to 7.5 KB of Nonvolatile Memory
– Built-In Error Correction Code (ECC)
– Configurable Write Protection
– Unified Memory of Program, Constants, and
Storage
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
– High FRAM-to-SRAM Ratio, up to 4:1
• High-Performance Analog
– Up to 8-Channel 10-Bit Analog-to-Digital
Converter (ADC)
– Internal 1.5-V Reference
– Sample-and-Hold 200 ksps
• Intelligent Digital Peripherals
– Two 16-Bit Timer With Three Capture/Compare
Registers Each (Timer_A3)
– One 16-Bit Counter-Only RTC
– 16-Bit Cyclic Redundancy Check (CRC)
• Enhanced Serial Communications With Support for
Pin Remap Feature (See Device Comparison)
– One eUSCI_A Supports UART, IrDA, and SPI
– One eUSCI_B Supports SPI and I2C
(1)
Minimum supply voltage is restricted by SVS levels (see
VSVSH- and VSVSH+ in PMM, SVS and BOR).
1.2
•
•
•
• Clock System (CS)
– On-Chip 32-kHz RC Oscillator (REFO)
– On-Chip 16-MHz Digitally Controlled Oscillator
(DCO) With Frequency-Locked Loop (FLL)
– ±1% Accuracy With On-Chip Reference at
Room Temperature
– On-Chip Very Low-Frequency 10-kHz Oscillator
(VLO)
– On-Chip High-Frequency Modulation Oscillator
(MODOSC)
– External 32-kHz Crystal Oscillator (LFXT)
– Programmable MCLK Prescalar of 1 to 128
– SMCLK Derived from MCLK With
Programmable Prescalar of 1, 2, 4, or 8
• General Input/Output and Pin Functionality
– Total of 15 I/Os on VQFN-20 Package
– 15 Interrupt Pins (P1 and P2) Can Wake MCU
From Low-Power Modes
• Development Tools and Software
– Development Tools
– MSP-TS430RHL20 Target Development Kit
• Family Members (Also See Device Characteristics)
– MSP430FR2422: 7.25KB of Program FRAM +
256B of Information FRAM + 2KB of RAM
• Package Options
– 20-Pin: VQFN (RHL)
– 16-Pin: TSSOP (PW)
• For Complete Module Descriptions, See the
MSP430FR4xx and MSP430FR2xx Family User's
Guide
Applications
Industrial Sensors
Battery Packs
Portable Appliances
•
•
Electric Toothbrushes
Low-Power Medical, Health, and Fitness
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR2422
SLASEE5 – JANUARY 2018
1.3
www.ti.com
Description
MSP430FR2422 is part of the MSP430™ value line microcontroller (MCU) portfolio, TI’s lowest cost family
of MCUs for sensing and measurement applications. The MSP430FR2422 MCU provides 8KB of
nonvolatile memory with an 8-channel 10-bit ADC. The architecture, FRAM, and integrated peripherals,
combined with extensive low-power modes, are optimized to achieve extended battery life in portable and
battery-powered sensing applications. Available in a 16-pin TSSOP or a 20-pin VQFN package.
TI's MSP430 ultra-low-power FRAM microcontroller platform combines uniquely embedded FRAM and a
holistic ultra-low-power system architecture, allowing system designers to increase performance while
lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and
endurance of RAM with the nonvolatility of flash.
The MSP430FR2422 MCU is supported by an extensive hardware and software ecosystem with reference
designs and code examples to get your design started quickly. Development kits include the MSPTS430RHL20 20-pin target development board. TI also provides free MSP430Ware™ software, which is
available as a component of Code Composer Studio™ IDE desktop and cloud versions within TI Resource
Explorer. The MSP430 MCUs are also supported by extensive online collateral, training, and online
support through the E2E™ Community Forum.
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (2)
MSP430FR2422IPW16
TSSOP (16)
5 mm × 4.4 mm
MSP430FR2422IRHL
VQFN (20)
4.5 mm × 3.5 mm
(1)
(2)
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
CAUTION
System-level ESD protection must be applied in compliance with the devicelevel ESD specification to prevent electrical overstress or disturbing of data or
code memory. See MSP430 System-Level ESD Considerations for more
information.
2
Device Overview
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1.4
SLASEE5 – JANUARY 2018
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
XIN
DVCC
DVSS
RST/NMI
LFXT
Power
Management
Module
P1.x/P2.x
XOUT
Clock
System
FRAM
RAM
MPY32
CRC16
7.25KB
+256B
2KB
32-bit
Hardware
Multiplier
16-bit
Cyclic
Redundancy
Check
I/O Ports
P1 : 8 IOs
P2 : 7 IOs
Interrupt,
Wakeup,
PA : 15 IOs
2 × TA
eUSCI_A0
eUSCI_B0
RTC
Counter
BAKMEM
ADC
Timer_A3
3 CC
Registers
(UART,
IrDA, SPI)
16-bit
Real-Time
Clock
32-bytes
Backup
Memory
8 channels
Single-end
10 bit
200 ksps
MAB
16-MHz CPU
inc.
16 Registers
MDB
EEM
TCK
TMS
TDI/TCLK
TDO
SBWTCK
SBWTDIO
SYS
JTAG
Watchdog
2
(SPI, I C)
LPM3.5 Domain
SBW
Copyright © 2016, Texas Instruments Incorporated
•
•
•
•
Figure 1-1. Functional Block Diagram
The MCU has one main power pair of DVCC and DVSS that supplies digital and analog modules.
Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with
±5% accuracy.
P1 and P2 feature the pin interrupt function and can wake up the MCU from all LPMs, including
LPM3.5 and LPM4.
Each Timer_A3 has three capture/compare registers, but only CCR1 and CCR2 are externally
connected. CCR0 registers can be used only for internal period timing and interrupt generation.
In LPM3.5, the RTC module can be functional while the rest of the peripherals are off.
Device Overview
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Table of Contents
1
2
3
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 1
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 3
Revision History ......................................... 5
Device Comparison ..................................... 6
Related Products ..................................... 6
3.1
4
5
Terminal Configuration and Functions .............. 7
4.1
Pin Diagrams ......................................... 7
4.2
Pin Attributes ......................................... 8
4.3
Signal Descriptions .................................. 10
4.4
Pin Multiplexing
4.5
Buffer Types......................................... 12
4.6
Connection of Unused Pins ......................... 12
.....................................
12
Specifications ........................................... 13
5.1
Absolute Maximum Ratings ......................... 13
5.2
ESD Ratings
5.3
5.4
13
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 14
........................................
Recommended Operating Conditions ...............
Active Mode Supply Current Per MHz ..............
Low-Power Mode LPM0 Supply Currents Into VCC
Excluding External Current..........................
Low-Power Mode (LPM3, LPM4) Supply Currents
(Into VCC) Excluding External Current ..............
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current ....................
Typical Characteristics - Low-Power Mode Supply
Currents .............................................
5.5
5.6
5.7
5.8
5.9
4
6
7
8
14
14
15
16
17
Thermal Resistance Characteristics ................ 18
5.11
Timing and Switching Characteristics ............... 18
............................................
.................................................
6.3
Operating Modes ....................................
6.4
Interrupt Vector Addresses..........................
6.5
Bootloader (BSL) ....................................
6.6
JTAG Standard Interface............................
6.7
Spy-Bi-Wire Interface (SBW)........................
6.8
FRAM................................................
6.9
Memory Protection ..................................
6.10 Peripherals ..........................................
6.11 Input/Output Diagrams ..............................
6.12 Device Descriptors ..................................
6.13 Memory ..............................................
6.14 Identification .........................................
Applications, Implementation, and Layout........
7.1
Device Connection and Layout Fundamentals ......
6.1
Overview
6.2
CPU
7.2
13
5.10
Detailed Description ................................... 38
9
38
38
38
39
41
41
42
42
42
42
51
55
56
64
65
65
Peripheral- and Interface-Specific Design
Information .......................................... 68
Device and Documentation Support ............... 70
8.1
Getting Started and Next Steps ..................... 70
8.2
Device Nomenclature ............................... 70
8.3
Tools and Software
8.4
Documentation Support ............................. 74
8.5
Community Resources .............................. 75
8.6
Trademarks.......................................... 75
8.7
Electrostatic Discharge Caution ..................... 76
8.8
Export Control Notice
8.9
Glossary ............................................. 76
.................................
...............................
72
76
Mechanical, Packaging, and Orderable
Information .............................................. 77
Table of Contents
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
COMMENTS
January 2018
*
Initial release
Revision History
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3 Device Comparison
Table 3-1 summarizes the features of the available family members.
Table 3-1. Device Comparison (1) (2)
DEVICE
PROGRAM FRAM
+ INFORMATION
FRAM (bytes)
SRAM
(bytes)
TA0,TA1
eUSCI_A
eUSCI_B
10-BIT ADC
CHANNELS
GPIOs
PACKAGE
MSP430FR2422IRHL
7424 + 256
2048
2, 3 × CCR (3)
1
1
8
15
20 RHL
(VQFN)
MSP430FR2422IPW16
7424 + 256
2048
2, 3 × CCR (3)
1
1
5
11
16 PW
(TSSOP)
(1)
(2)
(3)
3.1
For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at
www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.
Related Products
For information about other devices in this family of products or related products, see the following links.
Microcontroller (MCU) Product Selection TI's low-power and high-performance MCUs, with wired and
wireless connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power MCUs One platform. One ecosystem. Endless possibilities.
Enabling the connected world with innovations in ultra-low-power microcontrollers with
advanced peripherals for precise sensing and measurement
Products for FRAM MCUs 16-bit microcontrollers for ultra-low-power sensing and system management
in building automation, smart grid, and industrial designs.
Companion Products for MSP430FR2422 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs TI Designs Reference Design Library is a robust reference design library that spans
analog, embedded processor, and connectivity. Created by TI experts to help you jump start
your system design, all TI Designs include schematic or block diagrams, BOMs, and design
files to speed your time to market.
6
Device Comparison
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4 Terminal Configuration and Functions
4.1
Pin Diagrams
P2.3/TA1.2/UCB0STE/A5
P2.2/TA1.1/A4
P1.6/UCA0CLK/TA0CLK/TDI/TCLK
P1.7/UCA0STE/TDO
P1.4/UCA0TXD/UCA0SIMO/TA0.1/TCK
P1.5/UCA0RXD/UCA0SOMI/TA0.2/TMS
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
DNC
Figure 4-1 shows the pinout of the 20-pin RHL package.
19 18 17 16 15 14 13 12
P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/Veref-
20
11
P2.4/TA1CLK/UCB0CLK/A6
10
P2.5/UCB0SIMO/UCB0SDA/A7
MSP430FR2422IRHL
5
6
RST/NMI/SBWTDIO
DVCC
DVSS
7
8
9
P2.6/UCB0SOMI/UCB0SCL
4
P2.0/UCA0TXD/UCA0SIMO/XOUT
3
P2.1/UCA0RXD/UCA0SOMI/XIN
2
TEST/SBWTCK
1
P1.0/UCB0STE/A0/Veref+
P1.1/UCB0CLK/ACLK/A1/VREF+
Figure 4-1. 20-Pin RHL Package (Top View)
Figure 4-2 shows the pinout of the 16-pin PW package.
P1.1/UCB0CLK/ACLK/A1/VREF+
1
16
P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/Veref-
P1.0/UCB0STE/A0/Veref+
2
15
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
TEST/SBWTCK
3
14
DNC
RST/NMI/SBWTDIO
4
13
P1.4/UCA0TXD/UCA0SIMO/TA0.1/TCK
MSP430FR2422IPW16
DVCC
5
12
P1.5/UCA0RXD/UCA0SOMI/TA0.2
DVSS
6
11
P1.6/UCA0CLK/TA0CLK/TDI/TCLK
P2.1/UCA0RXD/UCA0SOMI/XIN
7
10
P1.7/UCA0STE/TDO
P2.0/UCA0TXD/UCA0SIMO/XOUT
8
9
P2.2/TA1.1/A4
Figure 4-2. 16-Pin PW Package (Top View)
Terminal Configuration and Functions
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Pin Attributes
Table 4-1 lists the attributes of all pins.
Table 4-1. Pin Attributes
PIN NUMBER
RHL
1
PW16
1
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
I/O
LVCMOS
DVCC
–
ACLK
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
SIGNAL NAME (1)
A1
VREF+
2
2
3
3
4
4
I
Analog
Power
–
P1.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
I/O
LVCMOS
DVCC
–
A0
I
Analog
DVCC
–
Veref+
I
Analog
Power
–
TEST (RD)
I
LVCMOS
DVCC
OFF
SBWTCK
I
LVCMOS
DVCC
–
RST (RD)
I
LVCMOS
DVCC
OFF
NMI
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
–
N/A
SBWTDIO
5
5
DVCC
P
Power
DVCC
6
6
DVSS
P
Power
DVCC
N/A
P2.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
–
UCA0SOMI
I/O
LVCMOS
DVCC
–
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
–
UCA0SIMO
I/O
LVCMOS
DVCC
–
XOUT
O
LVCMOS
DVCC
–
P2.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
–
UCB0SCL
I/O
LVCMOS
DVCC
–
P2.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
–
UCB0SDA
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
7
7
XIN
P2.0 (RD)
8
9
10
8
–
–
A7
P2.4 (RD)
11
–
TA1CLK
UCB0CLK
A6
(1)
(2)
(3)
(4)
(5)
(6)
8
(2)
Signals names with (RD) denote the reset default pin name.
To determine the pin mux encodings for each pin, see Section 6.11.
Signal Types: I = Input, O = Output, I/O = Input or Output
Buffer Types: LVCMOS, Analog, or Power (see Table 4-3)
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
N/A = Not applicable
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
RHL
12
PW16
–
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
P2.3 (RD)
I/O
LVCMOS
DVCC
OFF
TA1.2
I/O
LVCMOS
DVCC
–
UCB0STE
I/O
LVCMOS
DVCC
–
SIGNAL NAME (1)
A5
13
9
I
Analog
DVCC
–
P2.2 (RD)
I/O
LVCMOS
DVCC
OFF
TA1.1
I/O
LVCMOS
DVCC
–
A4
14
15
10
11
I
Analog
DVCC
–
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
–
TDO
O
LVCMOS
DVCC
–
P1.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
–
TA0CLK
I
LVCMOS
DVCC
–
TDI
I
LVCMOS
DVCC
–
TCLK
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
–
UCA0SOMI
I/O
LVCMOS
DVCC
–
TA0.1
I/O
LVCMOS
DVCC
–
TMS
I
LVCMOS
DVCC
–
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
–
UCA0SIMO
I/O
LVCMOS
DVCC
–
TA0.2
P1.5 (RD)
16
17
18
19
12
13
14
15
I/O
LVCMOS
DVCC
–
TCK
I
LVCMOS
DVCC
–
DNC
–
–
–
–
P1.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
–
UCB0SCL
I/O
LVCMOS
DVCC
–
MCLK
O
LVCMOS
DVCC
–
A3
20
16
(2)
I
Analog
DVCC
–
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
–
UCB0SDA
I/O
LVCMOS
DVCC
–
SMCLK
O
LVCMOS
DVCC
–
A2
I
Analog
DVCC
–
Veref-
I
Analog
Power
–
Terminal Configuration and Functions
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Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
FUNCTION
SIGNAL NAME
PIN NUMBER
RHL
PW
PIN
TYPE (1)
2
2
I
Analog input A0
A0
ADC
Clock
Debug
GPIO
(1)
(2)
10
DESCRIPTION
A1
1
1
I
Analog input A1
A2
20
16
I
Analog input A2
A3
19
15
I
Analog input A3
A4
11
9
I
Analog input A4
A5
10
–
I
Analog input A5
A6
9
–
I
Analog input A6
A7
13
–
I
Analog input A7
Veref+
2
2
I
ADC positive reference
Veref-
20
16
I
ADC negative reference
ACLK
1
1
I/O
ACLK output
MCLK
19
15
O
MCLK output
SMCLK
20
16
O
SMCLK output
XIN
7
7
I
Input terminal for crystal oscillator
XOUT
8
8
O
Output terminal for crystal oscillator
SBWTCK
3
3
I
Spy-Bi-Wire input clock
SBWTDIO
4
4
I/O
TCK
17
13
I
Test clock
TCLK
15
11
I
Test clock input
TDI
15
11
I
Test data input
TDO
14
10
O
Test data output
Spy-Bi-Wire data input/output
TEST
3
3
I
Test mode pin – selected digital I/O on JTAG pins
TMS
16
12
I
Test mode select
P1.0
2
2
I/O
General-purpose I/O
P1.1
1
1
I/O
General-purpose I/O
P1.2
20
16
I/O
General-purpose I/O
P1.3
19
15
I/O
General-purpose I/O
P1.4
17
13
I/O
General-purpose I/O (2)
P1.5
16
12
I/O
General-purpose I/O (2)
P1.6
15
11
I/O
General-purpose I/O (2)
P1.7
14
10
I/O
General-purpose I/O (2)
P2.0
8
8
I/O
General-purpose I/O
P2.1
7
7
I/O
General-purpose I/O
P2.2
13
9
I/O
General-purpose I/O
P2.3
12
–
I/O
General-purpose I/O
P2.4
11
–
I/O
General-purpose I/O
P2.5
10
–
I/O
General-purpose I/O
P2.6
9
–
I/O
General-purpose I/O
Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
PW
PIN
TYPE (1)
UCB0SCL (3)
19
15
I/O
eUSCI_B0 I2C clock
(3)
20
16
I/O
eUSCI_B0 I2C data
9
–
I/O
eUSCI_B0 I2C clock
10
–
I/O
eUSCI_B0 I2C data
DVCC
5
5
P
Power supply
DVSS
6
6
P
Power ground
Output of positive reference voltage with ground as reference
SIGNAL NAME
UCB0SDA
I2C
PIN NUMBER
RHL
FUNCTION
UCB0SCL (3)
(3)
UCB0SDA
Power
VREF+
1
1
P
UCA0STE
14
10
I/O
eUSCI_A0 SPI slave transmit enable
UCA0CLK
15
11
I/O
eUSCI_A0 SPI clock input/output
UCA0SOMI (3) (4)
16
12
I/O
eUSCI_A0 SPI slave out/master in
(3) (4)
UCA0SIMO
SPI
17
13
I/O
eUSCI_A0 SPI slave in/master out
UCA0SOMI (3) (4)
7
7
I/O
eUSCI_A0 SPI slave out/master in
UCA0SIMO (3) (4)
8
8
I/O
eUSCI_A0 SPI slave in/master out
UCB0STE (3)
2
2
I/O
eUSCI_B0 slave transmit enable
UCB0CLK (3)
1
1
I/O
eUSCI_B0 clock input/output
UCB0SOMI (3)
19
15
I/O
eUSCI_B0 SPI slave out/master in
(3)
UCB0SIMO
20
16
I/O
eUSCI_B0 SPI slave in/master out
(3)
12
–
I/O
eUSCI_B0 slave transmit enable
UCB0CLK (3)
11
–
I/O
eUSCI_B0 clock input/output
UCB0STE
UCB0SOMI
System
DESCRIPTION
(3)
9
–
I/O
eUSCI_B0 SPI slave out/master in
UCB0SIMO (3)
10
–
I/O
eUSCI_B0 SPI slave in/master out
NMI
4
4
I
Nonmaskable interrupt input
RST
4
4
I
Active-low reset input
TA0.1
17
13
I/O
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
TA0.2
16
12
I/O
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
TA0CLK
15
11
I
TA1.1
13
9
I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
TA1.2
12
–
I/O
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
TA1CLK
11
–
I
Timer clock input TACLK for TA1
(3)
16
12
I
eUSCI_A0 UART receive data
UCA0TXD (3)
17
13
O
eUSCI_A0 UART transmit data
7
7
I
eUSCI_A0 UART receive data
Timer clock input TACLK for TA0
Timer_A
UCA0RXD
UART
UCA0RXD
UCA0TXD
(3)
(3)
DNC
Do not connect
QFN Pad
QFN thermal pad
(3)
(4)
8
8
O
eUSCI_A0 UART transmit data
18
14
–
Do not connect
Pad
–
–
QFN package exposed thermal pad. TI recommends connecting to
VSS.
These signal assignments are controlled by the USCIARMP bit of the SYSCFG3 register or the USCIBRMP bit of the SYSCFG2
register. Only one group can be selected at one time.
Signal assignments on these pins are controlled by the remap functionality and are selected by the USCIARMP bit in the SYSCFG3
register. Only one group can be selected at one time. The CLK and STE assignments are fixed and shared by both SPI function groups.
Terminal Configuration and Functions
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Pin Multiplexing
Pin multiplexing for this MCU is controlled by both register settings and operating modes (for example, if
the MCU is in test mode). For details of the settings for each pin and diagrams of the multiplexed ports,
see Section 6.11.
4.5
Buffer Types
Table 4-3 defines the pin buffer types that are listed in Table 4-1
Table 4-3. Buffer Types
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
LVCMOS
3.0 V
Y (1)
Programmable
See
Section 5.11.4
See
Section 5.11.4
Analog
3.0 V
N
N/A
N/A
N/A
See analog modules in
Section 5 for details.
Power (DVCC)
3.0 V
N
N/A
N/A
N/A
SVS enables hysteresis on
DVCC.
Power (AVCC)
3.0 V
N
N/A
N/A
N/A
BUFFER TYPE
(STANDARD)
(1)
OTHER
CHARACTERISTICS
Only for input pins.
4.6
Connection of Unused Pins
Table 4-4 lists the correct termination of unused pins.
Table 4-4. Connection of Unused Pins (1)
PIN
POTENTIAL
COMMENT
Px.0 to Px.7
Open
Switched to port function, output direction (PxDIR.n = 1)
RST/NMI
DVCC
47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown (2)
TEST
Open
This pin always has an internal pull-down enabled.
(1)
(2)
12
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 1.1 nF when using MCUs with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Voltage applied at DVCC pin to VSS
–0.3
4.1
UNIT
V
Voltage applied to any other pin (2)
–0.3
VCC + 0.3
(4.1 V Max)
V
Diode current at any device pin
±2
mA
Maximum junction temperature, TJ
85
°C
125
°C
Storage temperature, Tstg
(1)
(2)
(3)
(3)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22‑C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
5.3
Recommended Operating Conditions
VCC
Supply voltage applied at DVCC pin (1) (2) (3)
VSS
Supply voltage applied at DVSS pin
TA
Operating free-air temperature
–40
85
TJ
Operating junction temperature
–40
85
CDVCC
Recommended capacitor at DVCC (4)
4.7
MIN
fSYSTEM
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
MAX
3.6
0
Processor frequency (maximum MCLK frequency)
fACLK
NOM
2.0
(3) (5)
UNIT
V
V
10
°C
°C
µF
No FRAM wait states
(NWAITSx = 0)
0
8
With FRAM wait states
(NWAITSx = 1) (6)
0
16 (7)
MHz
40
kHz
16 (7)
MHz
Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-2.
A capacitor tolerance of ±20% or better is required.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
Specifications
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Active Mode Supply Current Into VCC Excluding External Current
(1)
FREQUENCY (fMCLK = fSMCLK)
EXECUTION
MEMORY
PARAMETER
TEST
CONDITION
1 MHz
0 WAIT STATES
(NWAITSx = 0)
TYP
IAM,
FRAM(0%)
IAM,
FRAM(100%)
IAM,
RAM
(1)
(2)
(2)
8 MHz
0 WAIT STATES
(NWAITSx = 0)
MAX
TYP
16 MHz
1 WAIT STATE
(NWAITSx = 1)
MAX
TYP
FRAM
0% cache hit ratio
3 V, 25°C
454
2620
2935
3 V, 85°C
471
2700
2980
FRAM
100% cache hit
ratio
3 V, 25°C
191
573
950
3 V, 85°C
199
592
974
RAM
3 V, 25°C
216
772
1300
UNIT
MAX
µA
3250
µA
1200
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5
Active Mode Supply Current Per MHz
VCC = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
dIAM,FRAM/df
5.6
TEST CONDITIONS
Active mode current consumption per MHz,
execution from FRAM, no wait states
TYP
UNIT
120
µA/MHz
[IAM (75% cache hit rate) at 8 MHz –
IAM (75% cache hit rate) at 1 MHz) / 7 MHz
Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
VCC = 3 V, TA = 25°C (unless otherwise noted) (1) (2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
(1)
(2)
14
8 MHz
MAX
TYP
16 MHz
MAX
TYP
2V
145
292
395
3V
155
300
394
UNIT
MAX
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
Specifications
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Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
ILPM3,XT1
Low-power mode 3, 12.5-pF crystal, includes SVS (2) (3) (4)
ILPM3,VLO
Low-power mode 3, VLO, excludes SVS (5)
ILPM3,
Low-power mode 3, RTC, excludes SVS (6)
ILPM4,
RTC
SVS
Low-power mode 4, includes SVS (7)
–40°C
TYP
MAX
25°C
TYP
(1)
85°C
MAX
TYP
MAX
6.2
3V
0.96
1.11
2.75
2V
0.93
1.08
2.78
3V
0.77
0.92
2.66
2V
0.75
0.90
2.60
3V
0.90
1.05
2.77
3V
0.51
0.64
2.30
2V
0.49
0.61
2.25
3V
0.35
0.48
2.13
2V
0.34
0.46
2.10
ILPM4
Low-power mode 4, excludes SVS (7)
ILPM4,VLO
Low-power mode 4, RTC is soured from VLO, excludes
SVS (8)
3V
0.43
0.56
2.21
2V
0.42
0.55
2.19
ILPM4,XT1
Low-power mode 4, RTC is soured from XT1, excludes
SVS (9)
3V
0.80
0.96
2.68
2V
0.79
0.94
2.64
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
6.0
UNIT
µA
µA
µA
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for MCUs with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
Low-power mode 3, 12.5-pF crystal, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3)
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
RTC periodically wakes up every second with external 32768-Hz input as source.
Low-power mode 4, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), CPU and all clocks are disabled, WDT and RTC
disabled
Low-power mode 4, VLO, excludes SVS test conditions:
Current for RTC clocked by VLO included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)
fXT1 = 0 Hz, fMCLK = fSMCLK = 0 MHz
Low-power mode 4, XT1, excludes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)
fXT1 = 32768 Hz, fMCLK = fSMCLK = 0 MHz
Specifications
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Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
ILPM3.5,
XT1
Low-power mode 3.5, 12.5-pF crystal, includes
SVS (1) (2) (3)
(also see Figure 5-3)
ILPM4.5,
SVS
Low-power mode 4.5, includes SVS (4)
ILPM4.5
(1)
(2)
(3)
(4)
(5)
16
Low-power mode 4.5, excludes SVS (5)
–40°C
TYP
25°C
MAX
TYP
85°C
MAX
TYP
MAX
1.54
3V
0.57
0.63
0.81
2V
0.54
0.60
0.79
3V
0.23
0.25
0.31
2V
0.21
0.23
0.29
3V
0.027
0.036
0.080
2V
0.022
0.031
0.073
UNIT
µA
0.45
0.15
µA
µA
Not applicable for MCUs with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
Low-power mode 3.5, 12.5-pF crystal, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = 0, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Specifications
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Typical Characteristics - Low-Power Mode Supply Currents
VCC = 3 V
RTC
SVS Disabled
VCC = 3 V
Figure 5-1. LPM3 Supply Current vs Temperature
VCC = 3 V
XT1
SVS Enabled
Figure 5-3. LPM3.5 Supply Current vs Temperature
RTC
SVS Disabled
Figure 5-2. LPM4 Supply Current vs Temperature
VCC = 3 V
SVS Enabled
Figure 5-4. LPM4.5 Supply Current vs Temperature
Table 5-1. Typical Characteristics – Current Consumption Per Module
MODULE
TEST CONDITIONS
Timer_A
REFERENCE CLOCK
MIN
TYP
MAX
UNIT
Module input clock
5
µA/MHz
eUSCI_A
UART mode
Module input clock
7
µA/MHz
eUSCI_A
SPI mode
Module input clock
5
µA/MHz
eUSCI_B
SPI mode
Module input clock
5
µA/MHz
5
µA/MHz
eUSCI_B
2
I C mode, 100 kbaud
RTC
CRC
From start to end of operation
Module input clock
32 kHz
85
nA
MCLK
8.5
µA/MHz
Specifications
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5.10 Thermal Resistance Characteristics
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance, still air
RθJC
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
(1)
(2)
VALUE (2)
VQFN 20 pin (RHL)
37.8
TSSOP 16 pin (PW16)
101.7
VQFN 20 pin (RHL)
34.1
TSSOP 16 pin (PW16)
33.7
VQFN 20 pin (RHL)
15.3
TSSOP 16 pin (PW16)
47.5
UNIT
ºC/W
ºC/W
ºC/W
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
5.11 Timing and Switching Characteristics
5.11.1 Power Supply Sequencing
Table 5-2 lists the characteristics of the SVS and BOR.
Table 5-2. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBOR, safe
Safe BOR power-down level (1)
0.1
V
tBOR, safe
Safe BOR reset delay (2)
10
ms
ISVSH,AM
SVSH current consumption, active mode
VCC = 3.6 V
ISVSH,LPM
SVSH current consumption, low-power modes
VCC = 3.6 V
VSVSH-
SVSH power-down level
1.71
1.80
1.87
VSVSH+
SVSH power-up level
1.76
1.88
1.99
VSVSH_hys
SVSH hysteresis
tPD,SVSH, AM
SVSH propagation delay, active mode
tPD,SVSH, LPM
SVSH propagation delay, low-power modes
(1)
(2)
1.5
240
µA
nA
80
V
V
mV
10
µs
100
µs
A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+.
V
Power Cycle Reset
V SVS+
SVS Reset
BOR Reset
V SVS–
V BOR
t BOR
t
Figure 5-5. Power Cycle, SVS, and BOR Reset Conditions
18
Specifications
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5.11.2 Reset Timing
Table 5-3 lists the timing characteristics of wakeup from LPMs and reset.
Table 5-3. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
tWAKE-UP FRAM
Additional wake-up time to activate the FRAM in
AM if previously disabled by the FRAM controller or
from a LPM if immediate activation is selected for
wakeup (1)
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode
(1)
3V
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode
(2)
3V
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode
tWAKE-UP LPM3.5
Wake-up time from LPM3.5 to active mode
3V
(2)
(2)
SVSHE = 1
10
UNIT
µs
200 +
2.5 / fDCO
ns
3V
10
µs
3V
350
µs
350
µs
1
ms
1
ms
tWAKE-UP-RESET
Wake-up time from RST or BOR event to active
mode (2)
3V
tRESET
Pulse duration required at RST/NMI pin to accept a
reset
3V
(2)
MAX
µs
Wake-up time from LPM4.5 to active mode
SVSHE = 0
TYP
10
tWAKE-UP LPM4.5
(1)
MIN
3V
2
µs
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Specifications
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5.11.3 Clock Specifications
Table 5-4 lists the characteristics of the LF XT1.
Table 5-4. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
fXT1, LF
XT1 oscillator crystal, low
frequency
LFXTBYPASS = 0
DCXT1, LF
XT1 oscillator LF duty cycle
Measured at MCLK,
fLFXT = 32768 Hz
fXT1,SW
XT1 oscillator logic-level squarewave input frequency
LFXTBYPASS = 1
DCXT1, SW
LFXT oscillator logic-level squareLFXTBYPASS = 1
wave input duty cycle
OALFXT
Oscillation allowance for
LF crystals (4)
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
CL,eff
Integrated effective load
capacitance (5)
See
tSTART,LFXT Start-up time
fFault,LFXT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
MIN
(8)
TYP
MAX
32768
30%
(2) (3)
70%
40%
(6)
XTS = 0 (9)
UNIT
Hz
32.768
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
(7)
Oscillator fault frequency
VCC
kHz
60%
200
kΩ
1
pF
1000
ms
0
3500
Hz
To improve EMI on the LFXT oscillator, observe the following guidelines:
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF
• For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF
• For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the
flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5 lists the frequency characteristics of the FLL.
Table 5-5. DCO FLL, Frequency
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
FLL lock frequency, 16 MHz, 25°C
fDCO,
FLL lock frequency, 16 MHz, –40°C to 85°C
Measured at MCLK, Internal
trimmed REFO as reference
VCC
MIN
3V
–1.0%
TYP
1.0%
3V
–2.0%
2.0%
3V
–0.5%
0.5%
40%
UNIT
FLL
FLL lock frequency, 16 MHz, –40°C to 85°C
Measured at MCLK, XT1
crystal as reference
fDUTY
Duty cycle
3V
Jittercc
Cycle-to-cycle jitter, 16 MHz
3V
0.25%
Jitterlong
Long term jitter, 16 MHz
3V
0.022%
tFLL, lock
FLL lock time, 16MHz
3V
280
20
MAX
Measured at MCLK, XT1
crystal as reference
Specifications
50%
60%
ms
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Table 5-6 lists the characteristics of the DCO.
Table 5-6. DCO Frequency
over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-6)
PARAMETER
TEST CONDITIONS
VCC
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
fDCO,
fDCO,
fDCO,
fDCO,
fDCO,
fDCO,
16MHz
12MHz
8MHz
4MHz
2MHz
1MHz
DCO frequency, 16 MHz
DCO frequency, 12 MHz
DCO frequency, 8 MHz
DCO frequency, 4 MHz
DCO frequency, 2 MHz
DCO frequency, 1 MHz
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
TYP
7.1
11.8
3V
MHz
17
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
27.7
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
5.5
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
9.1
3V
MHz
13.1
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
21.5
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
3.7
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
6.3
3V
MHz
9.0
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
14.9
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
1.9
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
3.2
3V
MHz
4.6
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
7.8
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
0.96
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
1.6
3V
MHz
2.3
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
4.0
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
0.5
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
0.85
3V
MHz
1.2
2.0
Specifications
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30
DCOFTRIM = 7
25
DCOFTRIM = 7
Frequency (MHz)
20
DCOFTRIM = 7
15
10
DCOFTRIM = 7
DCOFTRIM = 7
5
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
0
DCOFTRIM = 0
DCOFTRIM = 0
DCO
511
0
DCORSEL
511
0
0
511
0
1
VCC = 3 V
511
0
2
511
0
3
4
511
0
5
TA = –40°C to 85°C
Figure 5-6. Typical DCO Frequency
Table 5-7 lists the characteristics of the REFO.
Table 5-7. REFO
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO
dfREFO/dT
TEST CONDITIONS
TYP
TA = 25°C
3V
15
REFO calibrated frequency
Measured at MCLK
3V
32768
REFO absolute calibrated tolerance
–40°C to 85°C
REFO frequency temperature drift
Measured at MCLK (1)
REFO frequency supply voltage drift
Measured at MCLK at 25°C
fDC
REFO duty cycle
Measured at MCLK
tSTART
REFO start-up time
40% to 60% duty cycle
22
MIN
REFO oscillator current consumption
dfREFO/
dVCC
(1)
(2)
VCC
2.0 V to 3.6 V
–3.5%
3V
(2)
2.0 V to 3.6 V
2.0 V to 3.6 V
40%
MAX
UNIT
µA
Hz
+3.5%
0.01
%/°C
1
%/V
50%
50
60%
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(2.0 V to 3.6 V) – MIN(2.0 V to 3.6 V)) / MIN(2.0 V to 3.6 V) / (3.6 V – 2.0 V)
Specifications
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Table 5-8 lists the characteristics of the VLO.
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
TEST CONDITIONS
VLO frequency
Measured at MCLK
(1)
dfVLO/dT
VLO frequency temperature drift
Measured at MCLK
dfVLO/dVCC
VLO frequency supply voltage drift
Measured at MCLK (2)
fVLO,DC
Duty cycle
Measured at MCLK
(1)
(2)
VCC
TYP
3V
10
kHz
3V
0.5
%/°C
4
%/V
2.0 V to 3.6 V
3V
UNIT
50%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(2.0 V to 3.6 V) – MIN(2.0 V to 3.6 V)) / MIN(2.0 V to 3.6 V) / (3.6 V – 2.0 V)
NOTE
The VLO clock frequency is reduced by 15% (typical) when the device switches from active
mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a
violation of the VLO specifications (see Table 5-8).
Table 5-9 lists the characteristics of the MODOSC.
Table 5-9. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
MIN
TYP
MAX
fMODOSC
MODOSC frequency
PARAMETER
TEST CONDITIONS
3V
3.8
4.8
5.8
fMODOSC/dT
MODOSC frequency temperature drift
3V
fMODOSC/dVCC
MODOSC frequency supply voltage drift
fMODOSC,DC
Duty cycle
0.102
2.0 V to 3.6 V
3V
50%
%/V
60%
Specifications
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%/℃
1.02
40%
UNIT
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5.11.4 Digital I/Os
Table 5-10 lists the characteristics of the digital inputs.
Table 5-10. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
2V
0.90
1.50
3V
1.35
2.25
2V
0.50
1.10
3V
0.75
1.65
2V
0.3
0.8
3V
0.4
1.2
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
VIN = VSS or VCC
functions
5
pF
Ilkg(Px.y)
High-impedance leakage current of GPIO pins
See
External interrupt timing (external trigger pulse
duration to set interrupt flag) (3)
Ports with interrupt capability
(see block diagram and
terminal function descriptions)
t(int)
(1)
(2)
(3)
(1) (2)
20
2 V, 3 V
–20
2 V, 3 V
50
35
50
20
V
V
V
kΩ
nA
ns
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Table 5-11 lists the characteristics of the digital outputs.
Table 5-11. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
I(OHmax) = –3 mA (1)
TEST CONDITIONS
2V
1.4
2.0
I(OHmax) = –5 mA (1)
3V
2.4
3.0
I(OLmax) = 3 mA (1)
2V
0.0
0.60
I(OHmax) = 5 mA (1)
3V
0.0
0.60
2V
16
3V
16
VOH
High-level output voltage
VOL
Low-level output voltage
fPort_CLK
Clock output frequency
CL = 20 pF (2)
trise,dig
Port output rise time, digital only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port pins
CL = 20 pF
(1)
(2)
24
TYP
MAX
UNIT
V
V
MHz
2V
10
3V
7
2V
10
3V
5
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The port can output frequencies at least up to the specified limit and might support higher frequencies.
Specifications
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5.11.4.1 Typical Characteristics – Outputs at 3 V and 2 V
DVCC = 3 V
DVCC = 2 V
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Output Voltage
DVCC = 3 V
Figure 5-8. Typical Low-Level Output Current vs Low-Level
Output Voltage
DVCC = 2 V
Figure 5-9. Typical High-Level Output Current vs High-Level
Output Voltage
Figure 5-10. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
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5.11.5 VREF+ Built-in Reference
Table 5-12 lists the characteristics of the VREF+.
Table 5-12. VREF+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREF+
Positive built-in reference voltage
TCREF+
Temperature coefficient of built-in
reference voltage
EXTREFEN = 1 with 1-mA load current
VCC
MIN
TYP
MAX
UNIT
2 V, 3 V
1.15
1.19
1.23
V
30
µV/°C
5.11.6 Timer_A
Table 5-13 lists the characteristics of Timer_A.
Table 5-13. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fTA
TEST CONDITIONS
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
Timer_A input clock frequency
VCC
MIN
TYP
MAX
UNIT
16
MHz
2 V, 3 V
tTIMR
Timer Clock
Timer
CCR0-1
CCR0
0h
CCR0-1
1h
CCR0
0h
tHD,PWM
tVALID,PWM
TAx.1
Figure 5-11. Timer PWM Mode
Capture
tTIMR
Timer Clock
tSU,CCIA
t,HD,CCIA
TAx.CCIA
Figure 5-12. Timer Capture Mode
26
Specifications
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5.11.7 eUSCI
Table 5-14 lists the supported frequencies of the eUSCI in UART mode.
Table 5-14. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in Mbaud)
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
VCC
MIN
MAX
UNIT
2 V, 3 V
16
MHz
2 V, 3 V
5
MHz
Table 5-15 lists the characteristics of the eUSCI in UART mode.
Table 5-15. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TYP
UCGLITx = 0
tt
UART receive deglitch time
(1)
12
UCGLITx = 1
40
2 V, 3 V
UCGLITx = 2
68
UCGLITx = 3
(1)
UNIT
ns
110
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Table 5-16 lists the supported frequencies of the eUSCI in SPI master mode.
Table 5-16. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCI
eUSCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, MODCLK
Duty cycle = 50% ±10%
MIN
MAX
UNIT
8
MHz
Specifications
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Table 5-17 lists the characteristics of the eUSCI in SPI master mode.
Table 5-17. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, last clock to STE inactive
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
28
VCC
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
MIN
MAX
UNIT
1
UCxCLK
cycles
1
UCxCLK
cycles
2V
48
3V
37
2V
0
3V
0
ns
ns
2V
20
3V
20
2V
-6
3V
-5
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 513 and Figure 5-14.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 5-13. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tVALID,MO
tSTE,DIS
SIMO
Figure 5-14. SPI Master Mode, CKPH = 1
Specifications
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Table 5-18 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-18. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
tHD,SO
SOMI output data hold time
(1)
(2)
(3)
30
(3)
UCLK edge to SOMI valid,
CL = 20 pF
CL = 20 pF
VCC
MIN
2V
55
3V
45
2V
20
3V
20
MAX
ns
ns
2V
65
3V
40
2V
40
3V
35
2V
8
3V
6
2V
12
3V
12
68
42
3V
5
ns
ns
3V
5
ns
ns
2V
2V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-15 and Figure 5-16.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-15
and Figure 5-16.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 5-15. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 1
Specifications
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Table 5-19 lists the characteristics of the eUSCI in I2C mode.
Table 5-19. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
2 V, 3 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2 V, 3 V
0
ns
tSU,DAT
Data setup time
2 V, 3 V
250
ns
tSU,STO
tSP
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
Setup time for STOP
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
2 V, 3 V
0
MAX
2 V, 3 V
2 V, 3 V
4.7
µs
0.6
4.0
µs
0.6
UCGLITx = 0
50
600
UCGLITx = 1
25
300
12.5
150
UCGLITx = 2
2 V, 3 V
UCGLITx = 3
6.3
UCCLTOx = 1
tTIMEOUT Clock low time-out
µs
0.6
UCCLTOx = 2
tSU,STA
75
27
2 V, 3 V
30
UCCLTOx = 3
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-17. I2C Mode Timing
32
Specifications
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5.11.8 ADC
Table 5-20 lists the characteristics of the ADC power supply and input range conditions.
Table 5-20. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DVCC
ADC supply voltage
V(Ax)
Analog input voltage range
IADC
Operating supply current into
DVCC terminal, reference
current not included, repeatsingle-channel mode
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADCDIV = 0, ADCCONSEQx = 10b
CI
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC capacitor array,
including wiring and pad
RI
Input MUX ON resistance
DVCC = 2 V, 0 V = VAx = DVCC
VCC
MIN
All ADC pins
TYP
MAX
UNIT
2.0
3.6
V
0
DVCC
V
2V
185
3V
207
2.2 V
2.5
µA
3.5
pF
36
kΩ
Table 5-21 lists the ADC 10-bit timing parameters.
Table 5-21. ADC, 10-Bit Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC linearity
parameters
2 V to
3.6 V
0.45
5
5.5
MHz
Internal ADC oscillator
(MODOSC)
ADCDIV = 0, fADCCLK = fADCOSC
2 V to
3.6 V
3.8
4.8
5.8
MHz
2 V to
3.6 V
2.18
Conversion time
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,
fADCOSC = 4.5 MHz to 5.5 MHz
External fADCCLK from ACLK, MCLK, or SMCLK,
ADCSSEL ≠ 0
2 V to
3.6 V
fADCCLK
fADCOSC
tCONVERT
TEST CONDITIONS
tADCON
Turnon settling time of
the ADC
The error in a conversion started after tADCON is
less than ±0.5 LSB.
Reference and input signal are already settled.
tSample
Sampling time
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF.
Approximately 8 Tau (t) are required for an error
of less than ±0.5 LSB.
2.67
µs
12 ×
1 / fADCCLK
100
3V
2.0
µs
Specifications
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Table 5-22 lists the ADC 10-bit linearity parameters.
Table 5-22. ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
EI
Differential linearity error (10-bit mode)
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
EO
Offset error (8-bit mode)
Gain error (10-bit mode)
EG
Gain error (8-bit mode)
Total unadjusted error (10-bit mode)
ET
Total unadjusted error (8-bit mode)
VSENSOR
TCSENSOR
tSENSOR
(sample)
(2)
(3)
34
Veref+ reference
Integral linearity error (8-bit mode)
ED
(1)
TEST CONDITIONS
Integral linearity error (10-bit mode)
Veref+ reference
Veref+ reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
VCC
MIN
TYP
MAX
2.4 V to 3.6 V
–2
2
2.0 V to 3.6 V
–2
2
2.4 V to 3.6 V
–1
1
2.0 V to 3.6 V
–1
1
2.4 V to 3.6 V
–6.5
6.5
2.0 V to 3.6 V
–6.5
6.5
2.4 V to 3.6 V
2.0 V to 3.6 V
2.4 V to 3.6 V
2.0 V to 3.6 V
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
UNIT
LSB
LSB
mV
LSB
LSB
LSB
LSB
See
(1)
ADCON = 1, INCH = 0Ch,
TA = 0℃
3V
913
mV
See
(2)
ADCON = 1, INCH = 0Ch
3V
3.35
mV/℃
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB,
AM and all LPMs above LPM3
3V
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB, LPM3
3V
Sample time required if channel 12 is
selected (3)
30
µs
100
The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The device descriptor structure contains calibration values for 30℃ and 85℃ for each available reference voltage level. The sensor
voltage can be computed as VSENSE = TCSENSOR × (Temperature, ℃) + VSENSOR, where TCSENSOR and VSENSOR can be computed from
the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, tSENSOR(on).
Specifications
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5.11.9 FRAM
Table 5-23 lists the characteristics of the FRAM.
Table 5-23. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Data retention duration
IWRITE
Current to write into FRAM
IERASE
Erase current
tWRITE
Write time
tREAD
(1)
(2)
(3)
(4)
Read time
TYP
15
Read and write endurance
tRetention
MIN
10
TJ = 25°C
100
TJ = 70°C
40
TJ = 85°C
10
MAX
UNIT
cycles
years
IREAD (1)
nA
N/A (2)
nA
tREAD (3)
ns
(4)
NWAITSx = 0
1 / fSYSTEM
NWAITSx = 1
2 / fSYSTEM (4)
ns
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption parameter IAM,FRAM.
FRAM does not require a special erase sequence.
Writing into FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
Specifications
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5.11.10 Debug and Emulation
Table 5-24 lists the characteristics of the 2-wire SBW interface.
Table 5-24. JTAG, Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2 V, 3 V
0
8
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2 V, 3 V
0.028
15
µs
tSU, SBWTDIO
SBWTDIO setup time (before falling edge of SBWTCK in TMS and
TDI slot, Spy-Bi-Wire)
2 V, 3 V
4
ns
tHD,
SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI
slot, Spy-Bi-Wire)
2 V, 3 V
19
ns
tValid, SBWTDIO
SBWTDIO data valid time (after falling edge of SBWTCK in TDO
slot, Spy-Bi-Wire)
2 V, 3 V
31
ns
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2 V, 3 V
110
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time (2)
2 V, 3 V
15
100
µs
Rinternal
Internal pulldown resistance on TEST
2 V, 3 V
20
50
kΩ
(1)
(2)
SBWTDIO
35
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
Maximum tSBW,Ret time after pulling or releasing the TEST/SBWTCK pin low until the Spy-Bi-Wire pins revert from their Spy-Bi-Wire
function to their application function. This time applies only if the Spy-Bi-Wire mode is selected.
tSBW,EN
1/fSBW
tSBW,Low
tSBW,High
tSBW,Ret
TEST/SBWTCK
tEN,SBWTDIO
tValid,SBWTDIO
RST/NMI/SBWTDIO
tSU,SBWTDIO
tHD,SBWTDIO
Figure 5-18. JTAG Spy-Bi-Wire Timing
36
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Table 5-25 lists the characteristics of the 4-wire JTAG interface.
Table 5-25. JTAG, 4-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-19)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
10
MHz
fTCK
TCK input frequency (1)
2 V, 3 V
0
tTCK,Low
TCK low clock pulse duration
2 V, 3 V
15
ns
tTCK,High
TCK high clock pulse duration
2 V, 3 V
15
ns
tSU,TMS
TMS setup time (before rising edge of TCK)
2 V, 3 V
11
ns
tHD,TMS
TMS hold time (after rising edge of TCK)
2 V, 3 V
3
ns
tSU,TDI
TDI setup time (before rising edge of TCK)
2 V, 3 V
13
ns
tHD,TDI
TDI hold time (after rising edge of TCK)
2 V, 3 V
5
tZ-Valid,TDO
TDO high impedance to valid output time (after falling edge of TCK)
2 V, 3 V
26
ns
tValid,TDO
TDO to new valid output time (after falling edge of TCK)
2 V, 3 V
26
ns
tValid-Z,TDO
TDO valid to high-impedance output time (after falling edge of TCK)
2 V, 3 V
26
ns
tJTAG,Ret
Spy-Bi-Wire return to normal operation time
100
µs
Rinternal
Internal pulldown resistance on TEST
50
kΩ
(1)
ns
15
2 V, 3 V
20
35
fTCK may be restricted to meet the timing requirements of the module selected.
1/fTCK
tTCK,Low
tTCK,High
TCK
TMS
tSU,TMS
tHD,TMS
TDI
(or TDO as TDI)
tSU,TDI
tHD,TDI
TDO
tZ-Valid,TDO
tValid,TDO
tValid-Z,TDO
tJTAG,Ret
TEST
Figure 5-19. JTAG 4-Wire Timing
Specifications
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6 Detailed Description
6.1
Overview
The MSP430FR2422 is an ultra-low-power MCU. The architecture, combined with extensive low-power
modes, is optimized to achieve extended battery life in, for example, portable measurement applications.
The MCU features two 16-bit timers, two eUSCIs that support UART, SPI, and I2C, a hardware multiplier,
an RTC module, and a high-performance 10-bit ADC.
6.2
CPU
The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be handled
with all instructions.
6.3
Operating Modes
The MSP430 has one active mode and several software-selectable low-power modes of operation (see
Table 6-1). An interrupt event can wake the MCU from low-power mode LPM0, LPM3 or LPM4, service
the request, and restore the MCU back to the low-power mode on return from the interrupt program. Lowpower modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
NOTE
XT1CLK and VLOCLK can be active during LPM4 mode if requested by low-frequency
peripherals, such as RTC, WDT.
38
Detailed Description
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Table 6-1. Operating Modes
MODE
AM
LPM0
LPM3
LPM4
LPM3.5
LPM4.5
ACTIVE
MODE
(FRAM ON)
CPU OFF
STANDBY
OFF
ONLY RTC
SHUTDOWN
16 MHz
16 MHz
40 kHz
0
40 kHz
0
126 µA/MHz
40 µA/MHz
1.2 µA with
RTC counter
only in LFXT
0.49 µA
without SVS
0.73 µA with
RTC counter
only in LFXT
16 nA without
SVS
N/A
Instant
10 µs
10 µs
350 µs
350 µs
I/O
Maximum system clock
Power consumption at 25°C, 3 V
Wake-up time
N/A
All
All
I/O
RTC
I/O
Full
Regulation
Full
Regulation
Partial Power
Down
Partial Power
Down
Partial Power
Down
Power Down
SVS
On
On
Optional
Optional
Optional
Optional
Brownout
On
On
On
On
On
On
Wake-up events
Regulator
Power
MCLK
Clock (1)
Core
Peripherals
I/O
(1)
(2)
6.4
Active
Off
Off
Off
Off
Off
SMCLK
Optional
Optional
Off
Off
Off
Off
FLL
Optional
Optional
Off
Off
Off
Off
DCO
Optional
Optional
Off
Off
Off
Off
MODCLK
Optional
Optional
Off
Off
Off
Off
REFO
Optional
Optional
Optional
Off
Off
Off
ACLK
Optional
Optional
Optional
Off
Off
Off
XT1CLK
Optional
Optional
Optional
Off
Optional
Off
VLOCLK
Optional
Optional
Optional
Off
Optional
Off
CPU
On
Off
Off
Off
Off
Off
FRAM
On
On
Off
Off
Off
Off
RAM
On
On
On
On
Off
Off
Backup memory (2)
On
On
On
On
On
Off
Timer0_A3
Optional
Optional
Optional
Off
Off
Off
Timer1_A3
Optional
Optional
Optional
Off
Off
Off
WDT
Optional
Optional
Optional
Off
Off
Off
eUSCI_A0
Optional
Optional
Optional
Off
Off
Off
eUSCI_B0
Optional
Optional
Optional
Off
Off
Off
CRC
Optional
Optional
Off
Off
Off
Off
ADC
Optional
Optional
Optional
Off
Off
Off
RTC
Optional
Optional
Optional
Off
Optional
Off
On
Optional
State Held
State Held
State Held
State Held
General-purpose
digital input/output
The status shown for LPM4 applies to internal clocks only.
Backup memory contains 32 bytes of register space in peripheral memory. See Table 6-20 and Table 6-35 for its memory allocation.
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-2). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Detailed Description
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Table 6-2. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power up, Brownout, Supply supervisor
External reset RST
Watchdog time-out, Key violation
FRAM uncorrectable bit error detection
Software POR, BOR
FLL unlock error
SVSHIFG
PMMRSTIFG
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLUNLOCKIFG
Reset
FFFEh
63, Highest
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM bit error detection
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
Nonmaskable
FFFCh
62
User NMI
External NMI
Oscillator fault
NMIIFG
OFIFG
Nonmaskable
FFFAh
61
Timer0_A3
TA0CCR0 CCIFG0
Maskable
FFF8h
60
Timer0_A3
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV)
Maskable
FFF6h
59
Timer1_A3
TA1CCR0 CCIFG0
Maskable
FFF4h
58
Timer1_A3
TA1CCR1 CCIFG1, TA1CCR2 CCIFG2,
TA1IFG (TA1IV)
Maskable
FFF2h
57
RTC
RTCIFG
Maskable
FFF0h
56
Watchdog timer interval mode
WDTIFG
Maskable
FFEEh
55
eUSCI_A0 receive or transmit
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV)
Maskable
FFECh
54
eUSCI_B0 receive or transmit
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)
Maskable
FFEAh
53
ADC
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
Maskable
FFE8h
52
P1
P1IFG.0 to P1IFG.7 (P1IV)
Maskable
FFE6h
51
P2
P2IFG.0 to P2IFG.6 (P2IV)
Maskable
FFE4h
50
Reserved
Reserved
Maskable
FFE0h–FF88h
Table 6-3. Signatures
40
SIGNATURE
WORD ADDRESS
BSL Signature2
0FF86h
BSL Signature1
0FF84h
JTAG Signature2
0FF82h
JTAG Signature1
0FF80h
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6.5
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Bootloader (BSL)
The BSL lets users program the FRAM or RAM using either the UART serial interface or the I2C interface.
Access to the MCU memory through the BSL is protected by an user-defined password. Use of the BSL
requires four pins (see Table 6-4 and Table 6-5). The BSL entry requires a specific entry sequence on the
RST/NMI/SBWTDIO and TEST/SBWTCK pins. This device can support the blank device detection
automatically to invoke the BSL with bypass this special entry sequence for saving time and on board
programmable. For the complete description of the feature of the BSL, see the MSP430FR4xx and
MSP430FR2xx Bootloader (BSL) User's Guide.
Table 6-4. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.4
Data transmit
P1.5
Data receive
VCC
Power supply
VSS
Ground supply
Table 6-5. I2C BSL Pin Requirements and Functions
6.6
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.2
Data transmit and receive
P1.3
Clock
VCC
Power supply
VSS
Ground supply
JTAG Standard Interface
The MSP low-power microcontrollers support the standard JTAG interface, which requires four signals for
sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK
pin enables the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface
with MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide. For details on using the JTAG interface, see MSP430 Programming With the JTAG
Interface.
Table 6-6. JTAG Pin Requirements and Function
DEVICE SIGNAL
DIRECTION
JTAG FUNCTION
P1.4/.../TCK
IN
JTAG clock input
P1.5/.../TMS
IN
JTAG state control
P1.6/.../TDI/TCLK
IN
JTAG data input, TCLK input
P1.7/.../TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
DVCC
Power supply
DVSS
Ground supply
Detailed Description
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Spy-Bi-Wire Interface (SBW)
The MSP low-power microcontrollers support the 2-wire SBW interface. SBW can be used to interface
with MSP development tools and device programmers. Table 6-7 lists the SBW interface pin requirements.
For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide. For details on using the SBW interface, see the MSP430 Programming
With the JTAG Interface.
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
6.8
DEVICE SIGNAL
DIRECTION
SBW FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
DVCC
Power supply
DVSS
Ground supply
FRAM
The FRAM can be programmed using the JTAG port, SBW, the BSL, or in-system by the CPU. Features
of the FRAM include:
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
6.9
Memory Protection
The device features memory protection for user access authority and write protection, including options to:
• Secure the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
• Enable write protection to prevent unwanted write operation to FRAM contents by setting the control
bits in the System Configuration 0 register. For detailed information, see the SYS chapter in the
MP430FR4xx and MP430FR2xx Family User's Guide.
6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MP430FR4xx and MP430FR2xx Family User's Guide.
6.10.1 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power on and power off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC
channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily
represent as Equation 1 by using ADC sampling 1.5-V reference without any external components
support.
DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result
42
Detailed Description
(1)
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A 1.2-V reference voltage can be buffered, when EXTREFEN = 1 on PMMCTL2 register, and it can be
output to P1.1/../A1/VREF+ , meanwhile the ADC channel 1 can also be selected to monitor this voltage.
For more detailed information, see the MSP430FR4xx and MSP430FR2xx Family User's Guide.
6.10.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz crystal oscillator (XT1), an internal very-low-power low-frequency
oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled
oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz
reference clock, and an on-chip asynchronous high-speed clock (MODOSC). The clock system is
designed for cost-effective designs with minimal external components. A fail-safe mechanism is included
for XT1. The clock system module offers the following clock signals.
• Main Clock (MCLK): The system clock used by the CPU and all relevant peripherals accessed by the
bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,
16, 32, 64, or 128.
• Sub-Main Clock (SMCLK): The subsystem clock used by the peripheral modules. SMCLK derives from
the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
• Auxiliary Clock (ACLK): This clock is derived from the external XT1 clock or internal REFO clock up to
40 kHz.
All peripherals may have one or several clock sources depending on specific functionality. Table 6-8 lists
the clock distribution used in this device.
Table 6-8. Clock Distribution
CLOCK
SOURCE
SELECT
BITS
Frequency
Range
MCLK
SMCLK
ACLK
MODCLK
XT1CLK
VLOCLK
DC to
16 MHz
DC to
16 MHz
DC to
40 kHz
5 MHz
±10%
DC to
40 kHz
10 kHz
±50%
EXTERNAL PIN
CPU
N/A
Default
FRAM
N/A
Default
RAM
N/A
Default
CRC
N/A
Default
I/O
N/A
Default
TA0
TASSEL
10b
01b
TA1
TASSEL
10b
01b
00b (TA1CLK pin)
eUSCI_A0
UCSSEL
10b or 11b
01b
00b (UCA0CLK pin)
eUSCI_B0
UCSSEL
10b or 11b
01b
WDT
WDTSSEL
00b
01b
ADC
ADCSSEL
10b or 11b
01b
RTC
RTCSS
(1)
–
11b
00b (TA0CLK pin)
00b (UCB0CLK pin)
10b
00b
01b (1)
–
–
10b
11b
–
Controlled by the RTCCLK bit in the SYSCFG2 register
Detailed Description
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CPU
FRAM
SRAM
CRC
I/O
Timer_A
A0
Timer_A
A1
eUSCI_A0
eUSCI_B0
WDT
00
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10, 11
00
01
ADC10
11
01
RTC
10
00
01
10
11
10, 11
00
01
00
01
10
01
10
01
Clock System (CS)
10, 11
MCLK
SMCLK
ACLK
VLOCLK
MODCLK
Selected on SYSCFG2
UB0CLK
UA0CLK
TA1CLK
TA0CLK
XT1CLK
Figure 6-1. Clock Distribution Block Diagram
44
Detailed Description
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6.10.3 General-Purpose Input/Output Port (I/O)
Up to 15 I/O ports are implemented.
• P1 implements 8 bits, and P2 implements 7 bits.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPMx.5 wake-up input capability are available for P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise as a pair.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, see the Configuration After Reset section in the Digital I/O chapter of the
MP430FR4xx and MP430FR2xx Family User's Guide.
6.10.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as an interval timer and can generate interrupts at
selected time intervals. Table 6-9 lists the system clocks that can be used to source the WDT.
Table 6-9. WDT Clocks
WDTSSEL
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
Reserved
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6.10.5 System (SYS) Module
The SYS module handles many of the system functions within the device. These features include poweron reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset
interrupt vector generators, bootloader entry mechanisms, and configuration management (device
descriptors). The SYS module also includes a data exchange mechanism through SBW called a JTAG
mailbox mail box that can be used in the application. Table 6-10 summarizes the interrupts that are
managed by the SYS module.
Table 6-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
SYSSNIV, System NMI
SYSUNIV, User NMI
46
ADDRESS
015Eh
015Ch
015Ah
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wakeup (BOR)
08h
Security violation (BOR)
0Ah
Reserved
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
Uncorrectable FRAM bit error detection
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
FLL unlock (PUC)
24h
Reserved
22h, 26h to 3Eh
No interrupt pending
00h
SVS low-power reset entry
02h
Uncorrectable FRAM bit error detection
04h
Reserved
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
Reserved
0Eh
Reserved
10h
VMAIFG vacant memory access
12h
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
16h
Correctable FRAM bit error detection
18h
Reserved
1Ah to 1Eh
No interrupt pending
00h
NMIIFG NMI pin or SVSH event
02h
OFIFG oscillator fault
04h
Reserved
06h to 1Eh
Detailed Description
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
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6.10.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x16 + x12 + x5 + 1.
6.10.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I2C communications.
Additionally, eUSCI_A supports automatic baud-rate detection and IrDA. The eUSCI_A and eUSCI_B are
connected either from P1 port or P2 port, it can be selected from the USCIARMP of SYSCFG3 or
USCIBRMP bit of SYSCFG2. Table 6-11 lists the pin configurations that are required for each eUSCI
mode.
Table 6-11. eUSCI Pin Configurations
eUSCI_A0
eUSCI_B0
PIN (USCIARMP = 0)
UART
SPI
P1.4
TXD
SIMO
P1.5
RXD
SOMI
P1.6
–
SCLK
P1.7
–
STE
PIN (USCIARMP = 1)
UART
SPI
P2.0
TXD
SIMO
P2.1
RXD
SOMI
P1.6
–
SCLK
STE
P1.7
–
PIN (USCIBRMP = 0)
I2C
SPI
P1.0
–
STE
P1.1
–
SCLK
P1.2
SDA
SIMO
P1.3
SCL
SOMI
PIN (USCIBRMP = 1)
I2C
SPI
P2.3
–
STE
P2.4
–
SCLK
P2.5
SDA
SIMO
P2.6
SCL
SOMI
Detailed Description
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6.10.8 Timers (Timer0_A3, Timer1_A3)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare
registers each. Each timer supports multiple captures or compares, PWM outputs, and interval timing (see
and ). Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter on
overflow conditions and from each of the capture/compare registers. The CCR0 registers on both
Timer0_A3 and Timer1_A3 are not externally connected and can only be used for hardware period timing
and interrupt generation. In Up mode, they can be used to set the overflow value of the counter.
Timer_A0
TA0CLK
Timer_A1
00
ACLK
01
SMCLK
10
ACLK
01
VLO
11
SMCLK
10
TA1CLK
00
16-bit Counter
16-bit Counter
11
ACLK
00
VLO
01
DVSS
10
DVCC
11
00
TA0.0A
CCR0
TA0.0B
01
TA0.0A
CCR0
P1.4
DVSS
10
DVCC
11
P2.2
00
DVSS
10
DVCC
11
P2.3
00
DVSS
10
DVCC
11
TA0.0B
00
RTC
01
DVSS
10
DVCC
11
TA0.1A
P1.4
CCR1
TA0.1B
01
TA0.1A
P2.2
TA0.1B
To ADC Trigger
TA0.2A
P2.3
CCR1
P1.5
00
DVSS
10
DVCC
11
01
TA0.2A
P1.5
CCR2
TA0.2B
01
CCR2
TA0.2B
Coding
Carrier
eUSCI_A0
UCA0TXD/UCA0SIMO
Infrared
Logic (SYS)
P2.0/UCA0TXD/UCA0SIMO
Data
Figure 6-2. Timer0_A3 and Timer1_A3 Signal Connections
The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated
infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS
configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select),
IRDSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the
MP430FR4xx and MP430FR2xx Family User's Guide.
6.10.9 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The MPY module supports signed multiplication,
unsigned multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate
operations.
48
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6.10.10 Backup Memory (BAKMEM)
The BAKMEM supports data retention during LPM3.5. This device provides up to 32 bytes that are
retained during LPM3.5.
6.10.11 Real-Time Clock (RTC)
The RTC is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module may
periodically wake up the CPU from LPM0, LPM3 and LPM3.5 based on timing from a low-power clock
source such as the XT1 and VLO clocks. RTC also can be sourced from ACLK controlled by RTCCLK in
SYSCFG2. In AM, RTC can be driven by SMCLK to generate high-frequency timing events and interrupts.
The RTC overflow events trigger:
• Timer0_B3 CCI1B
• ADC conversion trigger when ADCSHSx bits are set as 01b
Table 6-12. RTC Clock Source
RTCSS
CLOCK SOURCE
00
Reserved
01
SMCLK, or ACLK is selected
10
XT1CLK
11
VLOCLK
6.10.12 10-Bit Analog-to-Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The
module implements a 10-bit SAR core, sample select control, a reference generator, and a conversion
result buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring
with three window comparator interrupt flags.
The ADC supports 10 external inputs and 4 internal inputs (see Table 6-13).
Table 6-13. ADC Channel Connections
ADCSHSx
ADC CHANNELS
EXTERNAL PIN
0
A0/Veref+
P1.0
1
A1 (1)
P1.1
2
A2/Veref-
P1.2
3
A3
P1.3
4
A4
P2.2
5
A5
P2.3
6
A6
P2.4
7
A7
P2.5
8
Not used
N/A
9
Not used
N/A
10
Not used
N/A
11
Not used
N/A
12
On-chip temperature sensor
N/A
13
Reference voltage (1.5 V)
N/A
14
DVSS
N/A
(1)
When A7 is used, the PMM 1.2-V reference voltage can be output to
this pin by setting the PMM control register. The 1.2-V voltage can
be measured by the A1 channel.
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Table 6-13. ADC Channel Connections (continued)
ADCSHSx
ADC CHANNELS
EXTERNAL PIN
15
DVCC
N/A
The analog-to-digital conversion can be started by software or a hardware trigger. Table 6-14 lists the
trigger sources that are available.
Table 6-14. ADC Trigger Signal Connections
ADCSHSx
TRIGGER SOURCE
BINARY
DECIMAL
00
0
ADCSC bit (software trigger)
01
1
RTC event
10
2
TA1.1B
11
3
Reserved
6.10.13 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
• EEM version: S
50
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6.11 Input/Output Diagrams
6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 6-3 shows the port diagram. Table 6-15 summarizes the selection of pin function.
A0 to A3
P1SEL.x = 11
P1REN.x
P1DIR.x
From Module1
00
01
10
11
2 bit
From Module2
DVSS
0
DVCC
1
00
01
10
11
P1OUT.x
From Module1
From Module2
DVSS
2 bit
P1SEL.x
EN
To module
D
P1IN.x
P1IE.x
Bus
Keeper
P1 Interrupt
Q
D
S
P1IFG.x
P1IES.x
From JTAG
To JTAG
Edge
Select
P1.0/UCB0STE/A0/Veref+
P1.1/UCB0CLK/ACLK/A1/VREF+
P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/VerefP1.3/UCB0SOMI/UCB0SCL/MCLK/A3
P1.4/UCA0TXD/UCA0SIMO/TA0.1/TCK
P1.5/UCA0RXD/UCA0SOMI/TA0.2/TMS
P1.6/UCA0CLK/TA0CLK/TDI/TCLK
P1.7/UCA0STE/TDO
Figure 6-3. Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Detailed Description
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Table 6-15. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS AND SIGNALS (1)
PIN NAME (P1.x)
P1.0/UCB0STE/A0/
Veref+
P1.1/UCB0CLK/ACLK/
A1/VREF+
P1.2/UCB0SIMO/
UCB0SDA/SMCLK/A2/
Veref-
P1.3/UCB0SOMI/
UCB0SCL/MCLK/A3
x
0
1
2
3
FUNCTION
P1DIR.x
P1SELx
ANALOG
FUNCTION (2)
JTAG
P1.0 (I/O)
I: 0; O: 1
00
0
0
UCB0STE
X
01
0
0
A0,Veref+
X
P1.1 (I/O)
I: 0; O: 1
00
0
0
UCB0CLK
X
01
0
0
ACLK
1
10
0
0
A1,VREF+
X
P1.2 (I/O)
P1.5/UCA0RXD/
UCA0SOMI/TA0.2/TMS
5
6
00
0
0
01
0
0
SMCLK
1
10
0
0
(1)
(2)
52
7
ADCPCTLx = 1 (x = 2) from
SYSCFG2
A2, Veref-
X
P1.3 (I/O)
I: 0; O: 1
00
0
0
UCB0SOMI/UCB0SCL
X
01
0
0
MCLK
1
10
0
0
X
N/A
ADCPCTLx = 1 (x = 3) from
SYSCFG2
N/A
I: 0; O: 1
00
0
Disabled
UCA0TXD/UCA0SIMO
X
01
0
Disabled
TA0.CCI1A
0
TA0.1
1
10
0
Disabled
JTAG TCK
X
X
X
TCK
P1.5 (I/O)
I: 0; O: 1
00
0
Disabled
UCA0RXD/UCA0SOMI
X
01
0
Disabled
TA0.CCI2A
0
TA0.2
1
10
0
Disabled
X
X
X
TMS
P1.6 (I/O)
I: 0; O: 1
00
0
Disabled
UCA0CLK
X
01
0
Disabled
TA0CLK
0
10
0
Disabled
JTAG TDI/TCLK
P1.7/UCA0STE/TDO
N/A
X
JTAG TMS
P1.6/UCA0CLK/
TA0CLK/TDI/TCLK
ADCPCTLx = 1 (x = 1) from
SYSCFG2
I: 0; O: 1
P1.4 (I/O)
4
N/A
UCB0SIMO/UCB0SDA
A3
P1.4/UCA0TXD/
UCA0SIMO/TA0.1/TCK
ADCPCTLx = 1 (x = 0) from
SYSCFG2
X
X
X
TDI/TCLK
P1.7 (I/O)
I: 0; O: 1
00
0
Disabled
UCA0STE
X
01
0
Disabled
JTAG TDO
X
X
X
TDO
X = don't care
Setting the bits disables both the output driver and input Schmitt trigger to prevent leakage when analog signals are applied.
Detailed Description
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6.11.2 Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-16 summarizes the selection of pin function.
A4 to A7
P2SEL.x = 11
P2REN.x
P2DIR.x
From Module1
00
01
10
11
2 bit
From Module2
DVSS
0
DVCC
1
00
01
10
11
P2OUT.x
From Module1
From Module2
DVSS
2 bit
P2SEL.x
EN
To module
D
P2IN.x
P2IE.x
Bus
Keeper
P2 Interrupt
Q
D
S
P2IFG.x
P2IES.x
Edge
Select
P2.0/UCA0TXD/UCA0SIMO/XOUT
P2.1/UCA0RXD/UCA0SOMI/XIN
P2.2/TA1.1/A4
P2.3/TA1.2/UCB0STE/A5
P2.4/TA1CLK/UCB0CLK/A6
P2.5/UCB0SIMO/UCB0SDA/A7
P2.6/UCB0SOMI/UCB0SCL
Figure 6-4. Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
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Table 6-16. Port P2 (P2.0 to P2.6) Pin Functions
CONTROL BITS AND SIGNALS (1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SELx
ANALOG
FUNCTION (2)
I: 0; O: 1
00
0
UCA0TXD/UCA0SIMO
X
01
0
XOUT
X
10
0
I: 0; O: 1
00
0
UCA0RXD/UCA0SOMI
X
01
0
XIN
X
10
0
I: 0; O: 1
00
0
01
0
P2.0 (I/O)
P2.0/UCA0TXD/
UCA0SIMO/XOUT
0
P2.1 (I/O)
P2.1/UCA0RXD/
UCA0SOMI/XIN
1
P2.2 (I/O)
P2.2/TA1.1/A4
2
TA1.CCI1A
0
TA1.1
1
A4
X
X
ADCPCTLx = 1 (x = 4)
from SYSCFG2 (2)
I: 0; O: 1
00
0
01
0
P2.3 (I/O)
P2.3/TA1.2/
UCB0STE/A5
3
TA1.CCI2A
0
TA1.2
1
UCB0STE
X
10
0
X
X
ADCPCTLx = 1 (x = 5)
from SYSCFG2 (2)
I: 0; O: 1
00
0
TA1CLK
0
01
0
UCB0CLK
X
10
0
X
X
ADCPCTLx = 1 (x = 6)
from SYSCFG2 (2)
I: 0; O: 1
00
0
X
10
0
X
X
ADCPCTLx = 1 (x = 7)
from SYSCFG2 (2)
I: 0; O: 1
00
0
X
10
0
A5
P2.4 (I/O)
P2.4/TA1CLK/
UCB0CLK/A6
4
A6
P2.5 (I/O)
P2.5/UCB0SIMO/
UCB0SDA/A7
5
UCB0SIMO/UCB0SDA
A7
P2.6/UCB0SOMI/
UCB0SCL
(1)
(2)
54
6
P2.6 (I/O)
UCB0SOMI/UCB0SCL
X = don't care
Setting the bits disables both the output driver and input Schmitt trigger to prevent leakage when analog signals are applied.
Detailed Description
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6.12 Device Descriptors
Table 6-17 lists the Device IDs of the devices. Table 6-18 lists the contents of the device descriptor taglength-value (TLV) structure for the devices.
Table 6-17. Device IDs
DEVICE ID
DEVICE
MSP430FR2422
1A05h
1A04h
83h
11h
Table 6-18. Device Descriptors
DESCRIPTION
ADDRESS
VALUE
Info length
1A00h
06h
CRC length
1A01h
06h
1A02h
Per unit
1A03h
Per unit
CRC value (1)
Information Block
1A04h
Device ID
1A05h
1A06h
Per unit
Firmware revision
1A07h
Per unit
Die record tag
1A08h
08h
Lot wafer ID
Die Record
Die X position
Die Y position
Test result
1A09h
0Ah
1A0Ah
Per unit
1A0Bh
Per unit
1A0Ch
Per unit
1A0Dh
Per unit
1A0Eh
Per unit
1A0Fh
Per unit
1A10h
Per unit
1A11h
Per unit
1A12h
Per unit
1A13h
Per unit
ADC calibration tag
1A14h
Per unit
ADC calibration length
1A15h
Per unit
1A16h
Per unit
1A17h
Per unit
1A18h
Per unit
1A19h
Per unit
1A1Ah
Per unit
1A1Bh
Per unit
1A1Ch
Per unit
1A1Dh
Per unit
ADC gain factor
ADC offset
ADC 1.5-V reference, temperature 30°C
ADC 1.5-V reference, temperature 85°C
(1)
See Table 6-17.
Hardware revision
Die record length
ADC calibration
MSP430FR2422
The CRC value covers the check sum from 0x1A04h to 0x1AEFh by applying the CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1.
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Table 6-18. Device Descriptors (continued)
MSP430FR2422
DESCRIPTION
Reference and DCO Calibration
ADDRESS
VALUE
Calibration tag
1A1Eh
12h
Calibration length
1A1Fh
04h
1A22h
Per unit
1A23h
Per unit
DCO tap setting for 16 MHz, temperature 30°C (2)
(2)
This value can be directly loaded into DCO bits in CSCTL0 registers to get accurate 16-MHz frequency at room temperature, especially
when the MCU exits from LPM3 and below. TI suggests using the predivider to decrease the frequency if the temperature drift might
result an overshoot beyond 16 MHz.
6.13 Memory
6.13.1 Memory Organization
Table 6-19 summarizes the memory organization of the devices.
Table 6-19. Memory Organization
ACCESS
MSP430FR2422
Read/Write
(Optional Write Protect) (1)
7.25KB
FFFFh to FF80h
FFFFh to E300h
Read/Write
2KB
27FFh to 2000h
Read/Write
(Optional Write Protect) (2)
256B
18FFh to 1800h
Bootloader (BSL1) Memory (ROM)
Read only
2KB
17FFh to 1000h
Bootloader (BSL2) Memory (ROM)
Read only
1KB
FFFFFh to FFC00h
Peripherals
Read/Write
4KB
0FFFh to 0000h
Memory (FRAM)
Main: interrupt vectors and signatures
Main: code memory
RAM
Information Memory (FRAM)
(1)
(2)
56
The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in the MP430FR4xx and
MP430FR2xx Family User's Guide for more details
The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in the MP430FR4xx and
MP430FR2xx Family User's Guide for more details
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6.13.2 Peripheral File Map
Table 6-20 lists the available peripherals and the register base address for each.
Table 6-20. Peripherals Summary
BASE ADDRESS
SIZE
Special Functions (See Table 6-21)
MODULE NAME
0100h
0010h
PMM (See Table 6-22)
0120h
0020h
SYS (See Table 6-23)
0140h
0040h
CS (See Table 6-24)
0180h
0020h
FRAM (See Table 6-25)
01A0h
0010h
CRC (See Table 6-26)
01C0h
0008h
WDT (See Table 6-27)
01CCh
0002h
Port P1, P2 (See Table 6-28)
0200h
0020h
RTC (See Table 6-29)
0300h
0010h
Timer0_A3 (See Table 6-30)
0380h
0030h
Timer1_A3 (See Table 6-31)
03C0h
0030h
MPY32 (See Table 6-32)
04C0h
0030h
eUSCI_A0 (See Table 6-33)
0500h
0020h
eUSCI_B0 (See Table 6-34)
0540h
0030h
Backup Memory (See Table 6-35)
0660h
0020h
ADC (See Table 6-36)
0700h
0040h
Table 6-21. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
SFR interrupt enable
SFR interrupt flag
SFR reset pin control
ACRONYM
OFFSET
SFRIE1
00h
SFRIFG1
02h
SFRRPCR
04h
Table 6-22. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
PMM control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
PMM control 2
PMMCTL2
04h
PMM interrupt flags
PMMIFG
0Ah
PM5 control 0
PM5CTL0
10h
Detailed Description
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Table 6-23. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System control
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
System configuration 0
SYSCFG0
20h
System configuration 1
SYSCFG1
22h
System configuration 2
SYSCFG2
24h
Table 6-24. CS Registers (Base Address: 0180h)
ACRONYM
OFFSET
CS control 0
REGISTER DESCRIPTION
CSCTL0
00h
CS control 1
CSCTL1
02h
CS control 2
CSCTL2
04h
CS control 3
CSCTL3
06h
CS control 4
CSCTL4
08h
CS control 5
CSCTL5
0Ah
CS control 6
CSCTL6
0Ch
CS control 7
CSCTL7
0Eh
CS control 8
CSCTL8
10h
Table 6-25. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
FRAM control 0
FRCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
Table 6-26. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
CRC data input
Table 6-27. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
Watchdog timer control
58
ACRONYM
OFFSET
WDTCTL
00h
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Table 6-28. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 input
Port P1 pulling enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
P1SEL1
0Ch
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
P1IE
1Ah
P1IFG
1Ch
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
Port P2 pulling enable
P2REN
07h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1
P2SEL1
0Ch
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
P2IE
1Bh
P2IFG
1Dh
Port P2 interrupt enable
Port P2 interrupt flag
Table 6-29. RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
RTCCTL
00h
RTCIV
04h
RTC modulo
RTCMOD
08h
RTC counter
RTCCNT
0Ch
RTC control
RTC interrupt vector
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Table 6-30. Timer0_A3 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
TA0EX0
20h
TA0IV
2Eh
TA0 control
TA0 counter
TA0 expansion 0
TA0 interrupt vector
Table 6-31. Timer1_A3 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
TA1 control
ACRONYM
OFFSET
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
Capture/compare 2
TA1CCR2
16h
TA1 counter
TA1 expansion 0
TA1 interrupt vector
60
TA1EX0
20h
TA1IV
2Eh
Detailed Description
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Table 6-32. MPY32 Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
16-bit operand 1 – multiply
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
16 × 16 result low word
16 × 16 result high word
ACRONYM
OFFSET
MPY
00h
MPYS
02h
MAC
04h
MACS
06h
OP2
08h
RESLO
0Ah
RESHI
0Ch
16 × 16 sum extension
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
MAC32L
18h
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32CTL0
2Ch
MPY32 control 0
Table 6-33. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI_A control word 1
UCA0CTLW1
02h
eUSCI_A control rate 0
UCA0BR0
06h
UCA0BR1
07h
eUSCI_A control rate 1
eUSCI_A modulation control
UCA0MCTLW
08h
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
lUCA0IRTCTL
12h
eUSCI_A IrDA receive control
IUCA0IRRCTL
13h
UCA0IE
1Ah
UCA0IFG
1Ch
UCA0IV
1Eh
eUSCI_A status
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
Table 6-34. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
eUSCI_B control word 0
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
Detailed Description
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Table 6-34. eUSCI_B0 Registers (Base Address: 0540h) (continued)
REGISTER DESCRIPTION
eUSCI_B status word
ACRONYM
OFFSET
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
eUSCI_B receive address
UCB0ADDRX
1Ch
UCB0ADDMASK
1Eh
UCB0I2CSA
20h
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
62
UCB0IE
2Ah
UCB0IFG
2Ch
UCB0IV
2Eh
Detailed Description
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Table 6-35. Backup Memory Registers (Base Address: 0660h)
ACRONYM
OFFSET
Backup memory 0
REGISTER DESCRIPTION
BAKMEM0
00h
Backup memory 1
BAKMEM1
02h
Backup memory 2
BAKMEM2
04h
Backup memory 3
BAKMEM3
06h
Backup memory 4
BAKMEM4
08h
Backup memory 5
BAKMEM5
0Ah
Backup memory 6
BAKMEM6
0Ch
Backup memory 7
BAKMEM7
0Eh
Backup memory 8
BAKMEM8
10h
Backup memory 9
BAKMEM9
12h
Backup memory 10
BAKMEM10
14h
Backup memory 11
BAKMEM11
16h
Backup memory 12
BAKMEM12
18h
Backup memory 13
BAKMEM13
1Ah
Backup memory 14
BAKMEM14
1Ch
Backup memory 15
BAKMEM15
1Eh
Table 6-36. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC control 0
ADCCTL0
00h
ADC control 1
ADCCTL1
02h
ADC control 2
ADCCTL2
04h
ADCLO
06h
ADC window comparator low threshold
ADC window comparator high threshold
ADCHI
08h
ADC memory control 0
ADCMCTL0
0Ah
ADC conversion memory
ADCMEM0
12h
ADC interrupt enable
ADC interrupt flags
ADC interrupt vector word
ADCIE
1Ah
ADCIFG
1Ch
ADCIV
1Eh
Detailed Description
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6.14 Identification
6.14.1 Revision Identification
The device revision information is included as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Hardware Revision entries in Section 6.12.
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Device ID entries in Section 6.12.
6.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in MSP430 Programming With the JTAG Interface.
64
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430 devices. These
guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling
capacitor to the DVCC and DVSS pins. Higher-value capacitors may be used but can impact supply rail
ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple
(within a few millimeters). Additionally, TI recommends separated grounds with a single-point connection
for better noise isolation from digital-to-analog circuits on the board and to achieve high analog accuracy.
DVCC
Digital
Power Supply
Decoupling
+
10 µF
100 nF
DVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass
capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the
respective oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT
pin can be used for other purposes. If the XIN and XOUT pins are not used, they must be terminated
according to Section 4.6.
Figure 7-2 shows a typical connection diagram.
XIN
CL1
XOUT
CL2
Figure 7-2. Typical Crystal Connection
Applications, Implementation, and Layout
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See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
7.1.3
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC sense feature detects the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target
board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the
jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's
Guide.
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TMS
TCK
TCK
GND
RST
TEST/SBWTCK
C1
1 nF
(see Note B)
DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
66
Applications, Implementation, and Layout
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
1 nF
(see Note B)
DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 10-nF pulldown capacitor. The pulldown capacitor
should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MP430FR4xx and MP430FR2xx Family User's Guide for more information on the referenced
control registers and bits.
7.1.5
Unused Pins
For details on the connection of unused pins, see Section 4.6.
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7.1.6
www.ti.com
General Layout Recommendations
•
•
•
•
7.1.7
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
Proper bypass capacitors on DVCC and reference pins, if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
Do's and Don'ts
During power up, power down, and device operation, DVCC must not exceed the limits specified in
Section 5.1. Exceeding the specified limits may cause malfunction of the device including erroneous writes
to RAM and FRAM.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC Peripheral
7.2.1.1
Partial Schematic
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used.
DVSS
Using an external
positive reference
VREF+/VEREF+
+
10 µF
100 nF
Using an external
negative reference
VEREF+
10 µF
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Figure 7-5 prevent this.
Quickly switching digital signals and noisy power supply lines can corrupt the conversion results, so keep
the ADC input trace shielded from those digital and power supply lines. Putting the MCU in low-power
mode during the ADC conversion improves the ADC performance in a noisy environment. If the device
includes the analog power pair inputs (AVCC and AVSS), TI recommends a noise-free design using
separate analog and digital ground planes with a single-point connection to achieve high accuracy.
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.
68
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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency
ripple. A bypass capacitor of 100 nF filters out any high-frequency noise.
7.2.1.3
Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins to avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
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8 Device and Documentation Support
8.1
Getting Started and Next Steps
For more information on the MSP low-power microcontrollers and the tools and libraries that are available
to help with your development, visit the Getting Started page.
8.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCUs and support tools. Each MSP430 MCU commercial family member has one of three
prefixes: MSP, PMS, or XMS. TI recommends two of three possible prefix designators for its support tools:
MSP and MSPX. These prefixes represent evolutionary stages of product development from engineering
prototypes (with XMS for devices and MSPX for tools) through fully qualified production devices and tools
(with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications of the final
device
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI internal qualification testing.
MSP – Fully-qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RHL) and temperature range (for example, T). Figure 8-1 provides a legend
for reading the complete device name for any family member.
70
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MSP 430 FR 2 422 I RHL T
Processor Family
MCU Platform
Device Type
Distribution Format
Series
Feature Set
Packaging
Temperature Range
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
MCU Platform
430 = MSP430 16-bit low-power platform
Device Type
Memory Type
FR = FRAM
Series
2 = Up to 16 MHz without LCD
Feature Set
First and Second Digits:
ADC10 Channels / eUSCIs / 16-bit Timers / I/Os
42 = Up to 8 / 2 / 2 / Up to 15
Temperature Range
I = –40°C to 85°C
Packaging
www.ti.com/packaging
Distribution Format
T = Small reel
R = Large reel
No Marking = Tube or tray
Third Digit:
FRAM (KB) / SRAM (KB)
2=8/2
Figure 8-1. Device Nomenclature
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Tools and Software
See the Code Composer Studio for MSP430 User's Guide for details on the available features.
Table 8-1 lists the debug features supported by these microcontrollers
Table 8-1. Hardware Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
EEM
VERSION
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
No
S
Design Kits and Evaluation Modules
MSP-TS430RHL20 20-Pin Target Development Board for MSP430FR2x MCUs
The
MSPTS430RHL20 is a stand-alone ZIF socket target board used to program and debug the
MSP430 in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.
The development board supports all MSP430FR252x and MSP430FR242x Flash parts in a
20-pin VQFN package (TI package code: RHL).
MSP-FET + MSP-TS430RHL20 FRAM Microcontroller Development Kit Bundle
The
MSPFET430RHL20-BNDL bundle combines two debugging tools that support the 20-pin RHL
package for the MSP430FR2422 microcontroller (for example, MSP430FR2422RHL). These
two tools include MSP-TS430RHL20 and MSP-FET.
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 design resources,
MSP430Ware software also includes a high-level API called MSP430 Driver Library. This
library makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430FR2422 Code Examples C Code examples are available for every MSP device that configures
each of the integrated peripherals for various application needs.
MSP Driver Library Driver Library's abstracted API keeps you above the bits and bytes of the MSP430
hardware by providing easy-to-use function calls. Thorough documentation is delivered
through a helpful API Guide, which includes details on each function call and the recognized
parameters. Developers can use Driver Library functions to write complete projects with
minimal overhead.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the application’s energy profile and
helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully utilize the unique ultra-low power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to squeeze every last nano amp
out of your application. At build time, ULP Advisor will provide notifications and remarks to
highlight areas of your code that can be further optimized for lower power.
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FRAM Embedded Software Utilities for MSP Ultra-Low-Power Microcontrollers The FRAM Utilities is
designed to grow as a collection of embedded software utilities that leverage the ultra-lowpower and virtually unlimited write endurance of FRAM. The utilities are available for
MSP430FRxx FRAM microcontrollers and provide example code to help start application
development. Included utilities include Compute Through Power Loss (CTPL). CTPL is utility
API set that enables ease of use with LPMx.5 low-power modes and a powerful shutdown
mode that allows an application to save and restore critical system components when a
power loss is detected.
IEC60730 Software Package The IEC60730 MSP430 software package was developed to be useful in
assisting customers in complying with IEC 60730-1:2010 (Automatic Electrical Controls for
Household and Similar Use – Part 1: General Requirements) for up to Class B products,
which includes home appliances, arc detectors, power converters, power tools, e-bikes, and
many others. The IEC60730 MSP430 software package can be embedded in customer
applications running on MSP430s to help simplify the customer’s certification efforts of
functional safety-compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430 Continuing to innovate in the low power and low cost
microcontroller space, TI brings you MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating point math library of scalar functions brings you up to 26x better
performance. Mathlib is easy to integrate into your designs. This library is free and is
integrated in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in
depth look at the math library and relevant benchmarks.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio is an integrated development environment (IDE) that supports all MSP
microcontroller devices. Code Composer Studio comprises a suite of embedded software
utilities used to develop and debug embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment, debugger, profiler, and many other
features. The intuitive IDE provides a single user interface taking you through each step of
the application development flow. Familiar utilities and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse
software framework with advanced embedded debug capabilities from TI resulting in a
compelling feature-rich development environment for embedded developers. When using
CCS with an MSP MCU, a unique and powerful set of plugins and embedded software
utilities are made available to fully leverage the MSP microcontroller.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) files directly to
the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which allows users to quickly begin application development on MSP
low-power microcontrollers (MCU). Creating MCU software usually requires downloading the
resulting binary program to the MSP device for validation and debugging. The MSP-FET
provides a debug communication pathway between a host computer and the target MSP.
Furthermore, the MSP-FET also provides a Backchannel UART connection between the
computer's USB interface and the MSP UART. This affords the MSP programmer a
convenient method for communicating serially between the MSP and a terminal running on
the computer. It also supports loading programs (often called firmware) to the MSP target
using the BSL (bootloader) through the UART and I2C communication protocols.
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MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 Flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that allow
the user to fully customize the process. The MSP Gang Programmer is provided with an
expansion board, called the Gang Splitter, that implements the interconnections between the
MSP Gang Programmer and multiple target devices. Eight cables are provided that connect
the expansion board to eight target devices (through JTAG or Spy-Bi-Wire connectors). The
programming can be done with a PC or as a stand-alone device. A PC-side graphical user
interface is also available and is DLL-based.
8.4
Documentation Support
The following documents describe the MSP430FR2422 microcontrollers. Copies of these documents are
available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for example, MSP430FR2422). In the upper right corner, click the "Alert me" button.
This registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
Errata
MSP430FR2422 Device Erratasheet Describes the known exceptions to the functional specifications for
all silicon revisions of this device.
User's Guides
MSP430FR4xx and MSP430FR2xx Family User's Guide
peripherals available in this device family.
Detailed description of all modules and
MSP430 Programming With the Bootloader (BSL) The MSP430 bootloader (BSL) lets users
communicate with embedded memory in the MSP430 microcontroller during the prototyping
phase, final production, and in service. Both the programmable memory (flash memory) and
the data memory (RAM) can be modified as required. Do not confuse the bootloader with the
bootstrap loader programs found in some digital signal processors (DSPs) that automatically
load program code (and data) from external memory to the internal memory of the DSP.
MSP430FR4xx and MSP430FR2xx Bootloader (BSL) User's Guide The bootloader (BSL) can program
memory during MSP430 MCU project development and updates. The BSL can be activated
by a utility that sends commands using a serial protocol. The BSL enables the user to control
the activity of the MSP430 device and to exchange data using a personal computer or other
device.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
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Application Reports
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs: (1) Component-level ESD testing and system-level ESD testing, their differences
and why component-level ESD rating does not ensure system-level robustness. (2) General
design guidelines for system-level ESD protection at different levels including enclosures,
cables, PCB layout, and on-board ESD protection devices. (3) Introduction to System
Efficient ESD Design (SEED), a codesign methodology of on-board and on-chip ESD
protection to achieve system-level ESD robustness, with example simulations and test
results. A few real-world system-level ESD protection design examples and their results are
also discussed.
8.5
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.6
Trademarks
MSP430, MSP430Ware, Code Composer Studio, E2E, EnergyTrace, ULP Advisor are trademarks of
Texas Instruments.
All other trademarks are the property of their respective owners.
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8.7
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Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.8
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.9
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation.
Copyright © 2018, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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MSP430FR2422
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PACKAGE OUTLINE
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
A
3.6
3.4
B
PIN 1 INDEX AREA
4.6
4.4
C
1 MAX
SEATING PLANE
0.08 C
2.05±0.1
2X 1.5
20X 0.5
0.3
SYMM
10
14X 0.5
2X
3.5
9
12
SYMM
21
3.05±0.1
19
2
PIN 1 ID
(OPTIONAL)
(0.2) TYP
11
1
20
4X (0.2)
20X 0.29
0.19
0.1
0.05
C A B
C
2X (0.55)
4219071 / A 06/2017
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1
20
2X (0.4)
20X (0.6)
19
2
20X (0.24)
14X (0.5)
SYMM
21
(3.05)
(4.3)
6X (0.525)
2X (0.75)
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
9
12
(R0.05) TYP
(Ø0.2) VIA
TYP)
11
10
4X (0.2)
4X
(0.775)
2X (0.55)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219071 / A 06/2017
NOTES: (continued)
4.
5.
6.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271) .
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to theri
locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
2X (1.5)
(0.55)
TYP
1
(0.56)
TYP
SOLDER MASK EDGE
TYP
20
20X (0.6)
2
19
20X (0.24)
14X (0.5)
(1.05)
TYP
SYMM
(4.3)
21
6X
(0.85)
(R0.05) TYP
METAL
TYP
12
9
2X
(0.775)
2X (0.25)
11
10
4X (0.2)
6X (0.92)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
75% PRINTED COVERAGE BY AREA
SCALE: 20X
4219071 / A 06/2017
NOTES: (continued)
7.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
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PACKAGE OPTION ADDENDUM
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23-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR2422IPW16
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2422
MSP430FR2422IPW16R
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2422
MSP430FR2422IRHLR
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2422
MSP430FR2422IRHLT
ACTIVE
VQFN
RHL
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2422
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430FR2422IPW16R
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430FR2422IRHLR
VQFN
RHL
20
3000
330.0
12.4
3.71
4.71
1.1
8.0
12.0
Q1
MSP430FR2422IRHLT
VQFN
RHL
20
250
180.0
12.4
3.71
4.71
1.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jan-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FR2422IPW16R
MSP430FR2422IRHLR
TSSOP
PW
16
2000
367.0
367.0
38.0
VQFN
RHL
20
3000
367.0
367.0
35.0
MSP430FR2422IRHLT
VQFN
RHL
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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