BOARDCOM ACPL-33JT Automotive 2.5 amp gate drive optocoupler Datasheet

ACPL-33JT
Automotive 2.5 Amp Gate Drive Optocoupler with
Integrated Flyback Controller for Isolated DC-DC
Converter, Integrated IGBT Desat Over Current
Sensing, Miller Current Clamping and UVLO Feedback
Data Sheet
Description
Features
The ACPL-33JT Automotive 2.5 Amp Gate Drive Optocoupler
features integrated flyback controller for isolated DC-DC
converter, IGBT desaturation sensing and fault feedback,
Under-Voltage LockOut (UVLO) with soft-shutdown and fault
feedback and active Miller current clamping. The fast
propagation delay with excellent timing skew performance
enables excellent timing control and efficiency. This full feature
optocoupler comes in a compact, surface-mountable SO-16
package for space-savings, is suitable for traction power train
inverter, power converter, battery charger, air-conditioner and
oil pump motor drives in HEV and EV applications.

Avago R2Coupler® isolation products provide reinforced
insulation and reliability that delivers safe signal isolation
critical in automotive and high temperature industrial
applications.
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Functional Diagram
Figure 1 ACPL-33JT Functional Diagram

VEE2
PGD
VCC2

Ramp Gen
OSC
COMP
Qualified to AEC-Q100 Grade 1 Test Guidelines
Automotive temperature range: -40°C to +125°C
Integrated flyback controller for isolated DC-DC converter
Regulated output voltage: 16V
Peak output current: 2.5A max.
Miller clamp sinking current: 2A
Input supply voltage range: 4.5V to 5.5V
Common mode rejection (CMR): > 50 kV/μs at VCM = 1500V
Propagation delay: 250 ns max.
Integrated fail-safe IGBT protection
— Desat sensing, “soft” IGBT turn-off and fault feedback
— Under voltage lock-out (UVLO) protection with
feedback
High noise immunity
— Miller current clamping
— Direct LED input with low input impedance and low
noise sensitivity
SO-16 package with 8-mm clearance and creepage
Regulatory approvals:
— UL1577, CSA
— IEC/EN/DIN EN 60747-5-5
S
R
LED2+
UVLO
VCC1

/UVLO

Input
Driver
DESAT
/FAULT
Output
Driver
VEE1
AN
CA
Applications

DESAT

VO
Control
VO

SSD
SSD Control
CLAMP
Miller Control
VEE2
Broadcom
-1-
Automotive isolated IGBT/MOSFET inverter gate drive
Automotive DC-DC converter
AC and brushless DC motor drives
Hybrid and plug-in hybrid power train inverter
Uninterruptible power supplies (UPSs)
ACPL-33JT
Data Sheet
CAUTION
Applications
Take normal static precautions in handling and assembly of this component to prevent damage, degradation, or
both, that might be induced by ESD. The components featured in this data sheet are not to be used in military or
aerospace applications or environments.
Table 1 Ordering Information
Part Number
ACPL-33JT
Option (RoHS Compliant)
–500E
Package
SO-16
Surface Mount
X
IEC/EN/DIN EN
60747-5-5
Tape and Reel
X
X
Quantity
850 per reel
To order, choose a part number from the Part Number column and combine with the desired option from the Option column to
form an order entry.
Example:
ACPL-33JT-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5
Safety Approval in RoHS compliant.
Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information.
Broadcom
-2-
ACPL-33JT
Data Sheet
Recommended Lead-free IR Profile
Figure 2 Package Outline Drawings (16-Lead Surface Mount)
0.457±0.127
[0.018±0.005]
RECOMMENDED LAND PATTERN
1.270
[0.050]
PART NUMBER
DATE CODE
RoHs-COMPLIANCE
INDICATOR
A 33JT
YYWW
EE
7.493 +0.254
-0.127
0.295 +0.010
-0.005
11.634
[0.458]
PACKAGE
BODY POSITION
2.160
[0.085]
Extended
Datecode for
lot tracking
10.363+0.254
-0.127
0.408 +0.010
-0.005
0.640
[0.025]
1.270
[0.050]
8.763±0.254
[0.345±0.010]
90 (X4)
3.505±0.127
[0.138±0.005]
0.203±0.102
[0.008±0.004]
STANDOFF
90 (X4)
( 0 - 8°)
0.254±0.102
[0.010±0.004]
0.750±0.254
[0.030±0.010]
10.363±0.254
[0.408±0.010]
Dimensions in millimeters (inches).
NOTE
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Lead coplanarity = 0.10 mm (0.004 inches) max
Floating lead protrusion = 0.254 mm ([0.010 inches) max
Mold flash on each side = 0.254 mm (0.010 inches) max
Recommended Lead-free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision).
Non-halide flux should be used.
Product Overview Description
The ACPL-33JT (shown in Figure 1) is a highly integrated power control device that incorporates all the necessary components for a
complete, reliable, isolated IGBT gate drive circuit. It features a flyback controller for isolated DC-DC converter, a high current gate
driver, Miller current clamping, IGBT desaturation sensing, IGBT soft shutdown (SSD), fault feeback and under voltage lock-out
(UVLO) protection and feedback in a SO-16 package. Direct LED input allows flexible logic configuration and differential current
mode driving with low input impedance, greatly increases its noise immunity.
Broadcom
-3-
ACPL-33JT
Data Sheet
Package Pinout
Package Pinout
Figure 3 Pin out of ACPL-33JT
1
VEE1
VEE2
16
2
PGD
LED2+
15
3
VCC1
DESAT
14
4
COMP
SSD
13
5
/UVLO
VCC2
12
6
/FAULT
VO
11
7
AN
CLAMP
10
8
CA
VEE2
9
Table 2 Pin Description
Pin No.
Pin Name
Function
Pin No.
Pin Name
Function
1
VEE1
Input IC common
16
VEE2
Output IC common and IGBT emitter reference
2
PGD
Primary gate drive for MOSFET
15
LED2+
No connection, for testing only
3
VCC1
Input power supply
14
DESAT
Desaturation over current sensing
4
COMP
Compensation network for Flyback Controller
13
SSD
Soft Shutdown
5
/UVLO
VCC2 Under Voltage Lock-Out feedback
12
VCC2
Output power supply
6
/FAULT
Over current fault feedback
11
VO
Driver output to IGBT gate
7
AN
Input LED anode
10
CLAMP
Miller current clamping output
8
CA
Input LED cathode
9
VEE2
Output IC common and IGBT emitter reference
Regulatory Information
The ACPL-33JT is approved by the following organizations:
Table 3 Regulatory Information
UL
Approved under UL 1577, component recognition program up to VISO = 5000 VRMS.
CSA
Approved under CSA Component Acceptance Notice #5, File CA 88324.
IEC/EN/DIN EN 60747-5-5
Approved under: IEC 60747-5-5, EN 60747-5-5, DIN EN 60747-5-5, IEC/EN/DIN EN60747-5-5
Broadcom
-4-
ACPL-33JT
Data Sheet
Regulatory Information
Table 4 IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Description
Symbol
Characterist
ic
Insulation Classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000 Vrms
I – IV
I – IV
I – IV
I – III
Climatic Classificationa
40/125/21
Pollution Degree (DIN VDE 0110/1.89)
Unit
2
Maximum Working Insulation Voltage
VIORM
1230
VPEAK
Input to Output Test Voltage, Method b
VIORM ×1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC
VPR
2306
VPEAK
Input to Output Test Voltage, Method a
VIORM × 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial Discharge < 5 pC
VPR
1968
VPEAK
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
8000
VPEAK
TS
PS,INPUT
PS,OUTPUT
175
400
1200
°C
mW
mW
RS
> 109
Ohm
Safety-limiting values – maximum values allowed in the event of a failure
Case Temperature
Input Power
Output Power
Insulation Resistance at TS, VIO = 500V
a.
Climatic classification denotes minimum operating temperature/ maximum operating temperature/ humidity test duration.
NOTE
1.
2.
Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective
circuits in application. Surface mount classification is class A in accordance with CECCOO802.
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety
Regulation section IEC 60747-5-5, EN/DIN EN 60747-5-5, for a detailed description of Method a and Method b partial
discharge test profiles.
Table 5 Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap
(Clearance)
L(101)
8.3
mm
Measured from input terminals to output terminals, shortest
distance through air.
Minimum External Tracking
(Creepage)
L(102)
8.3
mm
Measured from input terminals to output terminals, shortest
distance path along body.
0.5
mm
Through insulation distance conductor to conductor, usually
the straight line distance thickness between the emitter and
detector.
>175
Volts
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
CTI
IIIa
Material Group (DIN VDE 0110)
Broadcom
-5-
ACPL-33JT
Data Sheet
Regulatory Information
Table 6 Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Note
Storage Temperature
TS
–55
150
°C
Operating Temperature
TA
–40
125
°C
Output IC Junction Temperature
TJ
150
°C
Average Input Current
IF(AVG)
20
mA
Peak Transient Input Current (<1 μs
pulse width, 300pps)
IF(TRAN)
1
A
Reverse Input Voltage
VR
6.0
V
Input Supply Voltage b
VCC1 – VEE1
–0.5
6.0
V
Primary Gate Drive Voltageb
VPGD – VEE1
–0.5
VCC1
V
COMP Pin Voltage b
VCOMP – VEE1
–0.5
VCC1
V
/UVLO Output Currentc
I/UVLO
10
mA
/UVLO Pin Voltageb
V/UVLO – VEE1
6.0
V
/Fault Output Currentc
I/FAULT
10
mA
/Fault Pin Voltageb
V/FAULT – VEE1
–0.5
6.0
V
Output Supply Voltageb
VCC2 – VEE2
–0.5
25
V
Peak Output Currentc
|IO(peak)|
2.5
A
Gate Drive Output Voltage b
VO(peak) – VEE2
–0.5
VCC2+0.5
V
Miller Clamping Pin Voltageb
VCLAMP – VEE2
–0.5
VCC2+0.5
V
f
Desat Voltageb
VDESAT – VEE2
–0.5
VCC2+0.5
V
g
Soft Shutdown Pin Voltageb
VSSD – VEE2
–0.5
VCC2+0.5
V
Output IC Power Dissipation
PO
600
mW
a
Input IC Power Dissipation
PI
150
mW
a
–0.5
a
d
d
e
a.
Input IC power dissipation is derated linearly above 10 0°C from 15 0mW to 100 mW at 125 °C for high effective thermal conductivity
board. Output IC power dissipation is derated linearly above 100 °C from 600 mW to 350 mW at 125 °C for high effective thermal
conductivity board; see Figure 6. For power derating with low effective thermal conductivity board, see Figure 5.
b.
Absolute maximum voltage ratings imply transistor off state.
c.
Absolute maximum current ratings imply transistor on state.
d.
Duration of absolute maximum voltage applied to /UVLO or /Fault pin during the internal MOS turns ON is limited to maximum 10 μs
with maximum 5% duty cycle.
e.
Maximum pulse width=1 μs, maximum duty cycle=1%.
f.
When CLAMP pin is turned on, maximum pulse width is limited to 1 μs, maximum duty cycle=2%.
g.
Maximum pulse width=5 μs, maximum duty cycle=10%.
Broadcom
-6-
ACPL-33JT
Data Sheet
Electrical Specifications
Table 7 Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Notes
Operating Temperature
TA
–40
125
°C
Input IC Supply Voltage
VCC1
4.5
5.5
V
a
Total Output IC Supply Voltage
VCC2 – VEE2
15.2
16.8
V
b
Input LED Turn on Current
IF(ON)
10
16
mA
Input LED Turn off Voltage (VAN–VCA)
VF(OFF)
–5.5
0.8
V
Maximum PWM Duty Cycle
DMAX
50
%
Input Pulse Width
tON(LED)
500
ns
a.
In most applications, VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the IGBT
gate. In applications where VCC2 is powered up first, it is important to ensure that the input remains low until VCC1 reaches the proper operating voltage
to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down).
b.
15.2V is the recommended minimum operating supply voltage (VCC2 – VEE2) to ensure adequate margin in excess of the maximum VUVLO+ threshold of 14.5V.
Electrical Specifications
Unless otherwise specified, all Minimum/Maximum specifications are at recommended operating conditions, all voltages at input
IC are referenced to VEE1, all voltages at output IC are referenced to VEE2. All typical values at TA = 25 °C, VCC1 = 5 V, VCC2 – VEE2 = 16 V.
Table 8 Electrical Specifications
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
DCDC Flyback Converter
VCC1 MOS Threshold
VCC1_MOSTH
0.4
1.2
1.7
V
IFAULT = 2.0 mA
VCC1 Turn on Threshold
VCC1_TH
3.7
4.0
4.3
V
VCC1 Turn on Threshold Hysteresis
VCC1_TH_HYS
0.05
0.3
0.5
V
PWM Switching Frequency
fPWM
100
150
190
kHz
Primary Gate Drive Rise Time
trPGD
3
16
40
ns
CPGD = 1 nF
Primary Gate Drive Fall Time
tfPGD
3
14
40
ns
CPGD = 1 nF
Maximum PWM Duty Cycle
DMAX
50
55
60
%
Regulated VCC2 Voltage
VCC2 – VEE2
15.2
16.0
16.8
V
VCC2 Over Voltage Protection
Threshold
VOV_TH
18.0
20.5
22.0
V
VCC2 Over Voltage Protection
Threshold Hysteresis
VOV_TH_HYS
0.4
0.8
1.2
V
4.7
6.2
mA
VCOMP = 0V
10
a
8
IC Supply Current
Input Supply Current
ICC1
Output Supply Current
ICC2
6.5
10.30
14.20
mA
IF = 0 mA
11
LED Forward Voltage
VF
1.25
1.55
1.85
V
IF = 10 mA
12
LED Reverse Breakdown Voltage
VBR
6.0
11
V
IF = 10 μA
Input Capacitance
CIN
90
pF
Logic Input and Output
Broadcom
-7-
b
ACPL-33JT
Data Sheet
Electrical Specifications
Table 8 Electrical Specifications (Continued)
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
LED Turn on Current Threshold
Low-to-High
ITH+
0.5
2.7
7.5
mA
VO= 5V
13
LED Turn on Current Threshold
High-to-Low
ITH-
0.3
2.3
7.0
mA
VO = 5V
13
LED Turn on Current Hysteresis
ITH_HYS
/FAULT Logic Low Output Current
IFAULT_L
/FAULT Logic High Output Current
IFAULT_H
/UVLO Logic Low Output Current
IUVLO_L
/UVLO Logic High Output Current
UVLO_H
I
0.4
4
4
Note
mA
10
20
mA
VFAULT = 0.4V
0.01
2
μA
VFAULT = 5V
10
20
mA
VUVLO = 0.4V
0.01
2
μA
VUVLO = 5V
-1.7
-0.5
A
VO = VCC2 – 3 V
14
A
VO = VEE2 + 2.5V
15
A
VO = VCC2 – 14V
c
A
VO = VEE2 + 14V
c
V
IO = –100 mA
d, e
Gate Driver
High Level Output Current
IOH
Low Level Output Current
IOL
High Level Peak Output Current
IOH_PEAK
Low Level Peak Output Current
IOL_PEAK
2
High Level Output Voltage
VOH
VCC2–0.5
Low Level Output Voltage
VOL
IF to High Level Output Propagation
Delay Time
tPLH
IF to Low Level Output Propagation
Delay Time
0.5
2.4
-2
VCC2–0.2
0.1
0.5
V
IO = 100 mA
50
115
250
ns
tPHL
50
150
300
ns
Rg = 10
16, 21
Cg = 10 nF
f = 10 kHz
16, 21
Duty Cycle = 50%
Pulse Width Distortion
PWD
-175
35
230
ns
h, i
Dead Time Distortion
DTD
-230
-35
175
ns
i, j
VO 10% to 90% Rise Time
tR
10
76
280
ns
VO 90% to 10% Fall Time
tF
10
41
280
ns
Output High Level Common Mode
Transient Immunity
|CMH|
30
>50
kV/s
TA=25°C,
IF =10 mA,
VCM = 1500V
23
k
Output Low Level Common Mode
Transient Immunity
|CML|
30
>50
kV/s
TA = 25°C,
IF = 0 mA,
VCM = 1500V
24
l
VSSD = 14V
17
f
g
Active Miller Clamp and Soft Shutdown
Low Level SSD Current During Fault
Condition
ISSDLF
90
150
210
mA
Clamp Threshold Voltage
VTH_CLAMP
1
2.1
3
V
Clamp Low Level Sinking Current
ICLAMP
0.5
2
VCC2 UVLO Threshold Low to High
VUVLO+
12
13.4
VCC2 UVLO Threshold High to Low
VUVLO-
10
VCC2 UVLO Hysteresis
VUVLO_HYS
1.6
A
VCLAMP =
VEE2+2.5V
14.5
V
VO > 5V
e m
11.3
12.5
V
VO < 5V
e, n
2.1
2.4
V
VCC2 UVLO Protection
Broadcom
-8-
,
ACPL-33JT
Data Sheet
Electrical Specifications
Table 8 Electrical Specifications (Continued)
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
VCC2 to UVLO High Delay
tPLH_UVLO
9
20
μs
30
o
VCC2 to UVLO Low Delay
tPHL_UVLO
7
20
μs
30
p
VCC2 UVLO to VOUT High Delay
tUVLO_ON
5
6.5
μs
30
q
VCC2 UVLO to VOUT Low Delay
tUVLO_OFF
1.1
2
μs
30
r
18
Desaturation Protection
Desat Sensing Threshold
VDESAT
6.65
7.0
7.35
V
Desat Charging Current
ICHG
0.8
1.0
1.2
mA
VDESAT = 0V,
VDESAT =6V
19
Desat Discharging Current
IDSCHG
19
60
106
mA
VDESAT = 7.5V
20
Desat Blanking Time
tDESAT(BLANKING)
0.3
0.6
0.9
μs
RSSD = 0 
Cg= 10 nF
30
s
Desat Sense to 90% VGATE Delay
tDESAT(90%)
0.05
0.2
0.5
μs
22, 30
t
Desat Sense to 10% VGATE Delay
tDESAT(10%)
0.5
1.2
2
μs
22, 30
u
Desat to Low Level FAULT Signal Delay
tDESAT(FAULT)
4.4
8
μs
v
Output Mute Time due to Desaturation tDESAT(MUTE)
3
7.5
12
ms
30
w
Time Input Kept Low Before Fault Reset tDESAT(RESET)
to High
3
7.5
12
ms
30
x
a.
PWM switching frequency of primary gate drive (PGD) is dithered in a range of ±6% typically over 3.3 ms.
b.
CIN is measured between pin 7 and pin 8 of the IC.
c.
Maximum pulse width=1 μs, maximum duty cycle=1%.
d.
Maximum pulse width = 1.0 ms, maximum duty cycle = 1%.
e.
Once VOH of ACPL-33JT is allowed to go high (VCC2 – VEE2 > VUVLO), the DESAT detection features of the ACPL-33JT will be the primary source of IGBT
protection. Once VCC2 exceeds VUVLO+ threshold, DESAT will remain functional until VCC2 is below VUVLO- threshold. Thus, the DESAT detection and UVLO
features of the ACPL-33JT work in conjunction to ensure constant IGBT protection.
f.
tPLH is defined as propagation delay from 50% of LED input IF to 50% of High level output.
g.
tPHL is defined as propagation delay from 50% of LED input IF to 50% of Low level output.
h.
Pulse Width Distortion (PWD) is defined as (tPHL – tPLH) of any given unit.
i.
As measured from IF to VO.
j.
Dead Time Distortion (DTD) is defined as (tPLH – tPHL) between any two ACPL-33JT under the same test conditions.
k.
Common mode transient immunity in the output high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to ensure that the output
remains in the high state (that is, VO > 14V). CMH specification is guaranteed by design and not subjected to production test.
l.
Common mode transient immunity in the output low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to ensure that the output
remains in the low state (that is, VO < 2.0V). CML specification is guaranteed by design and not subjected to production test.
m.
This is the “increasing” (that is, turn-on or “positive going” direction) of VCC2 – VEE2.
n.
This is the “decreasing” (that is, turn-off or “negative going” direction) of VCC2 – VEE2.
o.
The delay time when VCC2 exceeded UVLO+ threshold to 50% of /UVLO positive going edge.
p.
The delay time when VCC2 exceeded UVLO- threshold to 50% of /UVLO negative going edge.
q.
The delay time when VCC2 exceeded UVLO+ threshold to 50% of High level output.
r.
The delay time when VCC2 exceeded UVLO- threshold to 50% of Low level output.
s.
The delay time for ACPL-33JT to respond to a DESAT fault condition without any external DESAT capacitor.
t.
The amount of time from when DESAT threshold is exceeded to 90% of VGATE at mentioned test conditions.
u.
The amount of time from when DESAT threshold is exceeded to 10% of VGATE at mentioned test conditions.
v.
The amount of time from when DESAT threshold is exceeded to /Fault output Low – 50% of VCC1 voltage.
w.
The amount of time when DESAT threshold is exceeded, Output is mute to LED input.
x.
The amount of time when DESAT Mute time is expired, LED input must be kept Low for Fault status to return to High.
Broadcom
-9-
ACPL-33JT
Data Sheet
Thermal Resistance Model for ACPL-33JT
Table 9 Package Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Input-Output Momentary
Withstand Voltage
VISO
5000
Resistance (Input-Output)
RI-O
109
Capacitance (Input-Output)
CI-O
VRMS
RH < 50%, t = 1 min., TA = 25°C
1014

VI-O = 500 Vdc
0.8
pF
f = 1 MHz
Thermal Resistance Model for ACPL-33JT
The diagram for measurement is shown in Figure 4. This is a multi chip package with four heat sources, the effect of heating of one
die due to the adjacent dice are considered by applying the theory of linear superposition. Here, one die is heated first and the
temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the second die is heated and all the dice
temperatures are recorded and so on until the 4th die is heated. With the known ambient temperature, the die junction
temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in
matrix form. This yields a 4 by 4 matrix for our case of four heat sources.
Figure 4 Diagram of ACPL-33JT for Measurement
Broadcom
- 10 -
ACPL-33JT
Data Sheet
Thermal Resistance Model for ACPL-33JT
R11: Thermal Resistance of Die1 due to heating of Die1 (C/W)
P1: Power dissipation of Die1 (W)
R12: Thermal Resistance of Die1 due to heating of Die2 (C/W))
P2: Power dissipation of Die2 (W)
R13: Thermal Resistance of Die1 due to heating of Die3 (C/W))
P3: Power dissipation of Die3 (W)
R14: Thermal Resistance of Die1 due to heating of Die4 (C/W))
P4: Power dissipation of Die4 (W)
R21: Thermal Resistance of Die2 due to heating of Die1 (C/W)
R22: Thermal Resistance of Die2 due to heating of Die2 (C/W)
T1: Junction temperature of Die1 due to heat from all dice (0 °C)
R23: Thermal Resistance of Die2 due to heating of Die3 (C/W)
T2: Junction temperature of Die2 due to heat from all dice (0 °C)
R24: Thermal Resistance of Die2 due to heating of Die4 (C/W)
T3: Junction temperature of Die3 due to heat from all dice (0 °C)
R31: Thermal Resistance of Die3 due to heating of Die1 (C/W)
T4: Junction temperature of Die4 due to heat from all dice (0 °C)
R32: Thermal Resistance of Die3 due to heating of Die2 (C/W)
R33: Thermal Resistance of Die3 due to heating of Die3 (C/W)
Ta: Ambient temperature (°C)
R34: Thermal Resistance of Die3 due to heating of Die4 (C/W)
R41: Thermal Resistance of Die4 due to heating of Die1 (C/W)
R42: Thermal Resistance of Die4 due to heating of Die2 (C/W)
R43: Thermal Resistance of Die4 due to heating of Die3 (C/W)
R44: Thermal Resistance of Die4 due to heating of Die4 (C/W)
T1: Temperature difference between Die1 junction and ambient (°C)
T2: Temperature deference between Die2 junction and ambient (°C)
T3: Temperature difference between Die3 junction and ambient (°C)
T4: Temperature deference between Die4 junction and ambient (°C)
T1 = (R11 × P1 + R12 × P2 + R13 × P3 + R14 × P4) + Ta ---------------------- (1)
T2 = (R21 × P1 + R22 × P2 + R23 × P3 + R24 × P4) + Ta --------------------- (2)
T3 = (R31 × P1 + R32 × P2 + R33 × P3 + R34 × P4) + Ta --------------------- (3)
T4 = (R41 × P1 + R42 × P2 + R43 × P3 + R44 × P4 ) + Ta --------------------- (4)
Broadcom
- 11 -
ACPL-33JT
Data Sheet
Thermal Resistance Model for ACPL-33JT
Measurement is done on low effective thermal conductivity board according to JEDEC Standard 51-3 and on high effective thermal
conductivity board according to JEDEC Standard 51-7.
Table 10 Test Boards
Low effective thermal
conductivity board
Test Board
Conditions
Single layer board for
signal
Outer layer: 2 oz.
copper thickness
76 mm × 76 mm
Thermal Resistance
R11 = 138°C/W
R12 = 87°C/W
R13 = 67°C/W
R14 = 87°C/W
R21 = 89°C/W
R22 = 241°C/W
R23 = 81°C/W
R24 = 95°C/W
R31 = 73°C/W
R32 = 92°C/W
R33 = 117°C/W
R34 = 118°C/W
R41 = 86°C/W
R42 = 96°C/W
R43 = 111°C/W
R44 = 225°C/W
Power Dissipation Derating Chart
Figure 5 PowerDerating Chart Using Low Effective Thermal
Conductivity Board
700
P - Power Dissipation - mW
Test Board
PI, Input IC
600
PO, Output IC
500
400
300
200
100
0
0
25
50
75
100
Ta - Ambient Temperature - °C
125
150
NOTE


76 mm × 76 mm
4-layer board that
embodies two signal
layers, a power plane
and a ground plane
Outer layers: 2 oz.
copper thickness
Inner layers: 1 oz.
copper thickness
R11 = 78°C/W
R12 = 34°C/W
R13 = 23°C/W
R14 = 29°C/W
R21 = 37°C/W
R22 = 165°C/W
R23 = 32°C/W
R24 = 31°C/W
R31 = 24°C/W
R32 = 33°C/W
R33 = 59°C/W
R34 = 48°C/W
R41 = 32°C/W
R42 = 34°C/W
R43 = 51°C/WR
44 = 136°C/W
Figure 6 Power Derating Chart Using High Effective Thermal
Conductivity Board
700
P - Power Dissipation - mW
High effective thermal
conductivity board
Input IC power dissipation is derated linearly above 65°C from
150 mW to 60 mW at 125°C.
Output IC power dissipation is derated linearly above 65°C
from 600 mW to 150 mW at 125°C.
600
PI, Input IC
PO, Output IC
500
400
300
200
100
0
0
25
50
75
100
Ta - Ambient Temperature - °C
125
150
NOTE


Broadcom
- 12 -
Input IC power dissipation is derated linearly above 100°C
from 150 mW to 100 mW at 125°C.
Output IC power dissipation is derated linearly above 100°C
from 600 mW to 350 mW at 125°C.
ACPL-33JT
Data Sheet
Notes on Thermal Calculation
Notes on Thermal Calculation
Application and environmental design for ACPL-33JT needs to ensure that the junction temperature of the internal ICs and LED
within the gate driver optocoupler do not exceed 150°C. The following equations calculate the maximum power dissipation and
corresponding effect on junction temperatures and can only be used as a reference for thermal performance comparison under
specified PCB layout as shown above. The thermal resistance model shown here is not meant to and will not predict the
performance of a package in an application-specific environment.
Calculation of Input IC Power Dissipation, P1
Input IC Power Dissipation (P1) = PI(Static) + PI(PGD)
where
PI(Static) – Static power dissipated by the input IC = ICC1 × VCC1
PI(PGD) – Switching power dissipated in the PGD pin = (VCC1 × QG_ExtMOS × fPWM_DCDC) × RO(MAX) / (RO(MAX) + RG_PGD)
QG_ExtMOS – Gate charge of external MOSFET connected to PGD pin at supply voltage
fPWM_DCDC – DC-DC switching frequency
RO(MAX) – Maximum PGD pin output impedance = 0.3V / 50 mA = 6
RG_PGD – Gate resistance connected to PGD pin
Example:
PI(Static) = 6 mA × 5. 5V = 33 mW
PI(PGD) = (5.5V × 5 nC ×190 kHz) × 6/ (6+ 10) = 1.96 mW
P1 = 33 mW + 1.96 mW = 34.96 mW
Calculation of Input LED Power Dissipation, P2
Input LED Power Dissipation (P2) = IF(LED) (Recommended Max.) × VF(LED) (at 125°C) × Duty Cycle
Example:
P2 = 16 mA × 1.25V × 50% duty cycle = 10 mW
Calculation of Output IC Power Dissipation, P3
Output IC Power Dissipation (P3) = PO(Static) + PHS + PLS
where
PO(Static) – Static power dissipated by the output IC = ICC2 × VCC2
PHS – High side switching power dissipation at VO pin = (VCC2 × QG × fPWM) × ROH(MAX) / (ROH(MAX) + RGH) / 2
PLS – Low side switching power dissipation at VO pin = (VCC2 × QG × fPWM) × ROL(MAX) / (ROL(MAX) + RGL) / 2
QG – IGBT gate charge at supply voltage
fPWM – Input LED switching frequency
ROH(MAX) – Maximum high side output impedance – (VCC2 – VOH(MIN)) / IOH(MIN)
RGH – Gate charging resistance
ROL(MAX) – Maximum low side output impedance – VOL(MAX) / IOL(MIN)
RGL – Gate discharging resistance
Broadcom
- 13 -
ACPL-33JT
Data Sheet
Notes on Thermal Calculation
Example:
ROH(MAX) = (VCC2 – VOH(MIN)) / IOH(MIN) = 3.0V / 0.5A = 6.0
ROL(MAX) = VOL(MAX) / IOH(MIN) = 2.5V / 0.5A = 5.0
PHS = (16V × 1μC × 10 kHz) × 6.0/ (6.0+ 10) / 2 = 30 mW
PLS = (16V × 1 μC × 10 kHz) × 5.0/ (5.0+ 10) / 2 = 26.7 mW
P3 = 14.2 mA × 16V + 30 mW + 26.7 mW = 283.9 mW
Calculation of LED2 Power Dissipation, P4
LED2 Power Dissipation (P4) = IF(LED2) (Design Max.) × VF(LED2) (at 125°C) × Duty Cycle
Example:
P4 = 16 mA × 1.25V × 50% duty cycle = 10 mW
Calculation of Junction Temperature for High Effective Thermal Conductivity Board:
Input IC Junction Temperature = (78°C/W × P1 + 34°C/W × P2 + 23°C/W × P3 + 29°C/W × P4) + Ta
Input LED Junction Temperature = (37°C/W × P1 + 165°C/W × P2 + 32°C/W × P3 + 31°C/W × P4) + Ta
Output IC Junction Temperature = (24° C/W × P1 + 33°C/W × P2 + 59°C/W × P3 + 48°C/W × P4) + Ta
LED2 Junction Temperature = (32°C/W × P1 + 34°C/W × P2 + 51°C/W × P3 + 136°C/W × P4) + Ta
Broadcom
- 14 -
ACPL-33JT
Data Sheet
Printed Circuit Board Layout Considerations
Printed Circuit Board Layout Considerations
Care must be taken while designing the layout of printed circuit board (PCB) for optimum performance.
Adequate spacing should always be maintained between the high voltage isolated circuitry and any input referenced circuitry. The
same minimum spacing between two adjacent high-side isolated regions of the printed circuit board must be maintained as well.
Insufficient spacing will reduce the effective isolation and increase parasitic coupling that will degrade CMR performance.
The placement and routing of supply bypass capacitors requires special attention. During switching transients, the majority of the
gate charge is supplied by the bypass capacitors. Maintaining short bypass capacitor trace lengths will ensure low supply ripple
and clean switching waveforms.
Bypass capacitors should be placed closely in between these pins: VCC1 (pin 3) to VEE1 (pin 1) and VCC2 (pin 12) to VEE2 (pin 9).
Ground plane connections are necessary for VEE1 and VEE2 in order to achieve maximum power as the ACPL-33JT is designed to
dissipate the majority of heat generated through these pins. Actual power dissipation will depend on the application environment
(PCB layout, airflow, part placement, and so on).
Figure 7 PCB Layout Considerations
Ground plane (V EE1).
Bypass capacitor
between VCC1 and VEE1.
ACPL-33JT
Bypass capacitor
between VCC2 and VEE2.
Maintain sufficient
isolation to minimize
adjacent planes coupling.
Ground plane (V EE2 ).
Broadcom
- 15 -
ACPL-33JT
Data Sheet
Typical Performance Plots
Typical Performance Plots
Figure 9 ICOMP vs. Supply Voltage
Figure 8 PWM Duty Cycle vs. VCOMP
ICOMP - COMPENSATION CURRENT - μA
D - PWM DUTY CYCLE - %
60
50
40
30
20
10
10
-40°C
25°C
125°C
5
0
-5
-10
-15
0
0
1
2
3
10
4
12
14
VCOMP - COMPENSATION VOLTAGE - V
Figure 10 ICC1 vs. Temperature
20
22
13
ICC2 - OUTPUT SUPPLY CURRENT - mA
5.5
ICC1 - INPUT SUPPLY CURRENT - mA
18
Figure 11 ICC2 vs. Temperature
6
5
4.5
4
3.5
12
11.5
11
10.5
10
9.5
9
-50
-25
0
25
50
TA - TEMPERATURE - qC
75
100
125
-50
-25
0
25
50
75
100
125
TA - TEMPERATURE - qC
Figure 12 IF vs. VF
Figure 13 ITH vs. Temperature
4
100.00
ITH - LED CURRENT THRESHOLD - mA
Ta = 25 °C
10.00
1.00
0.10
0.01
ICC2L
ICC2H
12.5
3
IF - FORWARD CURRENT - mA
16
VCC2 - SUPPLY VOLTAGE - V
3
2.5
2
1.5
1
1.2
1.3
1.4
1.5
VF - FORWARD VOLTAGE - V
1.6
Broadcom
- 16 -
ITH+
ITH-
3.5
-50
-25
0
25
50
TA - TEMPERATURE - qC
75
100
125
ACPL-33JT
Data Sheet
Typical Performance Plots
Figure 14 VOH vs. IOH
Figure 15 VOL vs. IOL
8
25°C
-40°C
125°C
14
25°C
-40°C
125°C
7
VOL - OUTPUT LOW VOLTAGE - V
VOH - OUTPUT HIGH VOLTAGE - V
16
12
10
6
5
4
3
2
1
8
0
1
2
3
4
0
5
0
1
IOH - OUTPUT HIGH CURRENT - A
Figure 16 TP vs. Temperature
200
150
100
50
180
160
140
120
100
80
60
-25
0
25
50
75
TA - TEMPERATURE - qC
100
125
-40°C
25°C
125°C
40
20
0
0
-50
5
200
TPLH
TPHL
IF=13mA
4
Figure 17 ISSD vs. VSSD
ISSD - LOW LEVEL SOFT SHUTDOWN CURRENT
DURING FAULT CONDITION - mA
TP - OUTPUT PROPAGATION DELAY - ns
250
2
3
IOL - OUTPUT LOW CURRENT - A
0
2
4
6
8
10
VSSD - SSD VOLTAGE - V
Broadcom
- 17 -
12
14
16
ACPL-33JT
Data Sheet
Typical Performance Plots
Figure 18 VDESAT Threshold vs. Temperature
Figure 19 ICHG vs. Temperature
-0.9
ICHG - DESAT CHARGING CURRENT - mA
VDESAT - DESAT SENSING THRESHOLD - V
7.3
7.2
7.1
7
6.9
6.8
6.7
-50
-25
0
25
50
75
TA - TEMPERATURE - qC
100
125
100
125
IDSHG - DESAT DISCHARGING CURRENT - mA
100
90
80
70
60
50
40
30
-50
-25
0
25
50
TA - TEMPERATURE - qC
75
-1
-1.05
-1.1
-50
Figure 20 IDSCHG vs. Temperature
20
-0.95
Broadcom
- 18 -
-25
0
25
50
75
TA - TEMPERATURE - qC
100
125
ACPL-33JT
Data Sheet
Typical Performance Plots
Figure 21 Propagation Delay Test Circuit
VEE1
VEE2
PGD
LED2+
VCC1
DESAT
COMP
SSD
/UVLO
VCC2
VO
/FAULT
IF
AN
CLAMP
CA
VEE2
IF
1PF R
g
VO
10Ω
V Gate
+
_
Cg
10nF
t PLH
16V
Vo
ACPL-33JT
Figure 22 tDESAT(90%) and tDESAT(10%) Test Circuit
5V
10kΩ
_
+
VEE1
1PF
10kΩ
260Ω
VEE2
PGD
LED2+
VCC1
DESAT
COMP
SSD
/UVLO
VCC2
/FAULT
VO
AN
CLAMP
CA
VEE2
V DESAT
R SSD
0Ω
1PF R
g
VO
10Ω
V Gate
Cg
10nF
ACPL-33JT
Broadcom
- 19 -
+
_
16V
50%
t PHL
ACPL-33JT
Data Sheet
Typical Performance Plots
Figure 23 CMR VO High Test Circuit
PGD
VEE2
LED2+
VCC1
DESAT
VEE1
COMP
SSD
/UVLO
VCC2
130Ω
4.5V
+
_
1PF
Scope
VO
/FAULT
AN
CLAMP
CA
VEE2
10Ω
10nF
+
_
130Ω
ACPL-33JT
_
+
High Voltage Pulse
V CM =1500V
Figure 24 CMR VO Low Test Circuit
130Ω
VEE1
VEE2
PGD
LED2+
VCC1
DESAT
COMP
SSD
/UVLO
VCC2
/FAULT
VO
AN
CLAMP
CA
VEE2
1PF
Scope
10Ω
10nF
+
_
16V
130Ω
ACPL-33JT
+
_
High Voltage Pulse
V CM =1500V
Broadcom
- 20 -
16V
ACPL-33JT
Data Sheet
Typical Performance Plots
Table 11 Internal Connection Equivalent Circuits
Pin No.
Pin Name
Equivalent Circuits
Note
Input Common/GND
1
VEE1
1
2
PGD
VCC1
5V MOS
CONTROL
5V ESD
2
5V ESD
5V MOS
3
VCC1
3
5V ESD
COMP
5V MOS
4
RES
5V ESD
5V MOS
VCC1
5V MOS
VBIAS
5
RES
5V ESD
5V MOS
6
/FAULT
6
CONTROL
/UVLO
RES
5V ESD
5V MOS
CONTROL
5
Broadcom
- 21 -
5
CHARGE
PUMP
4
ACPL-33JT
Data Sheet
Typical Performance Plots
Table 11 Internal Connection Equivalent Circuits (Continued)
Pin No.
7, 8
Pin Name
Input LED
7 – Anode
8 – Cathode
9
VEE2
10
CLAMP
Equivalent Circuits
7
LED
8
Output Common
9
High Voltage Diode
10
CONTROL
High Voltage
ESD
DMOS
11
VO
VEE2
VCC2
DMOS
DRIVER
Body Diode
11
Body Diode
DMOS
12
VEE2
VCC2
12
High Voltage
ESD
13
Note
VEE2
SSD
VCC2
High Voltage
ESD
13
CONTROL
High Voltage
ESD
DMOS
VEE2
Broadcom
- 22 -
ACPL-33JT
Data Sheet
Typical Performance Plots
Table 11 Internal Connection Equivalent Circuits (Continued)
Pin No.
14
Pin Name
Equivalent Circuits
Note
DESAT
DMOS
High Voltage
ESD
VBIAS
RES
VCC2
RES
14
RES
CONTROL
High Voltage
ESD
VBIAS
DMOS
15
LED2+
VCC2
DMOS
CONTROL
VBIAS
RES
5V MOS
16
VEE2
VEE2
5V
ESD
15
LED
VEE2
Output Common
16
Broadcom
- 23 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Typical Application/Operation
Introduction to Fault Detection and Protection
The power stage of a typical three-phase inverter is susceptible to several types of failures, most of which are potentially
destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase or rail supply short circuits
due to user misconnect or bad wiring; control signal failures due to noise or computational errors; overload conditions induced by
the load; and component failures in the gate drive circuitry. Under any of these fault conditions, the current through the IGBTs can
increase rapidly, causing excessive power dissipation and heating. The IGBTs become damaged when the current load approaches
the saturation current of the device, and the collector-to-emitter voltage rises from saturation region to desaturation (active)
region. The drastically increased power dissipation very quickly overheats the power device and destroys it. To prevent damage to
the drive, fault protection must be implemented to reduce or turn off the over current during a fault condition.
A circuit providing fast local fault detection and shutdown is an ideal solution, but the number of required components, board
space consumed, cost, and complexity have until now limited its use to high performance drives. The features that this circuit must
have are high speed, low cost, low resolution, low power dissipation, and small size.
The ACPL-33JT satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between
the input and output, local IGBT desaturation detection and shutdown, and optically isolated fault and UVLO status feedback signal
into a single 16-pin surface mount package.
The fault detection method, which the ACPL-33JT has adopted, is to monitor the saturation (collector) voltage of the IGBT and to
trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device
slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach
destructive levels, the IGBT is shut off. During the off-state of the IGBT, the fault detect circuitry is simply disabled to prevent false
‘fault’ signals.
The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the
power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By
directly measuring the collector voltage, the ACPL-33JT limits the power dissipation in the IGBT, even with insufficient gate drive
voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored,
while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly
conservative over current threshold is not needed to protect the IGBT.
Typical Application Circuit
The ACPL-33JT has non-inverting gate control inputs, an open collector fault, and UVLO outputs suitable for wired ‘OR’ applications.
The application circuit shown in Figure 25 illustrates a typical gate drive implementation using the ACPL-33JT.
The two supply bypass capacitors (1 μF and 20 μF) provide filtering and the large transient currents necessary during a switching
transition. The Desat diode and 220 pF blanking capacitor are the necessary external components for the fault detection circuitry.
The gate resistor (RG_ON and RG_OFF) serves to limit gate charge and discharge current and indirectly controls the IGBT collector
voltage rise and fall times. The open collector fault and UVLO outputs have a passive 10 k pull-up resistor and a 330 pF filtering
capacitor.
Broadcom
- 24 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Figure 25 Typical Application Circuit with External Components
MBRS1100
Vin* = 6V – 24V
22nF
Ls
Lp
360Ω
Regulated V CC2 = 16V
10uF
20uF
TX1
MBRS1100
DC/DC
Q1
BUK98150-55A
10Ω
200kΩ
DC +5V
10K Ω
150pF
22nF
1uF
10K Ω
uC
330pF 330pF
IF
130Ω
130Ω
VEE1
VEE2
PGD
LED2+
VCC1
DESAT
COMP
SSD
/UVLO
VCC2
/FAULT
VO
AN
CLAMP
CA
VEE2
HV
R G_ON
220pF
MURA160T3
1kΩ
C
PBSS4041NX
G
10Ω
IGBT
1uF
10Ω
PBSS4041PX
E
50Ω
ACPL-33JT
R G_OFF
PBSS4041PX
50Ω
PBSS4041PX
NOTE
Component value subject to change with varying application requirements. *Vin range is dependent on
transformer design.
Operation of Integrated Flyback Controller
The primary control block implements direct duty cycle control logics for line and load regulation. The primary gate drive (PGD) pin
is connected to external MOSFET to switch the primary winding current. Secondary output voltage VCC2 is sensed and fed back to
the primary control circuits. VCC2 over voltage can be detected and the primary gate is turned off to protect secondary overvoltage
failure. The maximum PWM duty cycle is designed to be around 55% to ensure discontinuous operation mode under a high load
condition. For a complete isolated DC-DC converter, connect a discrete transformer to ACPL-33JT, as in Figure 25. Keep the LED off
when you are powering up VCC1. To ensure proper operation of the DC-DC converter, a fast VCC1 rise time (≤ 5 ms) is preferred for a
soft start function to control the inrush current.
The average PWM switching frequency of the primary gate drive (PGD) is dithered typically in a range of ±6%, typically over 3.3 ms.
This frequency dithering feature helps to achieve better EMI performance by spreading the switching and its harmonics over a
wider band.
Reference DC-DC Circuit
Figure 25 shows a reference circuit for DC-DC flyback conversion including the compensation network at pin 4, COMP. This
compensation network is referenced to a nominal transformer of Lp = 7 μH, Ls=86 μH. For Vin = 6V to 24V, this circuit will nominally
support a secondary-side load of up to 90 mA (including ICC2) at the regulated VCC2 voltage.
Users must further characterize the DC-DC flyback conversion across their target operating conditions and chosen components to
ensure that the required load can be supported.
Broadcom
- 25 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Soft Start Operation
ACPL-33JT is designed with built-in soft start feature. Once VCC1 is higher than VCC1_TH, the built-in soft start circuit starts to
function. Typical soft start timing is 10.5 ms, where a typical 3 μA soft start current (ICOMP) charges up the compensation network
through the VCOMP pin and gradually increases the VCOMP voltage to the correct working level. IC exits soft start after 10.5 ms and
goes into the transition period, where ICOMP is increased to typical 6 μA for 3.3 ms. Following that, IC goes into normal regulation
where ICOMP is increased to typical 10 μA. The soft start feature helps to reduce the inrush current. See Figure 26 for VCC1 and VCC2
start up profiles.
Figure 26 Operation of Integrated DCDC Flyback Controller
V CC1 (V)
5
V CC1_TH
Time
V SAW (V)
4.0
2.625
V COMP (V) 1.25
Time
Typical soft start time=10.5ms
5
V PGD (V)
0
Time
16
V CC2 (V)
0
NOTE
Time
VSAW is IC internal signal and cannot be measured externally.
Power Up Behavior
Figure 27 describes the power up behavior of typical application circuit showed in Figure 25. The power up behavior of ACPL-33JT
can be divided into three regions:



Non operation region where VCC1 is less than VCC1_MOSTH of 1.2V typical.
Initial operation region where VCC1 is more than typical 1.2V and less than VCC1_TH voltage. At this region, ACPL-33JT
acknowledges VCC1 is below the VCC1_TH, and pulls the UVLO and Fault pins Low.
Active operation region where VCC1 exceeds VCC1_TH. The primary gate drive (PGD) starts to work and regulates VCC2 to the
typical 16V. The fault pin will be released from the initial pull down; the UVLO pin will continue to be pulled down until VCC2
reaches the UVLO+ threshold.
Broadcom
- 26 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Figure 27 Power Up Behavior of Typical Circuit
5
V CC1 (V)
V CC1_TH
V CC1_MOSTH
Time
1
V /FAULT (V)
2
3
5
Time
V /UVLO (V)
5
Time
16
V CC2 (V)
V UVLO+
0
Time
Output Control and Status Flags
The outputs (VO, SSD, /FAULT and /UVLO) of the ACPL-33JT are controlled by the combination of VCC1, VCC2, input LED current (IF)
and IGBT desaturation condition. The following table shows the logic truth table for these outputs.
Table 12 ACPL-33JT Output Control
Input
Output
Conditions
VCC1
VCC2
IF
VO
Desat
SSD
/FAULT
/UVLO
VCC1 Under Voltage
Low
High
Low
Low
Low
High-Z
Low
Low
Low
High
High
Low
High
High-Z
Low
Low
VCC2 UVLO
Low
Low
X
X
Low
High-Z
Low
Low
High
Low
X
X
Low
High-Z
High
Low
Low
High
Low
High
Low
High-Z
Low
Low
Low
High
High
High
High-Z
Low
Low
Low
High
High
Low
High
Low
High-Z
High
High
High
High
High
High
High-Z
Low
Low
High
High
High
Low
Low
Low
High-Z
High
High
High
High
High
Low
High
High-Z
High
High
Over Current (Desaturation)
Normal switching
NOTE
The logic level is defined by the respective threshold of each function pin. VCC1 logic threshold refers to VCC1_TH.
/FAULT and /UVLO pins are pulled up with a 10 k resistor.
Broadcom
- 27 -
ACPL-33JT
Data Sheet
Typical Application/Operation
DESAT Fault Detection Blanking Time
After the IGBT is turned on, the DESAT fault detection circuitry must remain disabled for a short time period to allow the collector
voltage to fall below the DESAT threshold. This time period, called the total DESAT blanking time, is controlled by the both internal
DESAT blanking time tDESAT(BLANKING) and external blanking time, determined by the internal charge current, the DESAT voltage
threshold, and the external DESAT capacitor.
The total blanking time is calculated in terms of internal blanking time (tDESAT(BLANKING)), external capacitance (CBLANK), FAULT
threshold voltage (VDESAT), and DESAT charge current (ICHG) as:
Total DESAT blanking time, tBLANK = tDESAT(BLANKING) + CBLANK × VDESAT / ICHG
Description of Gate Driver and Miller Clamping
The gate driver is directly controlled by the LED current. When LED current is driven high the output of ACPL-33JT is capable of
delivering 2.5 A sourcing current to drive the IGBT’s gate. While LED is switched off the gate driver can provide 2.5A sinking current
to switch the gate off fast. Additional miller clamping pull-down transistor is activated when output voltage reaches about 2V with
respect to VEE2 to provide low impedance path to miller current as shown in Figure 28.
Figure 28 Gate Drive Signal Behavior
IF
VO
VGATE
Miller Clamp Threshold: 2V above V EE2
Description of Under Voltage Lock Out
Insufficient gate voltage to IGBT can increase turn on resistance of IGBT, resulting in large power loss and IGBT damage due to high
heat dissipation. ACPL-33JT monitors the output power supply constantly. When output power supply is lower than under voltage
lockout (UVLO) threshold gate driver output will shut off to protect IGBT from low voltage bias. During power up, the UVLO feature
forces the QCPL33JT’s output low to prevent unwanted turn-on at lower voltage.
Broadcom
- 28 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Figure 29 Circuit Behaviors at Power Up and Power Down
VCC1
VCC1_TH
VCC2
VUVLO -
VUVLO+
tUVLO_OFF
tUVLO_ON
LED I F
VO
/FAULT
/UVLO
tPHL_UVLO
tPLH_UVLO
Description of Over-Voltage Protection
If VCC2 is greater than the VCC2 Over-Voltage Protection threshold, the primary gate drive (PGD) pin on the primary side shuts
down and the DC-DC flyback conversion is stopped. Once VCC2 goes below the VCC2 over-voltage protection threshold, the primary
gate drive (PGD) starts to regulate again. There is no feedback status for this protection feature.
During a Short Circuit
1.
DESAT terminal monitors IGBT’s VCE voltage.
2.
When the voltage on the DESAT terminal exceeds 7V, the IGBT gate voltage (VGATE) is slowly lowered by soft shutdown (SSD)
pin. Output driver, VO enters into high impedance state.
3.
Output driver VO ignores all PWM commands during mute time (tDESAT(MUTE)).
4.
/FAULT output goes low, notifying the microcontroller of the fault condition.
5.
Microcontroller takes appropriate action.
6.
When tDESAT(MUTE) expires, the LED input need to be kept low for tDESAT(RESET) before fault condition can be cleared. /FAULT
status will return to high and SSD output will return to high impedance state.
7.
Output (VO) starts to respond to LED input after fault condition is cleared.
Broadcom
- 29 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Figure 30 Circuit Behaviors During Desaturation Event
tDESAT(RESET)
IF
tPHL
tPLH
Hi -Z
50%
V O state
SSD state
Clamp state
Hi -Z
SSD
tDESAT
Hi -Z
Clamp
Hi -Z
Hi -Z
(90%)
V GATE
V DESAT_TH
tDESAT(10%)
V DESAT
tDESAT (BLANKING)
V /FAULT
50%
tDESAT
(MUTE)
tDESAT (/FAULT)
Broadcom
- 30 -
Clamp
ACPL-33JT
Data Sheet
Typical Application/Operation
Additional Application Information on Isolated DC-DC Converter
The flyback converter uses direct duty cycle control in discontinuous mode. The output voltage is fed back through integrated
optocoupler as shown in Figure 31.
Figure 31 IGBT Gate Driver with Integrated Flyback Controller
X1
Vin
D3
D2
VCC2
C1
D1
DC/DC
Msw
PGD
VCC1
R1
Vbus+
VCOMP
R2
Rs
LED2
VCC2
Cs
Q1
DGND
LED1
C2
ACPL-33JT
VEE2
Q2
Vbus-
A few immediate benefits of this topology can be observed.




Output voltage is regulated gate by gate with integrated feedback.
Isolation boundary is well aligned with gate driver resulting concise PCB layout.
Primary gate is used to switch the external MOS (MSW) and this provides flexibility in power design.
Less discrete components are used and easy to design.
Feedback Control Loop
Isolated flyback converter is essentially a feedback control loop, whose loop dynamics must be carefully designed to ensure loop
stability.
Figure 32 shows a detailed block diagram of Broadcom’s isolated flyback converter architecture.
The feedback loop can be broken at duty cycle control voltage node VCOMP. The forward path includes path from VCOMP to VCC2.
The feedback path includes path from VCC2 to VCOMP..
Broadcom
- 31 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Figure 32 Block Diagram of Broadcom’s Isolated Flyback Converter
“flyback”
VCC2
Vin
Rco
Csn
Rsn
Cin
Co
Lp
Ls
Vsw
DC/DC
Msw
PGD
VCC2
Flyback Controller
Block Diagram
Ramp Gen
VCC1
U1
fPWM =150kHz
Icp
Feedback
Decoder
Photodiode
Amplifier
VCC2S
VCOMP
U2
Soft
Start
Rs
Cp
R1
R2
Feedback
Encoder
Cs
- Icp
Ramp Gen
fS =185kHz
Feedback Propagation Delay from VCC2 to VCOMP
If total propagation delay from VCC2 to the charge pump switches is , the feedback block diagram can be simplified as a zero delay
PWM generator circuit whose output is the ICOMP current and a digital delay (transport delay) block.
Figure 33 Simplified Block of Total Feedback Delay from VCC2 to VCOMP
VCC2
Transport Delay
PWM
“Zero delay”
τ
Delay
ICOMP
Delay = τ
Equivalent small signal model of feedback GM is H_FBGM (s) = gm / ((s + 1) / ))
Where gm is the transconductance gain from VCC2 to Charge Pump Output and  is the propagation delay.
In S-domain, transport delay is transformed to the following Laplace transform, H(S) = e-st. If t is small compared to the loop
bandwidth of interest, then e-st ≈ 1 / (s + 1 / ). This is true and good approximation if the PWM frequency is also >> Loop
Bandwidth.
From simulation, the propagation delay is in the 0.5 μs range and therefore the equivalent pole added to the system is the MHz
region which is many orders higher than the design loop bandwidth. The effects of this high order pole for purpose of phase and
gain margin can therefore be safely ignored.
Broadcom
- 32 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Description of Charge Pump Circuit Block
Figure 34 shows the charge pump circuit block. The net output current of the COMP pin is determined by the turn-on duty
difference of SW1 and SW2. If the duty of SW1 and SW2 is 50% each, there will be zero net ICOMP.
Figure 34 Charge Pump Circuit Block
PGD
Isolation
Comparator &
PG Drive
V COMP
ICOMP
RS
CP
Feedback
Decoder
SW1
Feedback
signal_Iso
13.3V
SW2
+
CS
-
+
_
COMP
VCC2_ISO
Table 13 Simulation of Key Parameters in the Feedback GM Path
Parameter
Min.
Typ.
Max.
Units
Simulation Conditions
Feedback Propagation Delay
387
450
540
ns
Wafer process corner simulation for –40 °C ≤ TJ ≤ 150 °C
Feedback GM, (Icomp/VCC2)
–0.772
–1.17
–1.75
μA/V
Wafer process corner simulation for –40 °C ≤ TJ ≤ 150 °C
Feedback Resistor Ratio
0.163
0.164
0.165
—
Wafer process corner simulation with ± 3sigma
Feedback Ramp Generator Saw Tooth
Frequency
159
185
209
kHz
Wafer process corner simulation for –40 °C ≤ TJ ≤ 150 °C
Loop Bandwidth and Phase Margin
The close loop feedback control system can be represented in small signal model as shown in Figure 35.
Figure 35 Small Signal Model of Flyback Converter Loop
Broadcom
- 33 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Close loop bandwidth and phase margin can be easily found out by running AC simulation on this circuit. Table 14 shows an
example of AC simulation result.
Table 14 Close Loop Bandwidth and Phase Margin Simulation. Conditions Rs = 200 kOhm, Cs = 22 nF, Cp = 100 pF
GM
R_Ratio
Vin
Ro
Vin
kOhm
Corner
μA/V
Loop
Phase
Band
Margin
Width
Hz
degree
Vbg
eff
Lp
fs
Vcc2
Io
Gtrxm
Gcomp
V
%
uH
kHz
V
mA
A/V
μA/V
Tj =- 40°C
Fast
Plot#1
Plot#2
–1.75 0.164
8
1.6
123
40.7
2.75
75%
7
150
16
10
0.0435
–10.67
–1.75 0.164
8
0.125 419
90.7
2.75
75%
7
150
16
128
0.1555
–10.67
–1.75 0.164
12
1.6
182
40.5
2.75
75%
7
150
16
10
0.0652
–10.67
–1.75 0.164
12
0.125 649
82.6
2.75
75%
7
150
16
128
0.2332
–10.67
–1.75 0.164
18
1.6
273
40.9
2.75
75%
7
150
16
10
0.0978
–10.67
–1.75 0.164
18
0.125 945
84.5
2.75
75%
7
150
16
128
0.3499
–10.67
–1.17 0.164
8
1.6
40.7
2.75
75%
7
150
16
10
0.0435
–7.13
–1.17 0.164
8
0.125 282
93.9
2.75
75%
7
150
16
128
0.1555
–7.13
–1.17 0.164
12
1.6
121
40.7
2.75
75%
7
150
16
10
0.0652
–7.13
–1.17 0.164
12
0.125 414
90.7
2.75
75%
7
150
16
128
0.2332
–7.13
–1.17 0.164
18
1.6
40.6
2.75
75%
7
150
16
10
0.0978
–7.13
–1.17 0.164
18
0.125 628
83
2.75
75%
7
150
16
128
0.3499
–7.13
–0.772 0.164
8
1.6
40.7
2.75
75%
7
150
16
10
0.0435
–4.71
–0.772 0.164
8
0.125 182
97
2.75
75%
7
150
16
128
0.1555
–4.71
–0.772 0.164
12
1.6
40.7
2.75
75%
7
150
16
10
0.0652
–4.71
–0.772 0.164
12
0.125 279
93.3
2.75
75%
7
150
16
128
0.2332
–4.71
–0.772 0.164
18
1.6
120
40.6
2.75
75%
7
150
16
10
0.0978
–4.71
–0.772 0.164
18
0.125 414
90.7
2.75
75%
7
150
16
128
0.3499
–4.71
Tj = 25°C
Typical
Plot#3
Plot#4
86
182
Tj=150°C
Slow
Plot#5
Plot#6
60
84
Where
GM:
Feedback transconductance = Icomp/VCC2 (Design value)
R_Ratio
Feedback resistor ratio = R2 / (R1 + R2)
Vin:
Input voltage supply
Ro:
Load resistor
Vbg:
Vcomp (Design value)
Lp:
Primary inductance
eff:
Efficiency (Assumption)
fs:
Switching frequency
Gcomp:
GM/R_Ratio
VCC2:
Regulated output voltage
Gtrxm:
Transconductance from Vcomp to :
Io = Vin/Vbg × (eff/(2 × Lp × fs × Ro))1/2
Io:
Output load current = VCC2 / Ro
Broadcom
- 34 -
ACPL-33JT
Data Sheet
Typical Application/Operation
Bode Plots of AC Simulation Result
Figure 36 Bode Plots for Fast Corner at Tj = –40°C, GM = 1.75 μA/V, Vin = 18V
Plot#2
945Hz, 84.5q
Plot#1
273Hz, 40.9q
Figure 37 Bode Plots for Typical Corner at Tj = 25°C, GM = 1.17 μA/V, Vin = 12V
Plot#4
414Hz, 90.7q
Plot#3
121Hz, 40.7q
Broadcom
- 35 -
Figure 38 Bode Plots for Slow Corner at Tj = 150°C, GM = 0.772 μA/V, Vin = 8 V
Plot#6
182Hz, 97q
Plot#5
60Hz, 40.7q
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site: www.broadcom.com.
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and the A logo are among the trademarks of Broadcom and/or its affiliates in the
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Copyright © 2016 by Broadcom. All Rights Reserved.
The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. For
more information, please visit www.broadcom.com.
Broadcom reserves the right to make changes without further notice to any
products or data herein to improve reliability, function, or design.
Information furnished by Broadcom is believed to be accurate and reliable.
However, Broadcom does not assume any liability arising out of the application
or use of this information, nor the application or use of any product or circuit
described herein, neither does it convey any license under its patent rights nor
the rights of others.
pub-005535 – December 5, 2016