Maxim MAX1011 Low-power, 90msps, 6-bit adc Datasheet

19-1335; Rev 0a; 2/98
KIT
ATION
EVALU
E
L
B
AVAILA
Low-Power, 90Msps, 6-Bit ADC
Features
♦ High Sampling Rate: 90Msps
The MAX1011’s input amplifier features a true differential
input, a -0.5dB analog bandwidth of 55MHz, and a userprogrammable input full-scale range of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled signal,
input offset is typically less than 1/4LSB. Dynamic performance is 5.85 effective number of bits (ENOB) with a
20MHz analog input signal, or 5.7 ENOB with a 50MHz
signal.
♦ Internal Bandgap Voltage Reference
The MAX1011 operates with +5V analog and +3.3V digital supplies for easy interfacing to +3.3V-logic-compatible
digital signal processors and microprocessors. It comes
in a 24-pin QSOP package.
♦ Single-Ended or Differential Input Drive
♦ Low Power Dissipation: 215mW
♦ Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
♦ ±1/4LSB INL and DNL (typ)
♦ ±1/4LSB Input Offset (typ)
♦ Internal Oscillator with Overdrive Capability
♦ 55MHz (-0.5dB) Bandwidth Input Amplifier with
True Differential Input
♦ User-Selectable Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
♦ Flexible, 3.3V, CMOS-Compatible Digital Outputs
Applications
IF Sampling Receivers
VSAT Receivers
Wide Local Area Networks (WLANs)
Instrumentation
Ordering Information
PART
TEMP. RANGE
MAX1011CEG
0°C to +70°C
PIN-PACKAGE
24 QSOP
Pin Configuration appears at end of data sheet.
Functional Diagram
OCC+
OCC-
IN+
IN-
ADC
INPUT
AMP
6
DATA
BUFFER
VREF
OFFSET
CORRECTION
GAIN
6
CLOCK
OUT
BANDGAP
REFERENCE
CLOCK
DRIVER
D0–D5
DCLK
TNK+
TNK-
MAX1011
________________________________________________________________ Maxim Integrated Products
1
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For small orders, phone 408-737-7600 ext. 3468.
MAX1011
General Description
The MAX1011 is a 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal reference, and a clock oscillator. The ADC converts analog
signals into binary-coded digital outputs at sampling
rates up to 90Msps. The ability to directly interface with
baseband signals makes the MAX1011 ideal for use in
a wide range of communications and instrumentation
applications.
MAX1011
Low-Power, 90Msps, 6-Bit ADC
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..........................................................-0.3V to +6.5V
VCCO to OGND......................................................-0.3V to +6.5V
GND to OGND ......................................................-0.3V to +0.3V
Digital and Clock Output Pins to OGND...-0.3V to VCCO (10sec)
All Other Pins to GND...............................................-0.3V to VCC
Continuous Power Dissipation (TA = +70°C)
24-Pin QSOP (derate 10mW/°C above +70°C)...........800mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
RES
6
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
No missing codes over temperature
VFSH
Full-Scale Input Range
Bits
-0.5
±0.25
0.5
LSB
-0.5
±0.25
0.5
LSB
GAIN = VCC (high gain)
118.75
125
131.25
VFSM
GAIN = open (mid gain)
237.5
250
262.5
VFSL
GAIN = GND (low gain)
475
500
525
mVp-p
INVERTING AND NONINVERTING ANALOG INPUTS
Input Open-Circuit Voltage
VAOC
2.25
2.35
2.45
V
Input Resistance
RIN
13
20
29
kΩ
Input Capacitance
CIN
Guaranteed by design
1.5
3
pF
Common-Mode Voltage Range
VCM
Other analog input driven with external source
(Note 2)
1.75
2.75
V
ROSC
Other oscillator input tied to VCC + 0.3V
4.8
12.1
kΩ
Digital Outputs Logic-High
Voltage
VOH
ISOURCE = 50µA
Digital Outputs Logic-Low
Voltage
VOL
ISINK = 400µA
OSCILLATOR INPUTS
Oscillator Input Resistance
8
DIGITAL OUTPUTS (D0–D5)
0.7VCCO
V
0.5
V
POWER SUPPLY
Supply Current
Power-Supply Rejection Ratio
Digital Outputs Supply Current
Power Dissipation
2
37
63.5
mA
PSRR
ICC
VCC = 4.75V to 5.25V (Note 3)
-65
-40
dB
ICCO
20MHz, full-scale analog inputs,
CL = 15pF (Note 4)
8.5
13.8
mA
PD
215
_______________________________________________________________________________________
mW
Low-Power, 90Msps, 6-Bit ADC
(VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), VIN = 20MHz sine, amplitude -1dB below
full scale, unless otherwise noted.)
Maximum Sample Rate
fMAX
Analog Input -0.5dB Bandwidth
BW
90
GAIN = GND, open, VCC
GAIN = open (mid gain)
Input Offset (Note 5)
5.6
GAIN = open (mid gain), fIN = 50MHz,
-1dB below full scale
5.7
ENOBH
ENOBL
GAIN = VCC (high gain)
GAIN = GND (low gain)
5.8
5.85
SINAD
GAIN = open (mid gain)
35.5
Guaranteed by design
-0.5
OFF
MHz
5.85
ENOBM
Effective Number of Bits
Signal-to-Noise Plus Distortion
Ratio
Msps
55
Bits
37
dB
0.5
LSB
TIMING CHARACTERISTICS (Data outputs: RL = 1MΩ, CL = 15pF)
Clock to Data Propagation
Delay
tPD
(Note 6)
Data Valid Skew
tSKEW
(Note 6)
Input to DCLK Delay
tDCLK
TNK+ to DCLK (Note 6)
Figure 8
5.5
ns
1
clock
cycle
Aperture Delay
Pipeline Delay
tAD
PD
Figure 8
3.0
ns
1
ns
4.5
ns
Note 1: Best-fit straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this commonmode input range (Figures 4 and 5).
Note 3: PSRR is defined as the change in the mid-gain, full-scale range as a function of the variation in V CC supply voltage,
expressed in decibels.
Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply transients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the digital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at compensation inputs (Figures 2 and 3).
Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. tDCLK is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capacitive load on the outputs is 15pF.
_______________________________________________________________________________________
3
MAX1011
AC ELECTRICAL CHARACTERISTICS
__________________________________________Typical Operating Characteristics
(VCC = +5V ±5%, VCCO = 3.3V ±300mV, fCLK = 90Msps, GAIN = open (midgain) MAX1011 evaluation kit, TA = +25°C, unless
otherwise noted.)
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
EFFECTIVE NUMBER OF BITS
vs. SAMPLING/CLOCK FREQUENCY
ANALOG INPUT BANDWIDTH
EFFECTIVE NUMBER OF BITS
MAGNITUDE (dB)
-0.2
5.4
5.2
-0.4
-0.6
MAX1011-03
0
5.8
5.6
6.0
MAX1011-02
MAX1011-01
6.0
5.9
5.8
5.7
-0.8
5.6
-1.0
5.5
fCLK = 90Msps
fIN = 20MHz
5.0
100
10
1
ANALOG INPUT FREQUENCY (MHz)
10
1
100
OSCILLATOR OPEN-LOOP PHASE NOISE
vs. FREQUENCY OFFSET
100
FFT PLOT
0
MAX1011-04
-50
-70
fIN = 19.9512MHz
fCLK = 90.000MHz
1024 POINTS
AC-COUPLED
SINGLE-ENDED
AVERAGED
-20
AMPLITUDE (dB)
PHASE NOISE (dBc)
10
CLOCK FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
-90
-110
MAX1011-05
EFFECTIVE NUMBER OF BITS
-40
-60
-130
-80
10k
1k
100k
1M
0
18
27
36
FREQUENCY (MHz)
INTEGRAL NONLINEARITY
vs. CODE
DIFFERENTIAL NONLINEARITY
vs. CODE
45
MAX1003-07
MAX1011-06
0.50
0.25
DNL (LSB)
0.25
0
0
-0.25
-0.25
-0.50
-0.50
0
10
20
30
CODE
4
9
FREQUENCY OFFSET FROM CARRIER (Hz)
0.50
INL (LSB)
MAX1011
Low-Power, 90Msps, 6-Bit ADC
40
50
60 64
0
10
20
30
40
CODE
_______________________________________________________________________________________
50
60 64
Low-Power, 90Msps, 6-Bit ADC
PIN
NAME
1
GAIN
FUNCTION
2
OCC+
Positive Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground
pin 2 for DC-coupled inputs.
3
OCC-
Negative Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled inputs. Ground
pin 3 for DC-coupled inputs.
4
IN+
Noninverting Analog Input
5
IN-
Inverting Analog Input
6
VCC
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 9).
7
TNK+
Positive Oscillator/Clock Input
8
TNK-
Negative Oscillator/Clock Input
9, 10,
12, 13
GND
Analog Ground
11
VCC
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 10).
14
VCC
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 13).
15
N.C.
No Connection
16
OGND
Digital Output Ground
17
VCCO
Digital Output Supply, +3.3V ±300mV. Bypass with a 47pF capacitor to OGND (pin 16).
18
DCLK
Digital Clock Output. Frames the output data.
19–24
D0–D5
Digital Outputs 0–5. D5 is the most significant bit (MSB).
Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).
_______________Detailed Description
Converter Operation
The MAX1011 integrates a 6-bit analog-to-digital converter (ADC), a buffered voltage reference, and oscillator circuitry. The ADC uses a flash conversion technique
to convert an analog input signal into a 6-bit parallel
digital output code. The MAX1011’s unique design
includes 63 fully differential comparators and a proprietary encoding scheme that ensures no more than
1LSB dynamic encoding error. The control logic interfaces easily to most digital signal processors (DSPs)
and microprocessors (µPs) with +3.3V CMOS-compatible logic interfaces. Figure 1 shows the MAX1011 in a
typical application.
Programmable Input Amplifier
The MAX1011 has a programmable-gain input amplifier
with a -0.5dB bandwidth of 55MHz and a true differential input. To maximize performance in high-speed
systems, the amplifier has less than 3pF of input
capacitance. The input amplifier gain is programmed
via the GAIN pin to provide three possible input fullscale ranges (FSRs) as shown in Table 1.
Single-ended and differential AC-coupled input circuit
examples are shown in Figures 2 and 3. Each of the
Table 1. Input Amplifier Programming
GAIN
INPUT FULL-SCALE RANGE
(mVp-p)
GND
500
Open
250
VCC
125
_______________________________________________________________________________________
5
MAX1011
Pin Description
MAX1011
Low-Power, 90Msps, 6-Bit ADC
amplifier inputs is internally biased to a 2.35V reference
through a 20kΩ resistor, eliminating external DC bias
circuits. A series 0.1µF capacitor is required at the
amplifier input for AC-coupled signals.
When operating with AC-coupled inputs, the input
amplifier’s DC offset voltage is nulled to within ±1/2LSB
by an on-chip, offset-correction amplifier. An external
compensation capacitor is required to set the dominant
pole of the offset-correction amplifier’s frequency
response (Figures 2 and 3). The compensation capacitor will determine the low-frequency corner of the analog input response according to the following formula:
fc = 1 / (0.1 x C)
where C is the value of the compensation capacitor in
µF, and fc is the corner frequency in Hz.
MAX1011
RF
6 BITS
6
DATA
BUFFER
DIGITAL
DEMODULATOR
OR
DSP
DCLK
LO
TANK
Figure 1. IF Sampling Receiver
0.22µF
0.22µF
OCC+
OCC+
OCC-
OFFSET
CORRECTION
OFFSET
CORRECTION
0.1µF
0.1µF
IN+
INPUT
AMP
VSOURCE
IN+
INPUT
AMP
VSOURCE
IN-
IN0.1µF
0.1µF
20k
MAX1011
20k
2.35V INTERNAL REFERENCE
Figure 2. Single-Ended AC-Coupled Input
6
OCC-
20k
MAX1011
20k
2.35V INTERNAL REFERENCE
Figure 3. Differential AC-Coupled Input
_______________________________________________________________________________________
Low-Power, 90Msps, 6-Bit ADC
ADC
The ADC block receives the analog signal from the
input amplifier. The ADC uses flash conversion with 63
fully differential comparators to digitize the analog input
signal into a 6-bit output in offset binary format.
The MAX1011 features a proprietary encoding scheme
that ensures no more than 1LSB dynamic encoding
error. Dynamic encoding errors resulting from metastable states may occur when the analog input voltage,
at the time the sample is taken, falls close to the decision point for any one of the input comparators. The
resulting output code for typical converters can be
incorrect, including false full- or zero-scale outputs. The
MAX1011’s unique design reduces the magnitude of
this type of error to 1LSB.
Internal Voltage Reference
An internal buffered-bandgap reference is included on
the MAX1011 to drive the ADC’s reference ladder. The
on-chip reference and buffer eliminate any external
(high-impedance) connections to the reference ladder,
minimizing the potential for noise coupling from external circuitry while ensuring that the voltage reference,
input amplifier, and reference ladder track well with
variations of temperature and power supplies.
Oscillator Circuit
The MAX1011 includes a differential oscillator, which is
controlled by an external parallel resonant (tank) network as shown in Figure 6. Alternatively, the oscillator
may be overdriven with an external clock source as
shown in Figure 7.
Internal Clock Operation (Tank)
If the tank circuit is used, the resonant inductor should
have a sufficiently high Q and a self-resonant frequency (SRF) of at least twice the intended oscillator frequency. Coilcraft’s 1008HS-221, with an SRF of
700MHz and a Q of 45, works well for this application.
Generate different clock frequency ranges by adjusting
varactor and tank elements.
An internal clock-driver buffer is included to provide
sharp clock edges to the internal flash comparators.
The buffer ensures that the comparators are simultaneously clocked, maximizing the ADC’s effective number
of bits (ENOB) performance.
OFFSET CORRECTION DISABLED
OCC+
OFFSET CORRECTION DISABLED
OCC-
OCC+
OFFSET
CORRECTION
OFFSET
CORRECTION
IN+
IN+
INPUT
AMP
VSOURCE
VCM
1.75V TO 2.75V
INPUT
AMP
VSOURCE
IN20k
OCC-
IN-
MAX1011
20k
2.35V INTERNAL REFERENCE
Figure 4. Single-Ended DC-Coupled Input
20k
DIFFERENTIAL SOURCE
WITH COMMON MODE
FROM 1.75V TO 2.75V.
MAX1011
20k
2.35V INTERNAL REFERENCE
Figure 5. Differential DC-Coupled Input
_______________________________________________________________________________________
7
MAX1011
For applications where a DC component of the input
signal is present, Figures 4 and 5 show single-ended
and differential DC-coupled input circuits. The amplifier’s input common-mode voltage range extends from
1.75V to 2.75V. To prevent attenuation of the input
signal’s DC component in this mode, disable the offsetcorrection amplifier by grounding the OCC+ and OCCpins (Figures 4 and 5).
MAX1011
Low-Power, 90Msps, 6-Bit ADC
VCLK = 300mVp-p TO 1.25Vp-p
47k
0.1µF
50Ω
TNK+
47pF
10k
5pF
VTUNE
Z0 = 50Ω
TNK+
CLK
DRIVER
220nH
VCLK
50Ω
CLK
DRIVER
TNK-
TNK0.1µF
47pF
MAX1011
47k
MAX1011
50Ω
VTUNE = 0V TO 8V
fOSC = 70MHz TO 109MHz
VARACTOR DIODE PAIR IS M/A-COM MA4ST079CK-287
(SOT23 PACKAGE)
INDUCTOR COILCRAFT 1008HS-221.
Figure 6. Tank Resonator Oscillator
Figure 7. External Clock Drive Circuit
External Clock Operation
To accommodate designs that use an external clock,
the MAX1011’s internal oscillator can be overdriven by
an external clock source (Figure 7). The external clock
source should be a sinusoid to minimize clock phase
noise and jitter, which can degrade the ADC’s ENOB
performance. AC couple the clock source (recommended voltage level is approximately 1Vp-p) to the
oscillator inputs (Figure 7).
improved conversion accuracy. Use of separate
ground planes is strongly recommended.
The entire board needs good DC bypassing for both
analog and digital supplies. Place the power-supply
bypass capacitors close to where the power is routed
onto the board, i.e., close to the connector. 10µF electrolytic capacitors with low-ESR ratings are recommended. For best effective bits performance, minimize
capacitive loading at the digital outputs. Keep the digital output traces as short as possible.
The MAX1011 requires a +5V ±5% power supply for
the analog supply (VCC) and a +3.3V ±300mV power
supply connected to V CCO for the logic outputs.
Bypass each of the VCC supply pins to its respective
GND with high-quality ceramic capacitors located as
close to the package as possible (Table 2). Consult the
evaluation kit manual for a suggested layout and
bypassing scheme.
Output Data Format
The conversion results are output on a 6-bit-wide data
bus. Data is latched into the ADC output latch following
a pipeline delay of one clock cycle (Figure 8). Output
data is clocked out of the ADC’s data output pins (D0
through D5) on the rising edge of the clock output
(DCLK), with a DCLK-to-data propagation delay (tPD) of
3.0ns. The MAX1011 outputs are +3.3V CMOS-logic
compatible.
Transfer Function
Figure 9 shows the MAX1011’s nominal transfer function.
Output coding is offset binary with 1LSB = FSR / 63.
___________Applications Information
The MAX1011 is designed with separate analog and
digital power-supply and ground connections to isolate
high-current digital noise spikes from the more sensitive analog circuitry. The high-current digital output
ground (OGND) and analog ground (GND) should be
at the same DC level, connected at only one location
on the board. This will provide best noise immunity and
8
Table 2. Bypassing Guide
VCC/
VCCO
(PIN)
BYPASS
TO GND/
OGND
(PIN)
CAPACITOR
VALUE
Analog Inputs
11
10
0.01µF
Oscillator/Clock
6
9
0.01µF
Converter
14
13
0.01µF
Digital Output
17
16
47pF
SUPPLY
FUNCTION
_______________________________________________________________________________________
Low-Power, 90Msps, 6-Bit ADC
MAX1011
N
N+1
ANALOG
INPUT
N+2
tAD
50%
TNK+
(INPUT CLOCK)
tDCLK
1.4V
tPD
DCLK
tSKEW
1.4V
DATA OUT
DATA VALID N - 1
DATA VALID N
Figure 8. MAX1011 Timing Diagram
______________Dynamic Performance
Signal-to-noise and distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to all
other ADC output signals. The output spectrum is limited to frequencies above DC and below one-half the
ADC sample rate.
111111
111110
The theoretical minimum analog-to-digital noise is
caused by quantization error, and results directly from
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where
N is the number of bits of resolution. Therefore, a perfect 6-bit ADC can do no better than 38dB.
The FFT Plot (see Typical Operating Characteristics)
shows the result of sampling a pure 20MHz sinusoid at
a 90MHz clock rate. This FFT plot of the output shows
the output level in various spectral bands. The plot has
been averaged to reduce the quantization noise floor
and reveal the low-amplitude spurs. This emphasizes the
excellent spurious-free dynamic range of the MAX1011.
OUTPUT CODE
111101
100001
100000
011111
011110
000011
000010
000001
000000
-FSR
2
0
1LSB
INPUT VOLTAGE (IN+ TO IN-)
FSR
2
The effective resolution (or effective number of bits) the
ADC provides can be measured by transposing the
equation that converts resolution to SINAD: N = (SINAD
- 1.76)/ 6.02 (see Typical Operating Characteristics).
Figure 9. Ideal Transfer Function
_______________________________________________________________________________________
9
Low-Power, 90Msps, 6-Bit ADC
MAX1011
Pin Configuration
Chip Information
TRANSISTOR COUNT: 2823
SUBSTRATE CONNECTED TO GND
TOP VIEW
GAIN 1
24 D5
OCC+ 2
23 D4
OCC- 3
22 D3
IN+ 4
IN- 5
21 D2
MAX1011
20 D1
19 D0
VCC 6
TNK+ 7
18 DCLK
TNK- 8
17 VCCO
GND 9
16 OGND
GND 10
15 N.C.
VCC 11
14 VCC
GND 12
13 GND
QSOP
10
______________________________________________________________________________________
Low-Power, 90Msps, 6-Bit ADC
QSOP.EPS
______________________________________________________________________________________
11
MAX1011
Package Information
MAX1011
Low-Power, 90Msps, 6-Bit ADC
NOTES
12
______________________________________________________________________________________
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