FEATURES FUNCTIONAL BLOCK DIAGRAM VDD Dual 14-bit SAR ADC Simultaneous sampling Throughput rate: 4.2 MSPS per channel Specified for a VDD of 2.5 V Power dissipation: 36 mW at 4.2 MSPS On-chip reference: 2.048 V ± 0.25%, 6 ppm/°C Dual conversion with read High speed serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible −40°C to +125°C Y grade operation, −40°C to +85°C B grade operation 16-lead TSSOP and 18-lead LFCSP packages Qualified for automotive applications VDRIVE AD7357 VINA+ 14-BIT SUCCESSIVE APPROXIMATION ADC T/H VINA– REFA BUF SCLK CONTROL LOGIC REF CS BUF REFB VINB+ 14-BIT SUCCESSIVE APPROXIMATION ADC T/H VINB– APPLICATIONS AGND AGND REFGND SDATAB DGND Figure 1. Automotive radar Data acquisition systems Motion control I and Q demodulation RFID readers GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7357 is a dual, 14-bit, high speed, low power, successive approximation analog-to-digital converter (ADC) that operates from a single 2.5 V power supply and features throughput rates up to 4.2 MSPS. The device contains two ADCs, each preceded by a low noise, wide bandwidth track-and-hold circuit that can handle input frequencies in excess of 110 MHz. 1. 1 The conversion process and data acquisition use standard control inputs allowing for easy interfacing to microprocessors or digital signal processors (DSPs). The input signal is sampled on the falling edge of CS; a conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. The AD7357 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With a 2.5 V supply and a 4.2 MSPS throughput rate, the device consumes 14 mA typically. The device also offers flexible power and throughput rate management options. The analog input range for the device is the differential common mode ±VREF/2. The AD7357 has an on-chip 2.048 V reference that can be overdriven when an external reference is preferred. The AD7357 is available in a 16-lead thin shrink small outline package (TSSOP) and an 18-lead lead frame chip scale package (LFCSP). 1 SDATAA 07757-001 Data Sheet Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC AD7357 2. 3. Two Complete ADC Functions. These functions allow simultaneous sampling and conversion of two channels. The conversion result of both channels is simultaneously available on separate data lines or in succession on one data line if only one serial port is available. High Throughput with Low Power Consumption. The AD7357 offers a 4.2 MSPS throughput rate with 36 mW power consumption. Simultaneous Sampling. The device features two standard successive approximation ADCs with accurate control of the sampling instant via a CS input and once off conversion control. Table 1. Related Devices Generic AD7356 AD7352 AD7266 Resolution 12-bit 12-bit 12-bit Throughput 5 MSPS 3 MSPS 2 MSPS AD7866 AD7366 AD7367 12-bit 12-bit 14-bit 1 MSPS 1 MSPS 1 MSPS Analog Input Differential Differential Differential/singleended Single-ended Single-ended bipolar Single-ended bipolar Protected by U.S. Patent No. 6,681,332. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com AD7357* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DESIGN RESOURCES View a parametric search of comparable parts. • AD7357 Material Declaration • PCN-PDN Information EVALUATION KITS • Quality And Reliability • AD7357 Evaluation Board • Symbols and Footprints DOCUMENTATION DISCUSSIONS Data Sheet View all AD7357 EngineerZone Discussions. • AD7357: Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC Data Sheet SAMPLE AND BUY SOFTWARE AND SYSTEMS REQUIREMENTS Visit the product page to see pricing options. • AD7352/AD7356/AD7357 Evaluation Software TECHNICAL SUPPORT REFERENCE DESIGNS Submit a technical question or find your regional support number. • CN0061 DOCUMENT FEEDBACK REFERENCE MATERIALS Submit feedback for this data sheet. Technical Articles • MS-2210: Designing Power Supplies for High Speed ADC • MS-2577: Model-Based Design of Advanced Motor Control Systems This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. AD7357 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driving Differential Inputs ....................................................... 16 Applications ....................................................................................... 1 Voltage Reference ....................................................................... 17 Functional Block Diagram .............................................................. 1 ADC Transfer Function ............................................................. 17 General Description ......................................................................... 1 Modes of Operation ....................................................................... 18 Product Highlights ........................................................................... 1 Normal Mode .............................................................................. 18 Revision History ............................................................................... 2 Partial Power-Down Mode ....................................................... 18 Specifications..................................................................................... 3 Full Power-Down Mode ............................................................ 19 Timing Specifications .................................................................. 6 Power-Up Times ......................................................................... 20 Absolute Maximum Ratings ............................................................ 7 Power vs. Throughput Rate ....................................................... 20 ESD Caution .................................................................................. 7 Serial Interface ................................................................................ 21 Pin Configurations and Function Descriptions ........................... 8 Application Suggestions................................................................. 22 Typical Performance Characteristics ........................................... 10 Grounding and Layout .............................................................. 22 Terminology .................................................................................... 12 Evaluating the AD7357 Performance ...................................... 22 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 23 Circuit Information .................................................................... 14 Ordering Guide .......................................................................... 24 Converter Operation .................................................................. 14 Automotive Products ................................................................. 24 Analog Input Structure .............................................................. 14 Analog Inputs .............................................................................. 16 REVISION HISTORY 12/15—Rev. D to Rev. E Changes to Figure 3 and Table 5 ..................................................... 8 10/15—Rev. C to Rev. D Changes to Figure 20 ...................................................................... 16 6/15—Rev. B to Rev. C Added 18-Lead LFCSP....................................................... Universal Change to Features Section ............................................................. 1 Changes to Table 2 ............................................................................ 5 Added Figure 3, Renumbered Sequentially .................................. 8 Change to Circuit Information Section ....................................... 13 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 2/11—Rev. 0 to Rev. A Changes to Features and Applications Sections ............................1 Changes to Table 2.............................................................................3 Added AD7357WY Temperature Range to Endnote 1 in Table 3....5 Changes to SDATAB, SDATAA Pin Description ............................7 Changes to Figure 20 and Figure 22 ............................................ 14 Changes to Figure 31...................................................................... 18 Changes to Ordering Guide .......................................................... 20 Added Automotive Products Section .......................................... 20 4/09—Revision 0: Initial Version 8/11—Rev. A to Rev. B Changes to Midscale Error Match Parameter, Table 2 ................ 3 Changes to Figure 21 and Figure 22............................................. 14 Added Voltage Reference Section ......................................................... 14 Rev. E | Page 2 of 24 Data Sheet AD7357 SPECIFICATIONS VDD = 2.5 ± 10% V, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, fSCLK = 80 MHz, fSAMPLE = 4.2 MSPS, TA = TMIN to TMAX1, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Signal-to-Noise and Distortion (SINAD)2 Min AD7357B/AD7357Y Typ Max 74.5 76.5 74 76 Min 74.5 74 74 AD7357WY Typ Max 76.5 76 73.5 Total Harmonic Distortion (THD)2 −83 −80 −83 Spurious Free Dynamic Range (SFDR) −85 −82 −85 −80 −79 −82 −81 Unit Test Conditions/ Comments fIN = 500 kHz sine wave dB dB dB −40°C to +25°C only dB dB −40°C to +25°C only dB dB Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms ADC to ADC Isolation2 CMRR2 SAMPLE-AND-HOLD Aperture Delay Aperture Delay Match Aperture Jitter Full Power Bandwidth At 3 dB At 0.1 dB DC ACCURACY Resolution Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 −86 −79 −100 −86 −79 −100 dB dB dB −100 −100 dB 3.5 40 16 16 ns ps ps 110 77 110 77 MHz MHz 14 14 ±2 ±0.5 Positive Full-Scale Error2 Positive Full-Scale Error Match2 Midscale Error2 Midscale Error Match2 Negative Full-Scale Error2 Negative Full-Scale Error Match2 ANALOG INPUT Fully Differential Input Range (VIN+ and VIN−) Common-Mode Voltage Range DC Leakage Current Input Capacitance 3.5 40 0.5 ±3 ±0.99 Bits LSB LSB ±20 ±20 0/35 ±12 ±20 ±20 ±20 ±20 0/38 ±15 ±20 ±20 LSB LSB LSB LSB LSB LSB VCM ± VREF/2 VCM ± VREF/2 V 1.6 V ±5 μA pF pF ±3 ±0.99 1.6 ±0.5 32 8 ±2 ±0.5 0.5 ±5 Rev. E | Page 3 of 24 ±0.5 32 8 −40°C to +25°C only −40°C to +25°C only fa = 1 MHz + 50 kHz, fb = 1 MHz − 50 kHz fIN = 1 MHz, fNOISE = 100 kHz to 2.5 MHz fNOISE = 100 kHz to 2.5 MHz At 0.1 dB Guaranteed no missed codes to 14 bits VCM = common-mode voltage; VIN+ and VIN− must remain within GND and VDD The voltage around which VIN+ and VIN− are centered When in track mode When in hold mode AD7357 Parameter REFERENCE INPUT/OUTPUT VREF Input Voltage Range Data Sheet Min AD7357B/AD7357Y Typ Max 2.048 + 0.1 VREF Input Current VREF Output Voltage VREF Temperature Coefficient VREF Long Term Stability VREF Thermal Hysteresis VREF Noise VREF Output Impedance LOGIC INPUTS Input Voltage High, VINH Low, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS Output Voltage High, VOH Low, VOL Floating State Leakage Current Floating State Output Capacitance Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD VDRIVE3 ITOTAL4 Normal Mode Operational Static Power-Down Mode Partial Full VDD 0.3 AD7357WY Typ Max Min 2.048 + 0.1 0.45 0.3 Unit VDD V 0.45 mA 2.038 2.058 2.038 2.058 V 2.043 2.053 2.043 2.053 V 20 ppm/°C ppm ppm μV rms Ω 6 100 50 60 1 20 0.6 × VDRIVE 6 100 50 60 1 0.6 × VDRIVE 0.3 × VDRIVE 0.3 × VDRIVE ±1 ±1 3 3 VDRIVE − 0.2 VDRIVE − 0.2 0.2 ±1 0.2 ±1 5.5 5.5 Straight binary When in reference overdrive mode ±2.048 V ± 0.5% maximum at VDD = 2.5 V ± 5% 2.048 V ± 0.25% maximum at VDD = 2.5 V ± 5% and 25°C For 1000 hours V V μA pF VIN = 0 V or VDRIVE V V μA pF Straight binary t2 + 15.5 × tSCLK ns t2 + 15.5 × tSCLK 33 4.2 2.25 2.25 Test Conditions/ Comments 2.75 3.6 2.25 2.25 33 4.2 ns MSPS Full-scale step input 2.75 3.6 V V Nominal VDD = 2.5 V Digital inputs = 0 V or VDRIVE 14 6 20 7.6 14 6 20 7.6 mA mA SCLK on or off 3.5 5 4.5 40 3.5 5 4.5 40 mA μA SCLK on or off SCLK on or off Rev. E | Page 4 of 24 Data Sheet Parameter Power Dissipation Normal Mode Operational Static Power-Down Mode Partial Full AD7357 Min AD7357B/AD7357Y Typ Max Min AD7357WY Typ Max Unit Test Conditions/ Comments 36 16 59 21 36 16 59 21 mW mW SCLK on or off 9.5 16 11.5 110 9.5 16 11.5 110 mW µW SCLK on or off SCLK on or off Temperature ranges are as follows: AD7357Y: −40°C to +125°C; AD7357B (TSSOP): −40°C to +85°C; AD7357B (LFCSP): −40°C to +125°C; AD7357WY: −40°C to +125°C. See the Terminology section. 3 The interface is functional with VDRIVE voltages down to 1.8 V. In this condition, the SCLK speed may need to be slowed down. See the access and hold times in the Timing Specifications section. 4 ITOTAL is the total current flowing in VDD and VDRIVE. 1 2 Rev. E | Page 5 of 24 AD7357 Data Sheet TIMING SPECIFICATIONS VDD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN 1, unless otherwise noted. Table 3. Parameter fSCLK tCONVERT tQUIET t2 t3 2 t42, 3 t5 t6 t7 2 t8 t9 t102 Latency Limit at TMIN , TMAX 500 80 t2 + 15.5 × tSCLK 5 5 6 Unit kHz min MHz max ns min ns min ns min ns max 12.5 11 9.5 9 5 5 ns max ns max ns max ns max ns min ns min 3.5 3 9.5 5 4.5 9.5 ns min ns min ns max ns min ns min ns max 1 conversion latency Description tSCLK = 1/fSCLK Minimum time between end of serial read and next falling edge of CS CS to SCLK setup time Delay from CS until SDATAA and SDATAB are three-state disabled Data access time after SCLK falling edge 1.8 V ≤ VDRIVE < 2.25 V 2.25 V ≤ VDRIVE < 2.75 V 2.75 V ≤ VDRIVE < 3.3 V 3.3 V ≤ VDRIVE ≤ 3.6 V SCLK low pulse width SCLK high pulse width SCLK to data valid hold time 1.8 V ≤ VDRIVE < 2.75 V 2.75 V ≤ VDRIVE ≤ 3.6 V CS rising edge to SDATAA, SDATAB, high impedance CS rising edge to falling edge pulse width SCLK falling edge to SDATAA, SDATAB, high impedance SCLK falling edge to SDATAA, SDATAB, high impedance Temperature ranges are as follows: AD7357Y: −40°C to +125°C; AD7357B (TSSOP): −40°C to +85°C; AD7357B (LFCSP): −40°C to +125°C; AD7357WY: −40°C to +125°C. Specified with a load capacitance of 10 pF on SDATAA and SDATAB. 3 The time required for the output to cross 0.4 V or 2.4 V. 1 2 Rev. E | Page 6 of 24 Data Sheet AD7357 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VDD to AGND, DGND, REFGND VDRIVE to AGND, DGND, REFGND VDD to VDRIVE AGND to DGND to REFGND Analog Input Voltages1 to AGND Digital Input Voltages2 to DGND Digital Output Voltages3 to DGND Input Current to Any Pin Except Supplies4 Operating Temperature Range AD7357Y AD7357B (TSSOP) AD7357B (LFCSP) AD7357WY Storage Temperature Range Junction Temperature TSSOP Package θJA Thermal Impedance θJC Thermal Impedance LFCSP Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Reflow Temperature (10 sec to 30 sec) ESD Rating −0.3 V to +3 V −0.3 V to +5 V −5 V to +3 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDRIVE + 0.3V −0.3 V to VDRIVE + 0.3 V ±10 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION −40°C to +125°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −65°C to +150°C 150°C 143°C/W 45°C/W 44°C/W 22°C/W 255°C 2 kV 1 Analog input voltages are VINA+, VINA−, VINB+, VINB−, REFA, and REFB. Digital input voltages are CS and SCLK. 3 Digital output voltages are SDATAA and SDATAB. 4 Transient currents of up to 100 mA do not cause SCR latch-up. 2 Rev. E | Page 7 of 24 AD7357 Data Sheet 14 VINA– 16 REFGND 15 REFA 17 AGND 18 REFB PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 13 VINA+ VINB– 1 AD7357 VINB+ 2 13 SDATAB AGND 5 12 DGND REFB 6 11 AGND VINB– 7 10 CS VINB+ 8 9 VDD NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND FOR MAXIMUM THERMAL CAPABILITY, SOLDER THE EXPOSED PAD TO THE PRINTED CIRCUIT BOARD (PCB). Figure 2. Pin Configuration, TSSOP 07757-103 SDATAA TOP VIEW (Not to Scale) SDATAA 9 AD7357 REFGND 4 SDATAB 8 SCLK DGND 7 15 14 VINA– 11 VDRIVE 10 SCLK VDD 4 07757-002 2 REFA 3 TOP VIEW (Not to Scale) NIC 3 VDRIVE CS 5 16 AGND 6 VINA+ 1 12 NIC Figure 3. Pin Configuration, LFCSP Table 5. Pin Function Descriptions TSSOP 1, 2 3, 6 Pin No. LFCSP 13, 14 15, 18 Mnemonic VINA+, VINA− REFA, REFB 4 16 REFGND 5, 11 6, 17 AGND 7, 8 9 1, 2 4 VINB−, VINB+ VDD 10 5 CS 12 7 DGND 13, 14 8, 9 SDATAB, SDATAA 15 10 SCLK Description Analog Inputs of ADC A. These analog inputs form a fully differential pair. Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each reference pin with a 10 μF capacitor. Provided that the output is buffered, take the on-chip reference from these pins and apply it externally to the rest of the system. The nominal internal reference voltage is 2.048 V and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range for the external reference is 2.048 V + 100 mV to VDD. Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Refer any external reference signal to this REFGND voltage. Decoupling capacitors must be placed between this pin and the REFA and REFB pins. Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. Refer all analog input signals to this AGND voltage. The AGND and DGND voltages must ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Analog Inputs of ADC B. These analog inputs form a fully differential pair. Power Supply Input. The VDD range for the AD7357 is 2.5 V ± 10%. Decouple the supply to AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor. Chip Select. Active low, logic input. This input provides the dual function of initiating conversions on the AD7357 and framing the serial data transfer. Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. Connect this pin to the DGND plane of a system. The DGND and AGND voltages must ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros, followed by the 14 bits of conversion data. The data is provided MSB first. If CS is held low for 18 SCLK cycles rather than 16, then two trailing zeros appear after the 14 bits of data. If CS is held low for an additional 18 SCLK cycles on either SDATAA or SDATAB , the data from the other ADC follows on the SDATAx pins. This allows data from a simultaneous conversion on both ADCs to gather in serial format on either SDATAA or SDATAB. Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This clock is also used as the clock source for the conversion process. Rev. E | Page 8 of 24 Data Sheet TSSOP 16 Pin No. LFCSP 11 Not applicable Not applicable 3, 12 AD7357 Mnemonic VDRIVE NIC EPAD Description Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin is decoupled to DGND. The voltage at this pin may be different than at VDD. No Internal Connection. These pins are not connected internally. Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and for maximum thermal capability, solder the exposed pad to the printed circuit board (PCB). Rev. E | Page 9 of 24 AD7357 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 20,000 –20 –40 NUMBER OF OCCURRENCES 16,384 POINT FFT fSAMPLE = 4.2MSPS fIN = 1MHz SINAD = 76.8dB THD = –84.5dB –80 –100 –120 10,000 5000 –140 0 250 500 750 1000 1250 1500 FREQUENCY (kHz) 1750 2000 07757-003 32 HITS 07757-006 dB –60 15,000 0 8188 Figure 4. Typical FFT 8189 8190 8191 8192 CODE 8193 8194 8195 Figure 7. Histogram of Codes 1.0 79 0.8 77 75 0.4 0.2 SNR (dB) DNL ERROR (LSB) 0.6 0 –0.2 –0.4 73 71 69 –0.6 0 4000 8000 12,000 16,000 CODE 65 07757-004 –1.0 07757-007 67 –0.8 0 Figure 5. Typical DNL 2 3 4 ANALOG INPUT FREQUENCY (MHz) 5 Figure 8. SNR vs. Analog Input Frequency 1.5 –60 1.0 –65 PSSR (dB) 0.5 0 –70 –75 –0.5 –1.5 0 4000 8000 CODE Figure 6. Typical INL 12,000 16,000 07757-008 –80 –1.0 –85 07757-005 INL ERROR (LSB) 1 0 5 10 15 20 SUPPLY RIPPLE FREQUENCY (MHz) 25 Figure 9. PSRR vs. Supply Ripple Frequency with No Supply Decoupling Rev. E | Page 10 of 24 Data Sheet AD7357 2.0482 10 2.0480 2.0478 +125°C +85°C +25°C –40°C 9 ACCESS TIME (ns) 2.0476 VREF (V) 2.0474 2.0472 2.0470 2.0468 8 7 2.0466 07757-009 2.0462 2.0460 0 500 1000 1500 2000 CURRENT LOAD (µA) 2500 5 3000 07757-012 6 2.0464 1.8 2.0 Figure 10. VREF vs. Reference Output Current Drive 3.0 3.2 INL MAX 3.4 3.6 +125°C +85°C +25°C –40°C 7 0.5 HOLD TIME (ns) 1.0 DNL MAX 0 DNL MIN –0.5 6 5 –1.0 0 10 20 30 40 50 60 SCLK FREQUENCY (MHz) 07757-010 INL MIN 70 4 80 Figure 11. Linearity Error vs. SCLK Frequency INL MAX 1.0 DNL MAX 0 DNL MIN –0.5 INL MIN –1.5 2.10 07757-011 –1.0 2.15 2.20 2.25 2.30 2.35 EXTERNAL VREF (V) 2.40 1.8 2.0 2.2 2.4 2.6 2.8 VDRIVE (V) 3.0 Figure 14. Hold Time vs. VDRIVE 1.5 0.5 07757-113 ERROR (LSB) 2.6 2.8 VDRIVE (V) 8 1.5 ERROR (LSB) 2.4 Figure 13. Access Time vs. VDRIVE 2.0 –1.5 2.2 2.45 2.50 Figure 12. Linearity Error vs. External VREF Rev. E | Page 11 of 24 3.2 3.4 3.6 AD7357 Data Sheet TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (1 LSB below the first code transition) and full scale (1 LSB above the last code transition). Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency, fS, as follows: Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Negative Full-Scale Error Negative full-scale error is the deviation of the first code transition (00 … 000) to (00 … 001) from the ideal (that is, −VREF + 0.5 LSB) after the midscale error has been adjusted out. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of a conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of conversion. Negative Full-Scale Error Match Negative full-scale error match is the difference in negative fullscale error between the two ADCs. Midscale Error Midscale error is the deviation of the midscale code transition (011 … 111) to (100 … 000) from the ideal (that is, 0 V). Midscale Error Match Midscale error match is the difference in midscale error between the two ADCs. Positive Full-Scale Error Positive full-scale error is the deviation of the last code transition (111 … 110) to (111 … 111) from the ideal (that is, VREF − 1.5 LSB) after the midscale error has been adjusted out. Positive Full-Scale Error Match Positive full-scale error match is the difference in positive fullscale error between the two ADCs. ADC to ADC Isolation ADC to ADC isolation is a measure of the level of crosstalk between ADC A and ADC B. It is measured by applying a fullscale 1 MHz sine wave signal to one of the two ADCs and applying a full-scale signal of variable frequency to the other ADC. The ADC-to-ADC isolation is the ratio of the power of the 1 MHz signal on the converted ADC to the power of the noise signal on the other ADC that appears in the FFT. The noise frequency on the unselected channel varies from 100 kHz to 2.5 MHz. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of the frequency, fS. The frequency of the input varies from 5 kHz to 25 MHz. CMRR (dB) = 10 log(Pf/PfS) Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical SINAD for an ideal N-bit converter with a sine wave input is given by SINAD = (6.02 N + 1.76) dB Thus, for a 12-bit converter, SINAD is 74 dB and for a 14-bit converter, SINAD is 86 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7357, it is defined as THD dB 20 log V 2 2 V 3 2 V 4 2 V 5 2 V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. PSRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Rev. E | Page 12 of 24 Data Sheet AD7357 Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7357 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification (see Table 2), where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Thermal Hysteresis Thermal hysteresis is the absolute maximum change of the reference output voltage after the device is cycled through temperature from either T_HYS+ = 25°C to TMAX to 25°C T_HYS− = 25°C to TMIN to 25°C It is expressed in ppm using the following equation: VHYS (ppm) = VREF (25°C) − VREF (T _ HYS) × 106 VREF (25°C) where: VREF(25°C) is VREF at 25°C. VREF(T_HYS) is the maximum change of VREF at T_HYS+ or T_HYS−. Rev. E | Page 13 of 24 AD7357 Data Sheet THEORY OF OPERATION The AD7357 is a high speed, dual, 14-bit, single-supply, successive approximation ADC. The device operates from a 2.5 V power supply and features throughput rates up to 4.2 MSPS. The control logic generates the ADC output code. The output impedances of the sources driving the VIN+ and VIN− pins must be matched; otherwise, the two inputs have different settling times, resulting in errors. The AD7357 contains two on-chip differential track-and-hold amplifiers, two successive approximation ADCs, and a serial interface with two separate data output pins. The device is housed in a 16-lead TSSOP package or an 18-lead LFCSP package, offering the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the device, but also provides the clock source for each successive approximation ADC. The AD7357 has an on-chip 2.048 V reference. If an external reference is desired, the internal reference can be overdriven with a reference value ranging from (2.048 V + 100 mV) to VDD. If the internal reference is to be used elsewhere in the system, the reference output needs to be buffered first. The differential analog input range for the AD7357 is VCM ± VREF/2. The AD7357 features power-down options to allow power saving between conversions. The power-down options are implemented via the standard serial interface, as described in the Modes of Operation section. CONVERTER OPERATION The AD7357 has two successive approximation ADCs, each based around two capacitive DACs. Figure 15 and Figure 16 show simplified schematics of one of these ADCs in acquisition and conversion phases, respectively. The ADC comprises control logic, an SAR, and two capacitive DACs. In Figure 15 (the acquisition phase), SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays may acquire the differential signal on the input. CAPACITIVE DAC VIN– COMPARATOR CS B VIN+ A SW1 A SW2 CONTROL LOGIC SW3 CS B VREF CAPACITIVE DAC 07757-014 CIRCUIT INFORMATION Figure 16. ADC Conversion Phase ANALOG INPUT STRUCTURE Figure 17 shows the equivalent circuit of the analog input structure of the AD7357. The four diodes provide ESD protection for the analog inputs. Take care to ensure that the analog input signals never exceed the supply rails by more than 300 mV. Exceeding the limit causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the device. The C1 capacitors in Figure 17 are typically 8 pF and can primarily be attributed to pin capacitance. The R1 resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 30 Ω. The C2 capacitors are the ADC sampling capacitors with a capacitance of 32 pF typically. VDD D VIN+ C1 R1 C2 D CAPACITIVE DAC CS B VIN+ VIN– COMPARATOR VDD A SW1 A SW2 CS CONTROL LOGIC SW3 D VIN– C1 CAPACITIVE DAC 07757-013 VREF D 07757-015 B R1 C2 Figure 17. Equivalent Analog Input Circuit Conversion Phase—Switches Open, Track Phase—Switches Closed Figure 15. ADC Acquisition Phase When the ADC starts a conversion (see Figure 16), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected when the conversion begins. The control logic and charge redistribution DACs add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. Rev. E | Page 14 of 24 Data Sheet AD7357 –66.0 –70.0 –74.0 –65 –67 –69 –71 THD (dB) –73 –75 –77 –79 –81 –83 07757-017 –85 –89 100 200 1000 1500 2000 ANALOG INPUT FREQUENCY (kHz) –82.0 –86.0 –90.0 0 1000 2000 3000 4000 ANALOG INPUT FREQUENCY (kHz) Figure 19. THD vs. Analog Input Frequency 10Ω 33Ω 50Ω 100Ω –87 –78.0 07757–118 When no amplifier drives the analog input, limit the source impedance to low values. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 18 shows a graph of the THD vs. the analog input signal frequency for various source impedances. Figure 19 shows a graph of the THD vs. the analog input frequency while sampling at 4.2 MSPS. In this case, the source impedance is 33 Ω. THD (dB) For ac applications, it is recommended to remove high frequency components from the analog input signal by the use of an RC low-pass filter on the analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input must be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and may necessitate the use of an input buffer amplifier. The choice of the operational amplifier is a function of the particular application. 2500 Figure 18. THD vs. Analog Input Frequency for Various Source Impedances Rev. E | Page 15 of 24 5000 AD7357 Data Sheet ANALOG INPUTS DRIVING DIFFERENTIAL INPUTS Differential signals have some benefits over single-ended signals, including noise immunity based on the common-mode rejection of the device and improvements in distortion performance. Figure 20 defines the fully differential input of the AD7357. Differential operation requires VIN+ and VIN− to be driven simultaneously with two equal signals that are 180° out of phase. Because not all applications have a signal preconditioned for differential operation, there is often a need to perform a singleended to differential conversion. VREF p-p Differential Amplifier AD7357* VREF p-p An ideal method of applying differential drive to the AD7357 is to use a differential amplifier such as the AD8138. This device can be used as a single-ended to differential amplifier or as a differential to differential amplifier. The AD8138 also provides common-mode level shifting. Figure 21 shows how the AD8138 is used as a single-ended to differential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors to minimize the effects of switched capacitance on the front end of the ADC. VIN– 07757-034 PINS OMITTED FOR CLARITY. Figure 20. Differential Input Definition The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN− pins in each differential pair (VIN+ − VIN−). VIN+ and VIN− are simultaneously driven by two signals each of amplitude VREF that are 180° out of phase. This amplitude of the differential signal is, therefore, −VREF to +VREF peak-to-peak regardless of the common mode (CM). The architecture of the AD8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. CM is the average of the two signals and is, therefore, the voltage on which the two inputs are centered. If the source for the analog inputs used has zero impedance, all four resistors (RG1, RG2, RF1, and RF2) must be the same. If the source has a 50 Ω impedance and a 50 Ω termination, for example, increase the value of RG2 by 25 Ω to balance this parallel impedance on the input and thus ensures that both the positive and negative analog inputs have the same gain. The outputs of the amplifier are perfectly matched balanced differential outputs of identical amplitude and are exactly 180° out of phase. CM = (VIN+ + VIN−)/2 This results in the span of each input being CM ± VREF/2. This voltage must be set up externally. When setting up the CM, ensure that that VIN+ and VIN− remain within GND/VDD. When a conversion occurs, CM is rejected, resulting in a virtually noise free signal of amplitude −VREF to +VREF corresponding to the digital codes of 0 to 16,383. CF1 2.048V 1.024V 0V RF1 RG1 VOCM +2.048V GND –2.048V RG2 +1.024V +5V AD8138 –5V RF2 CF2 10kΩ 10µF RS* +2.5V +2.5V TO +3.6V VINx+ VDD VDRIVE AD7357 RS* VINx– REFA/REFB 2.048V 1.024V 0V AGND AGND +5V OP177 +2.048V 10µF 10kΩ –5V *MOUNT AS CLOSE TO THE AD7352 AS POSSIBLE. RS = 33Ω; RG1 = RG2 = RF1 = RF2 = 499Ω; C F1 = CF2 = 39pF. Figure 21. Using the AD8138 as a Single-Ended to Differential Amplifier Rev. E | Page 16 of 24 07757-131 COMMON MODE VOLTAGE *ADDITIONAL VIN+ Data Sheet AD7357 Operational Amplifier Pair VOLTAGE REFERENCE An operational amplifier pair is used to directly couple a differential signal to one of the analog input pairs of the AD7357. The circuit configurations shown in Figure 22 and Figure 23 show how an operational amplifier pair can be used to convert a single-ended signal into a differential signal for a bipolar and unipolar input signal, respectively. The voltage applied to Point A sets up the common-mode voltage. In both diagrams, Point A is connected in some way to the reference. The AD8022 is a suitable dual operational amplifier that is used in this configuration to provide differential drive to the AD7357. The AD7357 allows the choice of a very low temperature drift internal voltage reference or an external reference. The internal 2.048 V reference of the AD7357 provides excellent performance and can be used in almost all applications. VREF p-p VREF 2 220Ω 220Ω V+ 27Ω When the internal reference is used, the reference voltage is present on the REFA and REFB pins. Decouple these pins to REFGND with 10 μF capacitors. The internal reference voltage can be used elsewhere in the system, provided it is buffered externally. The REFA and REFB pins can also be overdriven with an external voltage reference if desired. The applied reference voltage can range from 2.048 V + 100 mV to VDD. A common choice is to use an external 2.5 V reference such as the ADR441 or ADR431. 2.048V 1.024V 0V VIN+ GND V– 220Ω 220Ω 2.048V 1.024V 0V V+ A V– 27Ω ADC TRANSFER FUNCTION AD7357* VIN– The output coding for the AD7357 is straight binary. The designed code transitions occur at successive LSB values (such as 1 LSB or 2 LSB). The LSB size is (2 × VREF)/16,384. The ideal transfer characteristic of the AD7357 is shown in Figure 24. REFA/REFB 10kΩ 10µF 07757-132 10kΩ *ADDITIONAL PINS OMITTED FOR CLARITY. 440Ω GND 220Ω V+ 27Ω 2.048V 1.024V 0V VIN+ V– 220Ω 220Ω V+ A V– 27Ω 000 ... 010 000 ... 001 000 ... 000 AD7357* –VREF + 1 LSB VIN– –VREF + 0.5 LSB REFA/REFB 10kΩ +VREF – 1 LSB +VREF – 1.5 LSB ANALOG INPUT 20kΩ Figure 24. Deal Transfer Characteristic 10µF 07757-133 220Ω 2.048V 1.024V 0V *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 23. Dual Operational Amplifier Circuit to Convert a Single-Ended Bipolar Signal into a Differential Unipolar Signal Rev. E | Page 17 of 24 07757-023 2 × VREF p-p ADC CODE Figure 22. Dual Operational Amplifier Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal 111 ... 111 111 ... 110 111 ... 101 AD7357 Data Sheet MODES OF OPERATION The AD7357 mode of operation is selected by controlling the logic state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial power-down mode, and full power-down mode. After a conversion is initiated, the point at which CS is pulled high determines which powerdown mode, if any, the device enters. Similarly, if already in a power-down mode, CS can control whether the device returns to normal operation or remains in a power-down mode. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation and throughput rate ratio for the differing application requirements. NORMAL MODE Normal mode is intended for applications needing the fastest throughput rates. The user does not need to worry about any power-up times because the AD7357 remains fully powered at all times. Figure 25 shows the general diagram of the operation of the AD7357 in this mode. CS 10 14 LEADING ZEROS + CONVERSION RESULT 07757-018 SDATAA SDATAB PARTIAL POWER-DOWN MODE This mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion or a series of conversions can be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7357 is in partial power-down mode, all analog circuitry is powered down except for the on-chip reference and reference buffers. To enter partial power-down mode, interrupt the conversion process by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 26. When CS is brought high in this window of SCLKs, the device enters partial power-down mode, the conversion that was initiated by the falling edge of CS is terminated, and SDATAA and SDATAB go back into three-state. If CS is brought high before the second SCLK falling edge, the device remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line. Figure 25. Normal Mode Operation CS The conversion is initiated on the falling edge of CS, as described in the Serial Interface section. To ensure that the device remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge but before the 16th SCLK falling edge, the device remains powered up, but the conversion is terminated and SDATAA and SDATAB go back into three-state. To complete the conversion and access the conversion result for the AD7357, 16 serial clock cycles are required. SDATA lines do not return to three-state after 16 SCLK cycles have elapsed, but instead do so when CS is brought high again. If CS is left low for another 2 SCLK cycles, two trailing zeros are clocked out after the data. If CS is left low for a further 16 SCLK cycles, the result for the other ADC on board is also accessed on the same SDATA line as shown in Figure 32 (see the Serial Interface section). When 32 SCLK cycles have elapsed, the SDATA line returns to three-state on the 32nd SCLK falling edge. If CS is brought high prior to this, the SDATA line returns to three-state at that point. Thus, CS may idle low after 32 SCLK cycles until it is brought high again sometime prior to the next conversion, if so desired, because the bus still returns to three-state upon completion of the dual result read. 1 2 10 14 SCLK SDATAA SDATAB THREE-STATE 07757-019 1 SCLK When a data transfer is complete and SDATAA and SDATAB have returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again (assuming the required acquisition time has been allowed). Figure 26. Entering Partial Power-Down Mode To exit this mode of operation and to power up the AD7357 again, perform a dummy conversion. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up after approximately 200 ns elapses (or one full conversion), and valid data results from the next conversion, as shown in Figure 27. If CS is brought high before the second falling edge of SCLK, the AD7357 again goes into partial power-down mode. This avoids accidental power-up due to glitches on the CS line. Although the device may begin to power up on the falling edge of CS, it powers down again on the rising edge of CS. If the AD7357 is already in partial power-down mode and CS is brought high between the second and 10th falling edges of SCLK, the device enters full power-down mode. Rev. E | Page 18 of 24 Data Sheet AD7357 To reach full power-down, the next conversion cycle must be interrupted in the same way, as shown in Figure 28. When CS has been brought high in this window of SCLKs, the device completely powers down. FULL POWER-DOWN MODE This mode is intended for use in applications where throughput rates slower than those in the partial power-down mode are required, as power-up from a full power-down takes substantially longer than from a partial power-down. This mode is more suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and, thus, power-down. When the AD7357 is in full power-down, all analog circuitry is powered down. Full powerdown is entered in a way that is similar to partial power-down, except that the timing sequence shown in Figure 26 must be executed twice. The conversion process must be interrupted in a similar fashion by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK. The device enters partial power-down mode at this point. Note that it is not necessary to complete the 16 SCLK pulses after CS has been brought high to enter a power-down mode. To exit full power-down mode and power up the AD7357, perform a dummy conversion, such as powering up from partial powerdown. On the falling edge of CS, the device begins to power up, as long as CS is held low until after the falling edge of the 10th SCLK. The required power-up time must elapse before a conversion can be initiated, as shown in Figure 29. THE PART IS FULLY POWERED UP; SEE THE POWER-UP TIMES SECTION. THE PART BEGINS TO POWER UP. tPOWER-UP1 CS 1 10 14 1 14 SDATAA SDATAB INVALID DATA 07757-020 SCLK VALID DATA Figure 27. Exiting Partial Power-Down Mode THE PART ENTERS PARTIAL POWER DOWN. THE PART BEGINS TO POWER UP. THE PART ENTERS FULL POWER DOWN. CS 1 2 10 14 1 2 10 THREE-STATE SDATAA SDATAB 14 THREE-STATE INVALID DATA INVALID DATA 07757-021 SCLK Figure 28. Entering Full Power-Down Mode THE PART BEGINS TO POWER UP. THE PART IS FULLY POWERED UP, SEE POWER-UP TIMES SECTION. tPOWER-UP2 CS SDATAA SDATAB 10 1 14 INVALID DATA 14 1 VALID DATA Figure 29. Exiting Full Power-Down Mode Rev. E | Page 19 of 24 07757-022 SCLK AD7357 Data Sheet To power up from partial power-down mode, one dummy cycle is required. The device is fully powered up after approximately 200 ns from the falling edge of CS has elapsed. As soon as the partial power-up time has elapsed, the ADC is fully powered up and the input signal is acquired properly. The quiet time, tQUIET, must still be allowed from the point where the bus goes back into three-state after the dummy conversion to the next falling edge of CS. To power up from full power-down, allow approximately 6 ms from the falling edge of CS, shown in Figure 29 as tPOWER-UP2. Note that during power-up from partial power-down mode, the track-and-hold, which is in hold mode while the device is powered down, returns to track mode after the first SCLK edge that the device receives after the falling edge of CS. POWER vs. THROUGHPUT RATE The power consumption of the AD7357 varies with the throughput rate. When using very slow throughput rates and as fast an SCLK frequency as possible, the various power-down options can be used to make significant power savings. However, the AD7357 quiescent current is low enough that even without using the power-down options, there is a noticeable variation in power consumption with sampling rate. This is true whether a fixed SCLK value is used or if it is scaled with the sampling rate. Figure 30 shows a plot of power vs. throughput rate when operating in normal mode for a fixed maximum SCLK frequency and an SCLK frequency that scales with the sampling rate. The internal reference is used for Figure 30. When power supplies are first applied to the AD7357, the ADC powers up in either of the power-down modes or in normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the device is fully powered up before attempting a valid conversion. Likewise, if the device is kept in partial power-down mode immediately after the supplies are applied, then initiate two dummy cycles. The first dummy cycle must hold CS low until after the 10th SCLK falling edge; in the second cycle, CS must be brought high between the second and 10th SCLK falling edges (see Figure 26). 38 34 30 26 80MHz SCLK 22 VARIABLE SCLK 18 14 10 07757-129 The AD7357 has two power-down modes: partial power-down and full power-down. They are described in detail in the Partial Power-Down Mode section and the Full Power-Down Mode section. This section describes the power-up time required when coming out of either of these modes. Note that the power-up times apply with the recommended decoupling capacitors in place on the REFA and REFB pins. Alternatively, if the device is placed into full power-down mode when the supplies are applied, three dummy cycles must be initiated. The first dummy cycle must hold CS low until after the 10th SCLK falling edge; the second and third dummy cycles place the device into full power-down mode (see Figure 28 and the Modes of Operation section). TOTAL POWER (mW) POWER-UP TIMES 0 1000 2000 3000 THROUGHPUT RATE (kSPS) Figure 30. Total Power vs. Throughput Rate Rev. E | Page 20 of 24 4000 Data Sheet AD7357 SERIAL INTERFACE Figure 31 shows the detailed timing diagram for serial interfacing to the AD7357. The serial clock (SCLK) provides the conversion clock and controls the transfer of information from the AD7357 during conversion. There is a single sample delay in the result that is clocked out from the AD7357. Likewise, if CS is held low for an additional 16 SCLK cycles on SDATAA, the data from the conversion on ADC A is output on SDATAB (see Figure 32). In this case, the SDATA line in use goes back into three-state on the 32nd SCLK falling edge or the rising edge of CS, whichever occurs first. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode. At this point, the analog input is sampled and the bus is taken out of three-state. The conversion is also initiated and requires a minimum of 16 SCLKs to complete. When 16 SCLK falling edges have elapsed, the track-and-hold goes back into track on the next SCLK rising edge, as shown in Figure 31 at Point B. On the rising edge of CS, the conversion is terminated and SDATAA and SDATAB go back into three-state. If CS is not brought high but is, instead, held low for an additional 16 SCLK cycles on SDATAA, the data from the conversion on ADC B is output on SDATAA. A minimum of 16 SCLK cycles are required to perform the conversion process and to access data from one conversion on either data line of the AD7357. Note that the data accessed on SDATAA and SDATAB is the result of the previous conversion. CS going low provides the leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with a second leading zero. Thus, the first falling clock edge on the serial clock has the leading zero provided and clocks out the second leading zero. The 14-bit result then follows with the final bit in the data transfer valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge depending on the SCLK frequency. The first rising edge of SCLK after the CS falling edge has the second leading zero provided and the 15th rising SCLK edge has DB0 provided. tACQUISITION CS t9 tCONVERT t6 1 3 2 B 4 t3 5 DB11 DB12 16 t5 t7 t4 SDATAA 0 0 DB13 SDATAB THREESTATE 2 LEADING ZEROS 15 DB10 DB2 t8 DB1 DB0 tQUIET 0 THREE-STATE 07757-024 t2 SCLK Figure 31. Serial Interface Timing Diagram CS t6 t2 SCLK 2 1 3 4 5 15 17 16 18 31 32 t5 THREESTATE 0 0 2 LEADING ZEROS t4 DB13 A DB12 A DB11 A t7 DB0 A 0 0 DB13 B DB12 B 2 ZEROS Figure 32. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs Rev. E | Page 21 of 24 DB1B DB0 B THREESTATE 07757-025 t3 SDATAA AD7357 Data Sheet APPLICATION SUGGESTIONS GROUNDING AND LAYOUT The analog and digital supplies to the AD7357 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The PCB that houses the AD7357 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates the use of easily separated ground planes. To provide optimum shielding for ground planes, a minimum etch technique is generally best. Sink the two AGND pins of the AD7357 in the AGND plane. Join the digital and analog ground plans in only one place. If the AD7357 is in a system where multiple devices require an AGND and DGND connection, still make the connection at one point only. Establish a star ground point as close as possible to the ground pins on the AD7357. Avoid running digital lines under the device because this couples noise onto the die. Allow the analog ground planes to run under the AD7357 to avoid noise coupling. The power supply lines to the AD7357 must use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. To avoid radiating noise to other sections of the board, shield fast switching signals, such as clocks with digital ground, and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, run traces on opposite sides of the board at right angles to each other. A microstrip technique is the best method, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is important; decouple all supplies with 10 μF tantalum capacitors parallel with 0.1 μF capacitors to GND. To achieve the best results from these decoupling components, place them as close as possible to the device, ideally right up against the device. The 0.1 μF capacitor must have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface-mount types. These low ESR and ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to logic switching. EVALUATING THE AD7357 PERFORMANCE The recommended layout for the AD7357 is outlined in evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the converter evaluation and development board (CED). The CED can be used in conjunction with the AD7357 evaluation board (as well as many other evaluation boards ending in the ED designator from Analog Devices, Inc.) to demonstrate and evaluate the ac and dc performance of the AD7357. The software allows the user to perform ac (fast Fourier transform) and dc (linearity) tests on the AD7357. The software and documentation are on a CD that is shipped with the evaluation board. Rev. E | Page 22 of 24 Data Sheet AD7357 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 0.20 0.09 SEATING PLANE 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 3.70 3.60 3.45 5.00 BSC PIN 1 INDICATOR (R 0.20) 0.65 BSC 18 14 13 1 4.00 BSC EXPOSED PAD 10 TOP VIEW PKG-003275 0.80 0.75 0.70 SEATING PLANE SIDE VIEW 0.35 0.30 0.25 0.50 0.40 0.30 0.20 REF 0.05 MAX 0.02 NOM 4 5 9 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 34. 18-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5mm × 4 mm Body, Very Very Thin Quad (CP-18-1) Dimensions shown in millimeters Rev. E | Page 23 of 24 2.70 2.60 2.45 05-18-2015-B INDEX AREA AD7357 Data Sheet ORDERING GUIDE Model 1, 2, 3, 4 AD7357BCPZ AD7357BCPZ-RL AD7357BRUZ AD7357BRUZ-500RL7 AD7357BRUZ-RL AD7357YRUZ AD7357YRUZ-500RL7 AD7357YRUZ-RL AD7357WYRUZ AD7357WYRUZ-RL EVAL-AD7357EDZ EVAL-CED1Z Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 18-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 18-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board Converter Evaluation and Development Board Package Option CP-18-1 CP-18-1 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. 3 The EVAL-AD7357EDZ can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z board for evaluation/demonstration purposes. 4 The EVAL-CED1Z is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the ED designator. 1 2 AUTOMOTIVE PRODUCTS The AD7357W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07757-0-12/15(E) Rev. E | Page 24 of 24