TI1 HPA02273ZQLR Flatlink transmitter Datasheet

SN75LVDS83C
SLLSE66A – OCTOBER 2010 – REVISED SEPTEMBER 2011
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FLATLINK™ TRANSMITTER
Check for Samples: SN75LVDS83C
FEATURES
1
•
2
•
•
•
•
•
•
LVDS Display Serdes Interfaces Directly to
LCD Display Panels with Integrated LVDS
Package: 4.5mm x 7mm BGA
1.8V up to 3.3V Tolerant Data Inputs to
Connect Directly to Low-Power, Low-Voltage
Application and Graphic Processors
Transfer Rate up to 85Mpps (Mega Pixel Per
Second); Pixel Clock Frequency Range 10MHz
to 85MHz
Suited for Display Resolutions Ranging From
HVGA up to HD With Low EMI
Operates From a Single 3.3V Supply and
148mW (typical) at 75MHz
•
•
•
•
28 Data Channels Plus Clock In Low-Voltage
TTL to 4 Data Channels Plus Clock Out
Low-Voltage Differential
Consumes Less Than 1mW When Disabled
Selectable Rising or Falling Clock Edge
Triggered Inputs
ESD: 5kV HBM
Support Spread Spectrum Clocking (SSC)
APPLICATIONS
•
•
•
LCD Display Panel Driver
UMPC and Netbook PC
Digital Picture Frame
DESCRIPTION
The SN75LVDS83C FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock
synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair
conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS
receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The
frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and
serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.
The frequency of CLKOUT is the same as the input clock, CLKIN.
swiv
Application
processor
(e.g. OMAPTM)
el
SN75LVDS83C
TM
FlatLink Transmitter
BGA Package: 4.5 x 7mm
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
SN75LVDS83C
SLLSE66A – OCTOBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The SN75LVDS83C requires no external components and little or no control. The data bus appears the same at
the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The
only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a
low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the
clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all
internal registers to a low-level.
The SN75LVDS83C is characterized for operation over ambient air temperatures of -10°C to 70°C.
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
SN75LVDS83CZQLR
LVDS83C in BGA package
56-pin ZQL LARGE Tape and Reel
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or
refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
MIN
MAX
Supply voltage range, VCC, IOVCC, LVDSVCC, PLLVCC (2)
-0.5
4
V
Voltage range at any output terminal
-0.5
VCC + 0.5
V
Voltage range at any input terminal
-0.5
IOVCC + 0.5
V
Continuous power dissipation
See the Thermal Information Table
–65
Storage temperature, Ts
Human Body Model (HBM)
ESD rating
(1)
(2)
(3)
(4)
(5)
2
(3)
all pins
150
°C
5
kV
Charged Device Model (CDM) (4) all pins
500
V
Machine Model (MM) (5) all pins
150
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
All voltages are with respect to the GND terminals.
In accordance with JEDEC Standard 22, Test Method A114-A.
In accordance with JEDEC Standard 22, Test Method C101.
In accordance with JEDEC Standard 22, Test Method A115-A.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
Supply voltage, VCC
2.8
3.3
3.6
LVDS output Supply voltage, LVDSVCC
2.8
3.3
3.6
PLL analog supply voltage, PLLVCC
2.8
3.3
3.6
1.62
1.8 / 2.5 / 3.3
3.6
IO input reference supply voltage, IOVCC
Power supply noise on any VCC terminal
UNIT
V
0.1
High-level input voltage, VIH
Low-level input voltage, VIL
IOVCC = 1.8V
IOVCC/2 + 0.3V
IOVCC = 2.5V
IOVCC/2 + 0.4V
IOVCC = 3.3V
IOVCC/2 + 0.5V
V
IOVCC = 1.8V
IOVCC/2 - 0.3V
IOVCC = 2.5V
IOVCC/2 - 0.4V
IOVCC = 3.3V
Differential load impedance, ZL
Operating free-air temperature, TA
V
IOVCC/2 - 0.5V
90
132
Ω
-10
70
C
THERMAL INFORMATION
THERMAL METRIC (1)
SN75LVDS83C
UNIT
ZQL (56 PINS)
θJA
Junction-to-ambient thermal resistance
67.1
°C/W
θJCtop
Junction-to-case (top) thermal resistance
25.2
°C/W
θJB
Junction-to-board thermal resistance
31.0
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
30.3
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
TIMING REQUIREMENTS
PARAMETER
Input clock period, tc
Input clock modulation
MIN
MAX
UNIT
11.76
100
ns
with modulation frequency 30kHz
8%
with modulation frequency 50kHz
6%
High-level input clock pulse width duration, tw
0.4 tc
Input signal transition time, tt
Data set up time, D0 through D27 before CLKIN (See Figure 3)
Data hold time, D0 through D27 after CLKIN
0.6 tc
ns
3
ns
2
ns
0.8
ns
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ZQL PACKAGE
(TOP VIEW)
6
5
4
3
2
1
D8
D7
D5
D4
D2
D1
D9
GND
D6
D3
D0
D27
D11
VCC
D10
GND
Y0P
Y0M
D13
D12
IOVCC
GND
Y1P
Y1M
D14
GND
GND
D16
D15
Y2P
Y2M
D17
D18
CLKSEL
GND
CLKP
CLKM
D19
GND
IOVCC
GND
Y3P
Y3M
D20
D21
D25
SHTDN
PLLVCC
GND
D22
D23
D24
D26
CLKIN
GND
K
J
H
G
F
LVDSVCC
E
D
C
B
A
ZQL PIN LIST
4
Ball #
Signal
Ball #
Signal
Ball #
Signal
A1
GND
A2
CLKIN
A3
D26
A4
D24
A5
D23
A6
D22
B1
GND
B2
PLLVCC
B3
SHTDN
B4
D25
B5
D21
B6
D20
C1
Y3M
C2
Y3P
C3
GND
C4
IOVCC
C5
GND
C6
D19
D1
CLKM
D2
CLKP
D3
GND
D4
CLKSEL
D5
D18
D6
D17
E1
Y2M
E2
Y2P
E3
ball not populated
E4
ball not populated
E5
D15
E6
D16
F1
LVDSVCC
F2
GND
F3
ball not populated
F4
ball not populated
F5
GND
F6
D14
G1
Y1M
G2
Y1P
G3
GND
G4
IOVCC
G5
D12
G6
D13
H1
Y0M
H2
Y0P
H3
GND
H4
D10
H5
VCC
H6
D11
J1
D27
J2
D0
J3
D3
J4
D6
J5
GND
J6
D9
K1
D1
K2
D2
K3
D4
K4
D5
K5
D7
K6
D8
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PIN FUNCTIONS
PIN
I/O
Y0P, Y0M, Y1P,
Y1M, Y2P, Y2M
Y3P, Y3M
DESCRIPTION
Differential LVDS data outputs.
Outputs are high-impedance when SHTDN is pulled low (de-asserted)
LVDS Out
Differential LVDS Data outputs.
Output is high-impedance when SHTDN is pulled low (de-asserted).
Note: if the application only requires 18-bit color, this output can be left open.
CLKP, CLKM
Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).
D0 – D27
Data inputs; supports 1.8V to 3.3V input voltage selectable by VDD supply. To connect a graphic
source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily
intuitive).
For input bit assignment see Figure 11 to Figure 14 for details.
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23,
and D27 to GND.
CLKIN
CMOS IN with
pulldn
Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
SHTDN
Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and
high (assert) for normal operation.
CLKSEL
Selects between rising edge input clock trigger (CLKSEL = VIH and falling edge input clock trigger
(CLKSEL = VIL).
VCC
3.3V digital supply voltage
IOVCC
PLLVCC
I/O supply reference voltage (1.8V up to 3.3V matching the GPU data output signal swing)
Power Supply (1)
3.3V PLL analog supply
LVDSVCC
3.3V LVDS output analog supply
GND
Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
(1)
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
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FUNCTIONAL BLOCK DIAGRAM
Parallel-Load 7-bit
Shift Register
D0, D1, D2, D3,
D4, D6, D7
7
Y0P
A,B,...G
SHIFT/LOAD
>CLK
Y0M
Parallel-Load 7-bit
Shift Register
D8, D9, D12, D13,
D14, D15, D18
7
Y1P
A,B,...G
SHIFT/LOAD
>CLK
Y1M
Parallel-Load 7-bit
Shift Register
D19, D20, D21, D22,
D24, D25, D26
7
Y2P
A,B,...G
SHIFT/LOAD
>CLK
Y2M
Parallel-Load 7-bit
Shift Register
D27, D5, D10, D11,
D16, D17, D23
7
Y3P
Y3M
A,B,...G
SHIFT/LOAD
>CLK
Control Logic
SHTDN
7X Clock/PLL
7XCLK
CLKIN
CLKOUTP
CLKOUTM
>CLK
CLKINH
CLKSEL
6
RISING/FALLING EDGE
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Dn
CLKIN
or
CLKIN
CLKOUT
Previous cycle
Next
Current cycle
Y0
D0-1
D7
D6
D4
D3
D2
D1
D0
D7+1
Y1
D8-1
D18
D15
D14
D13
D12
D9
D8
D18+1
Y2
D19-1
D26
D25
D24
D22
D21
D20
D19
D26+1
Y3
D27-1
D23
D17
D16
D11
D10
D5
D27
D23+1
Figure 1. Typical SN75LVDS83C Load and Shift Sequences
LVDSVCC
IOVCC
5W
D or
SHTDN
50W
7V
YnP or
YnM
10kW
300kW
7V
Figure 2. Equivalent Input and Output Schematic Diagrams
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VT
Input voltage threshold
|VOD|
Differential steady-state output voltage
magnitude
TEST CONDITIONS
MIN
TYP (1)
MAX
IOVCC/2
250
UNIT
V
450
mV
RL = 100Ω, See Figure 4
Δ|VOD|
Change in the steady-state differential
output voltage magnitude between
opposite binary states
VOC(SS)
Steady-state common-mode output
voltage
VOC(PP)
Peak-to-peak common-mode output
voltage
IIH
High-level input current
VIH = IOVCC
IIL
Low-level input current
VIL = 0 V
±10
μA
VOY = 0 V
±24
mA
1
See Figure 4
tR/F (Dx, CLKin) = 1ns
1.125
35
1.375
mV
V
35
mV
25
μA
IOS
Short-circuit output current
VOD = 0 V
±12
mA
IOZ
High-impedance state output current
VO = 0 V to VCC
±20
μA
Rpdn
Input pull-down integrated resistor on all
inputs (Dx, CLKSEL, SHTDN, CLKIN)
IOVCC = 1.8V
200
IOVCC = 3.3V
100
IQ
Quiescent current (average)
disabled, all inputs at GND;
SHTDN = VIL
2
kΩ
100
μA
SHTDN = VIH, RL = 100Ω (5 places),
grayscale pattern (Figure 5)
VCC = 3.3V, fCLK = 75MHz
ICC
CI
(1)
8
Supply current (average)
I(VCC) + I(PLLVCC) + I(LVDSVCC)
44.9
I(IOVCC) with IOVCC = 1.8V
0.1
mA
SHTDN = VIH, RL = 100Ω (5 places),
worst-case pattern (Figure 6),
VCC = 3.3V, fCLK = 75MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
55.1
I(IOVCC) with IOVCC = 1.8V
0.5
Input capacitance
2
mA
pF
All typical values are at VCC = 3.3V, TA = 25°C.
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SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
-0.15
0
0.15
ns
t0
Delay time, CLKOUT↑ after Yn valid
(serial bit position 0, equal D1, D9,
D20, D5)
t1
Delay time, CLKOUT↑ after Yn valid
(serial bit position 1, equal D0, D8,
D19, D27)
1
/7 tc - 0.15
1
/7 tc + 0.15
ns
t2
Delay time, CLKOUT↑ after Yn valid
(serial bit position 2, equal D7, D18,
D26. D23)
2
/7 tc - 0.15
2
/7 tc + 0.15
ns
t3
Delay time, CLKOUT↑ after Yn valid
(serial bit position 3; equal D6, D15,
D25, D17)
3
/7 tc - 0.15
3
/7 tc + 0.15
ns
t4
Delay time, CLKOUT↑ after Yn valid
(serial bit position 4, equal D4, D14,
D24, D16)
4
/7 tc - 0.15
4
/7 tc + 0.15
ns
t5
Delay time, CLKOUT↑ after Yn valid
(serial bit position 5, equal D3, D13,
D22, D11)
5
/7 tc - 0.15
5
/7 tc + 0.15
ns
t6
Delay time, CLKOUT↑ after Yn valid
(serial bit position 6, equal D2, D12,
D21, D10)
6
/7 tc - 0.15
6
/7 tc + 0.15
ns
tc(o)
Output clock period
Δtc(o)
See Figure 7, tC = 13.3ns,
|Input clock jitter| < 25ps (2)
tc
Output clock cycle-to-cycle jitter
(3)
tC = 13.3ns; clean reference clock, see
Figure 8
±26
tC = 13.3ns with 0.05UI added noise
modulated at 3MHz, see Figure 8
±44
High-level output clock pulse duration
tr/f
Differential output voltage transition
time (tr or tf)
See Figure 4
ten
Enable time, SHTDN↑ to phase lock
(Yn valid)
tdis
Disable time, SHTDN↓ to off-state
(CLKOUT high-impedance)
(1)
(2)
(3)
ps
4
tw
ns
200
/7 tc
250
ns
800
ps
f(clk) = 85MHz, See Figure 9
15
µs
f(clk) = 85MHz, See Figure 10
13
ns
All typical values are at VCC = 3.3 V, TA = 25°C.
|Input clock jitter| is the magnitude of the change in the input clock period.
The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed
over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
PARAMETER MEASUREMENT INFORMATION
tsu
thold
Dn
CLKIN
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns.
CLKSEL = 0V.
Figure 3. Set Up and Hold Time Definition
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PARAMETER MEASUREMENT INFORMATION (continued)
49.9W ± 1% (2 PLCS)
YP
VOD
VOC
YM
100%
80%
VOD(H)
0V
VOD(L)
20%
0%
tf
tr
VOC(PP)
VOC(SS)
VOC(SS)
0V
Figure 4. Test Load and Voltage Definitions for LVDS Outputs.
CLKIN
D0,8,16
D1,9,17
D2,10,18
D3,11,19
D4-7,12-15,20-23
D24-27
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 5. 16 Grayscale Test Pattern
10
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PARAMETER MEASUREMENT INFORMATION (continued)
T
CLKIN
EVEN Dn
ODD Dn
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 6. Worst-Case Power Test Pattern
t7
CLKIN
CLKOUT
t6
t5
t4
t3
t2
t0
Yn
t1
VOD(H)
~2.5V
CLKOUT
or Yn
1.40V
CLKIN
0.00V
~0.5V
VOD(L)
t7
t0-6
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 7. SN75LVDS83C Timing Definitions
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PARAMETER MEASUREMENT INFORMATION (continued)
Reference
+
Device
Under
Test
VCO
+
Modulation
v(t) = A sin(2 pfmodt)
HP8656B Signal
Generator,
0.1 MHz-990 MHz
RF Output
HP8665A Synthesized
Signal Generator,
0.1 MHz-4200 MHz
Device Under
Test
RF Output
Modulation Input
CLKIN
CLKOUT
DTS2070C
Digital
TimeScope
Input
Figure 8. Output Clock Jitter Test Set Up
CLKIN
Dn
ten
SHTDN
Invalid
Yn
Valid
Figure 9. Enable Time Waveforms
CLKIN
tdis
SHTDN
CLKOUT
Figure 10. Disable Time Waveforms
12
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APPLICATION INFORMATION
This section describes the power up sequence, provides information on device connectivity to various GPU and
LCD display panels, and offers a pcb routing example.
Power Up Sequence
The SN75LVDS83C does not require a specific power up sequence.
It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to
GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while
all other device blocks are still powered down.
It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device
will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true
input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output
stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still
lower than normal mode.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (SN75LVDS83C SHTDN input initially low):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t occur.
3. Enable video source output; start sending black video data.
4. Toggle LVDS83C shutdown to SHTDN = VIH.
5. Send >1ms of black video data; this allows the LVDS83C to be phase locked, and the display to show black
data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (SN75LVDS83C SHTDN input initially high):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set SN75LVDS83C input SHTDN = GND; wait for 250ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
Signal Connectivity
While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the
industry has aligned over the years on a certain data format (bit order). Figure 11 through Figure 14 show how
each signal should be connected from the graphic source through the SN75LVDS83C input, output and LVDS
LCD panel input. Detailed notes are provided with each figure.
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13
SN75LVDS83C
SLLSE66A – OCTOBER 2010 – REVISED SEPTEMBER 2011
SN75LVDS83C
4.8k
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
Y0M
Y0P
Y2M
Y2P
Y3M
Y3P
100
to column
driver
100
FPC
Cable
Panel connector
Y1M
Y1P
LVDS
timing
Controller
(8bpc, 24bpp)
100
100
to row driver
CLKOUTM
CLKOUTP
100
VCC
PLLVCC
LVDSVCC
24-bpp LCD Display
GND
SHTDN
D27
D5
D0
D1
D2
D3
D4
D6
D10
D11
D7
D8
D9
D12
D13
D14
D16
D17
D15
D18
D19
D20
D21
D22
D24
D25
D26
D23
CLKIN
CLKSEL
FORMAT2 (See Note A)
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
IOVCC
VDDGPUIO
GND
R0(LSB)
R1
R2
R3
R4
R5
R6
R7(MSB)
G0(LSB)
G1
G2
G3
G4
G5
G6
G7(LSB)
B0(LSB)
B1
B2
B3
B4
B5
B6
B7(MSB)
HSYNC
VSYNC
ENABLE
RSVD (Note C)
CLK
FORMAT1
Main board connector
24-bpc GPU
www.ti.com
3.3V
C2
3.3V
C3
(See Note B)
Main Board
Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each
color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of
each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by
checking the LCD display data sheet.
•
Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the
dominate data format for LCD panels.
•
Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
•
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
•
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.
Note D. RSVD must be driven to a valid logic level. All unused SN75LVDS83C inputs must be tied to a valid logic
level.
Figure 11. 24-Bit Color Host to 24-bit LCD Panel Application
14
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SN75LVDS83C
B0(LSB)
B1
B2
B3
B4
B5(MSB)
C1
100
FPC
Cable
Panel connector
to column
driver
CLKOUTM
CLKOUTP
LVDS
timing
Controller
(6-bpc, 18-bpp)
100
100
to row driver
18-bpp LCD Display
Y3M
Y3P
4.8k
1.8V or 2.5V
or 3.3V
Y1M
Y1P
Y2M
Y2P
IOVCC
VDDGPUIO
GND
HSYNC
VSYNC
ENABLE
RSVD
CLK
100
Rpullup
(See Note A)
VCC
PLLVCC
LVDSVCC
G0(LSB)
G1
G2
G3
G4
G5(MSB)
Y0M
Y0P
Main board connector
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
GND
R0(LSB)
R1
R2
R3
R4
R5(MSB)
SHTDN
CLKSEL
18-bpp GPU
3.3V
C2
3.3V
C3
Rpulldown
(See Note B)
Main Board
Note A. Leave output Y3 NC.
Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
•
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
•
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 12. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application
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15
SN75LVDS83C
SLLSE66A – OCTOBER 2010 – REVISED SEPTEMBER 2011
12-bpp GPU
www.ti.com
SN75LVDS83C
(See Note B)
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
(See Note B)
B2 or VCC
B3 or GND
B0
B1
B2
B3(MSB)
C1
FPC
Cable
t
Panell connector
Main board connector
CLKOUTM
CLKOUTP
LVDS
timing
Controller
(6-bpc, 18-bpp)
100
100
to row driver
18-bpp LCD Display
Y3M
Y3P
4.8k
1.8V or 2.5V
or 3.3V
100
Y2M
Y2P
IOVCC
VDDGPUIO
GND
HSYNC
VSYNC
ENABLE
RSVD
CLK
to column
driver
Rpullup
(See Note A)
VCC
PLLVCC
LVDSVCC
G2 or VCC
G3 or GND
G0
G1
G2
G3(MSB)
100
Y1M
Y1P
SHTDN
CLKSEL
(See Note B)
Y0M
Y0P
GND
R2 or VCC
R3 or GND
R0
R1
R2
R3(MSB)
3.3V
C2
3.3V
C3
Rpulldown
(See Note C)
Main Board
Note A. Leave output Y3 N.C.
Note B. R3, G3, B3: this MSB of each color also connects to the 5th bit of each color for increased dynamic range of
the entire color space at the expense of none-linear step sizes between each step. For linear steps with less dynamic
range, connect D1, D8, and D18 to GND.
R2, G2, B2: these outputs also connects to the LSB of each color for increased, dynamic range of the entire color
space at the expense of none-linear step sizes between each step. For linear steps with less dynamic range, connect
D0, D7, and D15 to VCC.
Note C.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
•
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
•
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 13. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application
16
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SN75LVDS83C
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www.ti.com
SN75LVDS83C
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
G7(MSB)
B0 and B1: NC
(See Note B)
B2
B3
B4
B5
B6
B7(MSB)
B0 and B1: NC
(See Note B)
CLKOUTM
CLKOUTP
C1
FPC
Cable
LVDS
timing
Controller
(6-bpc, 18-bpp)
100
100
to row driver
18-bpp LCD Display
Y3M
Y3P
4.8k
1.8V or 2.5V
or 3.3V
100
Y2M
Y2P
IOVCC
VDDGPUIO
GND
HSYNC
VSYNC
ENABLE
RSVD
CLK
to column
driver
Y1M
Y1P
t
Panell connector
G2
G3
G4
G5
G6
100
Main board connector
G0 and G1: NC
(See Note B)
Y0M
Y0P
SHTDN
CLKSEL
R7(MSB)
Rpullup
(See Note A)
VCC
PLLVCC
LVDSVCC
R2
R3
R4
R5
R6
GND
24-bpp GPU
R0 and R1: NC
(See Note B)
3.3V
C2
3.3V
C3
Rpulldown
(See Note C)
Main Board
Note A. Leave output Y3 NC.
Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down
to18-bit per pixel.
NoteC.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
•
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
•
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 14. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application
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SN75LVDS83C
SLLSE66A – OCTOBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
Typical Application Schematic
Figure 15 represents the schematic drawing of the SN75LVDS83C evaluation module.
J1
U1H
GND1
GND2
GND3
GND4
GND5
GND6
GND7
PLLGND
LVDSGND1
LVDSGND2
J3
CLKM
CLKP
Y0P
Y0M
Y1P
Y1M
Y2P
Y2M
IOVCC
R4
4.7k
R5
4.7k
R6
4.7k
R7
4.7k
R8
4.7k
R9
4.7k
Y3P
Y3M
R10
4.7k
JMP1
U1B
J2
K1
K2
J3
K3
J4
K5
D0
D1
D2
D3
D4
D6
D7
D1
D2
G2
G1
J5
E1
E2
sma_surface
J6
sma_surface
C2
C1
J7
sma_surface
SN75LVDS83CZQL
J8
sma_surface
J9
sma_surface
14
Header 7x2
J10
sma_surface
IOVCC
R11
4.7k
R12
4.7k
R13
4.7k
R14
4.7k
R15
4.7k
R16
4.7k
R17
4.7k
sma_surface
JMP2
U1C
K6
J6
G5
G6
F6
E5
D5
J4
sma_surface
H2
H1
1 2
SN75LVDS83CZQL
D8
D9
D12
D13
D14
D15
D18
sma_surface
U1A
SN75LVDS83CZQL
D0
D1
D2
D3
D4
D6
D7
J2
sma_surface
C3
C5
D3
F5
G3
H3
J5
A1
B1
F2
D8
D9
D12
D13
D14
D15
D18
1 2
IOVCC
IOVCC
14
SN75LVDS83CZQL
R2
R1
4.7k
Header 7x2
IOVCC
R18
4.7k
R19
4.7k
R20
4.7k
R21
4.7k
R22
4.7k
R23
4.7k
R24
4.7k
JMP6
U1G
JMP3
U1D
C6
B6
B5
A6
A4
B4
A3
D19
D20
D21
D22
D24
D25
D 26
D19
D20
D21
D22
D24
D25
D26
SHTDN
CLKSEL
1 2
B3
D4
SHTDN
CLKSEL
1 2
3 4
Header 2x2
SN75LVDS83CZQL
14
U1J
IOVCC
R25
4.7k
R26
4.7k
R27
4.7k
R28
4.7k
R29
4.7k
R30
4.7k
E3
E4
F3
F4
NC1
NC2
NC3
NC4
Header 7x2
SN75LVDS83CZQL
SN75LVDS83CZQL
R31
4.7k
JMP4
U1E
K4
H4
H6
E6
D6
A5
J1
D5
D10
D11
D16
D17
D23
D27
D5
D10
D11
D16
D17
D23
D27
VCC
1 2
IOVCC
U1I
VCC
PLLVCC
LVDSVCC
14
IOVCC1
IOVCC2
Header 7x2
SN75LVDS83CZQL
G4
B2
F1
H5
C4
SN75LVDS83CZQL
VCC
VCC
C31
1uF
C32
0.1uF
C33
0.01uF
VCC
C34
1uF
C35
0.1uF
C36
0.01uF
IOVCC
C40
1uF
C41
0.1uF
C42
0.01uF
C37
1uF
C38
0.1uF
C39
0.01uF
PLACE UNDER LVDS83C
(bottom pcb side)
Figure 15. Schematic Example (SN75LVDS83C Evaluation Board)
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PCB Routing
Figure 16 and Figure 17 show a possible breakout of the data input and output signals from the BGA package.
R1
R2
R3
R4
R5
R6
R7
R8
G0
G1
D8
D7
D5
D4
D2
D1
D9
GND
D6
D3
D0
D27
D11
VCC
D10
GND
Y0P
Y0M
D13
D12
IOVCC
GND
Y1P
Y1M
D14
GND
D16
D15
D17
D18
CLKSEL
D19
GND
IOVCC
D20
D21
D25
D22
D23
D24
G2
G3
G4
G5
G6
G7
B0
B1
LVDS GND LVDS VCC
Y2P
Y2M
GND
CLKP
CLKM
GND
Y3P
Y3M
B2
B3
B4
B5
B6
SHTDN PLLVCC LVDS GND
+PLL GND
D26
CLKIN
PLL GND
B7
HS
VS
EN
CLK
Figure 16. 24-Bit Color Routing (See Figure 11 for the Schematic)
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SN75LVDS83C
SLLSE66A – OCTOBER 2010 – REVISED SEPTEMBER 2011
G1
G0
D8
D7
www.ti.com
R5 R4 R3 R2
D5
D4
D2
R1
R0
D1
To GND
G2
G3
D9
GND
D6
D3
D0
D27
D11
VCC
D10
GND
Y0P
Y0M
D13
D12
IOVCC
GND
Y1P
Y1M
D14
GND
D16
D15
D17
D18
CLKSEL
D19
GND
IOVCC
G4
G5
B0
LVDS GND LVDS VCC
To GND
B1
Y2P
Y2M
GND
CLKP
CLKM
GND
Y3P
Y3M
B2
remains
unconnected
B3
B4
D20
D21
D22
D23
D25
SHTDN
PLLVCC LVDS GND
+PLL GND
CLKIN
B5
D24
PLL GND
D26
HS VS EN
CLK
Figure 17. 18-Bit Color Routing (See Figure 12, Figure 13, and Figure 14 for the Schematic)
20
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SN75LVDS83C
SLLSE66A – OCTOBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
REVISION HISTORY
Changes from Original (May 2009) to Revision A
•
Page
Multiply changes throughout the data sheet ......................................................................................................................... 1
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21
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HPA02273ZQLR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQL
56
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-2-260C-1 YEAR
-10 to 70
LVDS83C
SN75LVDS83CZQLR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQL
56
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-2-260C-1 YEAR
-10 to 70
LVDS83C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN75LVDS83CZQLR
Package Package Pins
Type Drawing
BGA MI
CROSTA
R JUNI
OR
ZQL
56
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
4.8
B0
(mm)
K0
(mm)
P1
(mm)
7.3
1.5
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN75LVDS83CZQLR
BGA MICROSTAR
JUNIOR
ZQL
56
1000
336.6
336.6
28.6
Pack Materials-Page 2
PACKAGE OUTLINE
ZQL0056A
JRBGA - 1 mm max height
SCALE 2.100
PLASTIC BALL GRID ARRAY
4.6
4.4
B
A
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.35
TYP
0.15
BALL TYP
0.1 C
3.25 TYP
(0.625) TYP
SYMM
K
(0.575) TYP
J
H
G
5.85
TYP
SYMM
F
E
D
C
56X
NOTE 3
B
A
0.65 TYP
BALL A1 CORNER
1
2
3
4
5
0.45
0.35
0.15
0.08
C B A
C
6
0.65 TYP
4219711/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. No metal in this area, indicates orientation.
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EXAMPLE BOARD LAYOUT
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
56X ( 0.33)
2
1
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
( 0.33)
METAL
( 0.33)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219711/B 01/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
56X ( 0.33)
(0.65) TYP
1
2
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4219711/B 01/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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