FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM FEATURES GENERAL DESCRIPTION Fast access time : 55ns Low power consumption: Operating current : 20/18mA (TYP.) Standby current : 2µA (TYP.) Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 2.0V (MIN.) Lead free and green package available Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA The AS6C2016 is a 2,097,152-bit low power CMOS static random access memory organized as 131,072 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C2016 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C2016 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS6C2016 (I) Operating Temperature -40 ~ 85℃ FEBRUARY/2008, V 1.c Vcc Range 2.7 ~ 5.5V Speed 55ns Alliance Memory Inc. Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 2µA 20/18mA Page 1 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0-A16 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# WE# OE# LB# UB# PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A16 Address Inputs DQ0 – DQ15 Data Inputs/Outputs DECODER I/O DATA CIRCUIT 128Kx16 MEMORY ARRAY CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground COLUMN I/O CONTROL CIRCUIT FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 2 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM PIN CONFIGURATION A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# 5 40 UB# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 Vcc 11 34 Vss Vss 12 33 Vcc DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 AS6C2016 A0 CE# A LB# OE# A0 B DQ8 UB# A3 DQ9 C DQ9 DQ10 D Vss A2 NC A4 CE# DQ0 A5 A6 DQ1 DQ2 DQ11 NC A7 DQ3 Vcc E Vcc DQ12 NC A16 DQ4 Vss F DQ14 DQ13 A14 29 DQ8 28 NC 18 27 A8 A15 19 26 A9 A14 20 25 A10 G DQ15 NC A13 21 24 A11 H NC A12 22 23 NC 1 DQ7 16 WE# 17 A16 A1 A15 DQ5 DQ6 A12 A13 WE# DQ7 A8 A9 A10 A11 NC 2 3 4 TFBGA 5 6 TSOP II ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) TA TSTG PD IOUT TSOLDER RATING -0.5 to 6.5 -0.5 to VCC+0.5 -40 to 85(I grade) -65 to 150 1 50 260 UNIT V V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 3 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# OE# H X L L L L L L L L X X H H L L L X X X WE# LB# X X H H H H H L L L UB# X H L X L H L L H L X H X L H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT High – Z DIN High – Z DIN DIN DIN SUPPLY CURRENT ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS TEST CONDITION SYMBOL PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL > VIN > VSS Input Leakage Current ILI VCC = = > VOUT > VSS, Output Leakage VCC = = ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min., II/O = 0mA ICC CE# =0.2V, - 55 Others at 0.2V or VCC-0.2V Average Operating Power supply Current Cycle time = 1µs ICC1 CE# = 0.2V , II/O = 0mA Other pins at 0.2V or VCC - 0.2V > VCC - 0.2V Standby Power CE# = ISB1 Supply Current Others at 0.2V or VCC - 0.2V MIN. 2.7 2.4 - 0.2 -1 TYP. 3.0 - *4 MAX. 5.5 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.4 - 2.7 - 0.4 V V - 20 60 mA - 4 10 mA - 2 50 µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. O Typical values are measured at VCC = VCC(TYP.) and TA = 25 C CAPACITANCE (TA = 25 C , f = 1.0MHz) O PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 4 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW AS6C2016-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 55 25 10 - UNIT AS6C2016-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 50 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 5 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 6 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout T OW High-Z (4) (4) tDW tDH Data Valid Din WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din FEBRUARY/2008, V 1.c tDH Data Valid Alliance Memory Inc. Page 7 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tAS tCW tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 8 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# > V = CC - 0.2V VCC = 2.0V CE# > IDR = VCC - 0.2V Other pins at 0.2V or VCC-0.2V See Data Retention tCDR Waveforms (below) tR MIN. 2.0 TYP. - MAX. 5.5 UNIT V - 1 20 µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) > VDR = 2.0V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR > CE# = Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (LB#, UB# controlled) > VDR = 2.0V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# VIH FEBRUARY/2008, V 1.c tR LB#,UB# > = Vcc-0.2V Alliance Memory Inc. VIH Page 9 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM PACKAGE OUTLINE DIMENSION θ Ⅱ Package Outline Dimension 44-pin 400mil TSOP-Ⅱ SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0 FEBRUARY/2008, V 1.c DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 Alliance Memory Inc. Page 10 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 11 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM ORDERING INFORMATION Alliance Organization VCC Range Package Operating Temp Speed ns AS6C2016-55ZIN 128K x 16 2.7 - 5.5V 44pin TSOP II Industrial ~ -40 F - 85 F 55 AS6C2016-55BIN 128K x 16 2.7 - 5.5V 48ball TFBGA Industrial ~ -40 F - 85 F 55 PART NUMBERING SYSTEM AS6C 2016 -55 Device Number low power S RAM prefix 20 = 2M 16 =x16 FEBRUARY/2008, V 1.c Access Time X X Package Option Temperature Range 44pin TSOP II I = Industrial 48ball TFBGA (-40 to + 85 C) Alliance Memory Inc. N N = Lead Free RoHS compliant part Page 12 of 13 FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM ® Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211 Copyright © Alliance Memory All Rights Reserved www.alliancememory.com © Copyright 2007 Alliance Memory, Inc. All rights reserved. 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