ON NCV47411 3.3 v to 20 v adjustable dual ldo with adjustable current limit and 3.3 v Datasheet

NCV47411
3.3 V to 20 V Adjustable
Dual LDO with Adjustable
Current Limit and 3.3 V
Logic Compatible Enable
Inputs
The NCV47411 is a dual integrated low dropout regulator with
100 mA per channel designed for use in harsh automotive
environments. It includes wide operating temperature and input
voltage ranges. The device is offered with adjustable voltage version
available in 3% output voltage accuracy. It has a high peak input
voltage tolerance and reverse input voltage protection. It also provides
overcurrent protection, overtemperature protection and enable for
control of the state of the output voltage of each channel. The
integrated current sense feature provides diagnosis and system
protection functionality. The current limit of the device is adjustable
by resistor connected to CSO pin for each channel. CSO pin output
current creates voltage drop across CSO resistor which is proportional
to output current of each channel.
Features
•
•
•
•
•
Two Adjustable Outputs: (from 3.3 V to 20 V) ±3% Output Voltage
Enable Inputs (3.3 V Logic Compatible Thresholds)
Adjustable Current Limit up to 150 mA
Protection Features:
♦ Current Limitation
♦ Thermal Shutdown
♦ Reverse Input Voltage
This is a Pb−Free Device
Typical Applications
•
•
•
•
Audio and Infotainment System
Instrument Cluster
Navigation
Satellite Radio
© Semiconductor Components Industries, LLC, 2013
December, 2013 − Rev. 1
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MARKING
DIAGRAM
14
NCV4
7411
ALYWG
G
TSSOP−14 EP
CASE 948AW
14
1
1
NCV47411
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Top View
1
Vin
CSO1
EN1
GND
EN2
CSO2
Vin
14
EPAD
Vout1
ADJ1
NC
NC
NC
ADJ2
Vout2
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
1
Publication Order Number:
NCV47411/D
NCV47411
Vin**
Vout1
Cin
1 mF
Cb1*
R11
ADJ1
CSO1
EN1
NCV47411
R12
CCSO1
1 mF
Cout1
10 mF
RCSO1
Vout2
Cb2*
R21
ADJ2
R22
CSO2
EN2
GND
CCSO2
1 mF
Cout2
10 mF
RCSO2
Cb1*, Cb2* − Optional, see Regulator Stability Considerations section
** − Both Vin pins must be connected together on PCB
Figure 1. Application Schematic
(See Application Section for More Datails)
Vin
Vout1
VOLTAGE
REFERENCE
EN1
VREF 1
VREF 2
ENABLE
SATURATION
PROTECTION
THERMAL
SHUTDOWN
ICSO1 = Iout1 / 50
PASS DEVICE 1
AND
CURRENT MIRROR
SP1
+
VREF 2
2.55 V
−
TSD1
CSO1
SP1
+
GND
VREF 1
1.275 V
−
ADJ1
TSD1
Vin
EN2
Vout2
ENABLE
SATURATION
PROTECTION
THERMAL
SHUTDOWN
ICSO2 = Iout2 / 50
PASS DEVICE 2
AND
CURRENT MIRROR
SP2
+ VREF 2
2.55 V
−
TSD2
CSO2
SP2
+
VREF 1
1.275 V
−
TSD2
Figure 2. Simplified Block Diagram
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2
ADJ2
NCV47411
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
1
Vin
Description
2
CSO1
3
EN1
Enable Input 1; low level disables the Channel 1.
4
GND
Power Supply Ground.
5
EN2
Enable Input 2; low level disables the Channel 2.
6
CSO2
7
Vin
8
Vout2
Regulated Output Voltage 2.
9
ADJ2
Adjustable Voltage Setting Input 2. See Application Section for more details.
10
NC
Not Connected. (Not internally bonded)
Power Supply Input. (All Vin pins must be connected on PCB)
Current Sense Output 1, Current Limit setting and Output Current value information. See Application
Section for more details.
Current Sense Output 2, Current Limit setting and Output Current value information. See Application
Section for more details.
Power Supply Input. (All Vin pins must be connected on PCB)
11
NC
Not Connected. (Not internally bonded)
12
NC
Not Connected. (Not internally bonded)
13
ADJ1
Adjustable Voltage Setting Input 1. See Application Section for more details.
14
Vout1
Regulated Output Voltage 1.
EPAD
EPAD
Exposed Pad is connected to Ground. Connect to GND plane on PCB.
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NCV47411
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
Vin
−42
45
V
Enable Input Voltage
VEN1,2
−42
45
V
ADJ Input Voltage
VADJ1,2
−0.3
10
V
CSO Voltage
VCSO1,2
−0.3
7
V
Vout1,2
−1
40
V
Junction Temperature
TJ
−40
150
°C
Storage Temperature
TSTG
−55
150
°C
Input Voltage DC
Output Voltage
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. ESD CAPABILITY (Note 1)
Rating
Symbol
Min
Max
Unit
ESD Capability, Human Body Model
ESDHBM
−2
2
kV
ESD Capability, Machine Model
ESDMM
−200
200
V
1. This device series incorporates ESD protection and is tested by the following methods:
a) ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010)
b) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Table 4. LEAD SOLDERING TEMPERATURE AND MSL (Note 2)
Rating
Symbol
Min
Max
Unit
Moisture Sensitivity Level
MSL
1
1
−
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions
TSLD
−
265 peak
°C
2. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 5. THERMAL CHARACTERISTICS (Note 3)
Rating
Symbol
Value
Unit
°C/W
Thermal Characteristics (single layer PCB)
Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)
RθJA
RψJL
52
9.5
Thermal Characteristics (4 layers PCB)
Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)
RθJA
RψJL
28.5
8.4
°C/W
3. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
4. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate, assuming equal power dissipation
of both channels. Single layer − according to JEDEC51.3, 4 layers − according to JEDEC51.7
Table 6. RECOMMENDED OPERATING RANGES
Rating
Input Voltage (Note 5)
Nominal Output Voltages
Output Current Limit (Note 6)
Junction Temperature
Current Sense Output (CSO) Capacitor
Symbol
Min
Max
Unit
Vin
4.4
40
V
Vout_nom1,2
3.3
20
V
ILIM1,2
10
150
mA
TJ
−40
150
°C
CCSO1,2
1.0
4.7
mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Minimum Vin = 4.4 V or (Vout_nom1,2 + 0.5 V), whichever is higher.
6. Corresponding RCSO1,2 is in range from 12.75 kW down to 850 W.
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NCV47411
Table 7. ELECTRICAL CHARACTERISTICS
Vin = 13.5 V, VEN1,2 = 3.3 V, RCSO1,2 = 0 W, CCSO1,2 = 1 mF, Cin = 1 mF, Cout1,2 = 10 mF, ESR = 1.5 W. Min and Max values are valid for
temperature range −40°C ≤ TJ ≤ +150°C unless noted otherwise and are guaranteed by test, design or statistical correlation. Typical
values are referenced to TJ = 25°C (Note 7)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Vout1,2
−3
−
+3
%
REGULATOR OUTPUTS
Output Voltage (Accuracy %)
(Note 8)
Vin = Vin_min to 40 V
Iout1,2 = 5 mA to 100 mA
Line Regulation
(Note 8)
Vin = Vin_min to (Vout_nom1,2 + 20 V)
Iout1,2 = 5 mA
Regline1,2
−
0.05
1.0
%
Load Regulation
Vin = (Vout_nom1,2 + 8.5 V)
Iout1,2 = 5 mA to 100 mA
Regload1,2
−
0.05
1.4
%
Dropout Voltage
(Note 9)
Vout_nom1,2 = 5 V, Iout1,2 = 100 mA
VDO1,2 = Vin − Vout1,2
VDO1,2
−
250
550
mV
IDIS
−
0.07
10
mA
DISABLE AND QUIESCENT CURRENTS
Disable Current
VEN1,2 = 0 V
Quiescent Current,
Iq = Iin − (Iout1 + Iout2)
Iout1,2 = 500 mA,
Vin = (Vout_nom1,2 + 8.5 V)
Iq
−
235
370
mA
Quiescent Current,
Iq = Iin − (Iout1 + Iout2)
Iout1,2 = 100 mA,
Vin = (Vout_nom1,2 + 8.5 V)
Iq
−
15
50
mA
Vout1,2 = 0.9 x Vout_nom1,2
Vin = (Vout_nom1,2 + 8.5 V)
ILIM1,2
150
−
−
mA
PSRR1,2
−
75
−
dB
Vn1,2
−
130
−
mVrms
0.99
−
1.8
1.9
−
2.31
2
9
20
−
1.6
−
VCSO_Ilim1.2
2.346
(−8 %)
2.55
2.754
(+8 %)
V
VCSO1,2
−
−
3.3
V
Iout1,2/ICSO1,2
−
(−10 %)
50
−
(+10 %)
−
ICSO_off1,2
−
−
10
mA
TSD1,2
150
−
195
°C
CURRENT LIMIT PROTECTION
Current Limit
PSRR & NOISE
Power Supply Ripple Rejection
f = 100 Hz, 0.5 Vp−p1,2
Output Noise Voltage
f = 10 Hz to 100 kHz, Cb1,2 = 10 nF
ENABLE
Vth(EN1,2)
Enable Input Threshold Voltage
Logic Low (OFF)
Logic High (ON)
Vout1,2 ≤ 0.1 V
Vout1,2 ≥ 0.9 x Vout_nom1,2
Enable Input Current
VEN1,2 = 3.3 V
Turn On Time
from Enable ON to 90% of Vout
Iout1,2 = 100 mA, Cb1,2 = 10 nF,
Rn1 = 82 kW, Rn2 = 27 kW
IEN1,2
V
ton
mA
ms
OUTPUT CURRENT SENSE
CSO Voltage Level at Current Limit
Vout1,2 = 0.9 x Vout_nom1,2,
(Vout_nom1,2 = 5 V)
RCSO1,2 = 2.55 kW
CSO Transient Voltage Level
CCSO1,2 = 4.7 mF, RCSO1,2 = 2.55 kW
Iout1,2 pulse from 10 mA to 100 mA,
tr = 1 ms
Output Current to CSO Current Ratio
(Note 10)
VCSO1,2 = 2 V, Iout1,2 = 10 mA to 100 mA
(Vout_nom1,2 = 5 V)
CSO Current at no Load Current
VCSO1,2 = 0 V, Iout1,2 = 0 mA,
(Vout_nom1,2 = 5 V)
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Iout1,2 = 2.5 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA ≈ TJ. Low duty cycle
pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
8. Minimum input voltage Vin_min is 4.4 V or (Vout_nom1,2 + 1 V) whichever is higher
9. Measured when the output voltage Vout1,2 has dropped by 2% of Vout1,2 from the nominal value obtained at Vin = Vout_nom1,2 + 8.5 V.
10. Not guaranteed in dropout.
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NCV47411
TYPICAL CHARACTERISTICS
400
Vin = 13.5 V
Iout1,2 = 5 mA
1.29
Iq, QUIESCENT CURRENT (mA)
VREF1, REFERENCE VOLTAGE (V)
1.3
1.28
1.27
1.26
1.25
1.24
1.23
−40 −20
350
300
250
200
150
100
0
0
0
20 40 60 80 100 120 140 160
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Reference Voltage vs. Temperature
5
10
35
40
45
0
TJ = 25°C
Iout1,2 = 5 mA
TJ = 25°C
Rout1,2 = 4.7 kW
Vout_nom1,2 = 5 V
−1
Iin, INPUT CURRENT (mA)
1.2
1
0.8
0.6
0.4
0.2
−2
−3
−4
−5
−6
−7
0
0
0.5
1.5
1
2
2.5
3
3.5
4
4.5
−8
−45
5
−40
−35
Vin, INPUT VOLTAGE (V)
Figure 5. Reference Voltage vs. Input Voltage
−30 −25 −20 −15 −10
Vin, INPUT VOLTAGE (V)
−5
0
Figure 6. Input Current vs. Input Voltage
(Reverse Input Voltage)
490
Vin = 13.5 V
Vout_nom1,2 = 5 V
450
ILIM1,2, OUTPUT CURRENT LIMIT
(mA)
500
VDO1,2, DROPOUT VOLTAGE (mV)
15
20
25
30
Vin, INPUT VOLTAGE (V)
Figure 4. Quiescent Current vs. Input Voltage
1.4
VREF1, REFERENCE VOLTAGE (V)
TJ = 25°C
Iout1,2 = 500 mA
Vout_nom1,2 = 5 V
50
TJ = 150°C
400
350
300
TJ = 25°C
250
200
TJ = −40°C
150
100
50
0
0
20
40
60
100
120
80
Iout1,2, OUTPUT CURRENT (mA)
140
450
TJ = −40°C
430
410
TJ = 25°C
390
370
TJ = 150°C
350
330
310
290
270
160
Vout1,2 = 4.5 V
Vout_nom1,2 = 5 V
470
0
Figure 7. Dropout Voltage vs. Output Current
5
10
15
20
25
30
35
Vin, INPUT VOLTAGE (V)
40
Figure 8. Output Current Limit vs. Input
Voltage
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45
NCV47411
160
3.0
Vout1,2 = 3.3 V to 20 V
TJ = 25°C
140
VCSO1,2, CSO VOLTAGE (V)
ILIM1,2, OUTPUT CURRENT LIMIT (mA)
TYPICAL CHARACTERISTICS
120
100
80
60
40
20
0
Vout1,2 = 3.3 V to 20 V
TJ = 25°C
ILIM1,2 = 10 mA to 150 mA
2.5
2.0
1.5
1.0
0.5
0
0
2
4
8
RCSO1,2, (kW)
6
10
12
0
14
Figure 9. Output Current Limit vs. RCSO
16
2.5
Iq, QUIESCENT CURRENT (mA)
Iq, QUIESCENT CURRENT (mA)
TJ = 25°C
Vin = Vout_nom1,2 + 8.5 V
2.0
1.5
1.0
0.5
0
0
50.4
50.2
50.0
49.8
49.6
49.4
49.2
0
10
8
6
4
2
0
1
10
100
Iout1,2, OUTPUT CURRENT (mA)
10
20 30 40
50 60
70
80
Iout1,2, OUTPUT CURRENT (mA)
90 100
Figure 12. Quiescent Current vs. Output Current
(High Load)
Iout1,2/ICSO1,2, OUTPUT CURRENT TO
CSO CURRENT RATIO (−)
TJ = 25°C
Vin = Vout_nom1,2 + 8.5 V
50.6
12
20
51.0
50.8
TJ = 25°C
Vin = Vout_nom1,2 + 8.5 V
14
0
15
10
Iout1,2, OUTPUT CURRENT (mA)
5
Figure 11. Quiescent Current vs. Output Current
(Low Load)
Iout1,2/ICSO1,2, OUTPUT CURRENT TO
CSO CURRENT RATIO (−)
125
Figure 10. Output Current (% of ILIM) vs. CSO
Voltage
3.0
49.0
25
50
75
100
Iout1,2, OUTPUT CURRENT (% of ILIM1,2)
1000
50.0
48.0
46.0
44.0
42.0
40.0
38.0
36.0
TJ = 25°C
Vin = 4.5 V
Vout_nom1,2 = 5 V
34.0
32.0
30.0
0
Figure 13. Output Current to CSO Current
Ratio vs. Output Current
1
10
100
Iout1,2, OUTPUT CURRENT (mA)
Figure 14. Output Current to CSO Current
Ratio vs. Output Current (In Dropout)
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1000
NCV47411
TYPICAL CHARACTERISTICS
Unstable Region
Area above curves
1400
Vout_nom1,2 = 20 V
1200
1000
Vout_nom1,2 = 5 V
Vout_nom1,2 = 3.3 V
TJ = 25°C
Vin = Vout_nom1,2 + 8.5 V
Cout1,2 = 10−100 mF,
Cb1,2 = none
0.1
Stable Region
Area below curves
0.01
0
20
40
60
80
100
Iout1,2, OUTPUT CURRENT (mA)
800
600
TJ = 25°C
Vin = 12 V
Cb1,2 = 10 nF
Iout1,2 = 5 mA
400
200
0
120
10
Figure 15. Output Capacitor Stability Region
vs. Output Current
100
f = 10 Hz − 100 kHz
Vn1,2 = 125 mVrms
1000
10000
FREQUENCY (Hz)
Figure 16. Noise vs. Frequency
100
Iout1,2 = 5 mA
90
80
PSRR1,2 (dB)
ESR (W)
10
1
Vn1,2, OUTPUT NOISE DENSITY
(nV/HZ1/2)
100
70
60
Iout1,2 = 100 mA
50
40
TJ = 25°C
Vin = 13.5 V (DC) + 0.5 VPP (AC)
Vout_nom1,2 = 5 V
30
20
10
100
1000
10000
FREQUENCY (Hz)
Figure 17. PSRR vs. Frequency
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100000
100000
NCV47411
DEFINITIONS
General
Current Limit
All measurements are performed using short pulse low
duty cycle techniques to maintain junction temperature as
close as possible to ambient temperature.
Current Limit is value of output current by which output
voltage drops below 90% of its nominal value.
PSRR
Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).
Output voltage
The output voltage parameter is defined for specific
temperature, input voltage and output current values or
specified over Line, Load and Temperature ranges.
Line Transient Response
Typical output voltage overshoot and undershoot
response when the input voltage is excited with a given
slope.
Line Regulation
The change in output voltage for a change in input voltage
measured for specific output current over operating ambient
temperature range.
Load Transient Response
Typical output voltage overshoot and undershoot
response when the output current is excited with a given
slope between low-load and high-load conditions.
Load Regulation
The change in output voltage for a change in output
current measured for specific input voltage over operating
ambient temperature range.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 175°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Dropout Voltage
The input to output differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. It is measured when the output
drops 2% of Vout_nom_n below its nominal value. The
junction temperature, load current, and minimum input
supply requirements affect the dropout level.
Maximum Package Power Dissipation
The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.
Quiescent and Disable Currents
Quiescent Current (Iq) is the difference between the input
current (measured through the LDO input pin) and the
output load current. If Enable pin is set to LOW the regulator
reduces its internal bias and shuts off the output, this term is
called the disable current (IDIS).
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NCV47411
APPLICATIONS INFORMATION
Circuit Description
to maintain junction temperature close to ambient
temperature.
The NCV47411 is an integrated dual low dropout
regulator that provides a regulated voltage at 100 mA to
each output. It is enabled with an input to the enable pin. The
regulator voltage is provided by a PNP pass transistor
controlled by an error amplifier with a bandgap reference,
which gives it the lowest possible dropout voltage. The
output current capability is 100 mA per output, and the base
drive quiescent current is controlled to prevent
oversaturation when the input voltage is low or when the
output is overloaded. The integrated current sense feature
provides diagnosis and system protection functionality. The
current limit of the device is adjustable by resistor connected
to CSO1,2 pin. Voltage on CSO1,2 pin is proportional to
output current. The regulator is protected by both current
limit and thermal shutdown. Thermal shutdown occurs
above 150°C to protect the IC during overloads and extreme
ambient temperatures.
Calculating Bypass Capacitor
If improved stability (reducing output voltage ringing
during transients) is demanded, connect the bypass
capacitor Cb1,2 between Adjustable Input pin and Vout1,2 pin
according to Applications circuit at Figure 1. Parallel
combination of bypass capacitor Cb1,2 with the feedback
resistor Rn1 contributes in the device transfer function as an
additional zero and affects the device loop stability,
therefore its value must be optimized. Attention to the
Output Capacitor value and its ESR must be paid. See also
Stability in High Speed Linear LDO Regulators Application
Note, AND8037/D for more information. Optimal value of
bypass capacitor is given by following expression
C bn +
2
p
1
fz
R n1
(F )
(eq. 1)
where:
Rn1 ­ the upper feedback resistor
fz ­ the frequency of the zero added into the device transfer
function by Rn1 and Cb1 external components.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (Vout1,2) and drives the base of
a PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature stable output.
Saturation control of the PNP is a function of the load current
and input voltage. Oversaturation of the output power
device is prevented, and quiescent current in the ground pin
is minimized.
Set the Rn1 resistor according to output voltage
requirement. Chose the fz with regard on the output
capacitance Cout1,2, refer to the table below.
Regulator Stability Considerations
Cout1,2 (mF)
10
22
47
100
fZ range
(kHz)
min 1.9
min 0.87
min 1.24
N/A*
*For Cout1,2 = 100 mF and higher Cb1,2 capacitors are not needed
for stability improvement. Cb1,2 capacitors are useful for noise
reduction. See electrical characteristic table.
The input capacitor (Cin) is necessary to stabilize the input
impedance to avoid voltage line influences. The output
capacitor (Cout1,2) helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
value and ESR of the capacitor will vary considerably. The
capacitor manufacturer’s data sheet usually provides this
information. The value for the output capacitor Cout1,2,
shown in Figure 1 should work for most applications; see
also Figure 12 for output stability at various load and Output
Capacitor ESR conditions. Stable region of ESR in
Figure 12 shows ESR values at which the LDO output
voltage does not have any permanent oscillations at any
dynamic changes of output load current. Marginal ESR is
the value at which the output voltage waving is fully damped
during four periods after the load change and no oscillation
is further observable.
ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors Cout1,2 from
the table above to define the frequency ranges of additional
zero required for stability:
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)
Enable Inputs
An enable pin is used to turn a channel on or off. By
holding the pin down to a voltage less than 0.99 V, the output
of the channel will be turned off. When the voltage on the
enable pin is greater than 2.31 V, the output of the channel
will be enabled to power its output to the regulated output
voltage. The enable pins may be connected directly to the
input pin to give constant enable to the output channel.
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10
NCV47411
Setting the Output Voltage
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV47411 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCV47411 can handle is given by:
The output voltage range can be set between 3.3 V and
20 V. This is accomplished with an external resistor divider
feeding back the voltage to the IC back to the error amplifier
by the voltage adjust pin ADJ1,2. The internal reference
voltage is set to a temperature stable reference (VREF1) of
1.275 V. The output voltage is calculated from the following
formula. Ignoring the bias current into the ADJ1,2 pin:
ǒ
V out_nom_n + V REF1 1 )
R n1
R n2
Ǔ
P D(MAX) +
(eq. 2)
Setting the Output Current Limit
The output current limit can be set between 10 mA and
150 mA by external resistor RCSO1,2 (see Figure 1).
Capacitor CCSO1,2 of 1 mF in parallel with RCSO1,2 is
required for stability of current limit control circuitry (see
Figure 1).
I LIM1,2 + 50
1
R CSO1,2 + 50
1
Ǔ
1
50
P D [ V inǒI q@I out1,2Ǔ ) I out1ǒV in * V out1Ǔ ) I out2ǒV in * V out2Ǔ
(eq. 7)
or
V in(MAX) [
(eq. 3)
2.55
R CSO1,2
(eq. 4)
2.55
I LIM1,2
(eq. 5)
P D(MAX) ) ǒV out1
I out1Ǔ ) ǒV out2
I out1 ) I out2 ) I q
I out2Ǔ
(eq. 8)
120
RqJA, THERMAL RESISTANCE (°C/W)
ǒ
(eq. 6)
Since TJ is not recommended to exceed 150°C, then the
NCV47411 soldered on 645 mm2, 1 oz copper area, FR4 can
dissipate up to 2.4 W (single layer PCB) when the ambient
temperature (TA) is 25°C. See Figure 18 for RqJA versus
PCB area. The power dissipated by the NCV47411 can be
calculated from the following equations:
Use Rn2 < 50 kW to avoid significant voltage output errors
due to ADJ1,2 bias current.
Designers should consider the tolerance of Rn1 and Rn2
during the design phase.
V CSO1,2 + I out1,2 R CSO1,2
[T J(MAX) * T A]
R qJA
110
100
where:
RCSO1,2 − current limit setting resistor
VCSO1,2− voltage at CSO pin proportional to Iout1,2
ILIM1,2 − current limit value
Iout1,2 − output current actual value
CSO1,2 pin provides information about output current
actual value. The CSO1,2 voltage is proportional to output
current according to Equation 3.
Once output current reaches its limit value (ILIM1,2) set by
external resistor RCSO1,2 than voltage at CSO1,2 pin is
typically 2.55 V. Calculations of ILIM1,2 or RCSO1,2 values
can be done using equations Equations 4 and 5, respectively.
Designers should consider the tolerance of RCSO1,2
during the design phase.
1 oz, Single Layer
90
80
70
60
2 oz, Single Layer
50
40
1 oz, 4 Layer
30
2 oz, 4 Layer
20
0
100
200
300
400
500
600
COPPER HEAT SPREADER AREA (mm2)
Figure 18. Thermal Resistance vs. PCB
Copper Area
Thermal Considerations
As power in the NCV47411 increases, it might become
necessary to provide some thermal relief. The maximum
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11
700
NCV47411
Iout1,2, OUTPUT CURRENT (mA)
450
400
TA = −40°C
350
loaded equally) and input to output voltage differential (both
nominal output voltages are equal) in ambient temperature
range from −40°C to 125°C is shown in Figure 19. The
maximum DC output current per channel is the current when
the output voltage of corresponding channel has dropped 3%
below its nominal output voltage without activation of
thermal shutdown protection. Measurement was done in
temperature chamber using double−sized PCB 3 x 3 inch (75
x 75 mm), Cu layers thickness 1 oz (35 mm) with copper
occupying more than 90% of both sides surface.
Vout_nom1,2 = 5 V,
Vout1,2 = Vout_nom1,2 − 3%
Both Channels loaded equally.
Temperature equilibrium time = 90 s
300
TA = 25°C
250
TA = 85°C
200
TA = 125°C
150
100
50
Hints
Vin and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCV47411 and
make traces as short as possible. To achieve better GND
potential distribution on PCB towards output resistor
dividers connect not internally bonded pin No. 11 to GND
plane and EPAD.
0
0
5
10
15
20
25
30
35
40
45
Vin − Vout1,2, INPUT TO OUTPUT VOLTAGE
DIFFERENTIAL (V)
Figure 19. Maximum DC Output Current vs.
Input to Output Voltage Differential
Example of safe operating area (SOA) restricted by
maximum DC output current per channel (both channels
Table 8. ORDERING INFORMATION
Device
Output Voltage
NCV47411PAAJR2G
Adjustable
Marking
Line1: NCV4
Line2: 7411
Package
Shipping†
TSSOP−14 Exposed Pad
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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12
NCV47411
PACKAGE DIMENSIONS
TSSOP−14 EP
CASE 948AW
ISSUE C
B
NOTE 6
14
b
8
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
b1
E1
c1
E
NOTE 5
SECTION B−B
c
NOTE 8
PIN 1
REFERENCE
1
7
0.20 C B A
e
2X 14 TIPS
TOP VIEW
NOTE 6
A
0.05 C
0.10 C
14X
D
A2
NOTE 4
A
DETAIL A
B
M
14X b
0.10 C B
S
A
S
C
SEATING
PLANE c
B
NOTE 3
END VIEW
SIDE VIEW
D2
H
E2
L2
A1
L
NOTE 7
GAUGE
PLANE
C
DETAIL A
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
3.40
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.07 mm MAX. AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD IS 0.07.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 mm PER SIDE. DIMENSION D IS DETERMINED AT
DATUM H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER
SIDE. DIMENSION E1 IS DETERMINED AT DATUM H.
6. DATUMS A AND B ARE DETERMINED AT DATUM H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM
THE SEATING PLANE TO THE LOWEST POINT ON THE
PACKAGE BODY.
8. SECTION B−B TO BE DETERMINED AT 0.10 TO 0.25 mm
FROM THE LEAD TIP.
DIM
A
A1
A2
b
b1
c
c1
D
D2
E
E1
E2
e
L
L2
M
MILLIMETERS
MIN
MAX
−−−−
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.19
0.25
0.09
0.20
0.09
0.16
4.90
5.10
3.09
3.62
6.40 BSC
4.30
4.50
2.69
3.22
0.65 BSC
0.45
0.75
0.25 BSC
0_
8_
14X
1.15
3.06
6.70
1
14X
0.65
PITCH
0.42
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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13
NCV47411
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NCV47411/D