19-0690; Rev 0; 1/07 Dual Driver/Comparator/Load with Internal DACs The MAX9973/MAX9974 fully integrated, high-performance, dual-channel pin electronics driver/comparator/load (DCL) with built-in level-setting digital-to-analog converters (DACs) are ideally suited for memory and SOC automatic test equipment (ATE) applications. Each channel includes a three-level pin driver, a window comparator, dynamic clamps, a 1kΩ load, and seven independent level-setting DACs. The driver features a wide voltage range and high-speed operation, includes high-impedance and active-termination (3rd-level drive) modes, and is highly linear even at low voltage swings. Additionally, the driver provides highspeed differential multiplexer control inputs, with internal termination resistors that are compatible with ECL, LVPECL, LVDS, and GTL. The window comparators provide extremely low timing variation over changes in slew rate, pulse width, or overdrive voltage, and have open-collector outputs. When high-impedance mode is selected, the dynamic clamps provide damping of high-speed deviceunder-test (DUT) waveforms. The load facilitates fast contact testing when used in conjunction with the comparators, and functions as a pullup for open-drain/collector DUT_ outputs. The MAX9973/ MAX9974 are configured through a serial interface. The MAX9973/MAX9974 differ in two aspects: the position of the exposed heat slug and the pin arrangement. The MAX9973G/MAX9974G comparator outputs sink 8mA (typ), while the MAX9973H/MAX9974H comparator outputs sink 16mA (typ). The devices are available in a 64-pin (10mm x 10mm x 1.00mm) TQFP-EP package with an exposed paddle on top (MAX9973) or bottom (MAX9974) for heat removal. Power dissipation is only 700mW per channel. The full operating voltage range is -1.5V to +6.5V. Operation is specified at an internal die temperature of +40°C to +100°C, and features a temperature monitor output. Applications Memory Testers SOC Testers SPI is a trademark of Motorola Inc. Features 600Mbps at 3V High Speed 700mW per Channel Extremely Low Power Dissipation -1.5V to +6.5V Wide Voltage Range 200mV to 8V Wide Voltage Swing Range 10nA (max) Low-Leakage Mode Integrated Termination On-the-Fly (3rd-Level Drive) Integrated Voltage Clamps Passive Load or Pullup Very Low Timing Dispersion Minimal External Component Count SPITM-Compatible Serial Control Interface Ordering Information PART PIN-PACKAGE PKG CODE OUTPUT SINK CURRENT MAX9973GCCB 64 TQFP-EP-IDP** (10mm x 10mm x C64E-13R 1.00mm) 8mA MAX9973HCCB* 64 TQFP-EP-IDP** (10mm x 10mm x C64E-13R 1.00mm) 16mA MAX9974GCCB* 64 TQFP-EP† (10mm x 10mm x 1.00mm) — 8mA MAX9974HCCB* 64 TQFP-EP† (10mm x 10mm x 1.00mm) — 16mA Note: Devices are available in both leaded and lead-free packages. Specify lead free by adding a + symbol at the end of the part number when ordering. *Future product—contact factory for availability. **EP-IDP = Exposed paddle (inverted die paddle). †EP = Exposed paddle. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9973/MAX9974 General Description MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs ABSOLUTE MAXIMUM RATINGS SCLK, DIN, CS, RST, LOAD to GND .........-0.3V to (VDD + 0.3V) TEMP to GND ...........................................................-0.2V to +5V All Other Pins to GND ......................(VEE - 0.3V) to (VCC + 0.3V) DUT_ Short Circuit to -1.5V to +6.5V..........................Continuous Power Dissipation (TA = +70°C) MAX997_GCCB (derate 125mW/°C above +70°C)......10.0W* Storage Temperature Range .............................-65°C to +150°C Junction Temperature .....................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C VCC to GND ............................................................-0.3V to +11V VEE to GND...............................................................-6V to +0.3V VCC - VEE ................................................................-0.3V to +17V VDD to GND ..............................................................-0.3V to +5V VT0, VT1 to GND .......................................................-0.3V to +5V DGS to GND .......................................................................±0.7V DUT_ to GND.........................................................-2.5V to +7.5V DATA_, NDATA_, RCV_, NRCV_ to GND .................-2.5V to +5V DATA_ to NDATA_, RCV_ to NRCV_ .....................................±1V DATA_, NDATA_, RCV_, NRCV_ to VTERM_......................±1.5V *Dissipation wattage values are based on still air with no heat sink. Actual maximum power dissipation is a function of heat extraction technique and may be substantially higher. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DRIVER DC CHARACTERISTICS (RL ≥ 10MΩ, unless otherwise noted; includes DAC error) Output Voltage Range Output Offset Voltage VDHV_ VDLV_ = -1.5V, VDTV_ = +1.5V -1.45 +6.50 VDLV_ VDHV_ = +6.5V, VDTV_ = +1.5V -1.50 +6.45 -1.50 +6.50 VDTV_ VDHV_ = +6.5V, VDLV_ = -1.5V VDHV_ VDHV_ = +3V, VDLV_ = -1.5V, VDTV_ = +1.5V ±50 VDLV_ VDLV_ = 0V, VDHV_ = +6.5V, VDTV_ = +1.5V ±50 VDTV_ VDTV_ = +1.5V, VDHV_ = +6.5V, VDLV_ = -1.5V ±50 Output-Voltage Temperature Coefficient (Notes 2, 3) Gain 2 DHV_, DLV_, DTV_ ±75 ±400 VDHV_ VDLV_ = -1.5V, VDTV_ = +1.5V, VDHV_ = 0 and +4.5V 0.998 1 1.002 VDLV_ VDHV_ = +6.5V, VDTV_ = +1.5V, VDLV_ = 0 and +4.5V 0.998 1 1.002 VDTV_ VDHV_ = +6.5V, VDLV_ = -1.5V, VDTV_ = 0 and +4.5V 0.998 1 1.002 _______________________________________________________________________________________ V mV µV/°C V/V Dual Driver/Comparator/Load with Internal DACs (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS 0 to 3V relative to calibration points at 0 and 3V Linearity Error Full range relative to calibration points at 0 and 3V Crosstalk Term Voltage Dependence on DATA_ DC Power-Supply Rejection DC Output Resistance TYP MAX VDLV_ = -1.5V, VDTV_ = +1.5V, VDHV_ = 0, +0.75V, +1.5V, +2.25V, +3V ±5 VDHV_ = +6.5V, VDTV_ = +1.5V, VDLV_ = 0, +0.75V, +1.5V, +2.25V, +3V ±5 VDLV_ = -1.5V, VDHV_ = +6.5V, VDTV_ = 0, +0.75V, +1.5V, +2.25V, +3V ±5 VDLV_ = -1.5V, VDTV_ = +1.5V, VDHV_ = -1.25V and +6.5V ±5 VDHV_ = +6.5V, VDTV_ = +1.5V, VDLV_ = -1.5V and +6.25V ±5 VDLV_ = -1.5V, VDHV_ = +6.5V, VDTV_ = -1.5V and +6.5V ±5 VDHV_ to VDLV, VDLV_ = 0, VDTV_ = 1.5V, VDHV_ = 0.2V and 6.5V ±2 VDLV_ to VDHV, VDHV_ = +5V, VDTV_ = +1.5V, VDLV_ = -1.5V and +4.8V ±2 VDTV_ to VDLV_ and VDHV, VDHV_ = +3V, VDLV_ = 0, VDTV_ = -1.5V and +6.5V ±2 VDHV_ to VDTV, VDTV_ = +1.5V, VDLV_ = 0, VDHV_ = +1.6V and +3.0V ±3 VDLV_ to VDTV, VDTV_ = +1.5V, VDHV_ = +3V, VDLV_ = 0 and +1.4V ±3 VDTV_ = +1.5V, VDHV_ = +3V, VDLV_ = 0, DATA_ = 0 and 1 ±2 VDHV_, VDHV_ = 3V, VCC and VEE independently varied over full range 40 VDLV_, VDLV_ = 0, VCC and VEE independently varied over full range 40 VDTV_, VDTV_ = 1.5V, VCC and VEE independently varied over full range 40 VDLV_/VDUT_ = -1.5V/+6.5V, DATA_ = 0 DC Drive Current Limit MIN -60 VDHV_/VDUT_ = +6.5V/-1.5V, DATA_ = 1 +60 +120 VDTV_/VDUT_ = -1.5V/+6.5V, RCV_ = 1 -120 -60 VDTV_/VDUT_ = +6.5V/-1.5V, RCV_ = 1 +60 +120 48 mV mV mV dB -120 (Note 4) UNITS 50 52 mA Ω _______________________________________________________________________________________ 3 MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL DC Output Resistance Variation TYP MAX DATA_ = 1, VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, IDUT_ = 1mA to 40mA CONDITIONS MIN 1 2 DATA_ = 0, VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, IDUT_ = -1mA to -40mA 1 2 UNITS Ω AC CHARACTERISTICS (RDUT_ = 50Ω to ground) (Note 5) Dynamic Drive Current Drive-Mode Overshoot Termination-Mode Overshoot Settling Time (Note 8) (Note 6) 60 VDLV_ = 0, VDHV_ = 0.1V 30 mA VDLV_ = 0, VDHV_ = 1V (Note 2) 40 75 VDLV_ = 0, VDHV_ = 3V (Note 2) 50 175 VDLV_ = 0, VDHV_ = 5V (Note 2) 50 275 (Note 7) 0 To within 100mV, VDHV_ = 5V, VDLV_ = 0 0.25 To within 50mV, VDHV_ = 3V, VDLV_ = 0 0.25 To within 25mV, VDHV_ = 0.5V, VDLV_ = 0 0.25 mV mV ns TIMING CHARACTERISTICS (Notes 5, 9) Data to output; VDHV_ = 3V, VDLV_ = 0 2 3 Drive to high impedance, high impedance to drive (Note 10); VDHV_ = +1V, VDLV_ = -1V 1.7 4 Drive to term 2.7 4 Term to drive 1.7 4 Prop Delay Match (Note 2) tLH vs. tHL 50 100 Drivers within package; same edge 40 100 Prop-Delay Temperature Coefficient (Note 2) 1 5 VDHV_ = 1V, VDLV_ = 0, 2ns to 23ns pulse width 10 100 VDHV_ = 3V, VDLV_ = 0, 3ns to 22ns pulse width 10 100 VDHV_ = 5V, VDLV_ = 0, 4ns to 21ns pulse width 20 100 VDHV_ - VDLV_ = 1V, VDHV_ = 0 to 6V, (using a DC block) 25 Drive to high impedance vs. high impedance to drive; VDHV_ = 1V, VDLV_ = -1V (Note 11) 0.2 High impedance vs. data (Note 2) 0.4 Prop Delay (Note 2) Prop Delay Change vs. Pulse Width (Note 2) Prop Delay Change vs. Common Mode Delay Match Drive to term vs. term to drive; VDHV_ = 3V, VDL V_ = 0, VDT V_ = 1.5V ( Note 12) Terminate vs. data 4 1 0.7 _______________________________________________________________________________________ ns ps ps/°C ps ps ns Dual Driver/Comparator/Load with Internal DACs (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN 0.2VP-P programmed, VDHV_ = 0.2V, VDLV_ = 0, 20% to 80% Rise and Fall Time Rise and Fall Time Matching Minimum Pulse Width (Note 13) MAX 0.35 0.50 0.75 3VP-P programmed, VDHV_ = 3V, VDLV_ = 0, 10% to 90%, trim condition 1.0 1.2 1.5 ns 5VP-P programmed VDHV_ = 5V, VDLV_ = 0, 10% to 90% 2.0 0.2VP-P programmed, VDHV_ = 0.2V, VDLV_ = 0, 20% to 80% 40 1VP-P programmed, VDHV_ = 1V, VDLV_ = 0, 10% to 90% 150 3VP-P programmed, VDHV_ = 3V, VDLV_ = 0, 10% to 90 200 5VP-P programmed, VDHV_ = 5V, VDLV_ = 0, 10% to 90% (Note 2) 250 Positive or negative UNITS 0.20 1VP-P programmed, VDHV_ = 1V, VDLV_ = 0, 10% to 90% Relative to SC1 = SC0 = 0 Slew Rate TYP ps SC1 = 0, SC0 = 1, VDHV_ = 3V, VDLV_ = 0, 20% to 80% 75 SC1 = 1, SC0 = 0, VDHV_ = 3V, VDLV_ = 0, 20% to 80% 50 SC1 = 1, SC0 = 1, VDHV_ = 3V, VDLV_ = 0, 20% to 80% 25 0.2VP-P programmed, VDHV_ = 0.2V, VDLV_ = 0 0.4 1VP-P programmed VDHV_ = 1V, VDLV_ = 0 (Note 2) 0.7 2 3VP-P programmed VDHV_ = 3V, VDLV_ = 0 (Note 2) 1.5 2.5 5VP-P programmed VDHV_ = 5V, VDLV_ = 0 (Note 2) 2.4 3.5 % ns 0.2VP-P programmed, VDHV_ = 0.2V, VDLV_ = 0 2900 1VP-P programmed, VDHV_ = 1V, VDLV_ = 0 1300 3VP-P programmed, VDHV_ = 3V, VDLV_ = 0 600 5VP-P programmed, VDHV_ = 5V, VDLV_ = 0 400 Rise and Fall Time, Drive to Term VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, measured 10% to 90% of waveform 1.6 ns Rise and Fall Time, Term to Drive VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, measured 10% to 90% of waveform 0.7 ns Data Rate (Note 14) Mbps _______________________________________________________________________________________ 5 MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +6.5 V COMPARATOR DC CHARACTERISTICS Input Voltage Range -1.5 Differential Input Voltage ±8 V Minimum Hysteresis RHYST_ = open 0 mV Maximum Hysteresis RRHYST_ = 2.5kΩ 10 mV Input Offset Voltage VDUT_ = 1.5V Input-Voltage Temperature Coefficient (Notes 2, 15) Common-Mode Rejection Ratio CMRR VDUT_ = -1.5V, +6.5V ±75 50 ±50 mV ±400 µV/°C 70 dB Linearity Error, 0 to 3V VDUT_ = 0, 1.5V, 3V (Note 16) ±1 ±5 mV Linearity Error, Full Range VDUT_ = -1.5V, 0, +1.5V, +3V, +6.5V (Note 16) ±1 ±10 mV Power-Supply Rejection Ratio PSRR VDUT_ = -1.5V and +6.5V 50 75 dB 0.85 ns AC CHARACTERISTICS (Notes 17–20) Minimum Pulse Width (Note 21) Prop Delay 1.2 2 ns (Note 2) 2.6 5 ps/°C Prop Delay Match High/low vs. low/high; absolute value of delta for each comparator (Note 2) 40 100 ps Prop Delay Dispersion vs. Common-Mode Input Common-mode input -1.4V to +6.4V (Note 22) 20 3ns to 22ns pulse width, 500ps tRISE, positive and negative pulses 10 60 2ns to 23ns pulse width 10 100 Slew rate = 0.5V/ns to 2V/ns 10 100mV < VC_V_ < 900mV, driver in term mode, peak-to-peak within this window 40 50mV < VC_V__ < 950mV, driver in term mode, peak-to-peak within this window 60 100mV < VC_V_ < 900mV, driver in high impedance, peak-to-peak within this window 100 Prop-Delay Temperature Coefficient Prop Delay Dispersion vs. Pulse Width (Note 2) Prop Delay Dispersion vs. Slew Rate Waveform Tracking (Note 23) ps ps ps ps LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_) Termination Voltage V T_ 0 3.5 Output Voltage Compliance Set by IOUT, RTERM, and VT_ VT_ V Differential Rise Time 20% to 80% (Note 2) 200 400 ps Differential Fall Time 20% to 80% (Note 2) 200 400 ps 6 -0.5 V _______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER Termination Resistor Value SYMBOL CONDITIONS VT_ to CH_, NCH_, CL_, NCL_ MIN TYP 48 MAX UNITS 52 Ω VT_ - 0.02 VT_ V Output High Voltage VT_ = 0, 3.5V VT_ - 0.1 Output Low Voltage VT_ = 0, 3.5V VT_ - 0.55 VT_ - 0.4 VT_ - 0.35 V Output Voltage Swing VT_ = 0, 3.5V 350 400 450 mV CPHV_; IDUT_ = -1mA, CPHV_ = -0.4V and +6.6V, CPLV_ = -1.5V -0.3 +6.5 CPLV_; IDUT_ = 1mA, CPLV_ = -1.6V and +5.4V, CPHV_ = +6.5V -1.5 +5.3 Maximum Programmable CPHV_ IDUT_ = 0mA (Note 24) 7.2 Minimum Programmable CPLV_ IDUT_ = 0mA (Note 24) DYNAMIC CLAMPS Functional Clamp Range Offset Voltage V -2.5 V -2.2 IDUT_ = -1mA, CPHV_ = +1.5V, CPLV_ = -1.5V ±50 IDUT_ = +1mA, CPLV_ = +1.5V, CPHV_ = +6.5V ±50 Offset-Voltage Temperature Coefficient Power-Supply Rejection 7.5 0.5 IDUT_ = -1mA, CPHV_ = +1.5V, CPLV_ = -1.5V 40 IDUT_ = +1mA, CPLV_ = +1.5V, CPHV_ = +6.5V 40 V mV mV/°C dB High-Clamp Voltage Gain CPHV_ = 0, +6.5V, CPLV_ = -1.5V 0.99 1.01 V/V Low-Clamp Voltage Gain CPLV_ = -1.5V, +5.3V, CPHV_ = +6.5V 0.99 1.01 V/V 1 % Voltage Gain Matching Voltage-Gain Temperature Coefficient Linearity Static Output Current DC Impedance DC Impedance Variation (Note 25) 100 ppm/°C IDUT_ = -1mA, CPHV_ = 0, +1.5V, +3.25V, +5V, +6.5V ±30 IDUT_ = +1mA, CPLV_ = -1.5V, +0.5V, +2.25V, +4V, +5.3V ±30 CPHV_ = 0, CPLV_ = -1.5V, RL = 0Ω to +6.5V mV -120 -60 CPLV_ = +5V, CPHV_ = +6.5V, RL = 0Ω to -1.5V 60 120 High clamp, VCPHV_ = 2.5V, IDUT_ = -5mA and -15mA 48 55 Low clamp, VCPLV_ = 2.5V, IDUT_ = 5mA and 15mA 48 55 mA Ω High clamp, IDUT_ = -20mA and -30mA, CPHV_ = +2.5V, CPLV_ = -1.5V ±5 Low clamp, IDUT_ = 20mA and 30mA, CPLV_ = 2.5V, CPHV_ = 6.5V ±5 Ω _______________________________________________________________________________________ 7 MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Overshoot and Undershoot CONDITIONS MIN TYP (Note 26) 650 DHV_, DLV_, DTV_, CHV_, CLV_ 16 CPLV_, CPHV_ 12 Full-scale change to ±2.5mV 20 MAX UNITS mV LEVEL-SETTING DACs Resolution Differential Nonlinearity N DNL Voltage Settling Time Bits ±1 mV µs GROUND SENSE (DGS) Input Range VGS Relative to AGND_, verified by functional test -250 Gain +250 1 Input Resistance mV V/V 1 MΩ Reference Input 1k TRI-STATE LOAD (PULLUP/PULLDOWN) (Note 27) 2.5 Source Impedance When Enabled Tested at -5mA, 0, +5mA using a 0.5mA step 950 Maximum Source Current VDUT_ = +6.1V, VDTV_ = -1.1V 6.9 7.2 mA Maximum Sink Current VDUT_ = -1.1V, VDTV_ = +6.1V 6.9 7.2 mA 60 ns Turn-On Time Turn-Off Time V 1050 60 Ω ns Offset Voltage Output with no load, VDTV_ = 0 and 3V ±50 mV Linearity Error No load, VDTV_ = -1.5V to +6.5V ±25 mV TEMPERATURE MONITOR Nominal Voltage TJ = +70°C, RL ≥ 10MΩ 3.43 V Temperature Coefficient 10 mV/°C Output Resistance 15 kΩ DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_) Input High Voltage -1.6 +3.5 Input Low Voltage -2.0 +3.1 V ±0.15 ±1.00 V Differential Input Voltage Termination Resistor 50Ω to VTERM_ VTERM_ Voltage Range Verified by functional test V 48 52 Ω -2.0 +3.5 V Input High 2/3 (VDD) VDD V Input Low -0.1 1/3 (VDD) V SERIAL PORT INPUTS (CS, SCLK, DIN, RST, LOAD, VDD = 3.3V) 8 _______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 50 MHz SERIAL PORT TIMING (Note 28) SCLK Frequency SCLK Pulse-Width High t1 8 ns SCLK Pulse-Width Low t2 8 ns CS Low to SCLK High Setup t3 3.5 ns SCLK High to CS Low Hold t4 3.5 ns CS High to SCLK High Setup t5 3.5 ns SCLK High to CS High Hold t6 3.5 ns DIN to SCLK High Setup t7 3.5 ns DIN to SCLK High Hold t8 3.5 ns CS High Pulse Width t9 20 ns LOAD Low Pulse Width t10 20 ns RST Low Pulse Width t11 20 ns CS High to LOAD Low Hold Time t12 20 ns COMMON FUNCTIONS Operating Voltage Range (Note 29) DUT_ High-Impedance Leakage -1.5 +6.5 0 < VDUT_ < 3V ±2 VCLV_ = VCHV_ = +6.5V, VDUT_ = -1.5V ±5 VCLV_ = VCHV_ = -1.5V, VDUT_ = +6.5V DUT_ Low-Leakage Mode Leakage DUT_ Combined Capacitance V µA ±5 LEAK = 1, 0 < VDUT_ < 3V, TJ < +90°C -10 +10 LEAK = 1, VCLV_ = VCHV_ = +6.5V, VDUT_ = -1.5V, TJ < +90°C -10 +10 LEAK = 1, VCLV_ = VCHV_ = -1.5V, VDUT_ = +6.5V, TJ < +90°C -10 +10 Driver in terminate mode 2 Driver in high impedance 4 nA pF POWER SUPPLY Positive Supply Voltage VCC 9.5 9.75 10.5 Negative Supply Voltage VEE -5.2 -4.75 -4.5 V Logic Supply Voltage VDD 2.7 3.3 5.0 V Positive Supply Current ICC (Note 30) 70 85 mA Negative Supply Current IEE (Note 30) 150 180 mA Logic Supply Current IDD (Note 30) 1.2 2 mA 1.7 Power Dissipation (Notes 30, 31) 1.4 Power Dissipation per Channel (Notes 30, 31) 700 Note 1: Note 2: V W mW All minimum and maximum specifications are 100% production tested, unless otherwise noted. All other test limits are guaranteed by design. Tests are performed at nominal supply voltages, unless otherwise noted. Tested with TJ = +70°C with accuracy of ±15°C. Guaranteed by design and characterization. _______________________________________________________________________________________ 9 MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18: Note 19: Note 20: Note 21: Note 22: Note 23: Note 24: Note 25: Note 26: Note 27: Note 28: Note 29: Note 30: Note 31: 10 Change in any voltage over operating range. Includes both gain and offset temperature effects. Simulated over entire operating range. Verified at worst-case points, which are the endpoints. VDHV_ - VDLV_ > 250mV. DATA_ = 1, VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, IOUT = ±30mA. Different values within the range of 48Ω to 52Ω are available by custom trimming (contact factory). Rise time of the differential inputs DATA_ and RCV_ is 250ps (10% to 90%). SC1 = SC0 = 0, 40MHz, unless otherwise specified. 0 to 6V step, current supplied for a minimum of 10ns. VDTV_ = 1.5V, RS = 50Ω external signal driven into a transmission line to produce a 0/3V edge at the comparator input with ≤ 1.0ns rise time (10% to 90%). Measurement point is at comparator input. Measured from the 90% point of the driver output (relative to its final value) to the waveform settling to within the specified limit. Propagation delays are measured from the crossing point of the differential input signals to the 50% point of expected output swing. Measured from crossing point of RCV_/NRCV_ to 50% point of the output waveform. Four measurements are made: DHV_ to high impedance, DLV_ to high impedance, high impedance to DHV_, high impedance to DLV_. The worst difference is specified. Four measurements are made: DHV_ to DTV_, DLV_ to DTV_, DTV_ to DHV_, DTV_ to DLV_. The worst difference is specified. At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude. The pulse width is measured at DATA_ and NDATA_. Maximum data rate in transitions/second. A waveform that reaches at least 95% of its programmed amplitude may be generated at one-half of this frequency. Change in offset at any voltage over operating range. Includes both gain (CMRR) and offset temperature effects. Relative to straight line between 0 and 3V. All propagation delays measured from VDUT_ crossing calibrated CHV_/CLV_ threshold to crossing point of differential outputs. Load is a 500ps transmission line terminated with 1pF and 50Ω. All AC specifications are measured with DUT_ (comparator input) as the reference. 40MHz, 0 to 2V input to comparator, reference = 1V, 50% duty cycle, 1ns rise/fall time, ZS = 50Ω, driver in term mode with VDTV_ = 0, unless otherwise noted. At this pulse width, the output reaches at least 90% of its nominal peak-to-peak swing. The pulse width is measured at the crossing points of the differential outputs. 500ps rise and fall time. Timing specs are not guaranteed. VDUT_ = 200mVP-P, rise/fall time = 150ps, overdrive = 100mV, VDTV_ = VCM. Valid for common-mode ranges where the signal does not exceed the operating range. Specification is worst case (slowest to fastest) over the specified range. Input to comparator is 40MHz at 0 to 1V, 50% duty cycle, 1ns rise time. This specification is implicitly tested, by meeting the high-impedance leakage specification. Resistance measurements are made using small-signal voltage changes in the loading instrument. Absolute value of the difference in measured resistance over the specified range, tested separately for each current polarity. Ripple in the DUT_ signal after one round-trip delay. Stimulus is 0 to 3V, 2.5V/ns square wave from far end of 3ns transmission line with RS = 25Ω, clamps set to 0 and 3V. Any deviation from 2.5V affects offset and gain of all levels. Serial port timing specifications are measured at a logic supply voltage (VDD) of +3.3V, ensuring operation of the serial port at rated speed for VDD from +3.3V to +5.5V. The maximum usable output operating voltage is limited to -1.5V to +6.5V. Externally forced voltages may exceed this range without damage to the device, provided that they are limited per the Absolute Maximum Ratings. External clamps must be provided to limit voltages in this range, or damage to the device is likely. Total for dual device. RL ≥ 10MΩ. Worst case of the following conditions: driver enabled, LLEAK = 0; driver disabled, LLEAK = 0; driver enabled, RCV_ = 1; driver disabled, LLEAK = 1. Excludes dissipation of comparator output supply. A typical output configuration and V+ = 1.8V adds 30mW (typ) per channel to device power. ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs VDHV_ = 200mV 60 TIMING ERROR (ps) VDHV_ = 5V VDHV_ = 3V VDHV_ = 1V MAX9973 toc03 VDLV_ = 0 RL = 50Ω VDUT_ = 500mV/div VDHV_ = 500mV 80 MAX9973 toc02 VDLV_ = 0 RL = 50Ω VDUT_ = 50mV/div DRIVER 3V TRAILING-EDGE TIMING ERROR vs. PULSE WIDTH DRIVER LARGESIGNAL RESPONSE MAX9973 toc01 DRIVER SMALLSIGNAL RESPONSE 40 NEGATIVE PULSE 20 0 -20 POSITIVE PULSE VDHV_ = 100mV 0 -40 0 NORMALIZED AT PW = 12.5ns PERIOD = 25ns, VDHV_ = +3V, VDLV_ = 0 -60 t = 2.0ns/div 0 t = 2.0ns/div 5 10 15 25 20 PULSE WIDTH (ns) TIME DELAY (ps) NEGATIVE PULSE 10 0 POSITIVE PULSE -20 30 FALLING EDGE 20 10 0 DLV_ TO DTV_ -30 5 10 15 20 0 -1 0 1 2 3 4 COMMON-MODE VOLTAGE (V) DRIVE TO HIGH IMPEDANCE TRANSITION DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE 0 RL = 50Ω VDHV_ = +1V VDLV_ = -1V 2.0 1.5 t = 2.0ns/div 6 DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE DUT_ = DHV_ VDLV_ = -1.5V VDTV_ = 0 1.0 0.5 0 -0.5 1.5 DUT_ = DLV_ VDHV_ = +6.5V VDTV_ = 0 1.0 0.5 0 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 -2.0 t = 2.0ns/div 2.0 LINEARITY ERROR (mV) DHV_ TO HIGH IMPEDANCE 5 MAX9973 toc08 PULSE WIDTH (ns) DLV_ TO HIGH IMPEDANCE RL = 50Ω VDHV_ = 3.0V VDTV_ = 1.5V VDLV_ = 0 -20 25 LINEARITY ERROR (mV) 0 MAX9973 toc07 -50 RISING EDGE -10 NORMALIZED AT PW = 12.5ns PERIOD = 25ns, VDHV_ = +1V, VDLV_ = 0 -40 VDUT_ = 200mV/div DHV_ TO DTV_ MAX9973 toc09 -10 NORMALIZED AT VCM = +1.5V 40 VDUT_ = 250mV/div 30 MAX9973 toc05 40 TIMING ERROR (ps) 50 MAX9973 toc04 50 20 DRIVE TO TERM TRANSITION DRIVER TIME DELAY vs. COMMON-MODE VOLTAGE MAX9973 toc06 DRIVER 1V TRAILING-EDGE TIMING ERROR vs. PULSE WIDTH -1.5 -0.5 0.5 1.5 2.5 3.5 VDUT_ (V) 4.5 5.5 6.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDUT_ (V) ______________________________________________________________________________________ 11 MAX9973/MAX9974 Typical Operating Characteristics (TJ = +70°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TJ = +70°C, unless otherwise noted.) 1.0006 1.0000 1.9998 -1.5 NORMALIZED AT TJ = +70°C 0.9992 -1.5 -0.5 0.5 2.5 3.5 4.5 5.5 50 60 70 -2.0 80 90 40 100 60 70 80 90 TEMPERATURE (°C) TEMPERATURE (°C) COMPARATOR OFFSET vs. COMMON-MODE VOLTAGE COMPARATOR TIMING VARIATION vs. COMMON-MODE VOLTAGE COMPARATOR WAVEFORM TRACKING 15 0.4 0 -0.4 -0.8 FALLING EDGE 10 FALLING EDGE 5 0 -5 -1.2 -2.0 1.5 2.5 3.5 4.5 5.5 6.5 -100 -150 NORMALIZED AT 50% REFERENCE LEVEL VDUT_ = 1 TO 1V PULSE -250 -15 -1.5 -0.5 0.5 -50 -200 RISING EDGE -10 -1.6 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 RISING EDGE 0 TIMING VARIATION (ps) 0.8 NORMALIZED AT VCM = 1.5V 0 6.5 20 40 60 80 COMMON-MODE VOLTAGE (V) REFERENCE LEVEL (%) COMPARATOR TRAILING-EDGE TIMING VARIATION vs. PULSE WIDTH COMPARATOR TIMING VARIATION vs. INPUT SLEW RATE COMPARATOR DIFFERENTIAL OUTPUT RESPONSE HIGH PULSE 20 0 30 VDUT_ FALLING 20 10 0 NORMALIZED AT PW = 12.5ns 5 10 15 PULSE WIDTH (ns) NORMALIZED AT SR = 4V/ns -30 20 25 DOUBLE TERMINATED SIGNAL VDUT_ = 0 TO 3V PULSE VCHV_ = VCLV_ = 1.5V VDUT_ RISING -20 0 0 -10 LOW PULSE -40 VDUT_ = 100mV/div 40 -20 40 TIMING VARIATION (ps) 60 MAX9973 toc17 MAX9973 toc16 50 0 1 2 3 4 5 6 100 MAX9973 toc18 COMMON-MODE VOLTAGE (V) 80 100 50 MAX9973 toc14 20 TIMING VARIATION (ps) 1.2 12 50 VDUT_ (V) OTHER COMPARATOR REFERENCE = 2.5V NORMALIZED AT VCM = 1.5V 1.6 40 6.5 MAX9973 toc13 2.0 1.5 0 -1.0 0.9994 -2.5 0.5 -0.5 0.9996 -2.0 1.0 MAX9973 toc15 -1.0 -1.5 OFFSET (mV) 1.5 OFFSET (mV) 0 -0.5 1.0002 NORMALIZED AT TJ = +70°C 2.0 1.0004 0.5 GAIN (V/V) LINEARITY ERROR (mV) 1.0 2.5 MAX9973 toc11 DUT_ = DTV_ VDHV_ = +6.5V VDLV_ = -1.5V 1.5 1.0008 MAX9973 toc10 2.0 DRIVER OFFSET vs. TEMPERATURE DRIVER GAIN vs. TEMPERATURE MAX9973 toc12 DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE TIMING VARIATION (ps) MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs t = 2.0ns/div SLEW RATE (V/ns) ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs CLAMP RESPONSE AT SOURCE NORMALIZED AT TJ = +70°C 1.0 MAX9973 toc20 1.5 MAX9973 toc19 INPUT MAX9973 toc21 COMPARATOR OFFSET vs. TEMPERATURE COMPARATOR RESPONSE TO HIGH SLEW-RATE OVERDRIVE OUTPUT 600mV/div OFFSET (mV) VDUT_ = 150mV/div 0.5 0 -0.5 VSOURCE_ = 0 TO 3V SQUARE WAVE RS = 25Ω VCPLV_ = 0 VCPHV_ = +3V -1.0 0 -1.5 INPUT SLEW RATE = 4V/ns HIGH IMPEDANCE 0 -2.0 t = 2.0ns/div 40 50 60 70 80 90 t = 10ns/div 100 MAX9973/MAX9974 Typical Operating Characteristics (continued) (TJ = +70°C, unless otherwise noted.) TEMPERATURE (°C) CLAMP CURRENT vs. DIFFERENCE VOLTAGE LOW LEAKAGE CURRENT vs. DUT_ VOLTAGE 80 1200 MAX9973 toc23 30 MAX9973 toc22 100 20 20 0 800 10 IDUT_ (μA) LEAKAGE (pA) LEAKAGE (nA) 40 0 -10 -20 -60 1.5 2.5 3.5 4.5 5.5 6.5 -200 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 3.0 3.2 3.4 3.6 3.8 VDUT_ (V) VDUT_ (V) VCPHV_ (V) CLAMP CURRENT vs. DIFFERENCE VOLTAGE DRIVE 1V TO LOW LEAKAGE TRANSITION LOW LEAKAGE TO DRIVE 1V TRANSITION MAX9973 toc25 0 -200 4.0 MAX9973 toc27 MAX9973 toc26 200 IDUT_ (mA) 400 0 -30 -1.5 -0.5 0.5 600 200 -20 -40 VDUT_ = 3V VCPLV_ = 0 1000 60 MAX9973 toc24 HIGH-IMPEDANCE LEAKAGE CURRENT vs. DUT_ VOLTAGE C1 FALL 10.12ns C1 HIGH 504mV C1 RISE 815ns C1 HIGH 500mV C1 LOW 4mV C1 LOW 4mV -400 -600 -800 -1000 VDUT_ = 0 VCPHV_ = 3V -1200 -1.0 -0.8 -0.6 -0.4 -0.2 0 VCPLV_ (V) ______________________________________________________________________________________ 13 Typical Operating Characteristics (continued) (TJ = +70°C, unless otherwise noted.) 137.0 VDHV_ = +3.0V, VDLV_ = 0, VDTV_ = +1.5V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, HIGH IMPEDANCE, VCC = +9.75V 62.0 MAX9973 toc29 VDHV_ = +3.0V, VDLV_ = 0, VDTV_ = +1.5V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, HIGH IMPEDANCE, VEE = -5.25V 60.4 137.5 MAX9973 toc28 60.5 POSITIVE SUPPLY CURRENT vs. TEMPERATURE NEGATIVE SUPPLY CURRENT vs. NEGATIVE SUPPLY VOLTAGE 61.5 VDUT_ = VDTV_ = +1.5V, VDHV_ = +3V, VDLV_ = 0, VCHV_ = VCLV_ = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VCC = +9.75V, VEE = -5.25V MAX9973 toc30 POSITIVE SUPPLY CURRENT vs. POSITIVE SUPPLY VOLTAGE 136.5 60.2 61.0 136.0 ICC (mA) IEE (mA) ICC (mA) 60.3 135.5 135.0 60.1 60.5 60.0 134.5 60.0 59.5 134.0 59.9 59.0 133.5 9.9 10.1 10.3 10.5 -5.1 -5.0 -4.9 -4.8 -4.7 -4.6 40 -4.5 50 60 70 80 VEE (V) TEMPERATURE (°C) NEGATIVE SUPPLY CURRENT vs. TEMPERATURE DRIVER LARGE-SIGNAL RESPONSE INTO 500Ω DRIVER 1V 600Mbps SIGNAL RESPONSE VDLV_ = 0 RL = 500Ω CL = 0.1pF VDHV_ = 5V VDLV_ = 0 VDHV_ = +1V RL = 50Ω 135.0 134.5 VDUT_ = 100mV/div VDUT_ = 1V/div 136.0 135.5 VDHV_ = 3V VDHV_ = 1V 134.0 133.5 0 0 133.0 40 50 60 70 80 90 100 t = 2.0ns/div t = 0.5ns/div TEMPERATURE (°C) MAX9973 toc34 VDUT_ = 100mV/div 0 0 t = 0.5ns/div 14 VDLV_ = 0 VDHV_ = +3V RL = 50Ω VDUT_ = 250mV/div VDLV_ = 0 VDHV_ = +1V RL = 50Ω MAX9973 toc35 DRIVER 3V 600Mbps SIGNAL RESPONSE DRIVER 1V 1200Mbps SIGNAL RESPONSE 90 100 MAX9973 toc33 VCC (V) VDUT_ = VDTV_ = +1.5V, VDHV_ = +3V, VDLV_ = 0 VCHV_ = VCLV_ = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VCC = +9.75V, VEE = -5.25V 136.5 -5.2 MAX9973 toc32 137.0 9.7 MAX9973 toc31 9.5 IEE (mA) MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs t = 0.5ns/div ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs DRIVER DYNAMIC CURRENT-LIMIT RESPONSE MAX9973 toc36 MAX9973 toc37 DRIVER 3V 800Mbps SIGNAL RESPONSE VDLV_ = 0 VDHV_ = +3V RL = 50Ω IDUT_ = 50mA/div VDUT_ = 250mV/div DRIVER SOURCING 0 DRIVER SINKING 0 t = 50ns/div t = 0.5ns/div Pin Description PIN (MAX9973) NAME 1, 16, 18, 33, 36, 39, 42, 45, 48, 63 VEE Negative Power-Supply Input 2, 15, 24, 35, 37, 44, 46, 57 VCC Positive Power-Supply Input 3, 14 AGND 4 REF DAC Reference Input. Set to 2.5V with respect to DGS. 5 DGS DUT Ground Sense. DGS is the ground reference for the DACs. Connect DGS to ground of the device-under-test. 6 TEMP Temperature Monitor Output 7, 17, 32, 40, 41, 49, 64 GND Ground 8 CS 9 SCLK FUNCTION Analog Ground Connection Chip-Select Input. Serial port activation input. Serial-Clock Input. Clock for serial port. 10 DIN Data Input. Serial port data input. 11 VDD Digital Interface Power-Supply Input 12 LOAD 13 RST 19 NDATA1 20 DATA1 21 VTERM1 Load Input. Latches serial register data into DACs. Reset Input. Asynchronous reset input for the serial register. Channel 1 Multiplexer Control Input N Channel 1 Multiplexer Control Input Differential controls DATA1 and NDATA1 select driver 1’s input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1. Drive NDATA1 above DATA1 to select DLV1. Channel 1 RCV/NRCV and DATA/NDATA Termination Voltage Input. Termination voltage input for the RCV1, NRCV1, DATA1, and NDATA1 differential inputs. ______________________________________________________________________________________ 15 MAX9973/MAX9974 Typical Operating Characteristics (continued) (TJ = +70°C, unless otherwise noted.) Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 Pin Description (continued) 16 PIN (MAX9973) NAME FUNCTION 22 NRCV1 23 RCV1 Channel 1 Multiplexer Control Input 25, 34, 47, 56 N.C. No Connection. Make no connection. 26 NCL1 27 CL1 Channel 1 Low Comparator Output 28 VT1 Comparator Termination Voltage Input. Termination voltage for the comparator output pullup resistors for channel 1. 29 NCH1 30 CH1 31 RHYST1 Channel 1 Multiplexer Control Input N Channel 1 Low Comparator Output N Channel 1 High Comparator Output N Channel 1 High Comparator Output Differential controls RCV1 and NRCV1 place channel 1 in receive mode. Drive RCV1 above NRCV1 to place channel 1 into receive mode. Drive NRCV1 above RCV1 to place channel 1 into drive mode. Differential outputs of channel 1 low comparator. Differential outputs of channel 1 high comparator. Comparator Hysteresis Programming Input for Channel 1 38 DUT1 Channel 1 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load. 43 DUT0 Channel 0 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load. 50 RHYST0 Comparator Hysteresis Programming Input for Channel 0 51 CH0 52 NCH0 Channel 0 High Comparator Output 53 VT0 Comparator Termination Voltage Input. Termination voltage for the comparator output pullup resistors for channel 0. 54 CL0 Channel 0 Low Comparator Output 55 NCL0 Channel 0 Low Comparator Output N 58 RCV0 Channel 0 Multiplexer Control Input 59 NRCV0 Channel 0 Multiplexer Control Input N 60 VTERM0 Channel 0 RCV/NRCV and DATA/NDATA Termination Voltage Input. Termination voltage input for the RCV0, NRCV0, DATA0, and NDATA0 differential inputs. 61 DATA0 62 NDATA0 — EP Channel 0 High Comparator Output N Channel 0 Multiplexer Control Input Channel 0 Multiplexer Control Input N Differential outputs of channel 0 high comparator. Differential outputs of channel 0 low comparator. Differential controls RCV0 and NRCV0 place channel 0 in receive mode. Drive RCV0 above NRCV0 to place channel 0 into receive mode. Drive NRCV0 above RCV0 to place channel 0 into drive mode. Differential controls DATA0 and NDATA0 select driver 0’s input from DHV0 or DLV0. Drive DATA0 above NDATA0 to select DHV0. Drive NDATA0 above DATA0 to select DLV0. Exposed Heat Removal Paddle. The paddle is electrically isolated from the die. Make no electrical connection to EP. ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 VCC CS VEE SCLK VDD DIN SERIAL INTERFACE TEMP TO DCL AND DACs RST 24 GND LOAD AGND REF SERIAL INTERFACE COMMON TO BOTH CHANNELS LDEN_ TMSEL_ LLEAK_ S1_ S0_ DCL_ MODE CONTROL DHV_ DAC DTV_ DAC 1000Ω DLV_ DAC LOAD DLV_ DTV_ DGS 1 LDEN_ DHV_ BUFFER 0 SLEW-RATE CONTROL MULTIPLEXER 50Ω 1 DATA_ S0_ DUT_ 0 LLEAK_ S1_ NDATA_ RCV_ NRCV_ HIGH IMPEDANCE TMSEL_ VTERM_ MAX9973 MAX9974 4 x 50Ω CPHV_ DAC CLAMPS CPLV_ DAC CH_ - NCH_ + VT_ CHV_ DAC COMPARATORS 4 x 50Ω CL_ + NCL_ - CLV_ DAC ONE OF TWO IDENTICAL CHANNELS SHOWN Figure 1. Functional Diagram ______________________________________________________________________________________ 17 Detailed Description The MAX9973/MAX9974 are fully integrated, high-performance, dual-channel pin electronics driver/comparator/load (DCL) with built-in level-setting DACs. Each channel includes a three-level pin driver with three levelsetting DACs, a window comparator with two level-setting DACs, two dynamic clamps with two level-setting DACs, and a 1kΩ load driven by the driver’s DTV_ DAC. Figure 1 shows a functional diagram of the MAX9973/MAX9974. The three-level pin driver features a wide -1.5V to +6.5V voltage range and includes high-impedance and activetermination (3rd-level drive) modes. High-speed differential multiplexer control inputs DATA and RCV with internal termination resistors switch the driver between the three input levels. Figure 2 shows a block diagram of the simplified driver channel. The dynamic clamps provide damping of high-speed DUT waveforms when high-impedance receive mode is selected. The loads facilitate fast contact testing when used in conjunction with the comparators. Loads also function as pullups for a device-under-test that has open-drain/collector outputs. A serial interface configures the device and its functions. The MAX9973/MAX9974 are available in a 64-pin (10mm x 10mm x 1.00mm) TQFP-EP package with an exposed paddle on top (MAX9973) or bottom (MAX9974) for heat removal. Power dissipation is only 700mW per channel. The full operating voltage range is -1.5V to +6.5V. Operation is specified with an internal die temperature of +40°C to +100°C. The devices feature a temperature monitor output. The window comparators provide extremely low timing variation. The MAX9973G/MAX9974G comparator opencollector outputs sink 8mA (typ), while the MAX9973H/ MAX9974H comparator outputs sink 16mA (typ). Figure 3 shows the comparator function. The driver input is a high-speed multiplexer that selects one of three DAC voltages: DHV_, DLV_, or DTV_. The high-speed differential inputs DATA_/NDATA_ and RCV_/NRVC_, and mode-control bit TMSEL_ control the 0 SLEW RATE 1 DTV_ DAC 0 50Ω DUT_ 1 + - 1 HIGH IMPEDANCE DATA_ NDATA_ VTERM_ MAX9973 MAX9974 BUFFER 0 DHV_ DAC HIGH-SPEED INPUTS Output Driver 0 DLV_ DAC 4 x 50Ω RCV_ + NRCV_ CPHV_ DAC CLAMPS CPLV_ DAC DCL MODE CONTROL BITS LLEAK_ SC1_ 4 SC0_ COMPARATORS AND LOAD TMSEL_ MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs Figure 2. Simplified Driver Channel 18 ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 MAX9973G MAX9974G CHV_ DAC DUT_ - CH_ + NCH_ 8mA VT_ 4 x 50Ω 8mA VEE CLV_ DAC + CL_ - NCL_ Figure 3. Comparator Functional Diagram Table 1. Driver Channel Logic HIGH-SPEED INPUTS MODE CONTROL BITS DATA_/NDATA_ RCV_/NRCV_ TMSEL_ (D3) LLEAK_ (D2) DUT_ DATA_ > NDATA_ RCV_ < NRCV_ X 0 DHV_ DATA_ < NDATA_ RCV_ < NRCV_ X 0 DLV_ X RCV_ > NRCV_ 1 0 DTV_ X RCV_ > NRCV_ 0 0 High impedance (clamps engaged) X X X 1 Low leakage X = Don’t care. Table 2. Driver Slew-Rate Logic Table 3. Comparator Logic MODE CONTROL BITS DRIVER SLEW RATE (%) COMPARATOR OUTPUTS COMPARATOR INPUTS S1_ (D1) S0_ (D0) 0 0 100 (fastest) 0 1 75 CH_ NCH_ CL_ NCL_ 1 0 50 0 0 0 1 0 1 25 (slowest) 0 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 0 1 1 switching between the DAC voltages (Table 1). A slewrate circuit controls the slew rate of the buffer input with one of four possible slew rates selectable (Table 2). The 100% slew rate is a function of the inherent speed of the multiplexer (see the Driver Large-Signal Response graph HIGH LOW DUT_ > CHV_ DUT_ > CLV_ COMPARATOR COMPARATOR in the Typical Operating Characteristics). DUT_ can be toggled at high speed between driver and high-impedance modes, or can be placed into low-leakage mode ______________________________________________________________________________________ 19 using mode control bit LLEAK_ (Figure 2, Table 1). In high-impedance mode, the bias current at DUT_ is less than 5µA over the -1.5V to +6.5V range, while the node maintains its ability to track high-speed signals. In lowleakage mode, the bias current at DUT_ is further reduced to less than ±10nA, and signal tracking slows. See the Low-Leakage Mode section for more details. The nominal driver output resistance is 50Ω. Contact the factory for different resistance values within the 48Ω to 52Ω range. impedance mode (Figure 2). For transient suppression, set the clamp voltages to approximately the minimum and maximum expected DUT_ voltage range. The optimal clamp voltages are application-specific and must be empirically determined. If clamping is not desired, set the clamp voltages at least 0.7V outside the expected DUT_ voltage range; overvoltage protection remains active without loading DUT_. Comparators SCLK UNUSED WRITE ENABLE CH0 REGISTER ADDRESS MAX9973 MAX9974 UNUSED Clamps The voltage clamps (high and low) limit the voltage at DUT_ and suppress reflections when the channel is configured as a high-impedance receiver. The clamps behave as diodes with series 50Ω resistors connected to the outputs of high-current buffers. Internal circuitry compensates for the diode drop at 1mA clamp current. Set the clamp voltages using DACs CPHV_ and CPLV_. The clamps are enabled only when the driver is in high- WRITE ENABLE CH1 The MAX9973/MAX9974 provide two independent highspeed comparators for each channel. Each comparator has one input connected internally to DUT_ and the other input connected to either DAC CHV_ or DAC CLV_ (see Figures 1 and 3). Comparator outputs are a logical result of the input conditions, as indicated in Table 3. The comparator differential outputs are opencollector to ease interfacing with a wide variety of logic families. The MAX9973G/MAX9974G switch an 8mA current sink between the two outputs, while the REGISTER DATA MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 DIN RST CS ENABLE 1 4 5 LATCH WRITE ENABLE_ ADDRESS DATA CS DCL_ 5 DATA 5 MODE CONTROL BITS LOAD LOAD 1 4 16 LATCH WRITE ENABLE_ ADDRESS DATA CS DHV_ DAC 16 DATA DHV_ LOAD 1 4 16 LATCH WRITE ENABLE_ ADDRESS DATA CLV_ DAC 16 DATA CS CLV_ LOAD Figure 4. Serial Interface Block Diagram 20 ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs HIGH-SPEED INPUT REGISTER ADDRESS BITS MODE CONTROL BITS LOAD REGISTER FUNCTION A3 A2 A1 A0 0 0 0 0 DCL mode RCV_/NRCV_ LLEAK_ (D2) TMSEL_ (D3) LDEN_ (D4) 0 0 0 1 DHV_ level RCV_ < NRCV_ 0 X X Off 0 0 1 0 DLV_ level X 0 X 0 Off 0 0 1 1 DTV_ level RCV_ > NRCV_ 0 0 1 On 0 1 0 0 CHV_ level RCV_ > NRCV_ 0 1 1 Off 0 1 0 1 CLV_ level X 1 X X Off 0 1 1 0 CPHV_ level X = Don’t care. Table 5. Serial Interface Data Bit Definitions BIT FUNCTION A7 Not used A6 Not used A5 Write enable channel 1 A4 Write enable channel 0 A3 A1 Register address (Table 6) A0 D15–D0 1 1 1 CPLV_ level 1 X X X Not used Table 7. DCL Mode Control Bits DIN BIT A2 0 Register data MAX9973H/MAX9974H switch 16mA. The 50Ω output termination resistors connect to voltage input VT_. Each output provides a nominal 400mVP-P swing and 50Ω source termination. 1kΩ Load The 1kΩ load is a resistor connected to DUT_ from the output of an internal buffer. The buffer’s input is DAC DTV_ (Figure 1). The buffer sinks and sources at least 6.9mA. A switch separates the resistor from the buffer. Operate the switch with serial control bits LDEN_, LLEAK_, and TMSEL_, and through high-speed differential input RCV_/NRCV_. Table 4 shows the truth table for the load-switch operation. DUT Ground-Sense Input The DUT ground-sense input (DGS) senses the ground potential of the device-under-test and allows the output and DAC levels of the MAX9973/MAX9974 to be set relative to that ground potential. Connect DGS to the ground of the device-under-test. BIT NAME FUNCTION POWER-UP STATE D4 LDEN Load enable 0 D3 TMSEL Terminate select 0 D2 LLEAK Low-leakage enable 1 D1 S1 0 D0 S0 Slew-rate control (Table 2) 0 Low-Leakage Mode Asserting LLEAK_ through the serial interface or with the digital input RST places the MAX9973/MAX9974 in a very low-leakage state (see the Electrical Characteristics table). With LLEAK_ asserted, the comparators, driver, clamps, and active load are disabled. This mode is convenient for making IDDQ and PMU measurements without the need for an output disconnect relay. LLEAK_ is programmed independently for each channel, while RST acts on both channels simultaneously. Serial Interface and Device Control A CMOS-compatible serial interface controls the MAX9973/MAX9974 modes (Figure 4, Table 5). Control data flow into a 24-bit shift register and is latched when CS is taken high, as shown in Figure 5. The first eight bits, A7–A0, determine which of the two channels is being commanded, and which DAC or DCL the following 16 bits program. The 16 bits, D15–D0, set the DAC voltage or control the setup of the MAX9973/MAX9974 through the mode control bits, as shown in Tables 5, 6, 7, and Figure 6. ______________________________________________________________________________________ 21 MAX9973/MAX9974 Table 6. Register Addresses Table 4. Load Logic MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs t1 SCLK t4 t6 t2 t3 t5 CS t9 t7 t8 A7 DIN A0 D15 D0 t12 LOAD t10 RST t11 Figure 5. Serial-Interface Timing High-speed differential inputs RCV_/NRCV_ and DATA_/NDATA_, in conjunction with control bits TMSEL_, LLEAK_, and LDEN_, manage the features of each channel. RST sets LLEAK = 1 for both channels, forcing both channels into low-leakage mode; all other bits are unaffected. At power-up, hold RST low until VCC and VEE have stabilized. 22 Serial Communication Figure 5 and the serial port timing section of the Electrical Characteristics table show the serial interface timing requirements. Note that the first rising clock edge, after CS goes low, shifts in bit A7, and the last rising clock edge latches in bit D0. Forcing LOAD low then transfers the data from the serial input register to the DACs and DCLs. ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MAX9973/MAX9974 DCL RESERVED SET TO ZEROS MODE BITS SEE TABLES 1, 2 AND 4 FOR MODE SETTINGS DHV DAC SETTING DHV LEVEL = (DAC SETTING x 152.59μV) - 2.5V DTV DAC SETTING DTV LEVEL = (DAC SETTING x 152.59μV) - 2.5V DLV DAC SETTING DLV LEVEL = (DAC SETTING x 152.59μV) - 2.5V CHV DAC SETTING CHV LEVEL = (DAC SETTING x 152.59μV) - 2.5V CLV DAC SETTING CLV LEVEL = (DAC SETTING x 152.59μV) - 2.5V CPHV DAC SETTING UNUSED CPHV LEVEL = (DAC SETTING x 2.4414mV) - 2.5V CPLV DAC SETTING UNUSED CPLV LEVEL = (DAC SETTING x 2.4414mV) - 2.5V Figure 6. Register Data for DCL and DAC Programming DACs as Driver Channel Inputs Heat Removal Digital-to-analog converters, programmed through the serial interface, provide input voltages to the three input multiplexers (DHV_, DTV_, and DLV_), the clamps (CPHV_ and CPLV_), the comparators (CHV_ and CLV_), and the load (DTV_ doubles as the load input voltage source). Set the DAC output voltages as detailed in Figure 6. Under normal circumstances, the MAX9973 requires heat removal through the exposed paddle through the use of an external heat sink. The exposed paddle is electrically isolated from the die. Make no electrical connection to the exposed paddle. Temperature Monitor The MAX9973 supplies a temperature output signal, TEMP, that asserts a nominal output voltage of 3.43V at a die temperature of +70°C (343K). The output voltage changes proportionally with temperature at 10mV/°C, but is not calibrated. Power-Supply Considerations Bypass all VCC and VEE power pins each with a 0.01µF capacitor, and use bulk bypassing of at least 10µF on each supply. ______________________________________________________________________________________ 23 Dual Driver/Comparator/Load with Internal DACs GND RHYST0 CH0 NCH0 VT0 CL0 NCL0 N.C. VCC RCV0 NRCV0 VTERM0 DATA0 NDATA0 VEE GND MAX9973/MAX9974 Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VEE 1 48 VEE VCC 2 47 N.C. AGND 3 46 VCC REF 4 45 VEE DGS 5 44 VCC TEMP 6 43 DUT0 42 VEE GND 7 MAX9973 CS 8 41 GND 40 GND SCLK 9 DIN 10 39 VEE VDD 11 38 DUT1 LOAD 12 37 VCC RST 13 36 VEE AGND 14 35 VCC VCC 15 34 N.C. VEE 16 33 VEE GND RHYST1 CH1 NCH1 VT1 CL1 NCL1 N.C. VCC RCV1 NRCV1 VTERM1 DATA1 NDATA1 VEE GND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TQFP-EP-IDP Chip Information PROCESS: BiCMOS 24 ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs 64L TQFP.EPS PACKAGE OUTLINE, 64L TQFP, 10x10x1.00mm EXPOSED PAD OPTION, INVERTED DIE PAD 21-0162 A 1 2 ______________________________________________________________________________________ 25 MAX9973/MAX9974 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX9973/MAX9974 Dual Driver/Comparator/Load with Internal DACs Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) PACKAGE OUTLINE, 64L TQFP, 10x10x1.00mm EXPOSED PAD OPTION, INVERTED DIE PAD 21-0162 A 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 26 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.