TI1 EMB1432Q 60v 14-channel battery stack module analog front end Datasheet

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EMB1432Q
SNOSB86D – JUNE 2011 – REVISED OCTOBER 2014
EMB1432Q 60-V, 14-Channel Battery Stack Module Analog Front End
1 Features
3 Description
•
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The EMB1432Q Battery Stack Module Analog Front
End is a high voltage analog interface designed to
monitor a lithium battery stack. It is able to select and
level shift the voltage across any of 14 stacked
batteries and 2 low voltage auxiliary inputs,
multiplexing the signals to an output pin. The
multiplexer output is set by writing to an internal
register using the SPI™ protocol or by directly
addressing 4 digital pins. The voltage across each
battery can range from –2 V to 5.5 V without
damaging the AFE, with the top cell positive pin
reaching 60 V. The SENSE(N) input impedance
(when the Nth battery is selected) is 1 MΩ typ, and
the current drawn from SENSE(N-1) is 2 µA typ.
When not selected or in shutdown mode, the current
at any sense input drops to less than 1 µA.
1
Positive Supply Voltage 4.75 V to 5.5 V
Negative Supply Voltage −5.5 V to −4 V
Positive Supply Current 750 µA (max)
VBATT = (VSENSE(N) − VSENSE(N−1)) 0.5 V to 4.6 V
VSENSE(14) 60 V (max)
Input Sense Current 6 µA (max)
Input Referred Offset Voltage ±1 mV (Max)
Digital Interface Supply 2.7 V to 5.5 V
Gain 1
Gain Error 0.05% (max)
Ambient Operating Temperature −40°C to 125°C
AEC Q100 Grade 1
2 Applications
•
•
•
•
•
The EMB1432Q can precisely level shift a battery
voltage ranging from 0.5 V to 4.6 V with a gain of 1,
an input referred offset voltage of ±1 mV and a gain
error of 0.05% (max). The EMB1432Q operates with
5 V and –5 V supplies. Single supply operation is
also supported: the –5 V supply can be internally
generated using an internal charge pump. The I/O
communication interface can be supplied through
dedicated supply pins (VIO, DGND). The EMB1432Q
is designed to provide accurate analog output over
the AEC-Q100 type 2 temperature range of –40°C to
105°C and to be able to operate up to 125°C.
Li-Ion Battery Management Systems
Hybrid and Electric Vehicles
Grid Storage
48 V Systems
UPS
Typical Application
VIO
Flying Cap 10 nF
Device Information(1)
PART NUMBER
CHP
CHPnSD
EMB1432Q
+5V
CHM
PACKAGE
WQFN (48)
BODY SIZE (NOM)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
+
1 PF
CHPVP
0.1 PF
+
1 PF
EMB1432Q
DGND
CHPVM
0.1 PF
100
0.1 PF
VM
+
GND
+5V
1 PF
0.1 PF
+
VP
1 PF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
EMB1432Q
SNOSB86D – JUNE 2011 – REVISED OCTOBER 2014
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
6.7 Typical Characteristics .............................................. 9
7
Detailed Description ............................................ 11
7.1 Functional Block Diagram ....................................... 11
7.2 Device Functional Modes........................................ 12
8
Applications and Implementation ...................... 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 14
9
Device and Documentation Support.................. 16
9.1 Trademarks ............................................................. 16
9.2 Electrostatic Discharge Caution .............................. 16
9.3 Glossary .................................................................. 16
10 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
Page
•
Added AEC Q100 Grade 1 .................................................................................................................................................... 1
•
Added new Applications on page 1; Device Information, Handling Ratings and Thermal Information tables, Power
Supply Recommendations, Layout, and Device and Documentation Support and Mechanical, Packaging, and
Orderable Information sections; reformatted Detailed Description and Application and Implementation sections;
added "Q" to part number....................................................................................................................................................... 1
•
Changed paddle to pad ......................................................................................................................................................... 4
Changes from Revision B (April 2013) to Revision C
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 13
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5 Pin Configuration and Functions
SDI
nSD
nRS
CHPnSD
CHP
41
40
39
38
37
SDO
44
CLK
NC
45
nCS
MUX3
46
42
MUX2
47
43
MUX1
48
WQFN (RHS)
48-Pin
Top View
MUX0
1
36
CHM
NC
2
35
CHPVP
VIO
3
34
NC
DGND
4
33
CHPVM
GND
5
32
VM
NC
6
31
GNDREF
NC
7
30
NC
VSENSE14
8
29
NC
VSENSE13
9
28
VP
VSENSE12
10
27
NC
VSENSE11
11
26
OUT
VSENSE10
12
25
AUX1
EMB1432Q
24
AUX2
21
VSENSE1
23
20
VSENSE2
GND
19
VSENSE3
22
18
VSENSE4
VSENSEGND
17
VSENSE5
15
VSENSE7
16
14
VSENSE8
VSENSE6
13
VSENSE9
DAP (Bottom Side)
Pin Functions
PIN
DESCRIPTION
NAME
NO.
MUX0
1
Multiplexer direct addressing bit 0.
NC
2
No Connection.
VIO
3
Digital Positive Supply.
DGND
4
Digital Ground.
GND
5
Analog ground. Internally shorted to pin 23.
NC
6
No Connection.
NC
7
No Connection.
VSENSE14
8
Channel 14. To be connected to the positive rail of the 14th battery.
VSENSE13
9
Channel 13. To be connected to the negative rail of the 14th battery and to the positive rail of the 13th
battery.
VSENSE12
10
Channel 12. To be connected to the negative rail of the 13th battery and to the positive rail of the 12th
battery.
VSENSE11
11
Channel 11. To be connected to the negative rail of the 12th battery and to the positive rail of the 11th
battery.
VSENSE10
12
Channel 10. To be connected to the negative rail of the 11th battery and to the positive rail of the 10th
battery.
VSENSE9
13
Channel 9. To be connected to the negative rail of the 10th battery and to the positive rail of the 9th
battery.
VSENSE8
14
Channel 8. To be connected to the negative rail of the 9th battery and to the positive rail of the 8th
battery.
VSENSE7
15
Channel 7. To be connected to the negative rail of the 8th battery and to the positive rail of the 7th
battery.
VSENSE6
16
Channel 6. To be connected to the negative rail of the 7th battery and to the positive rail of the 6th
battery.
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Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
VSENSE5
17
Channel 5. To be connected to the negative rail of the 6th battery and to the positive rail of the 5th
battery.
VSENSE4
18
Channel 4. To be connected to the negative rail of the 5th battery and to the positive rail of the 4th
battery.
VSENSE3
19
Channel 3. To be connected to the negative rail of the 4th battery and to the positive rail of the 3rd
battery.
VSENSE2
20
Channel 2. To be connected to the negative rail of the 3rd battery and to the positive rail of the 2nd
battery.
VSENSE1
21
Channel 1. To be connected to the negative rail of the 2nd battery and to the positive rail of the 1st
battery.
VSENSEGND
22
Channel 0. To be connected to the negative rail of the 1st battery.
GND
23
Analog Ground. Internally shorted to pin 5.
AUX2
24
Auxiliary analog input 2, unbuffered input.
AUX1
25
Auxiliary analog input 1, unbuffered input.
OUT
26
Analog Output.
NC
27
No Connection.
VP
28
+5 V positive supply. Attach a 0.1 µF bypass capacitor between VP and GND, as close as possible to
the pins.
NC
29
No Connection.
NC
30
No Connection.
GNDREF
31
Reference ground for the AFE analog output.
VM
32
–5 V negative voltage supply. Attach a 0.1 µF bypass capacitor between VM and GND, as close as
possible to the pins. If internal charge pump is set on, connect VM to CHPVM.
CHPVM
33
–5 V charge pump generated voltage supply. If using internal charge pump attach a 0.1 µF to 1µF
reservoir capacitor between CHPVM and DGND and connect to CHPVM to VM.
NC
34
No Connection.
CHPVP
35
Charge pump positive supply. Attach a 0.1µF bypass capacitor between CHPVP and GND, as close as
possible to the pins. Connect to VP on the board if using the internal charge pump.
CHM
36
Connect to negative pin of the charge pump flying capacitor (10nF).
CHP
37
Connect to positive pin of the charge pump fly capacitor (10nF).
CHPnSD
38
Charge pump shutdown, active low. Connect to VIO to turn on charge pump, connect to GND to
shutdown charge pump.
nRS
39
AFE SPI register reset, active low. Connect to VIO for normal use, connect to GND to reset register.
nSD
40
AFE shut down, active low. Connect to VIO for normal use, connect to GND to shutdown AFE.
SDI
41
AFE SPI Serial Data In.
nCS
42
AFE SPI Chip Select, active low.
CLK
43
AFE SPI Clock.
SDO
44
AFE SPI Serial Data Out. In Tri-state when nCS is high.
NC
45
No Connection.
MUX3
46
Multiplexer direct addressing bit 3.
MUX2
47
Multiplexer direct addressing bit 2.
48
Multiplexer direct addressing bit 1.
Thermal Pad
Die Attach Pad, connect to GND.
MUX1
DAP
4
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2) (3)
MAX
UNIT
VP, VIO, CHPVP
Positive supply voltage
MIN
TYP
6
V
VM
Negative supply voltage
–6
V
CHM
Charge Pump negative pin
–6
V
CHP
Charge Pump positive pin
(VSENSE(N)-VSENSE(N-1))
Differential input voltage across battery cell
AUX1, AUX2
Auxiliary inputs
CHPnSD, nRS, nSD, MUX0, MUX1,
MUX2, MUX3, SDI, nCS, CLK, SDO
Digital inputs
6
V
5.5
V
6
V
VIO+0.3
V
−2
−0.3
VSENSE 14
70
V
Junction temperature (4)
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability for
specifications.
For soldering specifications: see SNOA549.
The maximum power dissipation is a function of TJ(MAX), RθJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC
board.
6.2 Handling Ratings
MIN
V(ESD)
(1)
Electrostatic discharge
MAX
Human body model (HBM), per AEC Q100-002 (1)
2000
Machine Model
200
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions (1)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VP, CHPVP
Analog positive supply voltage
4.75
5.5
V
VIO
Digital positive supply voltage
2.7
5.5
V
VM
Analog negative supply voltage
–5.5
–4.0
V
Operating temperature range
--40
125
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.4 Thermal Information
EMB1432Q
THERMAL METRIC
(1)
WQFN (RHS)
UNIT
48 PINS
RθJA
(1)
(2)
Junction-to-ambient thermal resistance (2)
24.8
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), RθJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC
board.
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6.5 Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for TA = 25°C, VP, = VIO = CHPVP = nRS = nSD = 5 V, GND = CHPnSD = 0 V,
VM = −5 V, 0.5 V < VBATT < 4.6 V, VBATT = VSENSE(N) − VSENSE(N−1).
PARAMETER
TA = 25°C, 1 V < VBATT < 4 V
Input offset voltage (4)
VOS
MIN (2)
TEST CONDITIONS
(5)
TA = 0°C to 65°C, 1 V < VBATT < 4 V (5)
VOSDRIFT
Long-term offset drift
500 hours OPL (5)
RSENSE
Sense input resistance
SENSE(N), Nth channel selected, VBATT = 4
V, FB = 0
1
−1.5
1.5
−2
2
−2.5 (6)
2.5 (6)
±0.25
0.92
(6)
SENSE(N−1) (7)
ISENSE
IVP
Sense input current
Positive supply current
IVM
Negative supply current
IVIO
VIO supply current
ICHPVP
IVR
AV
CHPVP supply current
1.06
0.004
0.5 (6)
0.004
4 (6)
Measurement mode, nSD = VIO, VBATT = 4 V
0.46
(6)
mA
µA
0.45
37
70
(6)
µA
0.002
0.25 (6)
µA
Measurement mode, nSD = VIO, VBATT = 4 V
100
(6)
µA
Shutdown mode, nSD = 0 V
0.01
8 (6)
µA
Charge pump on, connected to VM (CHPnSD
= VIO)
108
180 (6)
µA
Charge pump off (CHPnSD = 0 V)
3.3
8 (6)
µA
0.5
VP − 0.4
V
0
VP
V
Shutdown mode, nSD = 0 V
(5)
Input voltage range
SENSE(N) − SENSE(N−1)
Input voltage range,
auxiliary inputs
See
Gain
1 V < VBATT < 4 V
Gain error
TA = 25°C, 1 V < VBATT < 4 V (5)
(5)
(5)
250
1
V/V
±0.05%
±0.1% (6)
(5)
CL = 30 pF (5) (8)
SR
Slew rate
CL = 30 pF (5) (8) (9)
COUT
Output capacitive load
See
+PSR
Positive power supply
rejection
4.5 < VP < 5.5 V, f = 1 kHz
−PSR
Negative power supply
rejection
−5.5 V < VM < −4.5 V, f = 1 kHz (5) (8)
6
0.75
0.004
Measurement mode, nSD = VIO, VBATT = 4 V
TA = 0°C to 65°C, 1V < VBATT < 4 V
(5)
(6)
(7)
(8)
(9)
MΩ
µA
Shutdown mode, nSD = 0 V
Bandwidth
(4)
mV
(6)
Gain error drift
(3)
(6)
All other sense
pins except
SENSE(N)
when nSD = 5
V, all sense pins
when nSD = 0
V. (7)
BW
(2)
1.20
6 (6)
Nth channel selected,
VBATT = 4 V
UNIT
mV
2
TA = −40°C to 125°C, 1 V < VBATT < 4 V
(1)
MAX (2)
−1
TA = −40°C to 105°C, 1V < VBATT < 4 V (5)
TA = −40°C to 125°C, 1 V < VBATT < 4 V
TYP (3)
(5) (8)
(5) (8)
5
ppm/°C
500
kHz
7
V/µs
30
pF
70
dB
65
dB
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which
the device may be permanently degraded, either mechanically or electrically.
Limits are verified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are verified through
correlations using statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
Limits apply at the nominal temperature.
Limits apply at the temperature extremes.
Positive Bias Current corresponds to current flowing into the device.
This parameter is verified by design and/or characterization and is not tested in production.
The number specified is the slower of rising and falling slew rate and measured at 90% to 10%.
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Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured for TA = 25°C, VP, = VIO = CHPVP = nRS = nSD = 5 V, GND = CHPnSD = 0 V,
VM = −5 V, 0.5 V < VBATT < 4.6 V, VBATT = VSENSE(N) − VSENSE(N−1).
PARAMETER
0.51 (6)
VBATT = 4.6 V
4.59 (6)
4.61 (6)
ROUTAUX
Output resistance when
AUX1 or AUX2 are
selected
See
eN
Input voltage noise
0.1 Hz to 10 Hz (5) (8)
eN
Input voltage noise
density
f = 1 kHz
tSETTLE
1% settling time
Time from nCS rising edge to OUT voltage
stable, VOUT = 3.6 V
fCP
Charge pump switching
frequency
See
VIL
Input logic low threshold
See
See
VOL
Output logic low threshold
VOH
Output logic high
threshold
MAX (2)
0.49 (6)
Output voltage range
Input logic high threshold
TYP (3)
VBATT = 0.5 V
VOUT
VIH
MIN (2)
TEST CONDITIONS
(5)
UNIT
V
Ω
400
4
(5)
µVPP
825
1.5
(5) (8)
nV/rtHz
4 (6)
µs
380
(5)
kHz
0.3 × VIO
(5)
V
0.7 × VIO
V
ISDO = 100 µA (5)
0.2
ISDO = 2 mA (5)
0.5
ISDO = 100 µA (5)
VIO − 0.2
ISDO = 2 mA (5)
VIO − 0.6
V
V
6.6 Timing Requirements (1)
Unless otherwise specified, all limits ensured for TA = 25°C, 2.7 V < VIO < 5.5 V.
See (2)
MIN (3)
NOM
MAX (3)
UNIT
t1
High period, CLK,
100
ns
t2
Low period, CLK
100
ns
t3
Setup time, nCS to CLK
50
ns
t4
Setup time, SDI to CLK
30
ns
t5
Hold time, CLK to SDI
10
ns
t6
Setup time, SDO to CLK
30
ns
t7
Hold time, CLK to SDO
10
ns
t8
Hold time, CLK transition to nCS rising edge
50
ns
t9
nCS inactive
50
ns
t10
Propagation delay, nCS to SDO active
t11
Hold time, CLK transition to nCS falling edge
10
tr/tf
Signal rise and fall time, see (4)
1.5
(1)
(2)
(3)
(4)
50
ns
ns
5
ns
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which
the device may be permanently degraded, either mechanically or electrically.
Load for these tests is shown in Figure 1.
Limits are verified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are verified through
correlations using statistical quality control (SQC) method.
This parameter is verified by design and/or characterization and is not tested in production.
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IOL
VIO/2
TO PIN
CL
20 pF
IOH
Figure 1. Test Circuit Diagram
SCK
t11
t3
t2
t1
t4
t5
t8
nCS
DN
SDI
t10
SDO
t9
DN±4
t6
t7
OLD DN
OLD DN±4
Where:
DN = B3, DN-1 = B2, DN-2 = B1, DN-3 = B0, DN-4 = FB
Figure 2. Timing Diagram
8
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6.7 Typical Characteristics
1.01
1.01
1.00
1.00
0.99
0.99
GAIN (V/V)
GAIN (V/V)
Unless otherwise specified, TA = 25°C, VP = VIO = CHPVP = nRS = nSD = 5 V, GND = CHPnSD = 0 V, VM = −5 V, 0.5 V <
VBATT < 4.6 V, VBATT = VSENSE(N) − VSENSE(N−1), RL = 1 MΩ, CL = 30 pF.
0.98
0.98
0.97
0.97
0.96
0.96
Input: 1.5V to 2V
0.95
10
100
1k
10k
100k
0.95
10
1M
2.25
2.25
2.00
2.00
0.25 V/DIV
0.25 V/DIV
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 4. Large Signal Gain
FREQUENCY (Hz)
Figure 3. Small Signal Gain
1.75
1.50
1.75
1.50
Input: 1 kHz, 1.5V to 2V
Input: 1 kHz, 1.5V to 2V
1.25
1.25
1 Ps/DIV
1 Ps/DIV
Figure 5. Small Signal Step Response
Figure 6. Small Signal Step Response
5.0
5.0
4.0
4.0
3.0
3.0
1 V/DIV
1 V/DIV
Input: 1V to 4V
2.0
1.0
2.0
1.0
Input: 1 kHz, 1V to 4V
Input: 1 kHz, 1V to 4V
0.0
0.0
1 Ps/DIV
1 Ps/DIV
Figure 7. Large Signal Step Response
Figure 8. Large Signal Step Response
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C, VP = VIO = CHPVP = nRS = nSD = 5 V, GND = CHPnSD = 0 V, VM = −5 V, 0.5 V <
VBATT < 4.6 V, VBATT = VSENSE(N) − VSENSE(N−1), RL = 1 MΩ, CL = 30 pF.
5
4
Switching Between Battery 6 to Battery 5
Each Battery Approx. 3.6 V
4
3
2
(V)
NOISE (µV/rtHz)
3
nCS
2
1
VOUT
1
0
1
10
100
1k
10k
100k
0
(1 Ps/DIV)
Figure 10. Switching Waveform
80
80
60
60
40
40
PSR (dB)
PSR (dB)
FREQUENCY (Hz)
Figure 9. Voltage Noise vs. Frequency
20
20
0
0
VP = 4.5V to 5.5V
VM = -5V
VSENSE1 t VSENSEGND = 3V
-20
1
10
10
100
1k
VP =5V
VM = -5.5V to -4.5V
VSENSE1 t VSENSEGND = 3V
-20
10k 100k
1M
1
10
100
1k
10k 100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. +PSR vs. Frequency
Figure 12. −PSR vs. Frequency
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7 Detailed Description
7.1 Functional Block Diagram
VP = +5V
Channel
selector
VSENSE14
+
+
VSENSE13
+
VSENSE12
+
VSENSE11
+
VSENSE10
+
VSENSE9
+
VSENSE8
+
VSENSE7
+
VSENSE6
+
VSENSE5
CLK
SDI
S
P
I
nCS
nRS
SDO
VIO
DGND
MUX0
+
MUX1
MUX2
MUX3
M
U
X
VSENSE4
+
VSENSE3
+
VSENSE2
+
VSENSE1
OUT
EMB1432Q
VSENSEGND
GND
AUX1
AUX2
GND REF
nSD
CHPVM
CHPVP
OSC
CHP
DGND
CHM
CHPnSD
VM = CHPVM or -5V
Figure 13. Battery Stack Monitor
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7.2 Device Functional Modes
7.2.1 SPI Multiplexer Addressing Mode
To control the EMB1432Q using SPI connect the MUX0, MUX1, MUX2, and MUX3 pins to VIO.
The input source of the EMB1432Q is controlled by data stored in a programming register. Data to be written into
the control register is first loaded into the AFE via the serial interface. The serial interface control employs the 5
bits of an internal shift register. Data is loaded through the serial data input, SDI. Data passing through the shift
register are available through the serial data output, SDO. When the nCS is high the SDO is in tri-state. The
serial clock, CLK controls the serial loading process. The first bit entering the register is the source address code
MSB (B3). The last bit clocked in is the Force Current bit (FB).
At the 5th CLK falling edge, the first bit that was clocked in reappears at SDO. The falling edge of nCS which
occurs while CLK is high will enable the shift register to receive data. Each data bit is clocked into the shift
register on the rising edge of CLK. The rising edge of nCS loads the shift register content into the store register
and the addressing process begins. The settling time between the rising edge of nCS and a stable output is
approximately 2 µs. Operation is shown in Table 1.
Table 1. Register Organization
B3
B2
B1
B0
RESERVED
Address
Set to 0
Addresses from 0000b to 1101b will point to the battery stack, from the bottom battery at 0000b to the 14th
battery at 1101b. Addresses 1110b to 1111b point to Auxiliary Input 1 and Auxiliary Input 2, which are the 2
additional analog inputs.
7.2.2 Direct Multiplexer Addressing Mode
For maximizing the multiplexing speed of the 14 battery inputs, the SPI digital interface can be bypassed using
four dedicated bit lines (MUX[3:0]) for multiplexer addressing. If this mode is chosen, the selection of the source
is made by setting these 4 bits with MUX3 as MSB and MUX0 as LSB. Refer to Table 2 for each source address.
If this mode is not used, MUX0 to MUX3 pins must be tied to VIO to use SPI communication.
Note that Auxiliary Input 1 and Auxiliary Input 2 are not available in the Direct Multiplexer Addressing Mode. Also,
the SPI pins are ignored in this mode.
Table 2. Source Selection
DIRECT MULTIPLEXER ADDRESSING MODE
SPI MULTIPLEXER ADDRESSING MODE
Source
MUX3
MUX2
MUX1
MUX0
B3
B2
B1
B0
Source
Battery 1
0
0
0
0
0
0
0
0
Battery 1
Battery 2
0
0
0
1
0
0
0
1
Battery 2
Battery 3
0
0
1
0
0
0
1
0
Battery 3
Battery 4
0
0
1
1
0
0
1
1
Battery 4
Battery 5
0
1
0
0
0
1
0
0
Battery 5
Battery 6
0
1
0
1
0
1
0
1
Battery 6
Battery 7
0
1
1
0
0
1
1
0
Battery 7
Battery 8
0
1
1
1
0
1
1
1
Battery 8
Battery 9
1
0
0
0
1
0
0
0
Battery 9
Battery 10
1
0
0
1
1
0
0
1
Battery 10
Battery 11
1
0
1
0
1
0
1
0
Battery 11
Battery 12
1
0
1
1
1
0
1
1
Battery 12
Battery 13
1
1
0
0
1
1
0
0
Battery 13
Battery 14
1
1
0
1
1
1
0
1
Battery 14
12
AUX1
Not Selectable
1
1
1
0
AUX1
AUX2
Not Selectable
1
1
1
1
AUX2
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After the source address is programmed, the differential voltage appearing between Nth battery pins will be level
shifted and presented at the output. If one of the two auxiliary inputs is selected, the voltage difference between
this pin and GND is directly passed to the output pin. After a typical settling time of 2 μs the voltage at the output
is valid. To ensure high precision in the measurement, the clock signal should be turned off after source
selection.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Control Methods
The Multiplexer is a 16:1 single ended output. The selection of the source is made through either the MUX[3:0]
digital input pins or, if MUX[3:0]=1111b, through the SPI digital interface as described in SPI Multiplexer
Addressing Mode and Direct Multiplexer Addressing Mode.
8.2 Typical Applications
8.2.1 Double Supply Operation
CHP
CHPnSD
Figure 14 shows the EMB1432Q set up for double supply operation. The VM and VP pins should each have a
0.1 µF capacitor connected as close as possible to the pin. Each pin should also have a capacitor of at least 1
µF connected to it. CHPnSD should be connected to ground.
CHM
CHPVP
EMB1432Q
CHPVM
1 PF
+
DGND
-5V
GND
VM
0.1 PF
+5V
0.1 PF
+
VP
1 PF
Figure 14. Schematic for Double Supply Operation
8.2.2 Detailed Design Procedure
The EMB1432Q is provided with an internal charge pump which supplies the correct negative voltage to VM.
This enables the EMB1432Q to operate using only a single positive supply. This is done by doing the following:
1. Connect a 10nF flying capacitor between CHP and CHM.
2. Connect a ceramic capacitor of at least 1 µF between CHPVM and GND. It should be close to the CHPVM
pin. A 0.1 µF capacitor can also be connected between CHPVM and GND for additional filtering of the
charge pump switching noise.
3. Connect the negative supply pin VM to CHPVM. The 100 Ω resistor between CHPVM and VM is optional (it
can be replaced by a short) but recommended to filter the charge pump switching noise.
14
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Typical Applications (continued)
4. To enable the internal charge pump, tie CHPnSD to VIO. If CHPnSD is connected to GND the internal
charge pump is disabled.
8.2.3 Typical Application: Single Supply Operation
Figure 15 shows how to connect the external components to the EMB1432Q to use the charge pump. It is
advisable to connect the bypass capacitors on CHPVP and the storage capacitor on CHPVM to the DGND pin.
Flying Cap 10 nF
CHP
CHPnSD
VIO
+5V
CHM
+
1 PF
CHPVP
0.1 PF
+
1 PF
EMB1432Q
DGND
CHPVM
0.1 PF
100
0.1 PF
VM
+
GND
+5V
1 PF
0.1 PF
+
VP
1 PF
Figure 15. Schematic for Single Supply Operation
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9 Device and Documentation Support
9.1 Trademarks
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
9.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanica,l packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
EMB1432QSQ/NOPB
PREVIEW
WQFN
RHS
48
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
EMB1432Q
EMB1432QSQE/NOPB
PREVIEW
WQFN
RHS
48
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
EMB1432Q
EMB1432QSQX/NOPB
PREVIEW
WQFN
RHS
48
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
EMB1432Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
EMB1432QSQ/NOPB
WQFN
RHS
48
0
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
EMB1432QSQE/NOPB
WQFN
RHS
48
0
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
EMB1432QSQX/NOPB
WQFN
RHS
48
0
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
EMB1432QSQ/NOPB
WQFN
RHS
48
0
367.0
367.0
38.0
EMB1432QSQE/NOPB
WQFN
RHS
48
0
213.0
191.0
55.0
EMB1432QSQX/NOPB
WQFN
RHS
48
0
367.0
367.0
38.0
Pack Materials-Page 2
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