ICS932S801 Integrated Circuit Systems, Inc. K8 Clock Chip for Serverworks GC-HT 2-Way Servers Recommended Application: Serverworks GC-HT systems using AMD K8 processors Pin Configuration Features: • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • M/N programming via SMBus 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ICS932S801 X1 X2 VDD48 48MHz_0 48MHz_1 GND SCLK SDATA VDDHTT HTTCLK0 HTTCLK1 HTTCLK2 HTTCLK3 GNDHTT VDDPCI PCICLK0 PCICLK1 PCICLK2 PCICLK3 GNDPCI PD# VDDA GNDA IREF Output Features: • 4 - Pairs of AMD K8 clocks • 1 - Pair of SRC/PCI Express* clock • 2 - 14.318 MHz REF clocks • 2 - USB_48MHz clocks • 4 - HyperTransport 66 MHz clocks • 4 - PCI 33 MHz clocks VDDREF FS0/REF0 FS1/REF1 FS2 GND CPUCLK8T0 CPUCLK8C0 VDDCPU GNDCPU CPUCLK8T1 CPUCLK8C1 VDDCPU GNDCPU CPUCLK8T2 CPUCLK8C2 VDDCPU GNDCPU CPUCLK8T3 CPUCLK8C3 SPREAD_EN GNDSRC VDDSRC SRCCLKT0 SRCCLKC0 48-SSOP, TSSOP Functionality Power Groups Pin Number VDD GND 3 6 9 14 15 20 22 23 27 28 33,37,41 32,36,40 48 44 0959C—03/13/06 CPU HTT PCI MHz MHz MHz 0 Hi-Z Hi-Z Hi-Z 1 X X/3 X/6 1 0 180.00 60.00 30.00 0 1 1 220.00 73.12 36.56 1 0 0 100.00 66.66 33.33 1 0 1 133.33 66.66 33.33 1 1 0 166.67 66.66 33.33 1 1 1 200.00 66.66 33.33 Description FS2 FS1 FS0 48MHz 66MHz HTT Clocks 33 MHz PCI Clocks IREF, Analog Core SRC PLL, SRCCLK K8 CPU Clocks, CPU PLL REF Clocks, Xtal Oscillator 0 0 0 0 0 *Other names and brands may be claimed as the property of others. ICS932S801 Pin Descriptions PIN # PIN NAME PIN TYPE IN OUT PWR OUT OUT PWR I/O I/O PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 X1 X2 VDD48 48MHz_0 48MHz_1 GND SCLK SDATA VDDHTT HTTCLK0 HTTCLK1 HTTCLK2 HTTCLK3 GNDHTT VDDPCI PCICLK0 PCICLK1 PCICLK2 PCICLK3 GNDPCI 21 PD# 22 23 VDDA GNDA PWR OUT 24 IREF OUT 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SRCCLKC0 SRCCLKT0 VDDSRC GNDSRC SPREAD_EN CPUCLK8C3 CPUCLK8T3 GNDCPU VDDCPU CPUCLK8C2 CPUCLK8T2 GNDCPU VDDCPU CPUCLK8C1 CPUCLK8T1 GNDCPU VDDCPU CPUCLK8C0 CPUCLK8T0 GND FS2 FS1/REF1 FS0/REF0 VDDREF OUT OUT PWR PWR IN OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR IN I/O I/O PWR IN DESCRIPTION Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power pin for the 48MHz output.3.3V 48MHz clock output. 48MHz clock output. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Supply for HTT clocks, nominal 3.3V. 3.3V Hyper Transport output 3.3V Hyper Transport output 3.3V Hyper Transport output 3.3V Hyper Transport output Ground pin for the HTT outputs Power supply for PCI clocks, nominal 3.3V PCI clock output. PCI clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Asynchronous active low input pin used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. 3.3V power for the PLL core. Ground pin for the PLL core. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs Asynchronous, active high input to enable spread spectrum functionality. Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin. Frequency select pin. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V 0959C—03/13/06 2 ICS932S801 General Description The ICS932S801 is a main clock synthesizer chip that, when paired with ICS9DB108, provides all clocks required by Serverworks GC-HT-based servers. An SMBus interface allows full control of the device. Block Diagram REF(1:0) X1 XTAL OSC. X2 CPU PLL FS(2:0) PD# SPREAD SD ATA SCLK 48MHz(1:0) FIXED PLL PCI33 DIV PCICLK(3:0) HTT66 DIV HTTCLK(3:0) CPU DIV CPUCLK8(3:0) SRC DIV1 SRCCLK(0) CONTROL LOGIC SRC PLL IR EF Skew Characteristics Parameter T i Tsk_CPU_CPU m e Test Conditions CPU to CPU Skew Measured at crossing points of CPUCLKT rising edges 250 ps Meastured at crossing point for CPUCLKT and 1.5V for PCI clock 2000 ps Measured between rising edges at 1.5V 500 ps Meastured at crossing point for CPUCLKT and 1.5V for HT66 clock 2000 ps Measured at crossing points of CPUCLKT rising edges 200 ps Meastured at crossing point for CPUCLKT and 1.5V for PCI clock 200 ps Measured between rising edges at 1.5V 200 ps Meastured at crossing point for CPUCLKT and 1.5V for HT66 clock 200 ps I Tsk_CPU_PCI CPU to PCI skew n d e p Tsk_PCI33-HT66 PCI33 to HT66 skew e n e n Tsk_CPU_HT66 CPU to HT66 skew t T Tsk_CPU_CPU i m e Tsk_CPU_PCI Skew Unit Window Description CPU to CPU Skew CPU to PCI skew V a r Tsk_PCI33-HT66 PCI33 to HT66 skew i a n t Tsk_CPU_HT66 CPU to HT66 skew 0959C—03/13/06 3 ICS932S801 Table1: SRC Frequency Selection Table SRCFS1 B5b3 SRCFS0 B5b2 SRCCLK (MHz) 0 0 100.00 0 1 101.00 1 0 102.00 1 1 104.00 Table 2: CPU Divider Ratios Divider (1:0) Divider (3:2) Bit 00 01 10 11 LSB 00 0000 0001 0010 0011 Address 2 3 5 15 Div 01 0100 0101 0110 0111 Address 4 3 5 15 Div 01 0100 0101 0110 0111 Address 2 3 5 7 Div 01 0100 0101 0110 0111 Address 4 6 10 30 Div 10 1000 1001 1010 1011 Address 8 12 20 60 Div 11 1100 1101 1110 1111 Address MSB 16 24 40 120 Div 10 1000 1001 1010 1011 Address 16 12 20 60 Div 11 1100 1101 1110 1111 Address MSB 32 24 40 120 Div 10 1000 1001 1010 1011 Address 8 12 20 28 Div 11 1100 1101 1110 1111 Address MSB 16 24 40 56 Div Table 3: HTT Divider Ratios Divider (1:0) Divider (3:2) Bit 00 01 10 11 LSB 00 0000 0001 0010 0011 Address 8 6 10 30 Div Table 4: SRC Divider Ratios Divider (1:0) Divider (3:2) Bit 00 01 10 11 LSB 00 0000 0001 0010 0011 Address 4 6 10 14 Div 0959C—03/13/06 4 ICS932S801 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +3.8 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD VIN = 0 V; Inputs with no pull-up resistors -5 5 uA 1 -5 uA 1 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1 IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX all outputs driven 7 5 6 5 mA mA MHz nH pF pF pF 3 1 1 1 1 3 ms 1,2 33 5.5 0.4 kHz V V mA 1 1 1 1 1000 ns 1 300 ns 1 IIL1 Input Low Current Operating Current Powerdown Current 3 Input Frequency 1 Pin Inductance Input Capacitance Clk Stabilization 1 1,2 TSTAB VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or de-assertion of PD# to 1st clock Triangular Modulation TYP 325 100 14.31818 Modulation Frequency 30 VDD SMBus Voltage 2.7 VOL @ IPULLUP Low-level Output Voltage Current sinking at VOL = 0.4 V IPULLUP 4 SCLK/SDATA TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 3 Clock/Data Rise Time SCLK/SDATA TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 3 Clock/Data Fall Time 1 Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 0959C—03/13/06 5 MAX UNITS NOTES ICS932S801 Electrical Characteristics - K8 Push Pull Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load PARAMETER SYMBOL CONDITIONS Rising Edge Rate δV/δt Falling Edge Rate δV/δt Measured at the AMD64 processor's test load. 0 V +/- 400 mV (differential measurement) Differential Voltage Change in VDIFF_DC Magnitude VDIFF VCM Change in Common Mode Voltage ∆VCM Jitter, Cycle to cycle tjcyc-cyc 2 10 V/ns 1 2 10 V/ns 1 V 1 mV 1 V 1 200 mV 1 100 200 ps 1 0.4 ∆VDIFF Common Mode Voltage MIN TYP MAX UNITS NOTES -150 Measured at the AMD64 processor's test load. (single-ended measurement) 150 1.05 1.25 1.45 -200 Measurement from differential wavefrom. Maximum difference of cycle time between 2 adjacent cycles. 1.25 2.3 0 Measured using the JIT2 software package with a Tek 7404 scope. TIE (Time Interval Error) measurement tja -1000 1000 Jitter, Accumulated technique: Sample resolution = 50 ps, Sample Duration = 10 µs Measurement from differential dt3 45 53 Duty Cycle wavefrom Average value during switching RON Output Impedance 35 55 transition. Used for determining series 15 termination value. Measurement from differential tsrc-skew 250 Group Skew wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz 3 Spread Spectrum is off 0959C—03/13/06 6 1,2,3 % 1 Ω 1 ps 1 ICS932S801 Electrical Characteristics - SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER SYMBOL CONDITIONS MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 Voltage Low VLow Max Voltage Min Voltage Vovs Vuds Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Tabsmin tr tf d-tr d-tf MAX UNITS NOTES Ω 1 850 1,3 mV -150 150 1150 -300 250 Variation of crossing over all edges see Tperiod min-max values 100.00 MHz nominal 100.00 MHz spread @100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP 1,3 mV 1 1 350 550 mV 1 12 140 mV 1 ppm ns ns ns ps ps ps ps 1,2 2 2 1,2 1 1 1 1 -300 300 9.9970 10.0000 10.0030 9.9970 10.0530 9.8720 175 700 175 700 30 125 30 125 Measurement from differential 45 55 % 1 wavefrom Measurement from differential tsrc-skew Group Skew N/A ps wavefrom PCI Express Gen 1 phase jitter 38 86 ps 1, 4 CPU=200MHz, Spread off tjphase-pcie1 Jitter, Phase PCI Express Gen 1 phase jitter 52 86 ps 1, 4 CPU=200MHz, Spread on Measurement from differential tjcyc-cyc Jitter, Cycle to cycle 100 ps 1 wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 4 Per PCI SIG method for PCI Express Gen 1. Visit http://www.pcisig.com for details. Duty Cycle dt3 0959C—03/13/06 7 ICS932S801 Electrical Characteristics - PCICLK 33 MHz, HTTCLK 66 MHz Clocks TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm PCI33 Clock period Tperiod HTT66 Clock period Tperiod Output High Voltage Output Low Voltage VOH VOL see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread 66.67MHz output nominal 66.67MHz output spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V -300 29.9910 29.9910 14.9955 14.9955 2.4 Rising edge rate Falling edge rate VT = 1.5 V VT = 1.5 V VT = 1.5 V 1 1 45 Output High Current IOH Output Low Current IOL Edge Rate Edge Rate Duty Cycle Skew Jitter, Cycle to cycle δV/δt δV/δt dt1 tsk1 tjcyc-cyc TYP MAX UNITS Notes 300 30.0090 30.1598 15.0045 15.0799 0.55 -33 -33 30 38 4 4 55 200 250 ppm ns ns ns ns V V mA mA mA mA V/ns V/ns % ps ps 1,2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz Electrical Characteristics - 48MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod VOH VOL see Tperiod min-max values 48.00MHz output nominal IOH = -1 mA IOL = 1 mA V OH @ MIN = 1.0 V VOH@ MAX = 3.135 V VOL @MIN = 1.95 V VOL @ MAX = 0.4 V Rising edge rate Falling edge rate VT = 1.5 V VT = 1.5 V VT = 1.5 V -100 20.8257 2.4 Output High Current IOH Output Low Current IOL Edge Rate Edge Rate Duty Cycle Skew Jitter, Cycle to cycle δV/δt δV/δt dt1 tsk1 tjcyc-cyc 1 TYP MAX 100 20.8340 0.55 -33 -33 30 1 1 45 38 4 4 55 50 200 UNITS Notes ppm ns V V mA mA mA mA V/ns V/ns % ps ps Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz 2 0959C—03/13/06 8 1,2 2 1 1 1 1 1 1 1 1 1 1 1 ICS932S801 Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 27 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod VOH VOL -300 69.8270 2.4 Output High Current IOH Output Low Current IOL Edge Rate Edge Rate δV/δt δV/δt dt1 tsk1 tjcyc-cyc see Tperiod min-max values 14.318MHz output nominal IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Rising edge rate Falling edge rate VT = 1.5 V VT = 1.5 V VT = 1.5 V Duty Cycle Skew Jitter, Cycle to cycle 1 TYP MAX 300 69.8550 UNITS Notes 0.4 ppm ns V V 1 2 1 1 -29 -23 mA 1 29 27 mA 1 1 1 2 2 V/ns V/ns 1 1 45 55 50 1000 % ps ps 1 1 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz 2 0959C—03/13/06 9 ICS932S801 General SMBus serial interface information How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0959C—03/13/06 10 Not acknowledge stoP bit ICS932S801 SMBus Table: Frequency Select and Spread Control Register Pin # Name Control Function Type Byte 0 Bit 7 - FS Source Bit 6 - CPU SS_EN Bit 5 - SRC SS_EN Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Reserved FS3 FS2 FS1 FS0 0 1 PWD Latched Inputs SMBus 0 RW OFF ON 0 RW OFF ON 0 Latched Input or SMBus RW Frequency Select Spread Enable for CPU and SRC PLLs. Setting SPREAD_EN to '1', forces Spread ON for both PLLs. Reserved Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 RW Reserved Reserved 0 RW 0 RW See Functionality Table on Latched Page 1 RW Latched RW Latched SMBus Table: Output Control Register Pin # Name Control Function Byte 1 PCICLK3 Output Enable Bit 7 PCICLK2 Output Enable Bit 6 PCICLK1 Output Enable Bit 5 PCICLK0 Output Enable Bit 4 HTTCLK3 Output Enable Bit 3 HTTCLK2 Output Enable Bit 2 HTTCLK1 Output Enable Bit 1 HTTCLK0 Output Enable Bit 0 Type RW RW RW RW RW RW RW RW 0 Disable (Low) Disable (Low) Disable (Low) Disable (Low) Disable (Low) Disable (Low) Disable (Low) Disable (Low) 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 SMBus Table: Output Control Register Pin # Name Control Function Byte 2 48MHz_1 Output Enable Bit 7 48MHz_0 Output Enable Bit 6 REF1 Output Enable Bit 5 REF0 Output Enable Bit 4 CPUCLK8(3) Output Enable Bit 3 When Disabled CPUCLK8(2) Bit 2 CPUCLKT = 0 CPUCLK8(1) Bit 1 CPUCLK8(0) CPUCLKC = 1 Bit 0 Type RW RW RW RW RW RW RW RW 0 Disable (Low) Disable (Low) Disable (Low) Disable (Low) Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 0959C—03/13/06 11 ICS932S801 SMBus Table: SRCCLK(0) Output Control Register Byte 3 Pin # Name Control Function Bit 7 Reserved Reserved Bit 6 Reserved Reserved Bit 5 Reserved Reserved Bit 4 Reserved Reserved Bit 3 Reserved Reserved Bit 2 Reserved Reserved SRCCLK Power Down Bit 1 SRCCLK0 PD Drive Mode Bit 0 SRCCLK0 Output Enable Type RW RW RW RW RW RW 0 Reserved Reserved Reserved Reserved Reserved Reserved 1 Reserved Reserved Reserved Reserved Reserved Reserved PWD 0 0 0 0 0 0 RW Driven Hi-Z 0 RW Disable (Hi-Z) Enable 1 SMBus Table: 48MHz Drive Strength Control Register Byte 4 Pin # Name Control Function Bit 7 Reserved Reserved Bit 6 Reserved Reserved Bit 5 Reserved Reserved Bit 4 Reserved Reserved Bit 3 Reserved Reserved Bit 2 Reserved Reserved 5 Bit 1 48MHz_1 DS Drive Strength Control 4 Bit 0 48MHz_0 DS Drive Strength Control Type RW RW RW RW RW RW RW RW 0 Reserved Reserved Reserved Reserved Reserved Reserved 1X 1X 1 Reserved Reserved Reserved Reserved Reserved Reserved 2X 2X PWD 0 0 0 0 0 0 0 0 SMBus Table: SRC Frequency Select Register Byte 5 Pin # Name Control Function Bit 7 Reserved Reserved Bit 6 Reserved Reserved Bit 5 Reserved Reserved Bit 4 Reserved Reserved Bit 3 SRCFS1 SRC FS bit 1 Bit 2 SRCFS0 SRC FS bit 0 Bit 1 Reserved Reserved Bit 0 Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved See Table 1: SRC Frequency Select Reserved Reserved Reserved Reserved PWD 0 0 0 0 0 0 0 0 SMBus Table: Device ID Register Byte 6 Pin # Name Bit 7 DevID 7 Bit 6 DevID 6 Bit 5 DevID 5 Bit 4 DevID 4 Bit 3 DevID 3 Bit 2 DevID 2 Bit 1 DevID 1 Bit 0 DevID 0 Type R R R R R R R R Control Function Device ID MSB Device ID 6 Device ID 5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID LSB 0959C—03/13/06 12 0 - 1 - PWD 1 0 0 0 0 0 0 1 ICS932S801 SMBus Table: Vendor ID Register Byte 7 Pin # Name Bit 7 RID3 Bit 6 RID2 Bit 5 RID1 Bit 4 RID0 Bit 3 VID3 Bit 2 VID2 Bit 1 VID1 Bit 0 VID0 SMBus Table: Byte Count Register Byte 8 Pin # Name Bit 7 BC7 Bit 6 BC6 Bit 5 BC5 Bit 4 BC4 Bit 3 BC3 Bit 2 BC2 Bit 1 BC1 Bit 0 BC0 SMBus Table: Reserved Register Byte 9 Pin # Name Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved Control Function Revision ID VENDOR ID (0001 = ICS) Type R R R R R R R R 0 - 1 - Control Function Type 0 1 RW RW RW Writing to this register will Byte Count Programming RW configure how many bytes b(7:0) RW will be read back, default is RW 9 bytes. RW RW Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW SMBus Table: M/N Programming Enable Byte 10 Pin # Name Control Function Type CPU and SRC PLL M/N RW Bit 7 M/N_EN Programming Enable Bit 6 Reserved Reserved RW Bit 5 Reserved Reserved RW Bit 4 Reserved Reserved RW Bit 3 Reserved Reserved RW Bit 2 Reserved Reserved RW Bit 1 Reserved Reserved RW Bit 0 Reserved Reserved RW 0959C—03/13/06 13 PWD X X X X 0 0 0 1 PWD 0 0 0 0 1 0 0 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD 0 0 0 0 0 0 0 0 0 1 PWD Disable Enable 0 - - 0 0 0 0 0 0 0 ICS932S801 SMBus Table: CPU Frequency Control Register 0 1 PWD Pin # Name Control Function Type Byte 11 N Div8 N Divider Prog bit 8 RW The decimal representation X Bit 7 N Div9 N Divider Prog bit 9 RW of M and N Divier in Byte X Bit 6 M Div5 RW X 11 and 12 will configure Bit 5 M Div4 RW the CPU VCO frequency. X Bit 4 M Div3 RW Default at power up = latchX Bit 3 M Divider Programming in or Byte 0 Rom table. M Div2 RW X Bit 2 bit (5:0) M Div1 RW VCO Frequency = 14.318 X Bit 1 x [NDiv(9:0)+8] / M Div0 RW X Bit 0 [MDiv(5:0)+2] SMBus Table: CPU Frequency Control Register Byte 12 0 1 PWD Pin # Name Control Function Type N Div7 RW The decimal representation X Bit 7 N Div6 RW of M and N Divier in Byte X Bit 6 N Div5 RW X Bit 5 11 and 12 will configure N Div4 X Bit 4 N Divider Programming RW the CPU VCO frequency. N Div3 RW Default at power up = latchX Bit 3 Byte12 bit(7:0) and N Div2 RW X Bit 2 in or Byte 0 Rom table. Byte11 bit(7:6) N Div1 RW VCO Frequency = 14.318 X Bit 1 x [NDiv(9:0)+8] / N Div0 RW X Bit 0 [MDiv(5:0)+2] SMBus Table: CPU Spread Spectrum Control Register Pin # Name Control Function Byte 13 SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 Spread Spectrum SSP4 Bit 4 Programming bit(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 0 1 Type RW RW RW These Spread Spectrum RW bits in Byte 13 and 14 will program the spread RW pecentage of CPU RW RW RW PWD X X X X X X X X SMBus Table: CPU Spread Spectrum Control Register Byte 14 Pin # Name Control Function Reserved Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum SSP11 Bit 3 Programming bit(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 0 1 Type R RW RW These Spread Spectrum RW bits in Byte 13 and 14 will RW program the spread RW pecentage of CPU RW RW PWD 0 X X X X X X X 0959C—03/13/06 14 ICS932S801 SMBus Table: SRC Frequency Control Register Pin # Name Control Function Type 0 1 PWD Byte 15 N Div8 N Divider Prog bit 8 RW The decimal representation X Bit 7 N Div9 N Divider Prog bit 9 RW of M and N Divier in Byte X Bit 6 M Div5 RW X Bit 5 15 and 16 will configure M Div4 RW the SRC VCO frequency. X Bit 4 M Div3 RW Default at power up = latchX Bit 3 M Divider Programming M Div2 RW X Bit 2 in or Byte 0 Rom table. bits X M Div1 RW VCO Frequency = 14.318 Bit 1 x [NDiv(9:0)+8] / M Div0 RW X Bit 0 [MDiv(5:0)+2] SMBus Table: SRC Frequency Control Register 0 1 PWD Pin # Name Control Function Type Byte 16 N Div7 RW The decimal representation X Bit 7 N Div6 RW of M and N Divier in Byte X Bit 6 N Div5 RW X 15 and 16 will configure Bit 5 N Div4 RW the SRC VCO frequency. X Bit 4 N Divider Programming N Div3 RW Default at power up = latchX Bit 3 b(7:0) N Div2 RW in or Byte 0 Rom table. X Bit 2 N Div1 RW VCO Frequency = 14.318 X Bit 1 x [NDiv(9:0)+8] / N Div0 RW X Bit 0 [MDiv(5:0)+2] SMBus Table: SRC Spread Spectrum Control Register Pin # Name Control Function Byte 17 SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 Spread Spectrum SSP4 Bit 4 Programming b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 Type 0 1 RW RW RW These Spread Spectrum RW bits in Byte 17 and 18 will program the spread RW pecentage of SRC RW RW RW PWD X X X X X X X X SMBus Table: SRC Spread Spectrum Control Register Pin # Name Control Function Byte 18 Reserved Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum SSP11 Bit 3 Programming b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 Type 0 1 R RW RW These Spread Spectrum RW bits in Byte 17 and 18 will RW program the spread RW pecentage of SRC RW RW PWD 0 X X X X X X X 0959C—03/13/06 15 ICS932S801 SMBus Table: Programmable Output Divider Register Byte 19 Pin # Name Control Function Type Bit 7 CPUDiv3 RW CPU Divider Ratio Bit 6 CPUDiv2 RW Programming Bits Bit 5 CPUDiv1 RW Bit 4 CPUDiv0 RW HTT Divider Ratio Bit 3 HTTDiv3 RW Programming Bits (PCI RW Bit 2 HTTDiv2 divider is always 2x the RW Bit 1 HTTDiv1 HTT divider or 1/2 freq.) RW Bit 0 HTTDiv0 SMBus Table: Programmable Output Divider Register Byte 20 Pin # Name Control Function Bit 7 Reserved Reserved Bit 6 Reserved Reserved Bit 5 Reserved Reserved Bit 4 Reserved Reserved Bit 3 SRC_Div3 SRC_ Divider Ratio Bit 2 SRC_Div2 Programming Bits Bit 1 SRC_Div1 Bit 0 SRC_Div0 Type R R R R RW RW RW RW SMBusTable: Test Byte Register Byte 21 Test ` Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type RW RW RW RW RW RW RW RW Test Function ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST 0959C—03/13/06 16 0 1 See Table 2: CPU Divider Ratios See Table 3: HTT Divider Ratios 0 - 1 - See Table 4: SRC Divider Ratios Test Result Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD X X X X X X X X PWD X X X X X X X X PWD 0 0 0 0 0 0 0 0 ICS932S801 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS932S801 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 0959C—03/13/06 17 ICS932S801 300 mil SSOP c N L E1 INDEX AREA SYMBOL A A1 b c D E E1 e h L N a E 1 2 α h x 45° D A In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS N A1 -Ce In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° SEATING PLANE b .10 (.004) C 48 D mm. MIN 15.75 D (inch) MAX 16.00 MIN .620 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS932S801yFLFT Example: ICS XXXX y F - LF T Designation for tape and reel packaging RoHS Compliant Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0959C—03/13/06 18 MAX .630 ICS932S801 c N L E1 INDEX AREA E 1 2 a D A A2 A1 -Ce b SEATING PLANE aaa C (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS N 48 D mm. MIN 12.40 D (inch) MAX 12.60 MIN .488 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 Ordering Information ICS932S801yGLFT Example: ICS XXXX y G - LF T Designation for tape and reel packaging RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0959C—03/13/06 19 MAX .496 ICS932S801 Revision History Rev. B C Issue Date Description 1. Updated Electrical Characteristics Tables: i) Changed SRC jitter from 125ps to 100ps; ii) Changed PCI/HTT Skew from 500ps to 200ps; iii) Added USB Skew, 50ps. iv) Change REF Skew from 500ps to 50ps. 5/18/2005 2. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant". 1. Correct pin description of PD# (Pin 21). It does not contain a pull up resistor. 3/13/2006 2. Added PCIe Gen 1 phase noise numbers to SRC output characterisitics 0959C—03/13/06 20 Page # 14-16 18-19 2, 7