LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 LMH6583 16x8 550 MHz Analog Crosspoint Switch, Gain of 2 Check for Samples: LMH6583 FEATURES DESCRIPTION • • The LMH™ family of products is joined by the LMH6583, a high speed, non-blocking, analog, crosspoint switch. The LMH6583 is designed for high speed, DC coupled, analog signals like high resolution video (UXGA and higher). The LMH6583 has 16 inputs and 8 outputs. The non-blocking architecture allows an output to be connected to any input, including an input that is already selected. With fully buffered inputs the LMH6583 can be impedance matched to nearly any source impedance. The buffered outputs of the LMH6583 can drive up to two back terminated video loads (75Ω load). The outputs and inputs also feature high impedance inactive states allowing high performance input and output expansion for array sizes such as 16 x 16 or 32 x 8 by combining two devices. The LMH6583 is controlled with a 4 pin serial interface. Both single serial mode and addressed chain modes are available. 1 23 • • • • • • • • 16 Inputs and 8 Outputs 64-pin Exposed Pad HTQFP Package – −3 dB Bandwidth (VOUT = 2 VPP, RL = 1 kΩ) 550 MHz – −3 dB Bandwidth (VOUT = 2 VPP,RL = 150Ω) 450 MHz Fast Slew Rate 1800 V/μs Channel to Channel Crosstalk (10/ 100 MHz) −70/ −52 dBc All Hostile Crosstalk (10/ 100 MHz) −55/−45 dBc Easy to Use Serial Programming 4 Wire Bus Two Programming Modes Serial & Addressed Modes Symmetrical Pinout Facilitates Expansion. Output Current ±60 mA Gain of 1 Version also Available LMH6582 APPLICATIONS • • • • • • • • The LMH6583 comes in a 64-pin thermally enhanced HTQFP package. It also has diagonally symmetrical pin assignments to facilitate double sided board layouts and easy pin connections for expansion. Studio Monitoring/Production Video Systems Conference Room Multimedia Video Systems KVM (Keyboard Video Mouse) Systems Security/Surveillance Systems Multi Antenna Diversity Radio Video Test Equipment Medical Imaging Wide-Band Routers & Switches 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LMH is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LMH6583 SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 www.ti.com Connection Diagram 32 IN8 OUT7 VEE GND IN9 VEE VCC GND IN10 OUT6 VEE VCC IN11 OUT5 CFG VCC GND BCST IN12 VEE VEE GND OUT4 IN13 VCC IN14 VEE CFG DATA IN CS CLK 40 LOAD REGISTER RST DATA OUT CS MODE DIN MODE RST VCC OUT3 VEE GND GND OUT2 VCC OUT1 VEE DOUT GND CLK VCC OUT0 IN15 GND 136 CONFIGURATION REGISTER VCC GND BCST 64 SWITCH MATRIX 8 OUTPUTS 16 INPUTS IN0 VCC IN1 VEE IN2 VCC IN3 VEE IN4 VCC IN5 VEE IN6 VCC IN7 VEE 48 1 16 Figure 1. 64-Pin Exposed Pad HTQFP See Package Number PAP0064A Figure 2. Block Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) (3) Human Body Model 2000V Machine Model 200V VS ±6V IIN (Input Pins) ±20 mA (4) IOUT V− to V+ Input Voltage Range Maximum Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Soldering Information (1) (2) (3) (4) 2 Infrared or Convection (20 sec.) 235°C Wave Soldering (10 sec.) 260°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see ±3.3V Electrical Characteristics and ±5V Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum output current (IOUT) is determined by device power dissipation limitations. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 Operating Ratings Temperature Range (1) (2) −40°C to +85°C Supply Voltage Range ±3V to ±5.5V θJA θJC 27°C/W 0.82°C/W Thermal Resistance 64–Pin Exposed Pad HTQFP (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see ±3.3V Electrical Characteristics and ±5V Electrical Characteristics. The maximum power dissipation is a function of TJ(MAX)and θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. ±3.3V Electrical Characteristics (1) Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Frequency Domain Performance SSBW −3 dB Bandwidth LSBW VOUT = 0.5 VPP 425 VOUT = 2 VPP, RL = 1 kΩ 500 VOUT = 2 VPP, RL = 150Ω 450 MHz GF 0.1 dB Gain Flatness VOUT = 2 VPP, RL = 150Ω DG Differential Gain RL = 150Ω, 3.58 MHz/ 4.43 MHz 0.05 80 MHz % DP Differential Phase RL = 150Ω, 3.58 MHz/ 4.43 MHz 0.05 deg Time Domain Response tr Rise Time 2V Step, 10% to 90% 1.7 ns tf Fall Time 2V Step, 10% to 90% 1.4 ns OS Overshoot 2V Step 4 % 1700 V/µs 9 ns dBc (4) SR Slew Rate 4 VPP, 40% to 60% ts Settling Time 2V Step, VOUT within 0.5% Distortion And Noise Response HD2 2nd Harmonic Distortion 2 VPP, 10 MHz −76 HD3 3rd Harmonic Distortion 2 VPP, 10 MHz −76 dBc en Input Referred Voltage Noise >1 MHz 12 nV/ √Hz in Input Referred Noise Current >1 MHz 2 pA/ √Hz 16 ns XTLK Switching Time Crosstalk All Hostile, f = 100 MHz −45 dBc ISOL Off Isolation f = 100 MHz −60 dBc Static, DC Performance AV Gain VOS Output Offset Voltage 1.986 (5) 2.00 2.014 ±3 ±17 TCVOS Output Offset Voltage Average Drift IB Input Bias Current Non-Inverting (6) −5 µA TCIB Input Bias Current Average Drift Non-Inverting (5) -12 nA/°C VO Output Voltage Range RL = 100Ω ±2.1 V (1) (2) (3) (4) (5) (6) 38 mV ±1.75 µV/°C Electrical Table values apply only for factory testing conditions at the temperature indicated. No ensurance of parametric performance is indicated in the electrical tables under conditions different than those tested. Room Temperature limits are 100% production tested at 25°C. Device self heating results in TJ ≥ TA, however, test time is insufficient for TJto reach steady state conditions. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Slew Rate is the average of the rising and falling edges. Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Negative input current implies current flowing out of the device. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 3 LMH6583 SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 www.ti.com ±3.3V Electrical Characteristics (1) (continued) Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the temperature extremes. Symbol Parameter Conditions RL = ∞ (7) Min (2) +2.1 -2.05 Typ (3) Max (2) ±2.2 Units VO Output Voltage Range V PSRR Power Supply Rejection Ratio ICC Positive Supply Current RL = ∞ 98 120 mA IEE Negative Supply Current RL = ∞ 92 115 mA Tri State Supply Current RST Pin > 2.0V 17 25 mA 100 45 dB Miscellaneous Performance RIN Input Resistance Non-Inverting CIN Input Capacitance Non-Inverting RO Output Resistance Enabled Closed Loop, Enabled RO Output Resistance Disabled Disabled CMVR Input Common Mode Voltage Range IO Output Current 1100 Sourcing, VO = 0 V kΩ 1 pF 300 mΩ 1300 1450 Ω ±1.3 V ±50 mA Digital Control VIH Input Voltage High VIL Input Voltage Low VOH Output Voltage High >2.2 V VOL Output Voltage Low <0.4 V TS Setup Time 7 ns TH Hold Time 7 ns (7) 2.0 V 0.8 V This parameter is ensured by design and/or characterization and is not tested in production. ±5V Electrical Characteristics (1) Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 100Ω; Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Frequency Domain Performance SSBW −3 dB Bandwidth LSBW VOUT = 0.5 VPP 475 VOUT = 2 VPP, RL = 1 kΩ 550 VOUT = 2 VPP, RL = 150Ω 450 MHz GF 0.1 dB Gain Flatness VOUT = 2 VPP, RL = 150Ω 100 MHz DG Differential Gain RL = 150Ω, 3.58 MHz/ 4.43 MHz 0.04 % DP Differential Phase RL = 150Ω, 3.58 MHz/ 4.43 MHz 0.04 deg Time Domain Response tr Rise Time 2V Step, 10% to 90% 1.4 ns tf Fall Time 2V Step, 10% to 90% 1.3 ns OS Overshoot 2V Step SR Slew Rate 6 VPP, 40% to 60% ts Settling Time 2V Step, VOUT Within 0.5% (1) (2) (3) (4) 4 (4) 2 % 1800 V/µs 7 ns Electrical Table values apply only for factory testing conditions at the temperature indicated. No ensurance of parametric performance is indicated in the electrical tables under conditions different than those tested. Room Temperature limits are 100% production tested at 25°C. Device self heating results in TJ ≥ TA, however, test time is insufficient for TJto reach steady state conditions. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Slew Rate is the average of the rising and falling edges. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 ±5V Electrical Characteristics (1) (continued) Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 100Ω; Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Distortion And Noise Response HD2 2nd Harmonic Distortion 2 VPP, 5 MHz −80 HD3 3rd Harmonic Distortion 2 VPP, 5 MHz −70 dBc en Input Referred Voltage Noise >1 MHz 12 nV/ √Hz in Input Referred Noise Current >1 MHz 2 pA/ √Hz Switching Time XTLK ISOL Cross Talk Off Isolation dBc 15 ns All Hostile, f = 100 MHz −45 dBc Channel to Channel, f = 100 MHz −52 dBc f = 100 MHz −65 dBc Static, DC Performance AV Gain LMH6583 1.986 VOS Offset Voltage Input Referred TCVOS Output Offset Voltage Average Drift IB Input Bias Current Non-Inverting (6) −5 TCIB Input Bias Current Average Drift Non-Inverting (5) −12 nA/°C VO Output Voltage Range RL = 100Ω +3.3 −3.4 ±3.6 V VO Output Voltage Range RL = ∞ ±3.7 ±3.9 V PSRR Power Supply Rejection Ratio DC 42 45 dB XTLK DC Crosstalk DC, Channel to Channel −58 −90 dB ISOL DC Off Isloation DC −60 −90 dB ICC Positive Supply Current RL = ∞ 110 130 mA IEE Negative Supply Current RL = ∞ 104 124 mA Tri State Supply Current RST Pin > 2.0V 22 30 mA (5) 2.00 2.014 ±2 ±17 38 mV µV/°C −12 µA Miscellaneous Performance RIN Input Resistance Non-Inverting 100 CIN Input Capacitance Non-Inverting 1 pF RO Output Resistance Enabled Closed Loop, Enabled 300 mΩ RO Output Resistance Disabled Disabled, Resistance to Ground CMVR Input Common Mode Voltage Range IO Output Current Sourcing, VO = 0 V 1100 ±60 1300 kΩ 1450 Ω ±3.0 V ±70 mA Digital Control VIH Input Voltage High VIL Input Voltage Low VOH Output Voltage High >2.4 VOL Output Voltage Low <0.4 V TS Setup Time 5 ns TH Hold Time 5 ns (5) (6) 2.0 V 0.8 V V Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Negative input current implies current flowing out of the device. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 5 LMH6583 SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 2 VPP Frequency Response 2 VPP Frequency Response 1 1 0 -2 PHASE -3 -45 -4 -90 -5 VS = ±5V VOUT = 2 VPP -6 RL = 150: -7 10 -135 -180 -1 0 -2 PHASE -3 -45 -4 -90 -5 VS = ±3.3V -135 -6 VOUT = 2 VPP -180 RL = 150: -225 1000 100 -7 FREQUENCY (MHz) Figure 3. Figure 4. Large Signal Bandwidth Large Signal Bandwidth 1 GAIN GAIN -2 0 PHASE -45 -4 -90 -5 V = ±5V S -135 -6 VOUT = 2.8 VPP RL = 150: -7 1 10 100 FREQUENCY (MHz) -180 -1 -2 0 PHASE -3 -45 -4 -90 -5 VS = ±3.3V -135 -6 VOUT = 2.8 VPP -180 RL = 150: -7 -225 1000 1 10 100 FREQUENCY (MHz) Figure 5. -225 1000 Figure 6. Small Signal Bandwidth Small Signal Bandwidth 1 1 GAIN GAIN 0 0 PHASE -3 -45 -4 -90 -5 -135 VS = ±5V VOUT = 0.7 VPP -6 -180 -1 -2 -3 -45 -4 -90 -5 VS = ±3.3V -6 -135 VOUT = 0.7 VPP -180 RL = 100: RL = 100: -7 1 0 PHASE PHASE (°) -2 PHASE (°) -1 NORMALIZED GAIN (dB) 0 NORMALIZED GAIN (dB) PHASE (°) -1 NORMALIZED GAIN (dB) 0 PHASE (°) NORMALIZED GAIN (dB) 0 10 100 -225 1000 -7 1 FREQUENCY (MHz) 10 100 -225 1000 FREQUENCY (MHz) Figure 7. 6 -225 1000 100 10 FREQUENCY (MHz) 1 -3 PHASE (°) -1 NORMALIZED GAIN (dB) 0 PHASE (°) NORMALIZED GAIN (dB) GAIN GAIN 0 Figure 8. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Frequency Response 1 kΩ Load Group Delay 1 2.00 VS = ±5V GAIN 1.50 VOUT = 1V -1 VS = ±3.3V -2 -3 0 PHASE -45 -90 -4 VS = ±3.3V -5 -6 VOUT = 2 VPP RL = 1 k: -7 10 -135 100 GROUP DELAY (ns) VS = ±5V PHASE (°) NORMALIZED GAIN (dB) 0 1.00 0.50 0.00 -0.50 -1.00 -180 -1.50 -225 1000 -2.00 0 100 FREQUENCY (MHz) 200 Figure 9. VS = ±5V SINGLE CHANNEL 1.0 1.0 0.5 0.5 VOUT (V) VOUT (V) 500 2 VPP Pulse Response 1.5 0.0 VS = ±3.3V SINGLE CHANNEL 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 0 5 10 15 20 25 30 35 40 5 0 10 15 20 25 TIME (ns) TIME (ns) Figure 11. Figure 12. 4 VPP Pulse Response 30 35 40 4 VPP Pulse Response Broadcast 2.5 2.5 2.0 2 1.5 1.5 1.0 1 0.5 0.5 VOUT (V) VOUT (V) 400 Figure 10. 2 VPP Pulse Response 1.5 300 FREQUENCY (MHz) 0.0 -0.5 VS = ±5V BROADCAST 0 -0.5 -1 -1.0 -1.5 -1.5 VS = ±5V SINGLE CHANNEL -2.0 -2.5 0 5 10 15 20 25 30 -2 -2.5 35 40 0 5 10 15 TIME (ns) TIME (ns) Figure 13. Figure 14. 20 25 30 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 7 LMH6583 SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 4 VPP Pulse Response 6 VPP Pulse Response 2.5 4 2.0 3 1.5 2 0.5 VOUT (V) VOUT (V) 1.0 0.0 -0.5 1 0 -1 -1.0 -2 -1.5 -3 VS = ±3.3V SINGLE CHANNEL -2.0 -2.5 VS = ±5V SINGLE CHANNEL -4 0 5 10 15 20 25 30 35 40 0 5 10 TIME (ns) 20 25 30 35 40 TIME (ns) Figure 15. Figure 16. 2 VPP Off Isolation 2 VPP Crosstalk -50 -40 -50 -60 -60 CROSSTALK (dBc) CROSSTALK (dBc) 15 -70 -80 -90 -70 -80 -90 -100 -100 -110 -120 0.1 1 100 10 -110 0.1 1000 1 FREQUENCY (MHz) Figure 18. 2 VPP All Hostile Crosstalk Second Order Distortion (HD2) vs. Frequency -60 -65 -50 VS = ±5V RL = 100: VOUT = 4V DISTORTION dBc) BOTH INPUTS & OUTPUTS CROSSTALK (dBc) 1000 Figure 17. -40 -60 -70 -80 OUTPUTS ONLY -90 0.1 1 10 100 -70 VOUT = 2V -75 -80 -85 VOUT = 0.25V -90 INPUTS ONLY -100 0.001 0.01 1000 -95 FREQUENCY (MHz) 1 10 100 FREQUENCY (MHz) Figure 19. 8 100 10 FREQUENCY (MHz) Figure 20. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Third Order Distortion (HD3) vs. Frequency DISTORTION (dBc) -60 -55 VS = ±5V RL = 100: -65 VS = ±3.3V -60 VOUT = 4V -70 VOUT = 2V -75 -80 RL = 100: -65 DISTORTION (dBc) -55 Second Order Distortion vs. Frequency VOUT = 3V -70 VOUT = 2V -75 VOUT = 0.25V -80 -85 -85 VOUT = 0.25V -90 -90 -95 -95 10 1 100 10 1 FREQUENCY (MHz) Figure 21. Figure 22. Third Order Distortion vs. Frequency DISTORTION (dBc) -60 No Load Output Swing 4 VS = ±3.3V VS = ±5V 3 NO LOAD RL = 100: -65 OUTPUT VOLTAGE (V) -55 VOUT = 3V -70 VOUT = 2V -75 100 FREQUENCY (MHz) -80 -85 2 1 0 -1 -2 VOUT = 0.25V -3 -90 -4 -3 -95 10 1 100 1 0 FREQUENCY (MHz) Figure 23. Figure 24. Positive Swing over Temperature 2 3 Negative Swing Over Temperature -2.75 100°C VS = ±5V VS = ±5V 100: LOAD 100: LOAD 3.5 25°C -40°C 3.25 3 1.75 2 2.25 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) -1 INPUT VOLTAGE (V) 3.75 2.75 1.5 -2 -3 -3.25 -3.5 25°C -40°C -3.75 -2.25 INPUT VOLTAGE (V) 100°C -2 -1.75 -1.5 INPUT VOLTAGE (V) Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 9 LMH6583 SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) No Load Output Swing Positive Swing over Temperature 2.25 2.5 100: LOAD NO LOAD 1.5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 100°C VS = ±3.3V VS = ±3.3V 2 1 0.5 0 -0.5 -1 2 25°C -40°C 1.75 1.5 -1.5 -2 -2.5 -2 -1 0 1 1.25 0.75 2 1 1.25 1.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 27. Figure 28. Negative Swing over Temperature Enabled Output Impedance -1.25 1000 VS = ±3.3V 100 |Z| (:) OUTPUT VOLTAGE (V) 100: LOAD -1.5 -1.75 -2 25°C -40°C -2.25 -1.5 10 1 100°C -1.25 -1 0.1 0.1 -0.75 INPUT VOLTAGE (V) 1 10 100 1000 FREQUENCY (MHz) Figure 29. Figure 30. Disabled Output Impedance Switching Time 10000 4 1 3 0.5 1000 OUTPUT (V) |Z| (:) 2.5 100 2 0 1.5 1 -0.5 CFG 10 0.5 0 -1 DISABLE TO ENABLE -0.5 CONFIGURE PIN VOLTAGE (V) 3.5 ENABLE TO DISABLE 1 0.1 1 10 100 1000 -1.5 -50 -40 -30 -20 -10 0 FREQUENCY (MHz) TIME (ns) Figure 31. 10 -1 10 20 30 40 50 Figure 32. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 APPLICATION INFORMATION INTRODUCTION The LMH6583 is a high speed, fully buffered, non blocking, analog crosspoint switch. Having fully buffered inputs allows the LMH6583 to accept signals from low or high impedance sources without the worry of loading the signal source. The fully buffered outputs will drive 75Ω or 50Ω back terminated transmission lines with no external components other than the termination resistor. When disabled, the outputs are in a high impedance state. The LMH6583 can have any input connected to any (or all) output(s). Conversely, a given output can have only one associated input. INPUT AND OUTPUT EXPANSION The LMH6583 has high impedance inactive states for both inputs and outputs allowing maximum flexibility for Crosspoint expansion. In addition the LMH6583 employs diagonal symmetry in pin assignments. The diagonal symmetry makes it easy to use direct pin to pin vias when the parts are mounted on opposite sides of a board. As an example two LMH6583 chips can be combined on one board to form either an 16 x 16 crosspoint or a 32 x 8 crosspoint. To make a 16 x 16 cross-point all 16 input pins would be tied together (Input 0 on side 1 to input 15 on side 2 and so on) while the 8 output pins on each chip would be left separate. To make the 32 x 8 crosspoint, the 8 outputs would be tied together while all 32 inputs would remain independent. In the 32 x 8 configuration it is important not to have 2 connected outputs active at the same time. With the 16 x 16 configuration, on the other hand, having two connected inputs active is a valid state. Crosspoint expansion as detailed above has the advantage that the signal path has only one crosspoint in it at a time. Expansion methods that have cascaded stages will suffer bandwidth loss far greater than the small loading effect of parallel expansion. Output expansion is very straight forward. Connecting the inputs of two crosspoint switches has a very minor impact on performance. Input expansion requires more planning. As shown in Figure 34 and Figure 35 there are two ways to connect the outputs of the crosspoint switches. In Figure 34 the crosspoint switch outputs are connected directly together and share one termination resistor. This is the easiest configuration to implement and has only one drawback. Because the disabled output of the unused crosspoint (only one output can be active at a time) has a small amount of capacitance the frequency response of the active crosspoint will show peaking. This is illustrated in Figure 36 and Figure 37. In most cases this small amount of peaking is not a problem. As illustrated in Figure 35 each crosspoint output can be given its own termination resistor. This results in a frequency response nearly identical to the non expansion case. There is one drawback for the gain of 2 crosspoint, and that is gain error. With a 75Ω termination resistor the 1250Ω resistance of the disabled crosspoint output will cause a gain error. In order to counter act this the termination resistors of both crosspoints should be adjusted to approximately 71Ω. This will provide very good matching, but the gain accuracy of the system will now be dependent on the process variations of the crosspoint resistors which have a variability of approximately ±20%. 1 1 1 1 1 1 2 2 1 1 2 2 IN 3 4x4 2 2 OUT 3 IN 4x4 OUT IN 3 3 4 1 4x4 OUT 3 3 2 4 2 2 4 4 4 4 3 3 3 1 4 5 2 3 4 6 IN 4x4 OUT 5 1 6 5 1 2 6 2 7 3 7 3 8 4 8 4 7 IN 8 Figure 33. Output Expansion 4x4 4 OUT IN Figure 34. Input Expansion with Shared Termination Resistors 4x4 OUT Figure 35. Input Expansion with Separate Termination Resistors Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 4 11 LMH6583 SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 www.ti.com 2 2 OUTPUT CONNECTED DIRECTLY 0 -1 NO EXPANSION -2 -3 -4 -5 VS = ±3.3V -6 VOUT = 2 VPP -7 -8 10 0 -1 NO EXPANSION -2 -3 -4 -5 VS = ±5V -6 VOUT = 2 VPP -7 RL = 150: 1 OUTPUT CONNECTED DIRECTLY 1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 100 -8 1000 RL = 150: 1 10 FREQUENCY (MHz) 100 1000 FREQUENCY (MHz) Figure 36. Input Expansion Frequency Response Figure 37. Input Expansion Frequency Response DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Capacitive loads of 5 pF to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. For applications where maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values. When driving transmission lines the 50Ω or 75Ω matching resistor makes the series output resistor unnecessary. USING OUTPUT BUFFERING TO ENHANCE BANDWIDTH AND INCREASE RELIABILITY The LMH6583 crosspoint switch can offer enhanced bandwidth and reliability with the use of external buffers on the outputs. The bandwidth is increased by unloading the outputs and driving a higher impedance. The 1 kΩ load resistor was chosen to provide the best performance on our evaluation board. See Figure 9 in Typical Performance Characteristics for an example of bandwidth achieved with less loading on the outputs. For this technique to provide maximum benefit a very high speed amplifier such as the LMH6703 should be used, as shown in Figure 38. Besides offering enhanced bandwidth performance using an external buffer provides for greater system reliability. The first advantage is to reduce thermal loading on the crosspoint switch. This reduced die temperature will increase the life of the crosspoint. The second advantage is enhanced ESD reliability. It is very difficult to build high speed devices that can withstand all possible ESD events. With external buffers the crosspoint switch is isolated from ESD events on the external system connectors. LMH6703 LMH6583 OUTPUT BUFFER RL + - VOUT 560: 1 k: 560: Figure 38. Buffered Output 12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 In the example in Figure 38, the resistor RL is required to provide a load for the crosspoint output buffer. Without RLexcessive frequency response peaking is likely and settling times of transient signals will be poor. As the value of RL is reduced the bandwidth will also go down. The amplifier shown in the example is an LMH6703 this amplifier offers high speed and flat bandwidth. Another suitable amplifiers is the LMH6702. The LMH6702 is a faster amplifier that can be used to generate high frequency peaking in order to equalize longer cable lengths. If board space is at a premium the LMH6739 or the LMH6734 are triple, selectable gain buffers which require no external resistors. CROSSTALK When designing a large system such as a video router crosstalk can be a very serious problem. Extensive testing in our lab has shown that most crosstalk is related to board layout rather than occurring in the crosspoint switch. There are many ways to reduce board related crosstalk. Using controlled impedance lines is an important step. Using well decoupled power and ground planes will help as well. When crosstalk does occur within the crosspoint switch itself it is often due to signals coupling into the power supply pins. Using appropriate supply bypassing will help to reduce this mode of coupling. Another suggestion is to place as much grounded copper as possible between input and output signal traces. Care must be taken, though, not to influence the signal trace impedances by placing shielding copper too closely. One other caveat to consider is that as shielding materials come closer to the signal trace the trace needs to be smaller to keep the impedance from falling too low. Using thin signal traces will result in unacceptable losses due to trace resistance. This effect becomes even more pronounced at higher frequencies due to the skin effect. The skin effect reduces the effective thickness of the trace as frequency increases. Resistive losses make crosstalk worse because as the desired signal is attenuated with higher frequencies crosstalk increases at higher frequencies. SWITCH MATRIX 8 OUTPUTS 16 INPUTS DIGITAL CONTROL 136 CFG BCST DATA IN CS CLK CONFIGURATION REGISTER 40 LOAD REGISTER RST DATA OUT MODE Figure 39. Block Diagram The LMH6583 has internal control registers that store the programming states of the crosspoint switch. The logic is two staged to allow for maximum programming flexibility. The first stage of the control logic is tied directly to the crosspoint switching matrix. This logic consists of one register for each output that stores the on/off state and the address of which input to connect to. These registers are not directly accessible by the user. The second level of logic is another bank of registers identical to the first, but set up as shift registers. These registers are accessed by the user via the serial input bus. As described further below, there are two modes for programing the LMH6582, SERIAL PROGRAMMING MODE and ADDRESSED PROGRAMMING MODE. The LMH6583 is programmed via a serial input bus with the support of 4 other digital control pins. The Serial bus consists of a clock pin (CLK), a serial data in pin (DIN), and a serial data out pin (DOUT). The serial bus is gated by a chip select pin (CS). The chip select pin is active low. While the chip select pin is high all data on the serial input pin and clock pins is ignored. When the chip select pin is brought low the internal logic is set to begin receiving data by the first positive transition (0 to 1) of the clock signal. The chip select pin must be brought low at least 5 ns before the first rising edge of the clock signal. The first data bit is clocked in on the next negative Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 13 LMH6583 SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 www.ti.com transition (1 to 0) of the clock signal. All input data is read from the bus on the negative edge of the clock signal. Once the last valid data has been clocked in, the chip select pin must go high then the clock signal must make at least one more low to high transition. Otherwise invalid data will be clocked into the chip. The data clocked into the chip is not transferred to the crosspoint matrix until the CFG pin is pulsed high. This is the case regardless of the state of the Mode pin. The CFG pin is not dependent on the state of the Chip select pin. If no new data is clocked into the chip subsequent pulses on the CFG pin will have no effect on device operation. The programming format of the incoming serial data is selected by the MODE pin. When the mode pin is HIGH the crosspoint can be programmed one output at a time by entering a string of data that contains the address of the output that is going to be changed (Addressed Mode). When the mode pin is LOW the crosspoint is in Serial Mode. In this mode the crosspoint accepts a 40 bit array of data that programs all of the outputs. In both modes the data fed into the chip does not change the chip operation until the Configure pin is pulsed high. The configure and mode pins are independent of the chip select pin. THREE WIRE VS. FOUR WIRE CONTROl There are two ways to connect the serial data pins. The first way is to control all 4 pins separately, and the second option is to connect the CFG and the CS pins together for a 3 wire interface. The benefit of the 4 wire interface is that the chip can be configured independently of the CS pin. This would be an advantage in a system with multiple crosspoint chips where all of them could be programmed ahead of time and then configured simultaneously. The 4 wire solution is also helpful in a system that has a free running clock on the CLK pin. In this case, the CS pin needs to be brought high after the last valid data bit to prevent invalid data from being clocked into the chip. The three wire option provides the advantage of one less pin to control at the expense of having less flexibility with the configure pin. One way around this loss of flexibility would be If the clock signal is generated by an FPGA or microcontroller where the clock signal can be stopped after the data is clocked in. In this case the Chip select function is provided by the presence or absence of the clock signal. SERIAL PROGRAMMING MODE Serial programming mode is the mode selected by bringing the MODE pin low. In this mode a stream of 40 bits programs all 8 outputs of the crosspoint. The data is fed to the chip as shown in Table 1 through Table 4 (4 tables are required to show the entire data frame). The table is arranged such that the first bit clocked into the crosspoint register is labeled bit number 0. The register labeled Load Register in Figure 39 is a shift register. If the chip select pin is left low after the valid data is shifted into the chip and if the clock signal keeps running then additional data will be shifted into the register, and the desired data will be shifted out. Also illustrated is the timing relationships for the digital pins in Figure 40. It is important to note that all the pin timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS) must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to synchronize to allow data to be accepted on the next falling edge. After the final data bit has been clocked in, the chip select pin must go high, then the clock signal must make at least one more low to high transition. As shown in Figure 40, the chip select pin state should always occur while the clock signal is low. The configure (CFG) pin timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers. 14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 T-1 1 CLK 0 T0 T1 T37 T40 T39 T38 T41 TS TS 1 CS_N 0 1 CFG 0 TH TS 1 DIN 0 I0 I1 I... I38 I37 I40 I39 I41 1 MODE 0 TD 1 DOUT 0 I0 I1 Figure 40. Timing Diagram for Serial Mode Table 1. Serial Mode Data Frame (First 2 Words) (1) Output 0 Output 1 Input Address LSB 0 (1) 1 2 On = 0 Input Address MSB Off = 1 LSB 3 4 5 On = 0 6 7 MSB Off = 1 8 9 Off = TRI-STATE, Bit 0 is first bit clocked into device. Table 2. Serial Mode Data Frame (Continued) Output 2 Output 3 Input Address LSB 10 11 12 On = 0 Input Address MSB Off = 1 LSB 13 14 15 On = 0 16 17 MSB Off = 1 18 19 Table 3. Serial Mode Data Frame (Continued) Output 4 Output 5 Input Address LSB 20 21 22 On = 0 Input Address MSB Off = 1 LSB 23 24 25 On = 0 26 27 MSB Off = 1 28 29 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 15 LMH6583 SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 www.ti.com Table 4. Serial Mode Data Frame (Last 2 Words) (1) Output 6 Output 7 Input Address LSB 30 (1) 31 32 On = 0 Input Address MSB Off = 1 LSB 33 34 35 On = 0 36 37 MSB Off = 1 38 39 Bit 39 is last bit clocked into device. ADDRESSED PROGRAMMING MODE Addressed programming mode makes it possible to change only one output register at a time. To utilize this mode the mode pin must be High. All other pins function the same as in serial programming mode except that the word clocked in is 8 bits and is directed only at the output specified. In addressed mode the data format is shown in Table 5. Also illustrated is the timing relationships for the digital pins in Figure 41. It is important to note that all the pin timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS) must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to synchronize to allow data to be accepted on the next falling edge. After the final data bit has been clocked in, the chip select pin must go high, then the clock signal must make at least one more low to high transition. As shown in Figure 41, the chip select pin state should always occur while the clock signal is low. The configure (CFG) pin timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers. T1 1 CLK 0 T2 T3 T5 T4 T6 T7 T8 T9 T10 TS TS 1 CS_N 0 1 CFG 0 TH TS 1 DIN 0 A0 IO A2 A1 I1 I3 I2 I4 1 MODE 0 1 DOUT 0 HIGH IMPEDANCE Figure 41. Timing Diagram for Addressed Mode Table 5. Addressed Mode Word Format (1) Output Address LSB 0 (1) 16 1 Input Address MSB LSB 2 3 TRI-STATE 4 5 MSB 1 = TRI-STATE 0 = On 6 7 Bit 0 is first bit clocked into device. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 DAISY CHAIN OPTION IN SERIAL MODE The LMH6583 supports daisy chaining of the serial data stream between multiple chips. This feature is available only in the Serial programming mode. To use this feature serial data is clocked into the first chip DIN pin, and the next chip DIN pin is connected to the DOUT pin of the first chip. Both chips may share a chip select signal, or the second chip can be enabled separately. When the chip select pin goes low on both chips a double length word is clocked into the first chip. As the first word is clocking into the first chip the second chip is receiving the data that was originally in the shift register of the first chip (invalid data). When a full 40 bits have been clocked into the first chip the next clock cycle begins moving the first frame of the new configuration data into the second chip. With a full 80 clock cycles both chips have valid data and the chip select pin of both chips should be brought high to prevent the data from overshooting. A configure pulse will activate the new configuration on both chips simultaneously, or each chip can be configured separately. The mode, chip select, configure and clock pins of both chips can be tied together and driven from the same sources. SPECIAL CONTROL PINS The LMH6583 has two special control pins that function independent of the serial control bus. One of these pins is the reset (RST) pin. The RST pin is active high meaning that a logic 1 level the chip is configured with all outputs disabled and in a high impedance state. The RST pin programs all the registers with input address 0 and all the outputs are turned off. In this configuration the device draws only 20 mA. The reset pin can used as a shutdown function to reduce power consumption. The other special control pin is the broadcast (BCST) pin. The BCST pin is also active high and sets all the outputs to the on state connected to input 0. Both of these pins are level sensitive and require no clock signal. The two special control pins overwrite the contents of the configuration register. THERMAL MANAGEMENT The LMH6583 is packaged in a thermally enhanced Quad Flat Pack package. Even so, it is a high performance device that produces a significant amount of heat. With a ±5V supply, the LMH6583 will dissipate approximately 1.1W of idling power with all outputs enabled. Idling power is calculated based on the typical supply current of 110 mA and a 10V supply voltage. This power dissipation will vary within the range of 800 mW to 1.4W due to process variations. In addition, each equivalent video load (150Ω) connected to the outputs should be budgeted 30 mW of power. For a typical application with one video load for each output this would be a total power of 1.14 W. With a typical θJA of 27°C/W this will result in the silicon being 31°C over the ambient temperature. A more aggressive application would be two video loads per output which would result in 1.38 W of power dissipation. This would result in a 37°C temperature rise. For heavier loading, the HTQFP package thermal performance can be significantly enhanced with an external heat sink and by providing for moving air ventilation. Also, be sure to calculate the increase in ambient temperature from all devices operating in the system case. Because of the high power output of this device, thermal management should be considered very early in the design process. Generous passive venting and vertical board orientation may avoid the need for fan cooling or heat sinks. Also, the LMH6583 can be operated with a ±3.3V power supply. This will cut power dissipation substantially while only reducing bandwidth by about 10% (2 VPP output). The LMH6583 is fully characterized and factory tested at the ±3.3V power supply condition for applications where reduced power is desired. If a heat sink is desired AAVD/Thermalloy part # 375324B00035G is the proper size for the LMH6583 package. This heat sink comes with adhesive tape for ease in assembly. With natural convection the heat sink will reduce the θJA from 27°C/W to approximately 21°C/W. Using a fan will increase the effectiveness of the heat sink considerably. When doing thermal design it is important to note that everything from board layout to case material will impact the actual θJA of the device. The θJA specified in the datasheet is for a typical board layout. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 17 LMH6583 SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 www.ti.com 5 MAXIMUM POWER (W) 4.5 4 3.5 3.0 2.5 2 1.5 1 0.5 JUNCTION TEMPERATURE = 125°C TJA = 27°C/W 0 -40 -15 10 35 60 85 AMBIENT TEMPERATURE (°C) Figure 42. Maximum Dissipation vs. Ambient Temperature PRINTED CIRCUIT LAYOUT Generally, a good high frequency layout will keep power supply and ground traces away from the input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15 for more information). If digital control lines must cross analog signal lines (particularly inputs) it is best if they cross perpendicularly. TI suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization: Device Package Evaluation Board Part Number LMH6583 64-Pin HTQFP LMH730156 18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 LMH6583 www.ti.com SNOSAP5E – APRIL 2006 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH6583 19 PACKAGE OPTION ADDENDUM www.ti.com 27-Jan-2016 PACKAGING INFORMATION Orderable Device Status (1) LMH6583YA/NOPB ACTIVE Package Type Package Pins Package Drawing Qty HTQFP PAP 64 160 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 85 LMH6583YA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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