Micron MT36LSDT12872G Synchronous dram module Datasheet

1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Features
Synchronous DRAM Module
MT36LSDT12872 – 1GB
MT36LSDT25672 – 2GB
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules
Features
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Figure 1:
168-pin, dual in-line memory module (DIMM)
PC100- and PC133-compliant
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
Utilizes 125 MHz and 133 MHz SDRAM
components
Supports ECC error detection and correction
1GB (128 Meg x 72) and 2GB (256 Meg x 72)
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of PLL clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal SDRAM banks for hiding row access/
precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto precharge
Auto refresh mode
Self refresh mode: 64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Serial presence-detect (SPD)
Gold edge contacts
Table 1:
Standard 1.70in. (43.18mm)
Low-Profile 1.20in. (30.48mm)
Options
Timing Parameters
Access Time
Clock
CL = 2
CL = 3
Setup
Time
Hold
Time
-13E
-133
133 MHz
133 MHz
5.4ns
–
–
5.4ns
1.5
1.5
0.8
0.8
Table 2:
Marking
• Package
168-pin DIMM (standard)
G
168-pin DIMM (lead-free)
Y1
• Frequency/CAS Latency2
133 MHz/CL = 2
-13E
133 MHz/CL = 3
-133
• PCB
Standard 1.70in (43.18mm)
See note on page 2
Low-Profile 1.20in. (30.48mm) See note on page 2
CL = CAS (READ) latency
Module
Marking
168-Pin DIMM (MO-161)
Notes: 1. Contact Micron for product availability.
2. Registered mode adds one clock cycle to CL.
Address Table
Parameter
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
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SD36C128_256x72G.fm - Rev. E 6/05 EN
1GB
2GB
8K
4 (BA0, BA1)
256Mb (64 Meg x 4)
8K (A0–A12)
2K (A0–A9, A11)
2 (S0#, S2#; S1#, S3#)
8K
4 (BA0, BA1)
512Mb (128 Meg x 4)
8K (A0–A12)
4K (A0–A9, A11, A12)
2 (S0#, S2#; S1#, S3#)
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Features
Table 3:
Part Numbers
Part Number
MT36LSDT12872G-13E__
MT36LSDT12872Y-13E__
MT36LSDT12872G-133__
MT36LSDT12872Y-133__
MT36LSDT25672G-13E__
MT36LSDT25672Y-13E__
MT36LSDT25672G-133__
MT36LSDT25672Y-133__
Note:
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SD36C128_256x72G.fm - Rev. E 6/05 EN
Module Density
Configuration
System Bus Speed
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
The designators for component and PCB revision are the last two characters of each part
number. Consult factory for current revision codes. Example: MT36LSDT12872G-133B1.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignment
168-Pin DIMM Front
168-Pin DIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
Figure 2:
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
U2
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
VSS
NC
S2#
DQMB2
DQMB3
NC
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
NC
CKE1
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
NC
SDA
SCL
VDD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
106
CB5
127
VSS
148
107
VSS
128
CKE0
149
108
NC
129
S3#
150
109
NC
130 DQMB6 151
110
VDD
131 DQMB7 152
111
CAS#
132
NC
153
112 DQMB4 133
VDD
154
113 DQMB5 134
NC
155
114
S1#
135
NC
156
115
RAS#
136
CB6
157
116
VSS
137
CB7
158
117
A1
138
VSS
159
118
A3
139 DQ48 160
119
A5
140 DQ49 161
120
A7
141 DQ50 162
121
A9
142 DQ51 163
122
BA0
143
VDD
164
123
A11
144 DQ52 165
124
VDD
145
NC
166
125
CK1
146
NC
167
126
A12
147
REGE
168
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CK3
NC
SA0
SA1
SA2
VDD
168-Pin DIMM Pin Locations
Standard PCB
Front View
U1
CB1
VSS
NC
NC
VDD
WE#
DQMB0
DQMB1
S0#
NC
VSS
A0
A2
A4
A6
A8
A10
BA1
VDD
VDD
CK0
U3
U4
U6
U5
U7
U8
Low Profile PCB
Front View
U9
U12
U1
U2
U3
U4
U5
U6
U7
U9
U8
U11
U10
U12
U11
U10
U14
U14
PIN 84
PIN 41
PIN 1
PIN 84
PIN 41
PIN 1
Back View
U15
U16
U17
U18
U19
U20
U21
U22
Back View
U23
U16
U15
U17
U24
PIN 168
PIN125
U19
U20
U21
U22
U23
U24
PIN 85
PIN 168
Indicates a VDD or VDDQ pin
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SD36C128_256x72G.fm - Rev. E 6/05 EN
U18
3
PIN125
PIN 85
Indicates a VSS pin
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbol order; refer to Table 4 on page 3 for more information
Pin Numbers
Symbol
Type
Description
27, 111, 115
RAS#, CAS#, WE#
Input
42, 79, 125, 163
CK0–CK3
Input
128
CKE0
Input
30, 45, 114, 129
S0#–S3#
Input
28, 29, 46, 47, 112, 113, 130,
131
DQMB0–DQMB7
Input
39, 122
BA0, BA1
Input
33–38, 117–121, 123, 126
A0–A12
Input
83
SCL
Input
165–167
SA0–SA2
Input
147
REGE
Input
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95, 97–101,
103–104, 139–142, 144,
149–151, 153–156, 158–161
21, 22, 52, 53, 105, 106, 136,
137
82
DQ0–DQ63
Input/
Output
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK0 is distributed through an on-board PLL to all
devices. CK1–CK3 are terminated.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CK0 signal. Deactivating the clock provides POWER-DOWN
and SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
Chip select: S# enable (registered LOW) and disable (registered
HIGH) the command decoder. All commands are masked when
S# are registered HIGH. S# are considered part of the
command code.
Input/Output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (twoclock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect address inputs: These pins are used to
configure the presence-detect device.
Register enable: REGE permits the DIMM to operate in
“buffered” mode (LOW) or “registered” mode (HIGH).
Data I/Os: Data bus.
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CB0–CB7
SDA
Input/ Check bits.
Output
Input/ Serial presence-detect data: SDA is a bidirectional pin used to
Output transfer addresses and data into and data out of the presencedetect portion of the module.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Functional Block Diagram
Table 5:
Pin Descriptions (Continued)
Pin numbers may not correlate with symbol order; refer to Table 4 on page 3 for more information
Pin Numbers
Symbol
6, 18, 26, 40, 41, 49, 59, 73, 84,
90, 102, 110, 124, 133, 143,
157, 168
1, 12, 23, 32, 43, 54, 64, 68, 78,
85, 96, 107, 116, 127, 138, 148,
152, 162
24, 25, 31, 44, 48 50, 51 61, 62,
63, 80, 81, 108, 109, 132, 134,
135, 145, 146, 164
VDD
Supply Power supply: +3.3V ±0.3V.
VSS
Supply Ground.
NC
Type
–
Description
Not connected: Listed pins are not connected on these
modules.
Functional Block Diagram
All resistor values are 10Ω unless otherwise specified.
‘t’ indicates top portion of stacked SDRAM. ‘b’ indicates bottom portion of stacked
SDRAM.
Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/support/numbering.html.
Standard modules use the following SDRAM devices: MT48LC64M4A2TG (1GB);
MT48LC128M4A2TG (2GB). Lead-free modules use the following SDRAM devices:
MT48LC64M4A2P (1GB); MT48LC128M4A2P (2GB).
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Functional Block Diagram
Figure 3:
Functional Block Diagram
RS0#
RS1#
RDQMB0
RDQMB4
DQ0
DQ1
DQ2
DQ3
DQM CS#
DQ
U1t
DQ
DQ
DQ
DQM CS#
DQ
DQ U1b
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQM CS#
DQ
DQ U23t
DQ
DQ
DQM CS#
DQ
DQ U23b
DQ
DQ
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ
U2t
DQ
DQ
DQ
DQM CS#
DQ
DQ U2b
DQ
DQ
DQ36
DQ37
DQ38
DQ39
DQM CS#
DQ
DQ U22t
DQ
DQ
DQM CS#
DQ
DQ U22b
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQM CS#
DQ
U3t
DQ
DQ
DQ
DQM CS#
DQ
DQ U3b
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQM CS#
DQ
DQ
U21t
DQ
DQ
DQM CS#
DQ
DQ
U21b
DQ
DQ
DQ12
DQ13
DQ14
DQ15
DQM CS#
DQ
U4t
DQ
DQ
DQ
DQM CS#
DQ
DQ U4b
DQ
DQ
DQ44
DQ45
DQ46
DQ47
DQM CS#
DQ
DQ
U20t
DQ
DQ
DQM CS#
DQ
DQ U20b
DQ
DQ
CB0
CB1
CB2
CB3
DQM CS#
DQ
U5t
DQ
DQ
DQ
DQM CS#
DQ
DQ U5b
DQ
DQ
CB4
CB5
CB6
CB7
DQM
DQ
DQ U19t
DQ
DQ
CS#
DQM
DQ
DQ U19b
DQ
DQ
CS#
DQ16
DQ17
DQ18
DQ19
DQM CS#
DQ
U6t
DQ
DQ
DQ
DQM CS#
DQ
DQ U6b
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQM CS#
DQ
DQ U18t
DQ
DQ
DQM CS#
DQ
DQ U18b
DQ
DQ
DQ20
DQ21
DQ22
DQ23
DQM CS#
DQ
U7t
DQ
DQ
DQ
DQM CS#
DQ
DQ U7b
DQ
DQ
DQ52
DQ53
DQ54
DQ55
DQM CS#
DQ
U17t
DQ
DQ
DQ
DQM CS#
DQ
DQ U17b
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQM CS#
DQ
U8t
DQ
DQ
DQ
DQM CS#
DQ
DQ U8b
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQM CS#
DQ
DQ U16t
DQ
DQ
DQM CS#
DQ
DQ U16b
DQ
DQ
DQ28
DQ29
DQ30
DQ31
DQM CS#
DQ
U9t
DQ
DQ
DQ
DQM CS#
DQ
DQ U9b
DQ
DQ
DQ60
DQ61
DQ62
DQ63
DQM CS#
DQ
DQ U15t
DQ
DQ
DQM CS#
DQ
DQ U15b
DQ
DQ
RDQMB1
RDQMB5
RS2#
RS3#
RDQMB2
RDQMB6
RDQMB3
RDQMB7
U10, U11, U24
RAS#
CAS#
WE#
CKE0
CKE0
CKE1
A0-A12
BA0,BA1
S0#, S2#
S1#, S3#
DQMB0 - DQMB7
VDD
REGE
10K
R
E
G
I
S
T
E
R
S
RRAS#: SDRAMs
RCAS#: SDRAMs
SCL
WP
RWE#: SDRAMs
RCKE0: SDRAMs
SPD
U14
A0 A1 A2
U12
SDA
CK0
SA0 SA1 SA2
PLL
12pF
RCKE1: SDRAMs
RA0-RA12: SDRAMs
RBA0, RBA1: SDRAMs
RS0#, RS2#: Module Rank0
VDD
SDRAMs
VSS
SDRAMs
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
REGISTER x 3
CK1-CK3
12pF
RS1#, RS3#: Module Rank1
RDQMB0 - RDQMB7: SDRAMs
U41
CK0
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SD36C128_256x72G.fm - Rev. E 6/05 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
General Description
General Description
The MT36LSDT12872 and MT36LSDT25672 are high-speed CMOS, dynamic randomaccess, 1GB and 2GB memory modules organized in x72 (ECC) configurations. SDRAM
modules use internally configured quad-bank SDRAM devices with a synchronous interface (all signals are registered on the positive edge of clock signal CK).
Read and write accesses to SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank; A0–A12, select the device row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location
for the burst access.
SDRAM modules provide for programmable read or write burst lengths of 1, 2, 4, or 8
locations, or full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
SDRAM modules use an internal pipelined architecture to achieve high-speed operation. Precharging one device bank while accessing one of the other three device banks
will hide the PRECHARGE cycles and provide seamless, high-speed, random-access
operation.
SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between device banks in order to hide precharge time, and the capability to randomly change column addresses on each clock
cycle during a burst access. For more information regarding SDRAM operation, refer to
the 256Mb or 512Mb SDRAM component data sheets.
PLL and Register Operation
These modules can be operated in either registered mode (REGE pin HIGH), where the
control/address input signals are latched in the register on one rising clock edge and
sent to the SDRAM devices on the following rising clock edge (data access is delayed by
one clock), or in buffered mode (REGE pin LOW) where the input signals pass through
the register/buffer to the SDRAM devices on the same clock.
A phase-lock loop (PLL) on the modules is used to redrive the clock to the SDRAM
devices to minimize system clock loading. (CK0 is connected to the PLL, and CK1, CK2,
and CK3 are terminated.)
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Initialization
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All device
banks must then be precharged, thereby placing the device in the all device banks idle
state.
Once in the idle state, two auto refresh cycles must be performed. After the auto refresh
cycles are complete, the SDRAM is ready for mode register programming. Because the
mode register will power up in an unknown state, it should be loaded prior to applying
any operational command.
Mode Register Definition
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 4 on page 9. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be driven LOW during loading of the
mode register.
The mode register must be loaded when all device banks are idle, and the controller
must wait the specified time before initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 4 on page 9. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and
the interleaved burst types, and a full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached, as shown in
Table 6 on page 10. The block is uniquely selected by A1–Ai when BL = 2; A2–Ai when
BL = 4; and by A3–Ai when BL = 8. See Note 8 of Table 6 on page 10 for Ai values. The
remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the boundary is reached, as
shown in Table 6 on page 10.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mode Register Definition
Figure 4:
Mode Register Definition Diagram
A12 A11 A10
12
11
Reserved
A9
9
10
A8
8
A6
A7
6
7
WB Op Mode
A5
5
A4
A3
4
CAS Latency
3
1
2
BT
A1
A2
Address Bus
A0
0
Mode Register (Mx)
Burst Length
Program
M12, M11, M10 = “0, 0,0”
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
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SD36C128_256x72G.fm - Rev. E 6/05 EN
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
9
All other states reserved
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©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mode Register Definition
Table 6:
Burst Definition Table
Burst Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2, Cn+3,
Cn+4..., ...Cn-1, Cn...
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
A0
2
0
1
4
A2
8
Full Page
(y)
0
0
0
0
1
1
1
1
A1
A0
0
0
1
1
0
1
0
1
A1
A0
0
0
1
1
0
0
1
1
n=i
(location 0-y)
0
1
0
1
0
1
0
1
Notes: 1. For full-page accesses: y = 2,048 (1GB); y= 4,096 (2GB).
2. For BL = 2, i will select the block of two burst; A0 selects the starting column within the
block.
3. For BL = 4, i will select the block of four burst; A0–A1 select the starting column within the
block.
4. For BL = 8, i will select the block of eight burst; A0–A2 select the starting column within
the block.
5. For a full-page burst, the full row is selected and i will select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
7. For BL = 1, i will select the unique column to be accessed, and mode register bit M3 is
ignored.
8. Ai = A0–A9, A11 for 1GB;
Ai = A0–A9, A11, A12 for 2GB.
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mode Register Definition
Figure 5:
CAS Latency Diagram
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CAS latency = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CAS latency = 3
DON’T CARE
UNDEFINED
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 6 on page 10.
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two
or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a read command is registered at T0
and the latency is programmed to two clocks, the DQ will start driving after T1 and the
data will be valid by T2, as shown in the Figure 5 on page 11. Table 7 on page 12, indicates the operating frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mode Register Definition
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0–M2 applies to both read and write
bursts; when M9 = 1, the programmed burst length applies to read bursts, but write
accesses are single-location (non burst) accesses.
Table 7:
CAS Latency Table
Registered mode adds one clock cycle to CAS latency
Allowable Operating Clock Frequency (MHz)
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SD36C128_256x72G.fm - Rev. E 6/05 EN
Speed
CAS Latency = 2
CAS Latency = 3
-13E
-133
≤ 133
≤ 100
≤ 143
≤ 133
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Commands
Commands
Table 8 provides a quick reference of available commands. This is followed by a written
description of each command. For a more detailed description of commands and operations refer to the 256Mb or 512Mb SDRAM component data sheets.
Table 8:
SDRAM Command and DQMB Operation Truth Table
CKE is HIGH for all commands shown except Self Refresh
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh
mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CS#
RAS# CAS# WE# DQMB
H
L
L
L
L
L
L
L
X
H
L
H
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
H
L
L
L
H
X
X
X
L/H7
L/H7
X
X
X
L
–
–
L
–
–
L
–
–
L
–
–
X
L
H
ADDR
DQs
X
X
X
X
Bank/Row
X
Bank/Col
X
Bank/Col Valid
X
Active
Code
X
X
X
Op-Code
–
–
X
Active
High-Z
Notes
1
2
2
3
4, 5
6
7
7
Notes: 1. A0–A12 provide device row address. BA0, BA1 determine which device bank is made
active.
2. A0–A9, A11 (1GB) or 0–A9, A11, A12 (2GB) provide device column address; A10 HIGH
enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both
device banks are precharged and BA0, BA1 are “Don’t Care.”
4. This command is Auto Refresh if CKE is HIGH, Self Refresh if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
except for CKE.
6. A0–A12 define the op-code written to the Mode Register, and should be driven low.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay).
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Figure 6:
Absolute Maximum DC Ratings
Parameter
Min
Max
Units
Voltage on VDD supply relative to Vss
Voltage on inputs, NC or I/O pins relative to Vss
Operating temperature TOPR (commercial - ambient)
Storage temperature (plastic)
-1
-1
0
-55
+4.6
+4.6
+65
+150
V
V
°C
°C
DC Operating Specifications
Table 9:
DC Electrical Characteristics and Operating Conditions
Notes: 1, 5, 6; notes appear on page 19; VDD = VDDQ = +3.3V ±0.3V
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Input leakage current: Any input: 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
Output leakage current: DQs are disabled;
0V ≤ VIN ≤ VDD
Output levels: Output high voltage (IOUT = -4mA)
Output low voltage (IOUT = 4mA)
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SD36C128_256x72G.fm - Rev. E 6/05 EN
Command and
address, CKE
CK, DQMB, S#
DQ
14
Symbol
Min
Max
Units
Notes
VDD, VDDQ
VIH
VIL
3
2
-0.3
3.6
VDD + 0.3
0.8
V
V
V
22
22
-20
20
µA
33
IOZ
-10
-5
10
5
µA
33
VOH
VOL
2.4
–
–
0.4
V
V
II
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
DC Operating Specifications
Table 10:
IDD Specifications and Conditions – 1GB
SDRAM components only; Notes: 1, 5, 6, 11, 13; notes appear on page 19; VDD = VDDQ = +3.3V ±0.3V
Max
Parameter/Condition
Symbol
Operating current: Active mode; Burst = 2; READ or WRITE;
RC = tRC (MIN)
Standby current: Power-Down mode; All device banks idle;
CKE = LOW
Standby current: Active mode; CKE = HIGH; CS# = HIGH;
All device banks active after tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or WRITE; All
device banks active
t
RFC = tRFC (MIN)
Auto refresh current
tRFC = 7.8125µs
CS# = HIGH; CKE = HIGH
-13E
-133
Units
Notes
2,466
2,286
mA
IDD2b
72
72
mA
3, 18, 19,
30
30
IDD3a
756
756
mA
IDD4a
2,466
2,466
mA
IDD5b
IDD6b
10,260
126
9,720
126
mA
mA
IDD7b
90
90
mA
IDD1
a
t
Self refresh current: CKE ≤ 0.2V
Note:
Table 11:
3, 12, 19,
30
3, 18, 19,
30
3, 12
18, 19,
30, 31
4
a - Value calculated as one module rank in this operating condition, and all other module
ranks in power-down mode.
b - Value calculated reflects all module ranks in this operating condition.
IDD Specifications and Conditions – 2GB
SDRAM components only; Notes: 1, 5, 6, 11, 13; notes appear on page 19; VDD = VDDQ = +3.3V ±0.3V
Max
Parameter/Condition
Operating current: Active mode; Burst = 2; READ or WRITE;
tRC = tRC (MIN)
Standby current: Power-Down Mode; All device banks idle;
CKE = LOW
Standby current: Active Mode; CKE = HIGH; CS# = HIGH;
All device banks active after tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or WRITE; All
device banks active
t
RFC = tRFC (MIN)
Auto refresh current
t
RFC = 7.8125µs
CS# = HIGH; CKE = HIGH
Self refresh current: CKE ≤ 0.2V
Note:
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
Symbol
-13E
-133
Units
Notes
IDD1a
3,906
3,636
mA
IDD2b
72
72
mA
3, 18,
19, 30
30
IDD3a
1,476
1,476
mA
IDD4a
3,276
3,276
mA
IDD5b
IDD6b
14,400
360
13,320
360
mA
mA
IDD7b
216
216
mA
3, 12,
19, 30
3, 18,
19, 30
3, 12
18, 19,
30, 31
4
a - Value calculated as one module rank in this operating condition, and all other module
ranks in power-down mode.
b - Value calculated reflects all module ranks in this operating condition.
15
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Capacitance
Capacitance
Table 12:
Capacitance
Note: 2; notes appear on page 19
Parameter
Input capacitance: Address and command
Input capacitance: CKE
Input capacitance: CK
Input capacitance: S#, DQMB
Input/Output capacitance: DQ
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SD36C128_256x72G.fm - Rev. E 6/05 EN
16
Symbol
Min
Typ
Max
Units
CI1
CI2
CI2
CI4
CIO
–
–
–
–
8
8
16
14
5
–
–
–
–
pF
pF
pF
pF
pF
12
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
AC Operating Specifications
AC Operating Specifications
Table 13:
SDRAM Component Electrical Characteristics and Recommended AC Operating
Conditions
Notes: 5, 6, 8, 9, 11, 31; notes appear on page 19
AC Characteristic
-13E
Parameter
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
Sym
CL= 3
CL= 2
Min
AC(3)
AH
AS
tCH
tCL
tCK(3)
tCK(2)
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ(3)
tHZ(2)
tLZ
tOH
t
OHN
tRAS
tRC
tRCD
tREF
tRFC
tRP
tRRD
t
T
Exit SELF REFRESH-to-ACTIVE command
tWR
tXSR
Min
5.4
5.4
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
1.5
0.8
1.5
t
CL= 3
CL = 2
Max
tAC(2)
t
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out High-Z time
CL = 3
CL = 2
Data-out Low-Z time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE command period
ACTIVE-to-READ or WRITE delay
Refresh period
Auto refresh period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time
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SD36C128_256x72G.fm - Rev. E 6/05 EN
t
-133
Units
Notes
5.4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
27
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
0.8
1.5
5.4
5.4
1
3
1.8
37
60
15
120,000
5.4
6
1
3
1.8
44
66
20
64
66
15
14
0.3
1 CLK + 7ns
14
67
17
Max
1.2
120,000
64
66
20
15
0.3
1 CLK + 7.5ns
15
75
1.2
23
23
10
10
28
29
7
24
25
20
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
AC Operating Specifications
Table 14:
AC Functional Characteristics
Notes: 5, 6, 7, 8, 9, 11, 31; notes appear on page 19
Parameter
Symbol
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
Data-out to High-Z from PRECHARGE command
CL= 3
CL = 2
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SD36C128_256x72G.fm - Rev. E 6/05 EN
18
t
CCD
CKED
t
PED
t
DQD
tDQM
t
DQZ
t
DWD
t
DAL
t
DPL
t
BDL
t
CDL
tRDL
tMRD
tROH(3)
tROH(2)
t
-13E
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
-133
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
Units
t
CK
CK
t
CK
t
CK
tCK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
tCK
tCK
tCK
tCK
t
Notes
17
14, 34
14, 34
17, 34
17, 34
17, 34
17, 34
15, 21, 34
16, 21, 34
17, 34
17, 34
16, 21, 34
26
17, 34
17, 34
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Notes
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD = VDDQ = +3.3V ±0.3V; f = 1 MHz, TA = 25°C; pin under
test biased at 1.4V.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured; (0°C ≤ TA ≤ 55°C).
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. Vss and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3.0V, using a measurement reference
level of 1.5V. If the input transition time is longer than 1ns, then the timing is measured from VIL (MAX) and VIH (MIN) and no longer at the 1.5V midpoint. CLK should
always be referenced to crossover. Refer to Micron Technical Note TN-48-09.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR + tRP; clock(s) specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -133 and -13E.
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Notes
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for
a pulse width ≤ 3ns for all inputs except A12. VIH overshoot for pin A12 is limited to
VDDQ + 1V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one
third of the cycle rate.
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -13E;
and 7.5ns for -133 after the first clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For -133, CL = 3 and tCK = 7.5ns; for -13E, CL = 2 and tCK = 7.5ns.
30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
31. Refer to component data sheet for timing waveforms.
32. The value for tRAS used in -13E speed grade modules is calculated from
tRC - tRP = 45ns.
33. Leakage number reflects the worst case leakage possible through the module pin, not
what each memory device contributes.
34. This AC timing function will show an extra clock cycle when in registered mode.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Timing Requirements and Switching Characteristics
Timing Requirements and Switching Characteristics
Table 15:
Register Timing Requirements and Switching Characteristics
0°C ≤ TA ≤ 55°C
VDD = +3.3V ±0.3V
Register
SSTL
bit pattern by
JESD82-2
Table 16:
Symbol
Parameter
Condition
fclock
tpd1
Clock frequency
Propagation delay, single rank
(CK to Output)
propagation delay, dual rank
(CK to output)
Pulse duration
Setup time
Hold time
50pF to GND and
50 Ohms to Vtt
30pF to GND and
50Ω to VTT
CK, HIGH or LOW
Data before CK HIGH
Data after CK HIGH
tpd2
tw
tsu
th
Min
Max
Units
150
1.4
240
3.5
MHz
ns
0.7
2.4
ns
3.3
.75
.75
–
–
–
ns
ns
ns
PLL Clock Driver Timing Requirements And Switching Characteristics
0°C ≤ TA ≤ 55°C
VDD = +3.3V ±0.3V
Parameter
Operating clock frequency
Input duty cycle
Cycle to cycle jitter
Static phase offset
SSC induced skew
Output to output skew
Symbol
Min
Max
Units
fCK
50
44
-75
-150
–
–
140
55
75
150
150
150
MHz
%
ps
ps
ps
ps
tDC
tJIT
CC
t∅
tSSC
tSK
O
Notes
1, 2
Notes: 1. SSC = Spread Spectrum Clock. the use of SSC synthesizers on the system motherboard will
reduce EMI.
2. Skew is defined as the total clock skew between any two outputs and is therefore specified as a maximum only.
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Timing Requirements and Switching Characteristics
Figure 7:
Component Case Temperature vs. Airflow
100
Ambient Temperature = 25º C
90
Tmax- memory stress software
Degrees Celsius
80
70
Tave- memory stress software
60
50
Tave- 3D gaming software
40
30
Minimum Air Flow
20
2.0
1.0
0.5
0.0
Air Flow (meters/sec)
Notes: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM)
across all modules when installed in a system.
2. The component case temperature measurements shown above are obtained experimentally. The system used for experimental purposes is a dual-processor 600 MHz work station,
fully loaded with four MT36LSDT12872G modules. Case temperatures charted represent
worst-case component locations on modules installed in the internal slots of the system.
3. Temperature versus air speed data is obtained by performing experiments with the system
motherboard removed from its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard for testing are the processor(s)
and video card, all other peripheral devices are mounted outside of the wind tunnel test
chamber.
4. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic software application developed for internal use by Micron
Technology, Inc.
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Serial Presence Detect
Serial Presence Detect
SPD Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 8,
and Figure 9 on page 24).
SPD Start Condition
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Figure 10 on page 24).
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
Figure 8:
Data Validity
SCL
SDA
Data stable
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Data
change
23
Data stable
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©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Serial Presence Detect
Figure 9:
Definition of Start and Stop
SCL
SDA
Start
bit
Figure 10:
Stop
bit
Acknowledge Response From Receiver
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Table 17:
EEPROM Device Select Code
The most significant bit (b7) is sent first
Device Type Identifier
Select Code
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Memory area select code (two arrays)
Protection register select code
Table 18:
Chip Enable
EEPROM Operating Modes
Mode
Current address read
Random address read
Sequential read
Byte write
Page write
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SD36C128_256x72G.fm - Rev. E 6/05 EN
RW Bit
WC
BYTES
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
VIL
1
1
≥1
1
≤ 16
24
Initial Sequence
Start, device select, RW = 1
Start, device select, RW = 0, address
Restart, device select, RW = 1
Similar to current or random address read
Start, device select, RW = 0
Start, device select, RW = 0
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Serial Presence Detect
Figure 11:
SPD EEPROM Timing Diagram
tF
t HIGH
tR
t LOW
SCL
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
t DH
t AA
t BUF
SDA OUT
UNDEFINED
Table 19:
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
Symbol
Min
Max
Units
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD
Power supply current: SCL clock frequency = 100 KHz
VDD
VIH
VIL
VOL
ILI
ILO
ICCS
ICC Write
ICC Read
3
VDD x 0.7
-1
–
-10
-10
–
–
–
3.6
VDD + 0.5
VDD x 0.3
0.4
10
10
30
3
1
V
V
V
V
µA
µA
µA
mA
mA
Min
Max
Units
Notes
0.2
1.3
200
0.9
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
1
Table 20:
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
Symbol
t
AA
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
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tBUF
tDH
tF
t
HD:DAT
t
HD:STA
tHIGH
tI
tLOW
tR
f
SCL
tSU:DAT
tSU:STA
25
300
0
0.6
0.6
50
1.3
0.3
400
100
0.6
2
2
3
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Serial Presence Detect
Table 20:
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
Symbol
Stop condition setup time
WRITE cycle time
t
SU:STO
t
WRC
Min
Max
Units
Notes
10
µs
ms
4
0.6
Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between
SCL=1 and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal erase/program cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistor, and the EEPROM does not respond to its slave address.
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Serial Presence Detect
Table 21:
Serial Presence-Detect Matrix
“1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; VDD = +3.3V ±0.3V
Byte
Description
0
1
2
3
4
5
6
7
8
9
Number of bytes used by Micron
Total number of SPD memory bytes
Memory type
Number of row addresses
Number of column addresses
Number of module ranks
Module data width
Module data width (continued)
Module voltage interface levels
SDRAM cycle time, tCK (CAS latency = 3)
10
11
12
13
14
15
27
SDRAM access from clock, tAC (CAS latency = 3)
Module configuration type
Refresh rate/type
SDRAM width (primary SDRAM)
Error-checking SDRAM data width
Minimum clock delay from back-to-back random
column addresses,tCCD
Burst lengths supported
Number of banks on SDRAM device
CAS latencies supported
CS latency
WE latency
SDRAM module attributes
SDRAM device attributes: General
SDRAM cycle time, tCK
(CAS latency = 2)
SDRAM access from clock, tAC
(CAS latency = 2)
SDRAM cycle time, tCK
(CAS latency = 1)
SDRAM access from clock, tAC
(CAS latency = 1)
Minimum row precharge time, tRP
28
Minimum row active to row active, tRRD
29
Minimum RAS# to CAS# delay, tRCD
30
Minimum RAS# pulse width, tRAS (See note 1)
31
32
33
34
Module rank density
Command and address setup time, tAS, tCMS
Command and address hold time, tAH, tCMH
Data signal input setup time, tDS
16
17
18
19
20
21
22
23
24
25
26
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SD36C128_256x72G.fm - Rev. E 6/05 EN
27
Entry
(Version)
MT36LSDT12872
MT36LSDT25672
128
256
SDRAM
13
11 or 12
2
72
0
LVTTL
7ns (-13E)
7.5ns (-133)
5.4ns (-13E/-133)
ECC
7.81µs/SELF
4
4
1
80
08
04
0D
0B
02
48
00
01
70
75
54
02
82
04
04
01
80
08
04
0D
0C
02
48
00
01
70
75
54
02
82
04
04
01
1, 2, 4, 8, PAGE
4
2, 3
0
0
-13E/-133
0E
7.5ns (-13E)
8F
04
06
01
01
1F
0E
75
8F
04
06
01
01
1F
0E
75
5.4ns (-13E)
54
54
–
00
00
–
00
00
15ns (-13E)
20ns (-133)
14ns (-13E)
15ns (-133)
15ns (-13E)
20ns (-133)
45ns (-13E)
44ns (-133)
512MB / 1GB
1.5ns (-13E/-133)
0.8ns (-13E/-133)
1.5ns (-13E/-133)
0F
14
0E
0F
0F
14
2D
2C
80
15
08
15
0F
14
0E
0F
0F
14
2D
2C
01
15
08
15
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Serial Presence Detect
Table 21:
Serial Presence-Detect Matrix (Continued)
“1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; VDD = +3.3V ±0.3V
Byte
Entry
(Version)
Description
tDH
0.8ns (-13E/-133)
35
Data signal input hold time,
36–40 Reserved
41
Device minimum active/auto-refresh time, tRC
66ns (-13E)
71ns (-133)
42–61 Reserved
62
SPD revision
63
Checksum for bytes 0–62
64
65–71
72
73–90
91
92
93
94
95–98
99–125
126
127
REV. 2.0
-13E
-133
MICRON
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code (continued)
Manufacturing location
Module part number (ASCII)
PCB identification code
Identification code (continued)
Year of manufacture in BCD
Week of manufacture in BCD
Module serial number
Manufacturer-Specific data (RSVD)
System frequency
1–9
1–12
0
100 MHz
(-13E/-133)
MT36LSDT12872
MT36LSDT25672
08
00
3C
42
00
02
22
6E
2C
FF
01–09
Variable Data
01–0C
00
Variable Data
Variable Data
Variable Data
–
64
08
00
3C
42
00
02
A4
F0
2C
FF
01–09
Variable Data
01–0C
00
Variable Data
Variable Data
Variable Data
–
64
8F
SDRAM component and clock detail
tRAS
Notes: 1. The value of
used for the -13E module is calculated from
ification value is 37ns.
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28
8F
tRC
-
tRP.
Actual device spec-
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Module Dimensions
Module Dimensions
Figure 12:
168-Pin DIMM Dimensions – Standard PCB
FRONT VIEW
0.320 (8.13)
MAX
5.256 (133.50)
5.244 (133.20)
U1
U2
U3
U4
U6
U5
U7
U8
U9
0.079 (2.00) R
(2X)
1.705 (43.31)
1.695 (43.05)
U10
0.118 (3.00)
(2X)
U12
U11
U14
0.700 (17.78)
TYP.
0.118 (3.00) TYP.
0.054 (1.37)
0.046 (1.17)
0.250 (6.35) TYP.
0.039 (1.00) R(2X)
PIN 1
0.118 (3.00)
TYP.
0.040 (1.02)
TYP.
0.050 (1.27)
TYP.
PIN 84
4.550 (115.57)
BACK VIEW
U15
U16
U17
U18
U20
U19
U21
U22
U23
U24
0.128 (3.25)
(2X)
0.118 (3.00)
1.661 (42.18)
2.625 (66.68)
PIN 168
PIN 85
Note:All dimensions in inches (millimeters); MAX or typical where noted.
MIN
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Module Dimensions
Figure 13:
168-Pin DIMM Dimensions – Low-Profile
0.254 (6.45)
MAX
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
U12
0.079 (2.00) R
(2X)
U1
U2
U3
U4
U5
U7
U6
U8
U9
U11
0.118 (3.00)
(2X)
1.206 (30.63)
1.194 (30.33)
U10
0.700 (17.78)
U14
0.118 (3.00)
0.250 (6.35)
0.039 (1.00) R(2X)
PIN 1
0.118 (3.00)
0.040 (1.02)
PIN 84
0.050 (1.27)
0.054 (1.37)
0.046 (1.17)
4.550 (115.57)
BACK VIEW
U15
U16
U17
U18
U20
U19
U21
U22
U23
U24
0.128 (3.25)
(2X)
0.118 (3.00)
1.661 (42.18)
2.625 (66.68)
PIN 168
PIN 85
Note:All dimensions in inches (millimeters); MAX or typical where noted.
MIN
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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