LTP5901-WHM/LTP5902-WHM
SmartMesh WirelessHART Node
Wireless Mote Module
Network Features
n
n
n
n
Description
Complete Radio Transceiver, Embedded Processor,
and Networking Software for Forming a Self-Healing
Mesh Network
Compliant to WirelessHART (IEC62591) Standard
SmartMesh® Networks Incorporate:
n Time synchronized Network-Wide Scheduling
n Per Transmission Frequency Hopping
n Redundant Spatially Diverse Topologies
n Network-Wide Reliability and Power Optimization
n NIST Certified Security
SmartMesh Networks Deliver:
n >99.999% Network Reliability Achieved in the
Most Challenging Dynamic RF Environments Often
Found in Industrial Applications
n Sub 50µA Routing Nodes
LTP5901/2-WHM FEATURES
n
n
n
Industry-leading low power radio technology with:
n 4.5mA to receive a packet
n 5.4mA to transmit at 0dBm
n 9.7mA to transmit at 8dBm
RF modular certifications include USA, Canada, EU,
Japan, Taiwan, Korea, India, Australia and New Zealand
PCB assembly with chip antenna (LTP5901-WHM)
or with MMCX antenna connector (LTP5902-WHM).
QFN version (LTC®5800-WHM) available
SmartMesh WirelessHART wireless sensor networks are
self managing, low power networks built from wireless
nodes called motes. The LTP™5901-WHM/LTP5902-WHM
is the WirelessHART mote product in the Eterna®* family
of IEEE 802.15.4 printed circuit board assembly solutions,
featuring a highly-integrated, low power radio design by
Dust Networks® as well as an ARM Cortex-M3 32-bit
microprocessor running Dust’s embedded SmartMesh
WirelessHART networking software. Both the LTP5901WHM (with chip antenna), at 24mm × 42mm, and the
LTP5902-WHM (with MMCX connector), at 24mm × 37mm,
are designed for surface mount assembly.
With Dust’s time-synchronized WirelessHART networks, all
motes in the network may route, source or terminate data,
while providing many years of battery powered operation.
The SmartMesh WirelessHART software provided with
the LTP5901/2-WHM is fully tested and validated, and is
readily configured via a software Application Programming
Interface (API).
SmartMesh WirelessHART motes deliver a highly flexible
network with proven reliability and low power performance
in an easy-to-integrate platform.
L, LT, LTC, LTM, Eterna, SmartMesh, Linear Technology, the Linear logo, Dust and Dust
Networks are registered trademarks and LTP and the Dust Networks logo are trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217, 7791419, 7881239,
7898322, 8222965.
* Eterna is Dust Networks’ low power radio SoC architecture.
Typical Application
MANAGER
LTP5901-WHM
EXPANDED VIEW
LTP5903-WHR
MOTE
ANTENNA
MOTE
IN+
SENSOR
LTC2379-18 SPI
µCONTROLLER
UART
UART
ETHERNET
IN–
HOST
APPLICATION
MOTE
MOTE
MOTE
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1
LTP5901-WHM/LTP5902-WHM
Table of Contents
Network Features........................................... 1
LTP5901/2-WHM FEATURES............................... 1
Typical Application ......................................... 1
Description.................................................. 1
Smartmesh Network Overview............................ 3
Absolute Maximum Ratings............................... 4
Pin Configuration........................................... 4
Order Information........................................... 5
Recommended Operating Conditions.................... 5
DC Characteristics.......................................... 5
Radio Specifications....................................... 6
Radio Receiver Characteristics........................... 6
Radio Transmitter Characteristics........................ 7
Digital I/O Characteristics................................. 7
Temperature Sensor Characteristics..................... 8
Analog Input Chain Characteristics...................... 8
System Characteristics.................................... 8
UART AC Characteristics................................... 9
TIMEn AC Characteristics................................. 10
Radio Inhibit AC Characteristics......................... 10
Flash AC Characteristics.................................. 11
Flash SPI Slave AC Characteristics..................... 11
Typical Performance Characteristics................... 13
Pin Functions............................................... 17
Operation................................................... 21
Power Supply........................................................... 21
Supply Monitoring and Reset.................................. 21
Precision Timing...................................................... 21
Application Time Synchronization...........................23
Time References......................................................23
Radio.......................................................................23
UARTs......................................................................23
Autonomous MAC.................................................... 24
Security...................................................................25
Temperature Sensor................................................25
Radio Inhibit............................................................25
Software Installation................................................25
Flash Data Retention................................................25
State Diagram..........................................................26
Applications Information................................. 28
Regulatory and Standards Compliance.................... 28
Soldering Information.............................................. 28
Related Documentation................................... 28
Package Description...................................... 29
Revision History........................................... 31
Typical Application........................................ 32
Related Parts............................................... 32
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Smartmesh Network Overview
A SmartMesh network consists of a self-forming multi-hop,
mesh of nodes, known as motes, which collect and relay
data, and a Network Manager that monitors and manages
network performance and security, and exchanges data
with a host application.
SmartMesh networks communicate using a Time Slotted
Channel Hopping (TSCH) link layer, pioneered by Dust
Networks. In a TSCH network, all motes in the network
are synchronized to within less than a millisecond. Time
in the network is organized into timeslots, which enables
collision-free packet exchange and per-transmission
channel-hopping. In a SmartMesh network, every device
has one or more parents (e.g. mote 3 has motes 1 and
2 as parents) that provide redundant paths to overcome
communications interruption due to interference, physical
obstruction or multi-path fading. If a packet transmission
fails on one path, the next retransmission may try on a
different path and different RF channel.
A network begins to form when the network manager instructs
its on-board Access Point (AP) radio to begin sending advertisements - packets that contain information that enables
a device to synchronize to the network and request to join.
This message exchange is part of the security handshake
that establishes encrypted communications between the
manager or application, and mote. Once motes have joined
the network, they maintain synchronization through time
corrections when a packet is acknowledged.
The Network Manager uses health reports to continually
optimize the network to maintain >99.999% data reliability
even in the most challenging RF environments.
The use of TSCH allows SmartMesh devices to sleep inbetween scheduled communications and draw very little
power in this state. Motes are only active in timeslots
where they are scheduled to transmit or receive, typically
resulting in a duty cycle of < 1%. The optimization software in the Network Manager coordinates this schedule
automatically. When combined with the Eterna low power
radio, every mote in a SmartMesh network – even busy
routing ones – can run on batteries for years. By default,
all motes in a network are capable of routing traffic from
other motes, which simplifies installation by avoiding the
complexity of having distinct routers vs. non-routing end
nodes. Motes may be configured as non-routing to further
reduce that particular mote’s power consumption and to
support a wide variety of network topologies.
ALL NODES ARE ROUTERS.
THEY CAN TRANSMIT AND RECEIVE.
THIS NEW NODE CAN JOIN
ANYWHERE BECAUSE ALL
NODES CAN ROUTE.
HOST
APPLICATION
SNO 02
NETWORK MANAGER
AP
Mote
1
Mote
2
Mote
3
SNO 01
An ongoing discovery process ensures that the network
continually discovers new paths as the RF conditions
change. In addition, each mote in the network tracks performance statistics (e.g. quality of used paths, and lists of
potential paths) and periodically sends that information
to the network manager in packets called health reports.
At the heart of SmartMesh motes and network managers is the Eterna IEEE 802.15.4e System-on-Chip (SoC),
featuring Dust Networks’ highly-integrated, low power
radio design, plus an ARM Cortex-M3 32-bit microprocessor running SmartMesh networking software. The
SmartMesh networking software comes fully compiled
yet is configurable via a rich set of Application Programming Interfaces (APIs) which allows a host application
to interact with the network, e.g. to transfer information
to a device, to configure data publishing rates on one or
more motes, or to monitor network state or performance
metrics. Data publishing can be uniform or different for
each device, with motes being able to publish infrequently
or faster than once per second as needed.
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LTP5901-WHM/LTP5902-WHM
Absolute Maximum Ratings
(Note 1, Note 2)
Supply Voltage on VSUPPLY...................................4.20V
Input Voltage on AI_0/1/2/3 Inputs..........................1.98V
Voltage on any Digital I/O Pin..... –0.3V to VSUPPLY +0.3V
Input RF Level.......................................................10dBm
Storage Temperature Range (Note 3)...... –55°C to 105°C
Pin Configuration
Operating Temperature Range
LTP5901I/LPT5902I..............................–40°C to 85°C
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions be
observed when handling the LTP5901/LTP5902-WHM.
Pin functions shown in italics are currently not supported in software.
GND
1
66
GND
RESERVED
2
65
NC
NC
3
64
RADIO_INHIBIT / GPIO15
GPIO17
4
63
TIMEn / GPIO1
GPIO18
5
62
UART_TX
GPIO19
6
61
UART_TX_CTSn
AI_2
7
60
UART_TX_RTSn
AI_1
8
59
UART_RX
AI_3
9
58
UART_RX_CTSn
AI_0
10
57
UART_RX_RTSn
GND
11
56
GND
RESERVED
12
55
VSUPPLY
NC
13
54
RESERVED
NC
14
53
NC
RESETn
15
52
NC
TDI
16
51
FLASH_P_ENn / GPIO2
TDO
17
50
SPIS_SSn / SDA
TMS
18
49
SPIS_SCK / SCL
TCK
19
48
SPIS_MOSI / GPIO26 / UARTC1_RX
GND
20
47
SPIS_MISO / 1_WIRE / UARTC1_TX
DP4 (GPIO23)
21
46
PWM0 / GPIO16
RESERVED
22
45
DP1 (GPIO20) / TIMER16_IN
RESERVED
23
44
SPIM_SS_0n / GPIO12
RESERVED
24
43
SPIM_SS_1n / GPIO13
DP3 (GPIO22) / TIMER8_IN
25
42
GND
DP2 (GPIO21) / LPTIMER_IN
26
41
SPIM_SCK / GPIO9
SLEEPn / GPIO14
27
40
SPIM_MOSI / GPIO10
DP0 (GPIO0) / SPIM_SS_2n
28
39
IPCS_SSn / GPIO3
NC
29
38
SPIM_MISO / GPIO11
GND
30
37
GND
PC PACKAGE
IPCS_SCK / GPIO4
GND
34 35 36
IPCS_MOSI / GPIO5
IPCS_MISO / GP106
UARTCO_TX
UARTCO_RX
31 32 33
66-LEAD PCB
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Order Information
LEAD FREE FINISH†
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTP5901IPC-WHMA#PBF
LTP5901IPC-WHMA#PBF
66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna
–40°C to 85°C
LTP5902IPC-WHMA#PBF
LTP5902IPC-WHMA#PBF
66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX
Connector
–40°C to 85°C
†This product ships with the flash erased at the time of order. OEMs will need to program devices during development and manufacturing.
For legacy part numbers and ordering information go to: http://www.linear.com/LTP5901-WHM#orderinfo or
http://www.linear.com/LTP5902-WHM#orderinfo
*The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
Recommended Operating Conditions
The l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VSUPPLY Supply Voltage
MIN
Including Noise and Load Regulation
l
Supply Noise
50Hz to 2MHz
l
Operating Relative Humidity
Non-Condensing
l
Temperature Ramp Rate
While Operating in Network
l
TYP
2.1
MAX
UNITS
3.76
V
250
mV
10
90
%RH
–8
8
°C/Min
DC Characteristics
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
OPERATION/STATE
CONDITIONS
MIN
TYP
MAX
UNITS
Power-on Reset
During Power-on Reset, Maximum 750µs + VSUPPLY Rise
Time from 1V to 1.9V
12
mA
Doze
RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off,
All Data and State Retained, 32.768kHz Reference Active
1.2
µA
Deep Sleep
RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off,
All Data and State Retained, 32.768kHz Reference Inactive
0.8
µA
In-circuit Programming
RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz
20
mA
Peak Operating Current
+8dBm
+0dBm
System Operating at 14.7MHz, Radio Transmitting, During
Flash Write. Maximum duration 4.33 ms.
30
26
mA
mA
Active
ARM Cortex M3, RAM and Flash Operating, Radio and All
Other Peripherals Off. Clock Frequency of CPU and Peripherals
Set to 7.3728MHz, VCORE = 1.2V
1.3
mA
Flash Write
Single Bank Flash Write
3.7
mA
Single Bank Page or Mass Erase
2.5
mA
Radio Tx
+0dBm
+8dBm
Flash Erase
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
5.4
9.7
mA
mA
Radio Rx
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
4.5
mA
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LTP5901-WHM/LTP5902-WHM
Radio Specifications
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
2.4000
MAX
UNITS
2.4835
GHz
Frequency Band
l
Number of Channels
l
15
Channel Separation
l
5
MHz
l
2405 + 5•(k-11)
MHz
250
kbps
Channel Center Frequency
Where k = 11 to 25, as Defined by IEEE.802.15.4
Raw Data Rate
l
Antenna Pin ESD Protection
HBM Per JEDEC JESD22-A114F
Range (Note 4)
Indoor
Outdoor
Free Space
25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m
Above Ground
±6000
V
100
300
1200
m
m
m
Radio Receiver Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
Receiver Sensitivity
Packet Error Rate (PER) = 1% (Note 5)
–93
dBm
Receiver Sensitivity
PER = 50%
–95
dBm
Saturation
Maximum Input Level the Receiver Will
Properly Receive Packets
Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Above the Desired Signal, PER = 1% (Note 5)
Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Below the Desired Signal, PER = 1% (Note 5)
Desired Signal at –82dBm, Alternate Modulated Channel
10MHz Above the Desired Signal, PER = 1% (Note 5)
Desired Signal at –82dBm, Alternate Modulated Channel
10MHz Below the Desired Signal, PER = 1% (Note 5)
Desired Signal at –82dBm, Second Alternate Modulated
Channel Either 15MHz Above or Below, PER = 1% (Note 5)
Desired Signal at –82dBm, Undesired Signal is an 802.15.4
Modulated Signal at the Same Frequency, PER = 1%
0
dBm
22
dBc
19
dBc
40
dBc
36
dBc
42
dBc
–6
dBc
LO Feed Through
–55
dBm
Frequency Error Tolerance (Note 6)
±50
ppm
Symbol Error Tolerance
±50
ppm
–90 to –10
dBm
Adjacent Channel Rejection (High Side)
Adjacent Channel Rejection (Low Side)
Alternate Channel Rejection (High Side)
Alternate Channel Rejection (Low Side)
Second Alternate Channel Rejection
Co-Channel Rejection
MIN
Received Signal Strength Indicator (RSSI)
Input Range
RSSI Accuracy
RSSI Resolution
TYP
MAX
UNITS
±6
dB
1
dB
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LTP5901-WHM/LTP5902-WHM
Radio Transmitter Characteristics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
Output Power
High Calibrated Setting
Low Calibrated Setting
Spurious Emissions
Delivered to a 50Ω load
30 MHz to 1000 MHz
1 GHz to 12.75 GHz
2.4 GHz ISM Upper Band Edge (Peak)
2.4 GHz ISM Upper Band Edge (Average)
2.4 GHz ISM Lower Band Edge
Harmonic Emissions
2nd Harmonic
3rd Harmonic
RBW = 120kHz, VBW = 100Hz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 10Hz
RBW = 100kHz, VBW = 100kHz
Conducted Measurement Delivered to a 50Ω Load,
Resolution Bandwidth = 1MHz, Video Bandwidth = 1MHz.
MIN
TYP
MAX
UNITS
8
0
dBm
dBm
<–70
–45
–37
–49
–45
dBm
dBm
dBm
dBm
dBc
–50
–45
dBm
dBm
Conducted Measurement with a 50Ω Single-ended Load,
+8dBm Output Power. All Measurements Made with Max
Hold.
Digital I/O Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VIL
Low Level Input Voltage
(Note 7)
l
–0.3
MIN
TYP
0.6
V
VIH
High Level Input Voltage
(Note 8)
l
VSUPPLY
–0.3
V
VOL
Low Level Output Voltage
Type 1, IOL(MAX) = 1.2mA
l
VSUPPLY
+0.3
0.4
VOH
High Level Output Voltage
Type 1, IOH(MAX) = -0.8mA
l
VSUPPLY
–0.3
V
VOL
Low Level Output Voltage
Type 2, Low Drive, IOL(MAX) = 2.2mA
l
VSUPPLY
+0.3
0.4
VOH
High Level Output Voltage
Type 2, Low Drive, IOH(MAX) = –1.6mA
l
V
VOL
Low Level Output Voltage
Type 2, High Drive, IOL(MAX) = 4.5mA
l
VSUPPLY
+0.3
0.4
VOH
High Level Output Voltage
Type 2, High Drive, IOH(MAX) = –3.2mA
l
VSUPPLY
+0.3
V
Input Leakage Current
Input Driven to VSUPPLY or GND
VSUPPLY
–0.3
VSUPPLY
–0.3
Pull-Up / Pull-Down Resistance
MAX
UNITS
V
V
V
50
nA
50
kΩ
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7
LTP5901-WHM/LTP5902-WHM
Temperature Sensor Characteristics
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
Offset
Temperature Offset Error at 25°C
MIN
Slope Error
TYP
MAX
UNITS
±0.25
°C
±0.033
°C/°C
Analog Input Chain Characteristics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
Variable Gain Amplifier
Gain
Gain Error
DNL
DNL
INL
TYP
1
Offset-Digital to Analog Converter (DAC)
Full-scale
Resolution
Differential Non-Linearity
Analog to Digital Converter (ADC)
Full-scale, Signal
Resolution
Offset
Differential Non-Linearity
Integral Non-Linearity
Settling Time
Conversion Time
Current Consumption
8
2
1.80
4
1.80
1.8
1.4
Mid-Scale
10kΩ Source Impedance
40
Analog Inputs (Note 9)
Load
Series Input Resistance
MAX
2.7
12
1
1
10
20
20
1
UNITS
%
V
Bits
mV
V
mV
LSB
LSB
LSB
µs
µs
µA
pF
kΩ
System Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
Doze to Active State Transition
Doze to Radio Tx or Rx
QCCA
Charge to Sample RF Channel RSSI
Charge Consumed Starting from Doze State and
Completing an RSSI Measurement
QMAX
Largest Atomic Charge Operation
Flash Erase, 21 ms Max duration
RESETn Pulse Width
MAX
UNITS
5
µs
1.2
ms
4
µC
200
l
l
TYP
125
µC
µs
Total Capacitance
Note 13
l
6
µF
Total Inductance
Note 13
l
3
µH
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UART AC Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
Permitted Rx Baud Rate Error
CONDITIONS
Both Application Programming
Interface (API) and Command Line
Interface (CLI) UARTs
Both API and CLI UARTs
l
MIN
–2
TYP
MAX
2
UNITS
%
–1
0
1
2
%
ms
0
0
20
22
ms
ms
0
22
ms
tRX_INTERBYTE
Generated Tx Baud Rate Error
Assertion of UART_RX_RTSn to Assertion of
UART_RX_CTSn, or Negation of UART_RX_
RTSn to Negation of UART_RX_CTSn
Assertion of UART_RX_CTSn to Start of Byte
End of Packet (End of the Last Stop Bit) to
Negation of UART_RX_RTSn
Assertion of UART_TX_RTSn to Assertion of
UART_TX_CTSn
Negation of UART_TX_CTSn to Negation of
UART_TX_RTSn
Assertion of UART_TX_CTSn to Start of Byte
End of Packet (End of the Last Stop Bit) to
Negation of UART_TX_RTSn
Receive Inter-Byte Delay
tRX_INTERPACKET
Receive Inter-Packet Delay
l
20
ms
tTX_INTERPACKET
Transmit Inter-Packet Delay
l
1
Bit
Period
tTX to TX_CTS
Start of Byte to Negation of UART_TX_CTSn
l
0
ns
tRX_RTS to RX_CTS
tCTS_R to RX
tEOP to RX_RTS
tBEG_TX_RTS to TX_CTS
tEND_TX_CTS to TX_RTS
tTX_CTS to TX
tEOP to TX_RTS
l
l
l
l
2
l
Bit Period
0
0
2
1
100
l
Bit Period
Bit Period
ms
tEOP to RX_RTS
UART_RX_RTSn
tRX_RTS to_RX_CTS
tRX_RTS to_RX_CTS
UART_RX_CTSn
tRX_INTERBYTE
tRX_CTS to RX
UART_RX
BYTE 0
BYTE 1
tEOP to TX_RTS
UART_TX_RTSn
tBEG_TX RTS to TX_CTS
tEND_TX_CTS to_TX_RTS
tEND_TX_RTS to_TX_CTS
tTX to TX_CTS
UART_TX_CTSn
tTX_CTS to TX
UART_TX
BYTE 0
BYTE 1
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Figure 1. API UART Timing
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9
LTP5901-WHM/LTP5902-WHM
TIMEn AC Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
tSTROBE
PARAMETER
TIMEn Signal Strobe Width
l
125
tRESPONSE
Delay from Rising Edge of TIMEn to the Start
of Time Packet on API UART
Delay from End of Time Packet on API UART
to Falling Edge of Subsequent TIMEn
Timestamp Resolution (Note 10)
l
0
l
0
l
1
µs
Network-Wide Time Accuracy (Note 11)
l
±5
µs
tTIME_HOLD
CONDITIONS
MIN
TYP
MAX
UNITS
µs
100
ms
ns
tSTROBE
tTIME_HOLD
TIMEN
tRESPONSE
UART_TX
TIME INDICATION PAYLOAD
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Figure 2. Timestamp Timing
Radio Inhibit AC Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tRADIO_OFF
tRADIO_INHIBIT_STROBE
CONDITIONS
MIN
TYP
MAX
UNITS
Delay from Rising Edge of RADIO_INHIBIT to
Radio Disabled
l
20
ms
Maximum RADIO_INHIBIT Strobe Width
l
2
s
tRADIO_INHIBIT_STROBE
RADIO_INHIBIT
tRADIO_OFF
RADIO STATE
ACTIVE/OFF
OFF
ACTIVE/OFF
59012whm F03
Figure 3. RADIO_INHIBIT Timing
59012whmfa
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Flash AC Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
CONDITIONS
tWRITE
Time to Write a 32-bit Word (Note 12)
l
21
µs
tPAGE_ERASE
Time to Erase a 2KByte Page (Note 12)
l
21
ms
tMASS_ERASE
Time to Erase 256KByte Flash Bank (Note 12)
l
21
ms
Data Retention
MIN
25°C
85°C
105°C
TYP
MAX
100
20
8
UNITS
Years
Years
Years
Flash SPI Slave AC Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tFP_EN_to_RESET
Setup from Assertion of FLASH_P_ENn to
Assertion of RESETn
CONDITIONS
l
MIN
0
TYP
MAX
UNITS
ns
tFP_ENTER
Delay from the Assertion RESETn to the First
Falling Edge of IPCS_SSn
l
125
µs
tFP_EXIT
Delay from the Completion of the Last Flash SPI
Slave Transaction to the Negation of RESETn
and FLASH_P_ENn (Note 13)
l
10
µs
tSSS
IPCS_SSn Setup to the Leading Edge of
IPCS_SCK
l
15
ns
tSSH
IPCS_SSn Hold from Trailing Edge of IPCS_
SCK
l
15
ns
tCK
IPCS_SCK Period
l
300
ns
tDIS
IPCS_MOSI Data Setup
l
15
ns
tDIH
IPCS_MOSI Data Hold
l
5
tDOV
IPCS_MISO Data Valid
l
–5
30
ns
ns
tOFF
IPCS_MISO Data Tri-state
l
0
30
ns
59012whmfa
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flash spi slave ac characteristics
tFP_EN to_RESET
FLASH_P_ENn
tFP_ENTER
tFP_EXIT
RESETn
tSSS
tSSH
IPCS_SSn
tCK
IPCS_SCK
tDIS
tDIH
IPCS_MOSI
59012whm F04
Figure 4. Flash Programming Interface Timing
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: ESD (electrostatic discharge) sensitive device. ESD protection
devices are used extensively internal to Eterna. However, high electrostatic
discharge can damage or degrade the device. Use proper ESD handling
precautions.
Note 3: Extended storage at high temperature is discouraged, as this
negatively affects the data retention of Eterna’s calibration data. See the
FLASH Data Retention section for details.
Note 4: Actual RF range is subject to a number of installation-specific
variables including, but not restricted to ambient temperature, relative
humidity, presence of active interference sources, line-of-sight obstacles,
and near-presence of objects (for example, trees, walls, signage, and so
on) that may induce multipath fading. As a result, range varies.
Note 5: As Specified by IEEE Std. 802.15.4-2006: Wireless Medium
Access Control (MAC) and Physical Layer (PHY) Specifications for LowRate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.
org/findstds/standard/802.15.4-2011.html.
Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a
frequency tolerance of better than ±40 ppm.
Note 7: Per pin I/O types are provided in the Pin Functions section.
Note 8: VIH maximum voltage input must respect the VSUPPLY maximum
voltage specification.
Note 9: The analog inputs to the ADC can be modeled as a series resistor
to a capacitor. At a minimum the entire circuit, including the source
impedance for the signal driving the analog input should be designed
to settle to within ¼ LSB within the sampling window to match the
performance of the ADC.
Note 10: See the SmartMesh WirelessHART Mote API Guide for the time
indication notification definition.
Note 11: Network time accuracy is a statistical measure and varies over
the temperature range, reporting rate and the location of the device
relative to the manager in the network. See the Typical Performance
Characteristics section for a more detailed description.
Note 12: Code execution from flash banks being written or erased is
suspended until completion of the flash operation.
Note 13: Guaranteed by design. Not production tested.
59012whmfa
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Typical Performance Characteristics
Network motes typically route through at least two parents the traffic destined for the manager. The supply
current graphs shown below include a parameter called
traffic-weighted descendants. In these graphs the term
traffic-weighted descendants refers to an amount of
activity equivalent to the number of descendants if all of
the network traffic was directed to the mote in question.
Generally the number of descendants of a parent is more,
typically 2x or more, than the number of traffic-weighted
descendants. For example, with reference to Figure 6 mote
P1 has 0.75 traffic-weighted descendants. To obtain this
value notice that mote D1 routes half its packets through
mote P1 adding 0.5 to the traffic-weighted descendant
value; the other half of D1’s traffic is routed through its
other parent, P2. Mote D2 routes half its packets through
mote D1 (the other half going through parent P3), which
we know routes half its packets to mote P1, adding another
0.25 to the traffic-weighted descendant value for a total
traffic-weighted descendant value of 0.75.
as publishing rates increase. All synchronization testing
was performed with the 1-hop mote inside a temperature
chamber. Timing errors due to temperature changes and
temperature differences both between the manager and
this mote and between this mote and its descendents
therefore propagated down through the network. The synchronization of the 3-hop and 5-hop motes to the manager
was then affected by the temperature ramps even though
they were at room temperature. For 2°C/minute testing
the temperature chamber was cycled between –40°C and
85°C at this rate for 24 hours. For 8°C/minute testing, the
temperature chamber was rapidly cycled between 85°C and
45°C for 8 hours, followed by rapid cycling between –5°C
and 45°C for 8 hours, and lastly, rapid cycling between
–40°C and 15°C for 8 hours.
MANAGER
P1
As described in the Application Time Synchronization
section, Eterna provides two mechanisms for applications
to maintain a time base across a network. The synchronization performance plots that follow were generated
using the more precise TIMEn input. Publishing rate is
the rate a mote application sends upstream data. Synchronization improves as the publishing rate increases.
Baseline synchronization performance is provided for a
network operating with a publishing rate of zero. Actual
performance for applications in network will improve
120
10
8
MEDIAN LATENCY (s)
SUPPLY CURRENT (µA)
100
80
60
40
D2
7
Figure 6. Example Network Graph
Supply Current vs Reporting Interval
250
TWD=TRAFFIC WEIGHTED
DESCENDANTS
5 TWD
2 TWD
1 TWD
0 TWD
200
6
5
4
3
2
20
3-HOP
59012whm F06
5 HOPS
4 HOPS
3 HOPS
2 HOPS
1 HOPS
9
2-HOP
D1
Packet Latency vs Reporting Interval
TWD=TRAFFIC-WEIGHTED DESCENDANTS
5 TWD 30s REPORTING
2 TWD 5s REPORTING
2 TWD 30s REPORTING
0 TWD 5s REPORTING
0 TWD 30s REPORTING
P3
SUPPLY CURRENT (µA)
Supply Current vs Temperature
1-HOP
P2
150
100
50
1
0
–40
–20
0
40
60
20
TEMPERATURE (°C)
80
0
0
5
10
20
25
15
REPORTING INTERVAL (s)
59012whm F05a
30
0
0
59012whm F05b
5
10
20
25
15
REPORTING INTERVAL (s)
30
59012whm F05c
Figure 5
59012whmfa
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Typical Performance Characteristics
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, Room Temperature
µ = 0.1
σ = 35.0
30 N = 281490
25
20
15
10
5
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
18
µ = 0.7
16 σ = 63.0
N = 281492
14
12
10
8
6
4
2
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
8
6
4
2
0
–500
µ = 10.1
40 σ = 35.7
N = 92717
35
30
25
20
15
10
5
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
µ = 7.2
σ = 75.9
12 N = 92717
10
8
6
4
2
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
9
µ=6
8 σ = 125.7
N = 92719
7
6
5
4
3
2
1
0
–500
NORMALIZED FREQUENCY OF OCCURENCE (%)
µ = 15.3
40 σ = 39.4
N = 91114
35
30
25
20
15
10
5
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
59012whm G07
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 8°C/Min
14
µ = 10.9
σ = 81.5
12 N = 95165
10
8
6
4
2
0
–500
500
59012whm G06
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 8°C/Min
45
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
59012whm G05
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 8°C/Min
500
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 2°C/Min
14
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
59012whm G03
NORMALIZED FREQUENCY OF OCCURENCE (%)
45
59012whm G04
NORMALIZED FREQUENCY OF OCCURENCE (%)
µ = 0.8
σ = 110.7
10 N = 281493
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 2°C/Min
NORMALIZED FREQUENCY OF OCCURENCE (%)
NORMALIZED FREQUENCY OF OCCURENCE (%)
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 2°C/Min
0
–500
12
59012whm G02
59012whm G01
0
–500
500
NORMALIZED FREQUENCY OF OCCURENCE (%)
0
–500
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, Room Temperature
NORMALIZED FREQUENCY OF OCCURENCE (%)
35
NORMALIZED FREQUENCY OF OCCURENCE (%)
NORMALIZED FREQUENCY OF OCCURENCE (%)
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, Room Temperature
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
8
µ = 10.7
7 σ = 136.8
N = 95167
6
5
4
3
2
1
0
–500
59012whm G08
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
59012whm G09
59012whmfa
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Typical Performance Characteristics
As described in the SmartMesh Network Overview section, devices in network spend the vast majority of their
time inactive in their lowest power state (Doze). On a
synchronous schedule a mote will wake to communicate
with another mote. Regularly occurring sequences which
wake, perform a significant function and return to sleep
are considered atomic. These operations are considered
atomic as the sequence of events can not be separated
into smaller events while performing a useful function.
For example, transmission of a packet over the radio is an
atomic operation. Atomic operations may be characterized
in either charge or energy. In a time slot where a mote
successfully sends a packet, an atomic transmit includes
setup prior to sending the message, sending the message,
receiving the acknowledgment and the post processing
needed as a result of the message being sent. Similarly
in a time slot when a mote successfully receives a packet,
an atomic receive includes setup prior to listening, listen-
ing until the start of the packet transition, receiving the
packet, sending the acknowledge and the post processing
required due to the arrival of the packet.
To ensure reliability each mote in the network is provided
multiple time slots for each packet it nominally will send
and forward. The time slots are assigned to communicate
upstream with at least two different motes. When combined
with frequency hopping this provides temporal, spatial
and spectral redundancy. Given this approach a mote will
often listen for a message that it will never receive, since
the time slot is not being used by the transmitting mote.
It has already successfully transmitted the packet. Since
typically 3 timeslots are scheduled for every 1 packet to
be sent or forwarded, motes will perform more of these
atomic “Idle Listens” than atomic transmit or atomic receive
sequences. Examples of transmit, receive and idle listen
atomic operations are shown in Figure 7.
59012whmfa
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Typical Performance Characteristics
Atomic Operation - Maximum Length Transmit with Acknowledge, 10ms Time Slot (55.9µC Total Charge at 3.6V)
25
80
70
20
POWER UP
Tx PREP
DOZE
POST MESSAGE
PROCESSING
DOZE
60
50
10
40
30
5
CURRENT
CHARGE (µC)
CURRENT (mA)
15
Rx ACKNOWLEDGE
PACKET TRANSMISSION
20
0
10
CHARGE
–5
–2000
0
2000
4000
6000
8000
0
12000
10000
TIME (µs)
59012 F07a
Atomic Operation - Maximum Length Receive with Acknowledge, 10ms Time Slot (39.2µC Total Charge at 3.6V)
25
POWER UP
RADIO RECEIVE
DOZE
70
RECEIVE WITH AES
Tx ACKNOWLEDGE
POST
MESSAGE
PROCESSING
10
DOZE
60
50
40
30
5
CURRENT
CHARGE (µC)
CURRENT (mA)
15
GUARD TIME
20
RADIO Rx TURN ON
80
20
0
10
CHARGE
–5
–2000
0
2000
4000
6000
8000
10000
TIME (µs)
0
12000
59012 F07b
Atomic Operation - Idle Listen, 10ms Time Slot (15.1µC Total Charge at 3.6V)
25
DOZE
POWER UP
CURRENT (mA)
15
10
5
IDLE RECEIVE
RADIO Rx SHUT DOWN
20
70
DOZE
60
50
40
30
CURRENT
CHARGE (µC)
RADIO Rx TURN ON
80
20
0
10
CHARGE
–5
–2000
0
2000
4000
6000
8000
TIME (µs)
10000
0
12000
59012 F07c
Figure 7
59012whmfa
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Pin Functions
Pin functions shown in italics are currently not supported in software.
The following table organizes the pins by functional
groups. For those I/O with multiple functions the alternate
functions are shown on the second and third line in their
respective row. The No column provides the pin number.
The second column lists the function. The Type column
NO
POWER SUPPLY
I/O
PULL
1
GND
Power
-
-
Ground Connection
11
GND
Power
-
-
Ground Connection
20
GND
Power
-
-
Ground Connection
30
GND
Power
-
-
Ground Connection
34
GND
Power
-
-
Ground Connection
37
GND
Power
-
-
Ground Connection
42
GND
Power
-
-
Ground Connection
56
GND
Power
-
-
Ground Connection
66
GND
Power
-
-
Ground Connection
55
VSUPPLY
Power
-
-
Power Supply Input to Eterna
TYPE
I/O
PULL
1 (Note 14)
I
I/O
-
Radio Inhibit
General Purpose Digital I/O
NO
RADIO
TYPE
lists the I/O type. The I/O column lists the direction of the
signal relative to Eterna. The Pull column shows which
signals have a fixed passive pull-up or pull-down. The
Description column provides a brief signal description.
DESCRIPTION
DESCRIPTION
64
RADIO_INHIBIT
GPIO15
4
GPIO17
1
I/O
-
General Purpose Digital I/O
5
GPIO18
1
I/O
-
General Purpose Digital I/O
6
GPIO19
1
I/O
-
General Purpose Digital I/O
-
ANTENNA
N/A
N/A
-
Chip antenna (LTP5901) or MMCX Connector (LPT5902)
TYPE
I/O
PULL
NO
ANALOG
DESCRIPTION
7
AI_2
Analog
I
-
Analog Input 2
8
AI_1
Analog
I
-
Analog Input 1
9
AI_3
Analog
I
-
Analog Input 3
10
AI_0
Analog
I
-
Analog Input 0
TYPE
I/O
PULL
1
I
UP
NO
15
RESET
RESETn
NO
JTAG
DESCRIPTION
Reset Input, Active Low
TYPE
I/O
PULL
16
TDI
1
I
UP
JTAG Test Data In
17
TDO
1
O
-
JTAG Test Data Out
18
TMS
1
I
19
TCK
1
I
UP
DESCRIPTION
JTAG Test Mode Select
DOWN JTAG Test Clock
59012whmfa
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Pin Functions
NO
Pin functions shown in italics are currently not supported in software.
GPIOs (Note 15)
TYPE
I/O
PULL
DESCRIPTION
21
DP4 (GPIO23)
1
I/O
-
General Purpose Digital I/O
25
DP3 (GPIO22)
TIMER8_EXT
1
I/O
I
-
General Purpose Digital I/O
External Input to 8-Bit Timer/Counter
26
DP2 (GPIO21)
LPTIMER_EXT
1
I/O
I
-
General Purpose Digital I/O
External Input to Low Power Timer/Counter
28
DP0 (GPIO0)
SPIM_SS_2n
1
I/O
O
-
General Purpose Digital I/O
SPI Master Slave Select 2, Active Low
45
DP1 (GPIO20)
TIMER16_EXT
1
I/O
I
-
General purpose Digital I/O
External input to 16-Bit Timer/Counter
TYPE
I/O
PULL
NO
SPECIAL PURPOSE
27
SLEEPn
46
PWM0
TIMER16_OUT
GPIO16
63
TIMEn
GPIO1
NO
CLI
DESCRIPTION
1 (Note 14)
I
-
Deep Sleep, Active Low
2
O
O
I/O
-
Pulse Width Modulator 0
16-bit Timer/Counter Match Output/PWM Output
General Purpose Digital I/O
1 (Note 14)
I
I/O
-
Time Capture Request, Active Low
General Purpose Digital I/O
TYPE
I/O
PULL
DESCRIPTION
31
UARTC0_TX
2
O
-
CLI UART 0 Transmit
32
UARTC0_RX
1
I
UP
CLI UART 0 Receive
NO
TYPE
I/O
PULL
38
SPIM_MISO
GPIO11
SPI MASTER
1
I
I/O
-
SPI Master (MISO) Master In Slave Out Port
General Purpose Digital I/O
DESCRIPTION
40
SPIM_MOSI
GPIO10
2
O
I/O
-
SPI Master (MOSI) Master Out Slave In Port
General Purpose Digital I/O
41
SPIM_SCK
GPIO9
2
O
I/O
-
SPI Master (SCK) Serial Clock Port
General Purpose Digital I/O
43
SPIM_SS_1n
GPIO13
1
O
I/O
-
SPI Master Slave Select 1, Active Low
General Purpose Digital I/O
44
SPIM_SS_0n
GPIO12
1
O
I/O
-
SPI Master Slave Select 0, Active Low
General Purpose Digital I/O
NO
IPCS SPI/FLASH PROGRAMMING (Note 16)
TYPE
I/O
PULL
33
IPCS_MISO
TIMER 16 OUT
GPIO6
2
O
O
I/O
-
SPI Flash Emulation (MISO) Master In Slave Out Port
16-Bit Timer/Counter Match Output/PWM Output
General Purpose Digital I/O
DESCRIPTION
35
IPCS_MISO
TIMER 16 OUT
GPIO6
1
I
I
I/O
-
SPI Flash Emulation (MOSI) Master Out Slave In Port
External Input to 16-Bit Timer/Counter
General Purpose Digital I/O
36
IPCS_MISO
TIMER 16 OUT
GPIO6
1
I
I
I/O
-
SPI Flash Emulation (SCK) Serial Clock Port
External Input to 8-Bit Timer/Counter
General Purpose Digital I/O
39
IPCS_MISO
TIMER 16 OUT
GPIO6
1
I
I
I/O
-
SPI Flash Emulation Slave Select, Active Low
External Input to Low Power Timer/Counter
General Purpose Digital I/O
51
FLASH_P_ENn
1
I
UP
Flash Program Enable, Active low
59012whmfa
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Pin Functions
Pin functions shown in grey are currently not supported in software.
I2C/1-Wire/SPI Slave
NO
TYPE
I/O
PULL
DESCRIPTION
47
SPIS_MISO
UARTC1_TX
1_WIRE
2
O
O
I/O
-
SPI Slave (MISO) Master In Slave Out Port
CLI UART 1 Transmit
1 Wire Master
48
SPIS_MOSI
UARTC1_RX
GPIO26
1
I
I
I/O
-
SPI Slave (MOSI) Master Out Slave In Port
CLI UART 1 Receive
General Purpose Digital I/O
49
SPIS_SCK
SCL
2
I
I/O
-
SPI Slave (SCK) Serial Clock Port
I2C Serial Clock
50
SPIS_SSn
SDA
2
I
I/O
-
SPI Slave Select, Active Low
I2C Serial Data
NO
API UART
57
UART_RX_RTSn
58
UART_RX_CTSn
59
UART_RX
60
TYPE
I/O
PULL
1 (Note 14)
I
-
UART Receive (RTS) Request to Send, Active Low
DESCRIPTION
1
O
-
UART Receive (CTS) Clear to Send, Active Low
1 (Note 14)
I
-
UART Receive
UART_TX_RTSn
1
O
-
UART Transmit (RTS) Request to Send, Active Low
61
UART_TX_CTSn
1 (Note 14)
I
-
UART Transmit (CTS) Clear to Send, Active Low
62
UART_TX
2
O
-
UART Transmit
Note 14: These inputs are always enabled and must be driven or pulled to
a valid state to avoid leakage.
Note 15: See also pins 33, 35, 36, and 39 for additional GPIO ports.
VSUPPLY: System and I/O power supply. Provides power
to the module. The digital-interface I/O voltages are also
set by this voltage.
ANTENNA: Multiplexed receiver input and transmitter output
pin. The impedance presented to the MMCX connector
should be 50Ω, single-ended with respect to ground.
AI_0, AI_1, AI_2, AI_3: Analog Inputs. These pins are
multiplexed to the analog input chain. The analog input
chain, as shown in Figure 8, is software-configurable
and includes a variable-gain amplifier, an offset-DAC for
adjusting input range, and a 10b ADC. Valid input range
is between 0 to 1.8V.
Note 16: Embedded programming over the IPCS SPI bus is only avaliable
when RESETn is asserted.
ANALOG INPUT
+
3-BIT
VGA
10-BIT ADC
4-BIT DAC
59012whm F08
Figure 8. Analog Input Chain
RESETn: The asynchronous reset signal is internally pulled
up. Resetting Eterna will result in the ARM Cortex M3
rebooting and loss of network connectivity. Use of this
signal for resetting Eterna is not recommended except
during power-on and in-circuit programming.
59012whmfa
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19
LTP5901-WHM/LTP5902-WHM
Pin Functions
RADIO_INHIBIT: RADIO_INHIBIT provide a mechanism for
an external device to temporarily disable radio operaiton.
Failure to observe the timing requirements defined in
the Radio_Inhibit AC Characteristics table, may result
in unreliable netowrk operation. In designs where the
RADIO_INHIBIT function is not needed the input must
either be tied, pulled or actively driven low to avoid excess
leakage.
TMS, TCK, TDI, TDO: JTAG Port Supporting Software
Debug and Boundary Scan.
SLEEPn: The SLEEPn function is not currently supported
in software. The SLEEPn input must either be tied, pulled
or actively driven high to avoid excess leakage.
UART_RX, UART_RX_RTSn, UART_RX_CTSn, UART_TX,
UART_TX_RTSn, UART_TX_CTSn: The API UART interface
includes bi-directional wake up and flow control. Unused
input signals must be driven or pulled to their inactive state.
TIMEn: Strobing the TIMEn input is the most accurate
method to acquire the network time maintained by Eterna.
Eterna latches the network timestamp with sub-microsecond resolution on the rising edge of the TIMEn signal and
produces a packet on the API serial port containing the
timing information.
UARTC0_RX, UARTC0_TX: The CLI UART provides a
mechanism for monitoring, configuration and control of
Eterna during operation. For a complete description of the
supported commands see the SmartMesh WirelessHART
Mote CLI API Guide.
FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,
IPCS_SSn: The In-circuit Programming Control System
(IPCS) bus enables in-circuit programming of Eterna’s flash
memory. IPCS_SCK is a clock and should be terminated
appropriately for the driving source to prevent overshoot
and ringing.
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LTP5901-WHM/LTP5902-WHM
Operation
The LTP5901/LTP5902 is the world’s most energy-efficient
IEEE 802.15.4 compliant platform, enabling battery and
energy harvested applications. With a powerful 32-bit ARM
Cortex™-M3, best-in-class radio, flash, RAM and purposebuilt peripherals, Eterna provides a flexible, scalable and
robust networking solution for applications demanding
minimal energy consumption and data reliability in even
the most challenging RF environments.
Shown in Figure 9, Eterna integrates purpose-built peripherals that excel in both low operating-energy consumption and the ability to rapidly and precisely cycle between
operating and low-power states. Items in the gray shaded
region labeled “Analog Core” correspond to the analog/
RF components.
Supply Monitoring and Reset
Eterna integrates a Power-on reset (PoR) circuit. As the
RESETn input pin is nominally configured with an internal
pull-up resistor, no connection is required. For a graceful
shutdown, the software and the networking layers should
be cleanly halted via API commands prior to assertion
of the RESETn pin. See the SmartMesh WirelessHART
Mote API Guide for details on the disconnect and reset
commands. Eterna includes a soft brown-out monitor that
fully protects the flash from corruption in the event that
power is removed while writing to flash. Integrated flash
supervisory functionality, in conjunction with a fault tolerant
file system, yields a robust non-volatile storage solution.
Precision Timing
Power Supply
Eterna is powered from a single pin, VSUPPLY, which
powers the I/O cells and is also used to generate internal
supplies. Eterna’s two on-chip DC/DC converters minimize
Eterna’s energy consumption while the device is awake. To
conserve power the DC/DC converters are disabled when
the device is in low-power state. Eterna’s power supply
conditioning architecture, including the two integrated DC/
DC converters and three integrated low-dropout regulators, provides excellent rejection of supply noise. Eterna’s
operating supply voltage range is high enough to support
direct connection to lithium-thionyl chloride Li-SOCl2
sources and wide enough to support battery operation
over a broad temperature range.
A major feature of Eterna over competing 802.15.4 product offerings is its low-power dedicated timing hardware
and timing algorithms. This functionality provides timing
precision two to three orders of magnitude better than
any other low-power solution available at the time of
publication. Improved timing accuracy allows motes to
minimize the amount of radio listening time required to
ensure packet reception thereby lowering even further
the power consumed by SmartMesh networks. Eterna’s
patented timing hardware and timing algorithms provide
superior performance over rapid temperature changes,
further differentiating Eterna’s reliability when compared
with other wireless products. In addition, precise timing
enables networks to reduce spectral dead time, increasing
total network throughput.
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21
LTP5901-WHM/LTP5902-WHM
Operation
32kHz
DIGITAL CORE
ANALOG CORE
32kHz, 20MHz
TIMERS
SCHED
VOLTAGE REFERENCE
PRIMARY
DC/DC
CONVERTER
SRAM
72kB
CORE REGULATOR
CLOCK REGULATOR
PMU/
CLOCK
CONTROL
FLASH
512kB
RELAXATION
OSCILLATOR
ANALOG REGULATOR
PA
DC/DC
CONVERTER
PoR
FLASH
CONTROLLER
802.15.4
MOD
AES
CODE
LPF
DAC
PA
802.15.4
FRAMING
DMA
AUTO
MAC
SYSTEM
802.15.4
DEMOD
20MHz
PLL
ADC
LIMITER
BPF
PPF
LNA
AGC
RSSI
IPCS
SPI
SLAVE
CLI
UART
(2 PIN)
API
UART
(6 PIN)
ADC
CTRL
10-BIT
ADC
BAT
LOAD
VGA
PTAT
4-BIT
DAC
59012whm F09
Figure 9. Eterna Block Diagram
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LTP5901-WHM/LTP5902-WHM
Operation
Application Time Synchronization
32.768kHz Crystal
In addition to coordinating timeslots across the network,
which is transparent to the user, Eterna’s timing management is used to support two mechanisms to share network
time. Having an accurate, shared, network-wide time base
enables events to be accurately time stamped or tasks to
be performed in a synchronized fashion across a network.
Eterna will send a time packet through its serial interface
when one of the following occurs:
Once Eterna is powered up and the 32.768kHz crystal
source has begun oscillating, the 32.768kHz crystal remains operational while in the Active state, and is used as
the timing basis when in Doze state. See the State Diagram
section for a description of Eterna’s operational states.
n
Eterna receives an API request to read time
n
The TIMEn signal is asserted
The use of TIMEn has the advantage of being more accurate. The value of the timestamp is captured in hardware
relative to the rising edge of TIMEn. If an API request is
used, due to packet processing, the value of the timestamp
may be captured several milliseconds after receipt of
the packet due to packet processing. See the TIMEn AC
Characteristics section for the time function’s definition
and specifications.
20MHz Crystal
The 20MHz crystal source provides a frequency reference
for the radio, and is automatically enabled and disabled
by Eterna as needed.
Radio
Eterna includes three clock sources: an internal relaxation
oscillator, a low power oscillator designed for a 32.768kHz
crystal, and the radio reference oscillator designed for a
20MHz crystal.
Eterna includes the lowest-power commercially available
2.4GHz IEEE 802.15.4e radio by a substantial margin.
(Please refer to the Radio Specifications section for
power consumption numbers.). Eterna’s integrated power
amplifier is calibrated and temperature-compensated to
consistently provide power at a limit suitable for worldwide
radio certifications. Additionally, Eterna uniquely includes
a hardware-based autonomous MAC that handles precise
sequencing of peripherals, including the transmitter, the
receiver, and Advanced Encryption Standard (AES) peripherals. The hardware-based autonomous Media Access
Controller (MAC) minimizes CPU activity, thereby further
decreasing power consumption.
Relaxation Oscillator
UARTs
Time References
The relaxation oscillator is the primary clock source
for Eterna, providing the clock for the CPU, memory
subsystems, and all peripherals. The internal relaxation
oscillator is dynamically calibrated to 7.3728 MHz. The
internal relaxation oscillator typically starts up in a few
μs, providing an expedient, low-energy method for duty
cycling between active and low power states. Quick start-up
from the doze state, defined in the State Diagram section,
allows Eterna to wake up and receive data over the UART
and SPI interfaces by simply detecting activity on the
appropriate signals.
The principal network interface is through the application
programming interface (API) UART. A command-line
interface (CLI) is also provided for support of test and
debug functions. Both UARTs sense activity continuously,
consuming virtually no power until data is transferred
over the port and then automatically returning to their
lowest power state after the conclusion of a transfer. The
definition for packet encoding on the API UART interface
can be found in the SmartMesh WirelessHART Mote API
Guide and the CLI command definitions can be found in
the SmartMesh WirelessHART Mote CLI Guide.
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23
LTP5901-WHM/LTP5902-WHM
Operation
API UART Protocol
UART_TX_RTSn
The API UART protocol was created with the goal of
supporting a wide range of companion Multipoint Control
Units (MCUs) while reducing power consumption of the
system. The receive half of the API UART protocol includes
two additional signals in addition to UART_RX: UART_RX_
RTSn and UART_RX_CTSn. The transmit half of the API
UART protocol includes two additional signals in addition
to UART_TX: UART_TX_RTSn and UART_TX_CTSn. The
API UART protocol is referred to as Mode 4.
In the Figures accompanying the protocol descriptions,
signals driven by the companion processor are drawn
in black and signals driven by Eterna are drawn in blue.
UART Mode 4
UART Mode 4 incorporates level-sensitive flow control
on the TX channel and requires no flow control on the
RX channel, supporting 115200 baud. The use of levelsensitive flow control signals enables data rates above
9600 baud with the option of using a reduced set of
the flow control signals; however, Mode 4 has specific
limitations. First, the use of the RX flow control signals
(UART_RX_RTSn and UART_RX_CTSn) for Mode 4
are optional provided the use is limited to the industrial
temperature range (–40°C to 85°C); otherwise, the flow
control is mandatory. If RX flow control signals are
not used, UART_RX_RTSn should be tied to VSUPPLY
(inactive) and UART_RX_CTSn should be left unconnected.
Second, unless the companion processor is always ready
to receive a packet, the companion processor must negate
UART_TX_CTSn prior to the end of the current. Failure
to negate UART_TX_CTSn prior to the end of a packet
may result in back to back packets. Third, the companion
processor must wait at least tRX_RTS to RX_CTS between
transmitting packets. See the UART AC Characteristics
section for complete timing specifications. Packets are
HDLC encoded with one stop bit and no parity bit. The
use of the RX flow control signals (UART_RX_RTSn
and UART_RX_CTSn) for Mode 4 are optional. The flow
control signals for the TX channel are shown in Figure 10.
Transfers are initiated by Eterna asserting UART_TX_RTSn.
UART_TX_CTSn
UART_TX
BYTE 0
BYTE 1
59012whm F10
Figure 10. UART Mode 4 Transmit Flow Control
The UART_TX_CTSn signal may be actively driven by the
companion processor when ready to receive a packet
or UART_TX_CTSn may be tied low if the companion
processor is always ready to receive a packet. After
detecting a logic ‘0’ on UART_TX_CTSn Eterna sends the
entire packet. Following the transmission of the final byte
in the packet Eterna negates UART_TX_RTSn and waits for
tTX_INTERPACKET, defined in the UART AC Characteristics
section before asserting UART_TX_RTSn again.
For details on the timing of the UART protocol, see the
UART AC Characteristics section.
CLI UART
The Command Line Interface (CLI) UART port is a two
wire protocol (TX and RX) that operates at a fixed 9600
baud rate with one stop bit and no parity. The CLI UART
interface is intended to support command line instructions
and response activity.
Autonomous MAC
Eterna was designed as a system solution to provide a
reliable, ultra-low power, and secure network. A reliable
network capable of dynamically optimizing operation
over changing environments requires solutions that are
far too complex to completely support through hardware
acceleration alone. As described in the Precision Timing
section, proper time management is essential for optimizing
a solution that is both low power and reliable. To address
these requirements Eterna includes the Autonomous MAC,
which incorporates a co-processor for controlling all of
the time-critical radio operations. The Autonomous MAC
provides two benefits: first, preventing variable software
latency from affecting network timing and second, greatly
59012whmfa
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For more information www.linear.com/LTP5901-WHM or www.linear.com/LTP5902-WHM
LTP5901-WHM/LTP5902-WHM
Operation
reducing system power consumption by allowing the CPU
to remain inactive during the majority of the radio activity.
The Autonomous MAC, provides software-independent
timing control of the radio and radio-related functions,
resulting in superior reliability and exceptionally low power.
Security
Network security is an often overlooked component of a
complete network solution. Proper implementation of security protocols is significant in terms of both engineering
effort and market value in an OEM product. Eterna system
solutions provide a FIPS-197 validated encryption scheme
that includes authentication and encryption at the MAC
and network layers with separate keys for each mote.
This not only yields end-to-end security, but if a mote is
somehow compromised, communication from other motes
is still secure. A mechanism for secure key exchange allows keys to be kept fresh. To prevent physical attacks,
Eterna includes hardware support for electronically locking
devices, thereby preventing access to Eterna’s flash and
RAM memory and thus the keys and code stored therein.
Temperature Sensor
Eterna includes a calibrated temperature sensor on chip.
The temperature readings are available locally through
Eterna’s serial API, in addition to being available via the
network manager. The performance characteristics of
the temperature sensor can be found in the Temperature
Sensor Characteristics section.
Radio Inhibit
The RADIO_INHIBIT input enables an external controller
to temporarily disable the radio software drivers (for
example, to take a sensor reading that is susceptible to
radio interference). When RADIO_INHIBIT is asserted
the software radio drivers will disallow radio operations
including clear channel assessment, packet transmits,
or packet receipts. If the radio is active in the current
timeslot when RADIO_INHIBIT is asserted the radio will be
diabled after the present operation completes. For details
on the timing associated with RADIO_INHIBIT, see the
RADIO_INHIBIT AC Characteristics section.
Software Installation
Devices are supplied with the flash erased, requiring programming as part of the OEMs manufacturing procedure.
The US Department of Commerce places restrictions on
export of systems and software supporting encryption.
All of Linear/Dust product software produced to date
contains encryption and is subject to export regulations
and may be provided only via MyLinear, https://www.
linear.com/mylinear. Customers purchasing SmartMesh
products will receive a certificate containing a registration
key and registration instructions with their order. After
registering with the key, customers will be able to
download SmartMesh software images from MyLinear.
Once registered, customers will receive automated e-mail
notifications as software updates are made available.
Linear Technology offers the DC9010, in circuit programmer for the Eterna based products. While the DC9010, is
provided as a finished product, the design documents are
provided as a reference for customers.
Once software has been loaded, devices can be configured
via either the CLI or API ports. Configuration commands
and settings are defined in SmartMesh WirelessHART Mote
API Guide and SmartMesh WirelessHART Mote CLI Guide.
Flash Data Retention
Eterna contains internal flash (Non-Volatile Memory) to
store calibration results, unique ID, configuration settings
and software images. Flash retention over the operating
temperature range. See Electrical Characteristics and
Absolute Maximum Ratings sections.
Non destructive storage above the operating temperature
range of –40°C to 85°C is possible; although, this may
result in a degradation of retention characteristics.
The degradation in flash retention for temperatures >85°C
can be approximated by calculating the dimensionless
acceleration factor using the following equation:
Ea
1
1
−
•
k TUSE +273 TSTRESS +273
AF = e
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25
LTP5901-WHM/LTP5902-WHM
Operation
Where:
Serial Flash Emulation
AF = acceleration factor
When both RESETn and FLASH_P_ENn are asserted,
Eterna disables normal operation and enters a mode to
emulate the operation of a serial flash. In this mode, its
flash can be programmed.
Ea = activation energy = 0.6eV
k = 8.625 • 10–5eV/°K
TUSE = is the specified temperature retention in °C
TSTRESS = actual storage temperature in °C
Example: Calculate the effect on retention when storing
at a temperature of 105°C.
TSTRESS = 105°C
TUSE = 85°C
AF = 2.8
So the overall retention of the flash would be degraded
by a factor of 2.8, reducing data retention from 20 years
at 85°C to 7.1 years at 105°C.
State Diagram
In order to provide capabilities and flexibility in addition
to ultra low power, Eterna operates in various states, as
shown in Figure 11. State transitions shown in red are
not recommended.
Start Up
Start Up occurs as a result of either crossing the Power-on
reset threshold or asserting RESETn. After the completion
of Power-on reset or the falling edge of an internally
synchronized RESETn, Eterna loads its Fuse Table which,
as described in the previous section, includes setting
I/O direction. In this state, Eterna checks the state of
the FLASH_P_ENn and RESETn and enters the serial
flash emulation mode if both signals are asserted. If the
FLASH_P_ENn pin is not asserted but RESETn is asserted,
Eterna automatically reduces its energy consumption to
a minimum until RESETn is released. Once RESETn is
de-asserted, Eterna goes through a boot sequence, and
then enters the Active state.
Operation
Once Eterna has completed startup, Eterna transitions to
the Operational group of states (active/CPU active, active/
CPU inactive, and Doze). There, Eterna cycles between the
various states, automatically selecting the lowest possible power state while fulfilling the demands of network
operation.
Active State
In the Active State, Eterna’s relaxation oscillator is running
and peripherals are enabled as needed. The ARM Cortex-M3
cycles between CPU-active and CPU-inactive (referred to
in the ARM Cortex-M3 literature as “Sleep Now” mode).
Eterna’s extensive use of DMA and intelligent peripherals
that independently move Eterna between Active State and
Doze State minimizes the time the CPU is active, significantly reducing Eterna’s energy consumption.
Doze State
The Doze State consumes orders of magnitude less current than the Active State and is entered when all of the
peripherals and the CPU are inactive. In the Doze State
Eterna’s full state is retained, timing is maintained, and
Eterna is configured to detect, wake, and rapidly respond
to activity on I/Os (such as UART signals and the TIMEn
pin). In the Doze State the 32.768kHz oscillator and associated timers are active.
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For more information www.linear.com/LTP5901-WHM or www.linear.com/LTP5902-WHM
LTP5901-WHM/LTP5902-WHM
Operation
POWER-ON
RESET
VSUPPLY > PoR
RESETn LOW AND
FLASH_P_ENn LOW
LOAD FUSE
SETTINGS
RESETn LOW AND
FLASH_P_ENn HIGH
SET RESETn HIGH AND
FLASH_P_ENn HIGH
FOR 125µs, THEN
SET RESETn LOW
SERIAL FLASH
EMULATION
RESETn HIGH
AND
FLASH_P_ENn
HIGH
RESET
DEASSERT
RESETn
BOOT
START-UP
ASSERT RESETn
DOZE
ASSERT RESETn
CPU AND
PERIPHERALS
INACTIVE
HW OR PMU EVENT
OPERATION
ASSERT RESETn
CPU
ACTIVE
ACTIVE
CPU
INACTIVE
DEEP SLEEP
LOW POWER SLEEP
COMMAND
INACTIVE
59012whm F11
Figure 11. Eterna State Diagram
59012whmfa
For more information www.linear.com/LTP5901-WHM or www.linear.com/LTP5902-WHM
27
LTP5901-WHM/LTP5902-WHM
Applications Information
Regulatory and Standards Compliance
The RoHS-compliant design features include:
Radio Certification
n
RoHS-compliant solder for solder joints
The LTP5901 and LTP5902 have been certified under a
single modular certification, with the module name of
ETERNA2. Following the regulatory requirements provided in the ETERNA2 User’s Guide enables customers
to ship products in the supported geographies, by simply
completing an unintentional radiator scan of the finished
product(s). The ETERNA2 User’s Guide also provides
the technical information needed to enable customers
to further certify either the modules or products based
upon the modules in geographies that have not or do not
support modular certification.
n
RoHS-compliant base metal alloys
n
RoHS-compliant precious metal plating
Compliance to Restriction of Hazardous Substances
(RoHS)
Restriction of Hazardous Substances 2 (RoHS 2) is a
directive that places maximum concentration limits on
the use of certain hazardous substances in electrical and
electronic equipment. Linear Technology is committed to
meeting the requirements of the European Community
directive 2011/65/EU.
This product has been specifically designed to utilize
RoHS-compliant materials and to eliminate or reduce the
use of restricted materials to comply with 2011/65/EU.
n
RoHS-compliant cable assemblies and connector
choices
n
Lead-free QFN package
n
Halogen-free mold compound
n
RoHS-compliant and 245 °C re-flow compatible
Note: Customers may elect to use certain types of leadfree solder alloys in accordance with the European Community directive 2011/65/EU. Depending on the type of
solder paste chosen, a corresponding process change to
optimize reflow temperatures may be required.
Soldering Information
The LTP5901 and LTP5902 are suitable for both eutectic
PbSn and RoHS-6 reflow. The maximum reflow soldering temperature is 260°C. A more detailed description of
layout recommendations, assembly procedures and design
considerations is included in the LTP5901 and LTP5902
Hardware Integration Guide.
Related Documentation
TITLE
LOCATION
DESCRIPTION
SmartMesh WirelessHART User Guide
http://www.linear.com/docs/41887
The user’s guide provides theory of operation, and details of the
services supported
SmartMesh WirelessHART Mote API Guide http://www.linear.com/docs/41893
Definitions of the applications interface commands available over
the API UART
SmartMesh WirelessHART Mote CLI Guide http://www.linear.com/docs/41892
Definitions of the command line interface commands available
over the CLI UART
LTP5901 and LTP5902 Hardware Integra- http://www.linear.com/docs/41877
tion Guide
Recommended practices for designing with the LTP5901 and
LTP5902
ETERNA2 User’s Guide
The ETERNA2 module user’s guide includes certification
requirements applicable to certified geographies and support
documentation enabling customer certification in additional
geographies for the LTP5901 and LTP5902
http://www.linear.com/docs/42916
59012whmfa
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For more information www.linear.com/LTP5901-WHM or www.linear.com/LTP5902-WHM
LTP5901-WHM/LTP5902-WHM
Package Description
Please refer to http://www.linear.com/product/LTP5901-WHM#packaging for the most recent package drawings.
2.54
.100
1
.039
24
.94
1
.039
1.58 40
1.213 30.80
1.122 28.50
1.102 28
1.063 27
1.031 26.2
0.25
R.010 TYP
42
1.65
1
.039 TYP
.079 2
.039 1
0 0
.039 1
.87 22
.728 18.50
.630 16
.590 15
.551 14
.394 10
.444 11.27
.344 8.73
.236 6
.197 5
.157 4
0 0
.08 2
.08 2
Figure 12. LTP5901 Mechanical Drawing
59012whmfa
For more information www.linear.com/LTP5901-WHM or www.linear.com/LTP5902-WHM
29
LTP5901-WHM/LTP5902-WHM
Package Description
Please refer to http://www.linear.com/product/LTP5902-WHM#packaging for the most recent package drawings.
2.54
.100
4.50
.177
1
.039
24
.94
1
.039
1.40 35.5
1.272 32.30
1.213 30.80
1.122 28.50
1.102 28
1.063 27
1.031 26.20
0.25
R.010 TYP
37.5
1.48
1
.039 TYP
.078 2
.039 1
0 0
.039 1
.87 22
.728 18.5
.630 16
.590 15
.551 14
.394 10
.444 11.27
.344 8.73
.236 6
.197 5
.157 4
.071 1.80
0 0
.078 2
.078 2
Figure 13. LTP5902 Mechanical Drawing
59012whmfa
30
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LTP5901-WHM/LTP5902-WHM
Revision History
REV
DATE
DESCRIPTION
A
11/15
Updated ordering part numbers
PAGE NUMBER
5
Added total inductance, capacitance
8
Added Software Installation section
25
59012whmfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representathat information
the interconnection
of its circuits as described herein will
infringe on existing patent rights.
Fortion
more
www.linear.com/LTP5901-WHM
or not
www.linear.com/LTP5902-WHM
31
LTP5901-WHM/LTP5902-WHM
Typical Application
Mesh Network Thermistor
TADIRAN TL-5903
RT = 5k • AI_0 / (2 • AI_1 – AI_0)
T(°C) = 1 / {A + B [Ln(RT)] + C[Ln(RT)]3} – 273.15
A = 1.032 • 10–3
B = 2.387 • 10–4
C = 1.580 • 10–7
Li-SOCI2
LTP5902-WHM
VSUPPLY
VDDIN
ANTENNA
47µF
ATMEL SAM4L2
0.1µF
PA08 (GPO8)
0.1µF
GND2
VDDIO
4.7µF
GND1
0.1µF
FB
0.1µF
GND
LT6654-2.048
VOUT
VIN
UART_TX
UART_TX_RTSn
UART_TX_CTSn
UART_RX
UART_RX_RTSn
UART_RX_CTSn
22µF
4.7µF
0.1µF
PA04 (AD0)
VDDANA
VDDOUT
VDDCORE
5k
0.1%
10k, 0.2C
OMEGA 4406
1000pF
PA15 (USART1_RXD)
PA17 (EXTINT2)
PA05 (AD1)
PA13 (GP013)
PA16 (USART1_TXD)
PA14 (GPIO14)
PA18 (EXTINT3)
0.1µF
5k
0.1%
5k
0.1%
1000pF
ADVREFP
XOUT32
32.768kHz
GND
XIN32
59012whm TA02
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTP5903IPC-WHR
WirelessHART Embedded Manager
Manages Networks SmartMesh WirelessHart Nodes.
LTC5800-WHM
WirelessHART Mote
Ultralow Power Mote, 72-Lead 10mm × 10mm QFN
LT6654
Precision High Output Drive Low Noise 1.6ppm Peak-to-Peak Noise (0.1Hz to 10Hz, Sink/Source ±10mA, 5ppm/°C Max Drift)
Reference
LTC2379-18
18-Bit,1.6Msps/1Msps/500ksps/
250ksps Serial, Low Power ADC
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC
LTC3388-1/LTC3388-3 20V High Efficiency Nanopower StepDown Regulator
860nA IQ in Sleep, 2.7V to 20V Input, VOUT: 1.2V to 5.0V, Enable and Standby Pins
LTC3588-1
Piezoelectric Energy Generator with
Integrated High Efficiency Buck
Converter
VIN: 2.7V to 20V; VOUT(MIN): Fixed to 1.8V, 2.5V, 3.3V, 3.6V; IQ = 0.95μA; 3mm × 3mm
DFN-10 and MSOP-10E Packages
LTC3108-1
Ultralow Voltage Step-Up Converter
and Power Manager
VIN: 0.02V to 1V; VOUT = 2.5V, 3V, 3.7V, 4.5V Fixed; IQ = 6μA; 3mm × 4mm DFN-12 and
SSOP-16 Packages
LTC3459
Micropower Synchronous Boost
Converter
VIN: 1.5V to 5.5V; VOUT (MAX) = 10V; IQ = 10μA; 2mm × 2mm DFN, 2mm × 3mm DFN or
SOT-23 Package
59012whmfa
32 Linear Technology Corporation
LT 1115 REV A • PRINTED IN USA
1630 McCarthy Blvd., For
Milpitas,
CA 95035-7417
more information
www.linear.com/LTP5901-WHM or www.linear.com/LTP5902-WHM
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTP5901-WHM or www.linear.com/LTP5902-WHM
LINEAR TECHNOLOGY CORPORATION 2014