14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter AD9695 Data Sheet FEATURES APPLICATIONS JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range) SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range) Noise density −153.9 dBFS/Hz (1.59 V p-p input range) −155.6 dBFS/Hz (2.04 V p-p input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 V p-p to 2.04 V p-p (1.59 V p-p typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linerarity Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, WCDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation Oscilloscopes Spectrum analyzers Network analyzers Integrated RF test solutions Radars Electronic support measures, electronic counter measures, and electronic counter-counter measures High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths Hybrid fiber coaxial digital reverse path receivers Wideband digital predistortion FUNCTIONAL BLOCK DIAGRAM ADC CORE VREF ADC CORE BUFFER SPIVDD (1.8V) 14 DIGITAL DOWNCONVERTER DIGITAL DOWNCONVERTER JESD204B LINK AND Tx OUTPUTS SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SYNCINB± PDWN/STBY SYSREF± 4 JESD204B SUBCLASS 1 CONTROL CLOCK DISTRIBUTION FD_A/GPIO_A0 GPIO MUX CLK+ CLK– ÷2 SPI AND CONTROL REGISTERS FD_B/GPIO_B0 AD9695 ÷4 AGND SDIO SCLK CSB DRGND DGND 15660-001 VIN+B VIN–B DRVDD2 (1.8V) 14 SIGNAL MONITOR FAST DETECT DRVDD1 (0.95V) CROSSBAR MUX BUFFER DVDD (0.95V) CROSSBAR MUX VIN+A VIN–A AVDD3 AVDD1_SR (0.95V) (2.5V) AVDD2 (1.8V) PROGRAMMABLE FIR FILTER AVDD1 (0.95V) Figure 1. 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AD9695 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC General Description ........................................................ 42 Applications ....................................................................................... 1 DDC Frequency Translation ..................................................... 45 Functional Block Diagram .............................................................. 1 DDC Decimation Filters ........................................................... 53 Revision History ............................................................................... 3 DDC Gain Stage ......................................................................... 60 General Description ......................................................................... 4 DDC Complex to Real Conversion ......................................... 61 Product Highlights ........................................................................... 4 DDC Mixed Decimation Settings ............................................ 62 Specifications..................................................................................... 5 DDC Example Configurations ................................................. 64 DC Specifications ......................................................................... 5 Signal Monitor ................................................................................ 67 AC Specifications—1300 MSPS.................................................. 6 SPORT Over JESD204B ............................................................ 68 AC Specifications—625 MSPS .................................................... 8 Digital Outputs ............................................................................... 70 Digital Specifications ................................................................... 9 Introduction to the JESD204B Interface ................................. 70 Switching Specifications ............................................................ 10 JESD204B Overview .................................................................. 70 Timing Specifications ................................................................ 11 Functional Overview ................................................................. 71 Absolute Maximum Ratings.......................................................... 13 JESD204B Link Establishment ................................................. 71 Thermal Characteristics ............................................................ 13 Physical Layer (Driver) Outputs .............................................. 73 ESD Caution ................................................................................ 13 Setting Up the AD9695 Digital Interface ................................. 74 Pin Configuration and Function Descriptions ........................... 14 Deterministic Latency.................................................................... 80 Typical Performance Characteristics ........................................... 16 Subclass 0 Operation.................................................................. 80 1300 MSPS ................................................................................... 16 Subclass 1 Operation.................................................................. 80 625 MSPS ..................................................................................... 21 Multichip Synchronization............................................................ 82 Equivalent Circuits ......................................................................... 25 Normal Mode.............................................................................. 82 Theory of Operation ...................................................................... 27 Timestamp Mode ....................................................................... 82 ADC Architecture ...................................................................... 27 SYSREF± Input ........................................................................... 84 Analog Input Considerations.................................................... 27 SYSREF± Setup/Hold Window Monitor ................................. 86 Voltage Reference ....................................................................... 30 Latency ............................................................................................. 88 DC Offset Calibration ................................................................ 30 End to End Total Latency .......................................................... 88 Clock Input Considerations ...................................................... 30 Example Latency Calculations.................................................. 88 Power-Down/Standby Mode..................................................... 33 LMFC Referenced Latency........................................................ 88 Temperature Diode .................................................................... 33 Test Modes ....................................................................................... 90 ADC Overrange and Fast Detect .................................................. 34 ADC Test Modes ........................................................................ 90 ADC Overrange .......................................................................... 34 JESD204B Block Test Modes .................................................... 91 Fast Threshold Detection (FD_A and FD_B) ........................ 34 Serial Port Interface (SPI) .............................................................. 93 ADC Application Modes and JESD204B Tx Converter Mapping ........................................................................................................... 35 Configuration Using the SPI ..................................................... 93 Programmable Finite Impulse Response (FIR) Filters .............. 37 SPI Accessible Features .............................................................. 93 Supported Modes........................................................................ 37 Memory Map .................................................................................. 94 Programming Instructions ........................................................ 39 Reading the Memory Map Register Table............................... 94 Digital Downconverter (DDC) ..................................................... 42 Memory Map Registers ............................................................. 95 DDC I/Q Input Selection .......................................................... 42 Applications Information ............................................................ 133 DDC I/Q Output Selection ....................................................... 42 Power Supply Recommendations........................................... 133 Hardware Interface..................................................................... 93 Rev. 0 | Page 2 of 135 Data Sheet AD9695 Layout GuideLines ................................................................... 134 Ordering Guide .........................................................................135 AVDD1_SR (Pin 57) and AGND_SR (Pin 56 and Pin 60) .... 134 Outline Dimensions ..................................................................... 135 REVISION HISTORY 9/2017—Revision 0: Initial Version Rev. 0 | Page 3 of 135 AD9695 Data Sheet GENERAL DESCRIPTION The AD9695 is a dual, 14-bit, 1300 MSPS/625 MSPS analog-todigital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The −3 dB bandwidth of the ADC input is 2 GHz. The AD9695 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/ output (GPIO) pins, or use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9695 between the DDC modes is selectable via SPI-programmable profiles. In addition to the DDC blocks, the AD9695 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9695 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC. The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins. The AD9695 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI) and or PDWN/STBY pin. The AD9695 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +105°C junction temperature range. This product may be protected by one or more U.S. or international patents. Note that, throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. Rev. 0 | Page 4 of 135 Low power consumption per channel. JESD204B lane rate support up to 16 Gbps. Wide, full power bandwidth supports intermediate frequency (IF) sampling of signals up to 2 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management. Data Sheet AD9695 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS (AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speedgrade), DCS off (AD9695-625 speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade). Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error1 Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Voltage INPUT-REFERRED NOISE ANALOG INPUTS Differential Input Voltage Range Common-Mode Voltage (VCM) Differential Input Resistance Differential Input Capacitance Analog Full-Power Bandwidth POWER SUPPLY AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD1 DRVDD2 SPIVDD2 IAVDD1 IAVDD2 IAVDD3 IAVDD1_SR IDVDD IDRVDD13 IDRVDD2 ISPIVDD POWER CONSUMPTION Total Power Dissipation (Including Output Drivers)4 Power-Down Dissipation Standby5 Min 14 −0.48 −2.9 −2.64 −0.7 −7 1300 MSPS Typ Guaranteed 5 0 ±1 ±0.18 625 MSPS Max Min 14 Typ Max Unit Bits Guaranteed 5 0 +0.25 ±2.22 +2.6 ±0.18 +2.5 +0.8 ±2 +5 Codes % FSR % FSR % FSR LSB LSB ±9 69 ±6 123 ppm/°C ppm/°C 0.5 3.8 0.5 2.7 V LSB rms ±1 +0.48 +2.9 +2.64 0.8 5 −0.25 −2.6 −2.5 −0.8 −5 1.36 1.59 1.41 200 1.75 2 2.04 1.36 1.7 1.41 200 1.75 2 2.04 V p-p V Ω pF GHz 0.93 1.71 2.44 0.93 0.93 0.93 1.71 1.71 0.95 1.8 2.5 0.95 0.95 0.95 1.8 1.8 304 450 55 15 218 146 25 2 0.98 1.89 2.56 0.98 0.98 0.98 1.89 1.89 383 500 61 27 400 229 29 5 0.93 1.71 2.44 0.93 0.93 0.93 1.71 1.71 0.95 1.8 2.5 0.95 0.95 0.95 1.8 1.8 182 267 29 9 103 103 28 2 0.98 1.89 2.56 0.98 0.98 0.98 1.89 1.89 257 292 35 15 293 176 35 5 V V V V V V V V mA mA mA mA mA mA mA mA 1.39 1.6 215 890 2 0.86 0.98 200 740 1.35 W mW mW 1 DC offset calibration on (Register 0x0701, Bit 7 = 1 and Register 0x073B, Bit 7 = 0). The voltage level on the SPIVDD rail and on the DRVDD2 rail must be the same. 3 All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used. 4 Default mode. No DDCs used. 5 Can be controlled by SPI. 2 Rev. 0 | Page 5 of 135 AD9695 Data Sheet AC SPECIFICATIONS—1300 MSPS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 1300 MSPS, DCS on, buffer current settings specified in Table 11, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade). Table 2. Parameter1 ANALOG INPUT FULL SCALE NOISE DENSITY2 SIGNAL-TO-NOISE RATIO (SNR) fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) fIN = 10.3 MHz fIN = 172.3MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz Analog Input Full Scale = 1.36 V p-p Min Typ Max 1.36 −152.6 64.4 64.4 64.3 64.0 63.8 63.2 62.7 62.3 64.3 64.3 64.2 63.9 63.6 63.1 62.6 62.1 10.3 10.3 10.3 10.3 10.2 10.1 10.1 10.0 81 81 80 83 82 80 80 81 Analog Input Full Scale = 1.59 V p-p Min Typ Max 1.59 −153.9 64.5 64.3 10.3 74 Analog Input Full Scale = 2.04 V p-p Min Typ Max 2.04 −155.6 Unit V p-p dBFS/Hz 65.7 65.6 65.6 65.2 64.9 64.2 63.6 63.0 67.5 67.5 67.3 66.6 66.1 65.2 64.5 63.9 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 65.4 65.4 65.3 65.0 64.7 63.8 63.4 62.8 66.1 66.2 65.7 65.5 65.7 62.9 64.2 61.8 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 10.5 10.5 10.5 10.5 10.4 10.3 10.2 10.1 10.6 10.7 10.6 10.5 10.6 10.1 10.3 9.9 Bits Bits Bits Bits dBFS dBFS dBFS dBFS 79 78 77 80 81 76 80 79 73 72 71 72 79 67 78 68 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Rev. 0 | Page 6 of 135 Data Sheet Parameter1 WORST OTHER, EXCLUDING 2ND OR 3RD HARMONIC fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7.0 dBFS fIN1 = 170.8 MHz, fIN2 = 173.8 MHz fIN1 = 343.5 MHz, fIN2 = 346.5 MHz CROSSTALK3 Overrange Condition4 ANALOG INPUT BANDWIDTH, FULL POWER5 AD9695 Analog Input Full Scale = 1.36 V p-p Min Typ Max Analog Input Full Scale = 1.59 V p-p Min Typ Max −96 −95 −98 −95 −96 −90 −91 −90 −94 −96 −99 −95 −93 −89 −90 −90 −84 −83 >95 >95 2 −84 −82 >95 >95 2 1 −85 Analog Input Full Scale = 2.04 V p-p Min Typ Max Unit −101 −95 −98 −92 −91 −86 −84 −77 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS −83 −81 >95 >95 2 dBFS dBFS dB dB GHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured at a low analog input frequcency (10 MHz). 3 Crosstalk is measured at 10 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel. 4 The overrange condition is specified with 3 dB of the full-scale input range. 5 Full power bandwidth is the bandwidth of operation to achieve proper ADC performance. 2 Rev. 0 | Page 7 of 135 AD9695 Data Sheet AC SPECIFICATIONS—625 MSPS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS, DCS off, buffer current setting specified in Table 11, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade). Table 3. Parameter1 ANALOG INPUT FULL SCALE NOISE DENSITY2 SIGNAL-TO-NOISE RATIO (SNR) fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) fIN = 10.3 MHz fIN = 172.3MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz WORST OTHER, EXCLUDING 2ND OR 3RD HARMONIC fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7.0 dBFS fIN1 = 170.8 MHz, fIN2 = 173.8 MHz fIN1 = 343.5 MHz, fIN2 = 346.5 MHz CROSSTALK3 Overrange Condition4 Analog Input Full Scale = 1.36 V p-p Min Typ Max 1.36 −150.5 65.5 65.4 65.4 65.0 64.8 65.5 65.4 65.2 64.9 64.6 10.6 10.6 10.5 10.5 10.4 88 88 79 83 85 Analog Input Full Scale = 1.7 V p-p Min Typ Max 1.7 −152.3 65.5 66.3 10.6 75 Analog Input Full Scale = 2.04 V p-p Min Typ Max 2.04 −153.5 Unit V p-p dBFS/Hz 67.3 67.2 67.1 66.6 66.3 68.6 68.5 68.3 67.7 67.3 dBFS dBFS dBFS dBFS dBFS 66.9 67.0 67.0 65.4 65.0 67.2 68.0 67.9 67.0 67.0 dBFS dBFS dBFS dBFS dBFS 10.8 10.8 10.8 10.6 10.5 10.9 11.0 11.0 10.8 10.8 Bits Bits Bits Bits Bits 79 89 80 84 83 74 78 77 77 82 dBFS dBFS dBFS dBFS dBFS −99 −99 −98 −100 −100 dBFS dBFS dBFS dBFS dBFS −83 −84 >95 >95 dBFS dBFS dB dB −100 −101 −100 −98 −100 −101 −97 −102 −98 −98 −88 −89 >95 >95 −88 −89 >95 >95 Rev. 0 | Page 8 of 135 −90 Data Sheet Parameter1 ANALOG INPUT BANDWIDTH, FULL POWER5 AD9695 Analog Input Full Scale = 1.36 V p-p Min Typ Max 2 Analog Input Full Scale = 1.7 V p-p Min Typ Max 2 Analog Input Full Scale = 2.04 V p-p Min Typ Max 2 Unit GHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured at a low analog input frequcency (10 MHz). Crosstalk is measured at 10 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel. 4 The overrange condition is specified with 3 dB of the full-scale input range. 5 Full power bandwidth is the bandwidth of operation to achieve proper ADC performance. 2 3 DIGITAL SPECIFICATIONS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS (AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speedgrade), DCS off (AD9695-625 speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade). Table 4. Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) SYSREF INPUTS (SYSREF+, SYSREF−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0, FD_B/GPIO_B0) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUT (SDIO, FD_A, FD_B) Logic Compliance Logic 1 Voltage (IOH = 4 mA) Logic 0 Voltage (IOL = 4 mA) SYNCIN INPUTS (SYNCINB−, SYNCINB+) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Single-Ended per Pin) DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3) Logic Compliance Differential Output Voltage Differential Termination Impedance Min 400 Typ LVDS/LVPECL 800 0.65 32 Max Unit 1600 mV p-p V kΩ pF 0.9 400 LVDS/LVPECL 800 0.65 18 1 1800 2 mV p-p V kΩ pF CMOS 0.75 × SPIVDD 0 0.35 × SPIVDD 30 V V kΩ CMOS SPIVDD − 0.45 0 400 0.45 LVDS/LVPECL/CMOS 800 1800 0.65 2 18 1 V V mV p-p V kΩ pF SST 360 80 Rev. 0 | Page 9 of 135 520 100 770 1200 mV p-p Ω AD9695 Data Sheet SWITCHING SPECIFICATIONS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS (AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speedgrade), DCS off (AD9695-625 speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade). Table 5. Parameter CLOCK Clock Rate (at CLK+/CLK− Pins) Maximum Sample Rate1 Minimum Sample Rate2 Clock Pulse Width3 High Low OUTPUT PARAMETERS Unit Interval (UI)4 Rise Time (tR) (20% to 80% into 100 Ω Load) Fall Time (tF) (20% to 80% into 100 Ω Load) Phase-Locked Loop (PLL) Lock Time Data Rate per Channel (NRZ)5 LATENCY6 Pipeline Latency Fast Detect Latency Wake-Up Time7 Standby Power-Down APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out of Range Recovery Time Min 1300 MSPS Typ Max 0.24 1400 240 1.28 156.25 156.25 62.5 1.6875 Min 625 MSPS Typ Max 0.24 640 240 1.28 156.25 156.25 76.9 28 28 5 13 62.5 16 1.6875 Unit GHz MSPS MSPS ps ps 160 28 28 5 6.25 16 ps ps ps ms Gbps 56 26 56 26 Clock cycles Clock cycles 400 15 400 15 us ms 192 43 1 159.5 49.2 1 ps fs rms Clock cycles 1 The maximum sample rate is the clock rate after the divider. The minimum sample rate operates at 240 MSPS. See SPI Register 0x011A to reduce the threshold of the clock detect circuit. 3 Clock duty stabilizer (DCS) on. See SPI Register 0x011C and 0x011E to enable DCS. 4 Baud rate = 1/UI. A subset of this range can be supported. 5 Default L = 4. This number can change based on the sample rate and decimation ratio. 6 No DDCs used. L = 4, M = 2, and F = 1. 7 Wake-up time is defined as the time required to return to normal operation from power-down mode. 2 Rev. 0 | Page 10 of 135 Data Sheet AD9695 TIMING SPECIFICATIONS Table 6. Parameter CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tACCESS Test Conditions/Comments See Figure 3 Device clock to SYSREF+ setup time Device clock to SYSREF+ hold time See Figure 4 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Maximum time delay between falling edge of SCLK and output data valid for a read operation Time required for the SDIO pin to switch from an output to an input relative to the CSB rising edge (not shown in Figure 4) tDIS_SDIO Min Typ 10 N – 56 N+1 N – 54 SAMPLE N N – 53 N–1 CLK– CLK+ CLK– SERDOUT0– SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ A B C D E F G H I J CONVERTER0 SAMPLE N – 56 MSB A B C D E F G H I J CONVERTER0 SAMPLE N – 56 LSB A B C D E F G H I J CONVERTER0 SAMPLE N – 55 MSB A B C D E F G H I J CONVERTER0 SAMPLE N – 55 LSB SAMPLE N – 56 AND N – 55 ENCODED INTO ONE 8-BIT/10-BIT SYMBOL 15660-002 CLK+ SERDOUT0+ Figure 2. Data Output Timing Diagram CLK– CLK+ tSU_SR tH_SR 15660-003 SYSREF– SYSREF+ Figure 3. SYSREF± Setup and Hold Timing Diagram Rev. 0 | Page 11 of 135 ps ps 6 ns ns ns ns ns ns ns ns 10 ns APERTURE DELAY N – 55 Unit −70 120 4 2 40 2 2 10 10 Timing Diagrams ANALOG INPUT SIGNAL Max AD9695 Data Sheet tDS tS tHIGH tCLK tDH SDIO DON’T CARE DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 Figure 4. SPI Timing Diagram Rev. 0 | Page 12 of 135 D5 D4 D3 D2 D1 D0 DON’T CARE 15660-004 DON’T CARE tH tLOW CSB SCLK tACCESS Data Sheet AD9695 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 7. Parameter Electrical AVDD1 to AGND AVDD1_SR to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD1 to DRGND DRVDD2 to DRGND SPIVDD to DGND AGND to DRGND AGND to DGND DGND to DRGND VIN±x to AGND CLK± to AGND SCLK, SDIO, CSB to DGND PDWN/STBY to DGND SYSREF± to AGND SYNCINB± to DRGND Junction Temperature Range (TJ) Storage Temperature Range, Ambient (TA) Rating 1.05 V 1.05 V 2.00 V 2.70 V 1.05 V 1.05 V 2.00 V 2.00 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V AGND − 0.3 V to AVDD3 + 0.3 V AGND − 0.3 V to AVDD1 + 0.3 V DGND − 0.3 V to SPIVDD + 0.3 V DGND − 0.3 V to SPIVDD + 0.3 V 2.5 V 2.5 V −40°C to +125°C −65°C to +150°C Typical θJA, θJB, and θJC are specified vs. the number of printed circuit board (PCB) layers in different airflow velocities (in m/sec). Airflow increases heat dissipation effectively reducing θJA and θJB. In addition, metal in direct contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes, reduces θJA. Thermal performance for actual applications requires careful inspection of the conditions in an application. The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 7. Table 8. Thermal Resistance Package Type CP-64-17 Airflow Velocity (m/sec) 0 1.0 2.5 θJA1, 2 θJC_BOT1, 3 22.5 1.7 17.9 16.8 1 θJC_TOP1, 3 7.6 θJB1, 4 4.3 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 2 3 ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 13 of 135 θJT1,2 0.2 Unit °C/W °C/W °C/W AD9695 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD1 AVDD2 AVDD2 AVDD1 AGND_SR SYSREF– SYSREF+ AVDD1_SR AGND_SR AVDD1 CLK– CLK+ AVDD1 AVDD2 AVDD2 AVDD1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD9695 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD1 AVDD1 AVDD2 AVDD3 VIN–B VIN+B AVDD3 AVDD2 AVDD2 AVDD2 SPIVDD CSB SCLK SDIO DVDD DGND NOTES 1. ANALOG GROUND. CONNECT THE EXPOSED PAD TO THE ANALOG GROUND PLANE. 15660-005 FD_A/GPIO_A0 DRGND DRVDD1 SYNCINB– SYNCINB+ SERDOUT0– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ DRVDD1 DRGND FD_B/GPIO_B0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD1 AVDD1 AVDD2 AVDD3 VIN–A VIN+A AVDD3 AVDD2 AVDD2 AVDD2 DRVDD2 VREF SPIVDD PDWN/STBY DVDD DGND Figure 5. Pin Configuration (Top View) Table 9. Pin Function Descriptions Pin No. 1, 2, 47 to 49, 52, 55, 61, 64 3, 8 to 10, 39 to 41, 46, 50, 51, 62, 63 4, 7, 42, 45 5, 6 11 12 Mnemonic AVDD1 Type Power supply Description Analog Power Supply (0.95 V Nominal). AVDD2 Power supply Analog Power Supply (1.8 V Nominal). AVDD3 VIN−A, VIN+A DRVDD2 VREF Power supply Analog input Power supply Input/output 13, 38 14 SPIVDD PDWN/STBY Power supply Digital control input 15, 34 16, 33 DVDD DGND 17 FD_A/GPIO_A0 Power supply Ground power supply CMOS output Analog Power Supply (2.5 V Nominal). ADC A Analog Input Complement/True. Digital Driver Power Supply (1.8 V Nominal). Reference Voltage Input (0.50 V)/Do Not Connect. This pin is configurable through the SPI as a no connect pin or as an input. Do not connect this pin if using the internal reference. This pin requires a 0.50 V reference voltage input if using an external voltage reference source. Digital Power Supply for SPI (1.8 V Nominal). Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby. Digital Power Supply (0.95 V Nominal). Digital Control Ground Supply. These pins connect to the digital ground plane. 32 18, 31 FD_B/GPIO_B0 DRGND 19, 30 20 21 22, 23 DRVDD1 SYNCINB− SYNCINB+ SERDOUT0−, SERDOUT0+ SERDOUT1−, SERDOUT1+ 24, 25 CMOS output Ground power supply Power supply Digital input Digital input Data output Fast Detect Output for Channel A (FD_A). General-purpose input/output (GPIO) Pin A0 (GPIO_A0). Fast Detect Output for Channel B (FD_B). GPIO Pin B0 (GPIO_B0). Digital Driver Ground Supply. This pin connects to the digital driver ground plane. Digital Driver Power Supply (0.95 V Nominal). Active Low JESD204B LVDS/CMOS Sync Input True. Active Low JESD204B LVDS Sync Input Complement. Lane 0 Output Data Complement/True. Data output Lane 1 Output Data Complement/True. Rev. 0 | Page 14 of 135 Data Sheet Pin No. 26, 27 AD9695 35 Mnemonic SERDOUT2− SERDOUT2+ SERDOUT3−, SERDOUT3+ SDIO 36 37 43, 44 53, 54 56, 60 SCLK CSB VIN+B, VIN−B CLK+, CLK− AGND_SR 57 58, 59 AVDD1_SR SYSREF+, SYSREF− EPAD 28, 29 Type Data output Description Lane 2 Output Data Complement/True. Data output Lane 3 Output Data Complement/True. Digital control input/output Digital control input Digital control input Analog input Analog input Ground power supply Power supply Digital input SPI Serial Data Input/Output. Ground power supply SPI Serial Clock. SPI Chip Select (Active Low). ADC B Analog Input True/Complement. Clock Input True/Complement. Ground Reference for SYSREF±. Analog Power Supply for SYSREF± (0.95 V Nominal). Active High JESD204B LVDS System Reference Input Complement/True. Analog Ground. Connect the exposed pad to the analog ground plane. Rev. 0 | Page 15 of 135 AD9695 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1300 MSPS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 625 MSPS (AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speedgrade), DCS off (AD9695-625 speed grade), buffer current setting specified in Table 11, dc offset calibration enabled, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade). 10 AIN = 10.3MHz SNR = 65.7dBFS SFDR = 79.0dBFS BUFFER CURRENT = 300µA –30 –30 AMPLITUDE (dBFS) –50 –70 –90 –70 –90 200 400 600 FREQUENCY (MHz) –130 15660-305 0 0 AIN = 172.3MHz SNR = 65.6dBFS SFDR = 78.0dBFS BUFFER CURRENT = 300µA AIN = 1002.3MHz SNR = 64.9dBFS SFDR = 81.0dBFS BUFFER CURRENT = 300µA –10 –30 AMPLITUDE (dBFS) –50 –70 –90 –110 –50 –70 –90 0 200 400 600 FREQUENCY (MHz) 15660-306 –110 –130 0 200 400 600 FREQUENCY (MHz) Figure 7. Single-Tone FFT with Analog Input Frequency (fIN) = 172.3 MHz Figure 10. Single-Tone FFT with fIN = 1002.3 MHz AIN = 342.3MHz SNR = 65.6dBFS SFDR = 77.0dBFS BUFFER CURRENT = 300µA –10 AMPLITUDE (dBFS) –30 –50 –70 –90 –110 –50 –70 –90 –110 0 200 400 FREQUENCY (MHz) 600 15660-307 AMPLITUDE (dBFS) AIN = 1402.3MHz SNR = 64.2dBFS SFDR = 76.0dBFS BUFFER CURRENT = 300µA –10 –30 –130 15660-309 AMPLITUDE (dBFS) 600 Figure 9. Single-Tone FFT with fIN =752.3 MHz –30 –130 400 FREQUENCY (MHz) Figure 6. Single-Tone FFT with Analog Input Frequency (fIN) = 10.3 MHz –10 200 15660-308 –110 –110 –130 –50 –130 0 200 400 600 FREQUENCY (MHz) Figure 8. Single-Tone FFT with fIN = 342.3 MHz Figure 11. Single-Tone FFT with fIN = 1402.3 MHz Rev. 0 | Page 16 of 135 15660-310 AMPLITUDE (dBFS) –10 AIN = 752.3MHz SNR = 65.2dBFS SFDR = 80.0dBFS BUFFER CURRENT = 300µA –10 Data Sheet AD9695 67 AIN = 1702.3MHz SNR = 63.6dBFS SFDR = 80.0dBFS BUFFER CURRENT = 300µA –10 TJ = +105°C ROOM TJ = –40°C 66 65 –70 64 –90 63 –110 62 –130 0 200 600 400 FREQUENCY (MHz) 61 Figure 12. Single-Tone FFT with fIN = 1702.3 MHz 500 1000 1500 2000 ANALOG INPUT FREQUENCY (MHz) Figure 15. SNR vs. Analog Input Frequency (fIN) at Minimum, Room, and Maximum Temperatures 90 AIN = 1980.3MHz SNR = 63.0dBFS SFDR = 79.0dBFS BUFFER CURRENT = 300µA –10 0 15660-314 SNR (dBFS) –50 15660-311 AMPLITUDE (dBFS) –30 TJ = +105°C ROOM TJ = –40°C 85 80 –70 75 –90 70 –110 65 –130 200 0 400 600 FREQUENCY (MHz) 60 0 500 1000 2000 Figure 16. SFDR vs. Analog Input Frequency (fIN) at Minimum, Room, and Maximum Temperatures Figure 13. Single-Tone FFT with fIN = 1980.3 MHz 85 fIN1 = 170.8MHz fIN2 = 173.8MHz IMD = –84dBFS BUFFER CURRENT = 300µA –10 SNR SFDR AMPLITUDE (dBFS) 80 75 70 –60 –110 60 500 700 900 1100 1300 SAMPLE RATE (MHz) –160 0 200 400 600 FREQUENCY (MHz) Figure 17. Two-Tone FFT; fIN1 = 170.8 MHz, fIN2 = 173.8 MHz Figure 14. SNR/SFDR vs. Sample Rate, fIN =172.3 MHz Rev. 0 | Page 17 of 135 15660-316 65 15660-313 SNR/SFDR (dBFS) 1500 ANALOG INPUT FREQUENCY (MHz) 15660-315 SDFR (dBFS) –50 15660-312 AMPLITUDE (dBFS) –30 AD9695 0 Data Sheet 85 fIN1 = 343.5MHz fIN2 = 346.5MHz IMD = –82dBFS BUFFER CURRENT = 300µA SNR SFDR 80 SNR/SFDR (dBFS) AMPLITUDE (dBFS) –40 –90 75 70 0 200 400 60 –40 15660-317 –140 600 FREQUENCY (MHz) 10 60 110 JUNCTION TEMPERATURE (°C) 15660-320 65 Figure 21. SNR/SFDR vs. Junction Temperature, fIN = 172.3 MHz Figure 18. Two-Tone FFT; fIN1 = 343.5 MHz, fIN2 = 346.5 MHz 2 120 100 1 0 60 INL (LSB) SNR/SFDR (dB) 80 40 20 –1 –2 0 SFDR (dBFS) SNRFS SNR (dBc) SFDR (dBc) –60 –40 –20 0 ANALOG INPUT AMPLITUDE (dBFS) –4 0 15000 Figure 22. INL, fIN = 10.3 MHz 10 0.3 SFDR (dBFS) SFDR (dBc) IMD3 (dBc) IMD3 (dBFS) –10 0.2 0.1 DNL (LSB) –30 –50 –70 0 –0.1 –90 –0.2 –110 –0.3 –75 –55 –35 –15 ANALOG INPUT AMPLITUDE (dB) 15660-319 SFDR/IMD3 (dB) 10000 OUTPUT CODE Figure 19. SNR/SFDR vs. Analog Input Amplitude, fIN = 172.3 MHz –130 –95 5000 15660-321 –80 –0.4 0 5000 10000 OUTPUT CODE Figure 23. DNL, fIN = 10.3 MHz Figure 20. SFDR/IMD3 vs. Analog Input Amplitude, fIN = 172.3 MHz Rev. 0 | Page 18 of 135 15000 15660-322 –40 –100 –3 15660-318 –20 Data Sheet AD9695 1.8 NUMBER OF HITS 15000 10000 0 –16 –13 –10 –7 –4 –1 2 5 8 11 14 16 CODE 1.4 1.2 500 15660-323 5000 1.6 700 900 15660-326 POWER CONSUMPTION (W) 20000 1300 1100 SAMPLE RATE (MHz) Figure 27. Total Power Dissipation vs. Sample Rate (fS) Figure 24. Input Referred Noise Histogram 66 0 –2 65 –8 –10 64 CLOCK AMPLITUDE 400mV 600mV 800mV 1000mV 1200mV 1400mV 1600mV 1800mV 2000mV 63 –12 62 –14 0 1000 2000 3000 4000 AIN FREQUENCY (MHz) 61 15660-019 –16 Figure 25. Full Power Bandwidth 500 1000 1500 2000 ANALOG INPUT FREQUENCY (MHz) Figure 28. SNR vs. Analog Input Frequency at Different Clock Amplitudes 2.0 86 84 1.8 SFDR (dBFS) 82 1.6 80 78 76 BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT 74 1.2 –40 10 60 110 JUNCTION TEMPERATURE (°C) Figure 26. Total Power Dissipation vs. Junction Temperature 72 0 500 = 460µA = 400µA = 360µA = 300µA 1000 1500 ANALOG INPUT FREQUENCY (MHz) 2000 15660-328 1.4 15660-325 TOTAL POWER CONSUMPTION (W) 0 15660-327 –6 SNR (dBFS) AMPLITUDE (dBFS) –4 Figure 29. SFDR vs. Analog Input Frequency with Different Buffer Current Settings Rev. 0 | Page 19 of 135 AD9695 Data Sheet 90 68 67 80 IAVDD3 (mA) 65 64 63 60 0 500 1000 1500 2000 ANALOG INPUT FREQUENCY (MHz) 15660-329 2.04V 1.81V 1.59V 1.36V 62 61 Figure 30. SNR vs. Analog Input Frequency with Different Analog Input FullScale Values 90 85 SFDR (dBFS) 80 75 70 0 500 1000 1500 ANALOG INPUT FREQUENCY (MHz) 2000 15660-330 2.04V 1.81V 1.59V 1.36V 65 60 70 Figure 31. SFDR vs. Analog Input Frequency with Different Analog Input FullScale Values Rev. 0 | Page 20 of 135 50 300 350 400 450 BUFFER CURRENT SETTING (µA) Figure 32. IAVDD3 vs. Buffer Control 1 Setting in Register 0x1A4C 15660-331 SNR (dBFS) 66 Data Sheet AD9695 625 MSPS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 625 MSPS (AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speedgrade), DCS off (AD9695-625 speed grade), buffer current setting specified in Table 11, and dc offset calibration enabled, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade). 0 0 AIN = –1dBFS SNR = 67.2dBFS SFDR = 89dBFS BUFFER CURRENT = 160µA –20 AMPLITUDE (dBFS) –40 –60 –80 –80 –100 0 100 200 300 FREQUENCY (MHz) –120 15660-006 –120 –60 0 250 300 80 –40 SNR/SFDR (dBFS) –60 –80 60 40 20 –100 100 200 300 FREQUENCY (MHz) 15660-007 0 0 250 SNR SFDR 350 450 550 650 750 850 SAMPLE RATE (MSPS) Figure 34. Single-Tone FFT with fIN = 340 MHz 15660-010 AMPLITUDE (dBFS) 200 100 AIN = –1dBFS SNR = 67.1dBFS SFDR = 80dBFS BUFFER CURRENT = 160µA –20 Figure 37. SNR/SFDR vs. Sample Rate, fIN =172.3 MHz 0 100 AIN = –1dBFS SNR = 66.6dBFS SFDR = 84dBFS BUFFER CURRENT = 300µA –20 90 SNR/SFDR (dBFS) –40 –60 –80 –100 80 70 60 SFDR (TJ = –40°C) SNR (TJ = –40°C) SFDR (ROOM) SNR (ROOM) SFDR (TJ = +105°C) SNR (TJ = +105°C) 50 0 100 200 FREQUENCY (MHz) Figure 35. Single-Tone FFT with fIN =750 MHz 300 40 15660-008 AMPLITUDE (dBFS) 150 Figure 36. Single-Tone FFT with fIN = 1000 MHz 0 –120 100 FREQUENCY (MHz) Figure 33. Single-Tone FFT with Analog Input Frequency (fIN) = 172.3 MHz –120 50 15660-009 –100 –40 0 250 500 750 ANALOG INPUT FREQUENCY (MHz) 1000 15660-011 AMPLITUDE (dBFS) –20 AIN = –1dBFS SNR = 66.3dBFS SFDR = 83dBFS BUFFER CURRENT = 300µA Figure 38. SNR/SFDR vs. Analog Input Frequency (fIN) at Minimum, Room, and Maximum Temperatures Rev. 0 | Page 21 of 135 AD9695 Data Sheet 0 100 AIN1 AND A IN2 = –7dBFS SFDR = 88dBFS BUFFER CURRENT = 160µA 90 –60 –80 80 70 60 –100 50 –120 40 –40 0 100 200 300 FREQUENCY (MHz) SNR SFDR 10 15660-015 SNR/SFDR (dBFS) –40 15660-012 AMPLITUDE (dBFS) –20 60 JUNCTION TEMPERATURE (°C) Figure 39. Two-Tone FFT; fIN1 = 170.8 MHz, fIN2 = 173.8 MHz Figure 42. SNR/SFDR vs. Junction Temperature, fIN = 172.3 MHz 0 4 AIN1 AND A IN2 = –7dBFS SFDR = 89dBFS BUFFER CURRENT = 160µA –20 3 1 INL (LSB) AMPLITUDE (dBFS) 2 –40 –60 0 –1 –80 –2 –100 100 200 300 FREQUENCY (MHz) –4 0 5000 10000 15000 OUTPUT CODE Figure 40. Two-Tone FFT; fIN1 = 343.5 MHz, fIN2 = 346.5 MHz 15660-016 0 15660-013 –120 –3 Figure 43. INL, fIN = 10.3 MHz 120 0.25 0.20 100 0.15 0.10 DNL (LSB) 60 40 0 –0.05 –0.15 20 –0.20 SFDR (dBFS) SFDR (dBc) –80 –60 –40 –20 0 ANALOG INPUT AMPLITUDE (dBFS) Figure 41. SNR/SFDR vs. Analog Input Amplitude, fIN = 172.3 MHz –0.25 0 5000 10000 OUTPUT CODE Figure 44. DNL, fIN = 10.3 MHz Rev. 0 | Page 22 of 135 15000 15660-017 0 –100 0.05 –0.10 15660-014 SFDR (dB) 80 Data Sheet AD9695 6000 1.4 4000 3000 2000 1000 N + 15 0.8 0.6 0.4 0.2 650 850 750 68 67 –4 66 –6 –8 65 CLOCK AMPLITUDE 400mV p-p 600mV p-p 800mV p-p 1000mV p-p 1200mV p-p 1400mV p-p 1600mV p-p 1800mV p-p 2000mV p-p 2200mV p-p 64 –10 63 –12 62 –14 1000 2000 3000 4000 AIN FREQUENCY (MHz) 15660-019 61 0 0 200 400 600 800 1000 1200 ANALOG INPUT FREQUENCY (MHz) 15660-022 –2 SNR (dBFS) Figure 49. SNR vs. Analog Input Frequency at Different Clock Amplitudes Figure 46. Full Power Bandwidth 1.4 100 1.2 90 1.0 SFDR (dBFS) 80 0.8 0.6 70 60 0.4 10 60 110 JUNCTION TEMPERATURE (°C) Figure 47. Total Power Dissipation vs. Junction Temperature 40 15660-020 0 –40 BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT 50 0.2 0 200 400 600 800 = 160µA = 200µA = 240µA = 300µA 1000 ANALOG INPUT FREQUENCY (MHz) 1200 15660-023 AMPLITUDE (dBFS) 550 Figure 48. Total Power Dissipation vs. Sample Rate (fS) 0 TOTAL POWER DISSIPATION (W) 450 SAMPLE RATE (MSPS) Figure 45. Input Referred Noise Histogram –16 350 15660-018 N + 12 N+9 N+6 N+3 0 N–3 N–6 N–9 N – 12 N – 15 1.0 0 250 0 CODE 1.2 15660-021 TOTAL POWER DISSIPATION (W) NUMBER OF HITS 5000 Figure 50. SFDR vs. Analog Input Frequency with Different Buffer Current Settings (AIN < 1250 MHz) Rev. 0 | Page 23 of 135 AD9695 Data Sheet 80 69 BUFFER CURRENT = 400µA BUFFER CURRENT = 300µA BUFFER CURRENT = 240µA 68 67 75 SNR (dBFS) SFDR (dBFS) 66 70 65 64 63 65 62 1450 1650 60 650 15660-348 60 1250 1850 ANALOG INPUT FREQUENCY (MHz) Figure 51. SFDR vs. Analog Input Frequency with Different Buffer Current Settings (AIN > 1250 MHz), Register 0x1B03 = 0x02, Register 0x1B08 = 0xC1, Register 0x1B10 = 0x1C 750 850 950 1050 1150 1250 ANALOG INPUT FREQUENCY (MHz) 15660-026 INPUT FULL-SCALE = 1.36V p-p INPUT FULL-SCALE = 1.7V p-p INPUT FULL-SCALE = 2.04V p-p 61 Figure 54. SNR vs. Analog Input Frequency with Different Analog Input Full-Scale Values (AIN > 650 MHz) 85 70 69 80 68 75 SFDR (dBFS) 66 65 64 63 65 60 62 INPUT FULL-SCALE = 1.36V p-p INPUT FULL-SCALE = 1.7V p-p INPUT FULL-SCALE = 2.04V p-p 0 200 400 600 ANALOG INPUT FREQUENCY (MHz) INPUT FULL-SCALE = 1.36V p-p INPUT FULL-SCALE = 1.7V p-p INPUT FULL-SCALE = 2.04V p-p 55 50 650 15660-024 61 60 70 Figure 52. SNR vs. Analog Input Frequency with Different Analog Input Full-Scale Values (AIN < 650 MHz) 750 850 950 1050 1150 1250 ANALOG INPUT FREQUENCY (MHz) 15660-027 SNR (dBFS) 67 Figure 55. SFDR vs. Analog Input Frequency with Different Analog Input Full-Scale Values (AIN > 650 MHz) 80 100 95 70 90 60 IAVDD3 (mA) 80 75 70 40 65 60 30 0 200 400 ANALOG INPUT FREQUENCY (MHz) 600 15660-025 INPUT FULL-SCALE = 1.36V p-p INPUT FULL-SCALE = 1.7V p-p INPUT FULL-SCALE = 2.04V p-p 55 50 50 Figure 53. SFDR vs. Analog Input Frequency with Different Analog Input Full-Scale Values (AIN < 650 MHz) Rev. 0 | Page 24 of 135 20 160 210 260 310 360 BUFFER CURRENT (µA) Figure 56. IAVDD3 vs. Buffer Control 1 Setting in Register 0x1A4C 15660-028 SFDR (dBFS) 85 Data Sheet AD9695 EQUIVALENT CIRCUITS AVDD3 AVDD3 VIN+x 3.5pF AVDD3 400Ω EMPHASIS/SWING CONTROL (SPI) VCM BUFFER 10pF AVDD3 DRVDD1 AVDD3 100Ω DATA+ SERDOUTx+ x = 0, 1, 2, 3 VIN–x DRGND OUTPUT DRIVER AIN CONTROL (SPI) DATA– SERDOUTx– x = 0, 1, 2, 3 15660-029 3.5pF DRGND Figure 57. Analog Inputs Figure 60. Digital Outputs DRVDD1 AVDD1 CLK+ DRVDD1 15660-032 100Ω 25Ω DRGND 2.5kΩ 16kΩ DRVDD1 100Ω SYNCINB+ CMOS PATH SYNCINB PIN CONTROL (SPI) 10kΩ AVDD1 1.9pF 25Ω 16kΩ LEVEL TRANSLATOR 15660-030 DRGND VCM = 0.65V 130kΩ Figure 58. Clock Inputs 100Ω SYNCINB– 100Ω DRVDD1 10kΩ 1.9pF AVDD1_SR SYSREF+ DRGND 130kΩ 10kΩ DRGND 15660-033 CLK– DRGND Figure 61. SYNCINB± Inputs 1.9pF 130kΩ LEVEL TRANSLATOR 100Ω SPIVDD 10kΩ 1.9pF ESD PROTECTED 14808-026 SYSREF– AVDD1_SR SCLK 56kΩ ESD PROTECTED Figure 59. SYSREF± Inputs SPIVDD DGND Figure 62. SCLK Input Rev. 0 | Page 25 of 135 DGND 15660-034 130kΩ AD9695 Data Sheet SPIVDD SPIVDD ESD PROTECTED ESD PROTECTED 56kΩ PDWN/ STBY CSB 56kΩ ESD PROTECTED DGND PDWN CONTROL (SPI) 15660-035 DGND DGND DGND 15660-037 ESD PROTECTED Figure 65. PDWN/STBY Input Figure 63. CSB Input SPIVDD SPIVDD SDI DGND 56kΩ DGND DGND TEMPERATURE DIODE VOLTAGE OUTPUT AVDD2 SDO DGND EXTERNAL REFERENCE VOLTAGE INPUT VREF 15660-036 ESD PROTECTED VCM OUTPUT SPIVDD VREF PIN CONTROL (SPI) AGND Figure 66. VREF Input/Output Figure 64. SDIO Input SPIVDD SPIVDD ESD PROTECTED NCO BAND SELECT DGND FD_A/GPIO_A0, FD_B/GPIO_B0 SPIVDD FD JESD204B LMFC 56kΩ ESD PROTECTED JESD204B SYNC~ DGND DGND DGND FD PIN CONTROL (SPI) Figure 67. FD_A/GPIO_A0 and FD_B/GPIO_B0 Rev. 0 | Page 26 of 135 15660-039 SDIO 15660-038 ESD PROTECTED Data Sheet AD9695 THEORY OF OPERATION The AD9695 has two analog input channels and up to eight JESD204B output lane pairs. The ADC samples wide bandwidth analog signals of up to 2 GHz. The actual −3 dB roll-off of the analog inputs is 2 GHz. The AD9695 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. low-pass filter that limits unwanted broadband noise. For more information, refer to the Analog Dialogue article “TransformerCoupled Front-End for Wideband A/D Converters” (Volume 39, April 2005). In general, the precise front-end network component values depend on the application. Figure 68 shows the differential input return loss curve for the analog inputs across a frequency fange of 1 MHz to 10 GHz. The reference impedence is 100 Ω. The AD9695 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. 1: 1.000MHz 170.59nF 2: 100.000 MHz 45.72pF 3: 200.000MHz 12.07pF 4: 300.000MHz 6.49pF 5: 400.000MHz 4.70pF 6: 500.000MHz 4.00pF 182.88Ω –932.98mΩ 177.37Ω –34.81Ω 157.29Ω –65.95Ω 128.82Ω –81.70Ω 102.55Ω –84.58Ω 82.01Ω 1 –79.60Ω 2 3 6 4 ADC ARCHITECTURE The architecture of the AD9695 consists of an input buffered pipelined ADC. The input buffer provides a termination impedance to the analog input signal. This termination impedance is set to 200 Ω. The equivalent circuit diagram of the analog input termination is shown in Figure 29. The input buffer is optimized for high linearity, low noise, and low power across a wide bandwidth. The input buffer provides a linear high input impedance (for ease of drive) and reduces kickback from the ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample; at the same time, the remaining stages operate with the preceding samples. Sampling occurs on the rising edge of the clock. ANALOG INPUT CONSIDERATIONS The analog input to the AD9695 is a differential buffer. The internal common-mode voltage of the buffer is 1.41 V. The clock signal alternately switches the input circuit between sample mode and hold mode. Either a differential capacitor or two single-ended capacitors (or a combination of both) can be placed on the inputs to provide a matching passive network. These capacitors ultimately create a CH1 AVG = 1 > CH1: START 1.0MHz STOP 10.0000GHz 15660-200 5 The Subclass 1 JESD204B-based high speed, serialized output data lanes can be configured in one-lane (L = 1), two-lane (L = 2), and four-lane (L = 4) configurations, depending on the sample rate and the decimation ratio. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins. The SYSREF± pin in the AD9695 can also be used as a timestamp of data as it passes through the ADC and out of the JESD204B interface. Figure 68. AD9695 Different Input Return Loss For best dynamic performance, the source impedances driving VIN+x and VIN−x must be matched such that any commonmode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. For the AD9695, the available span is programmable through the SPI port from 1.36 V p-p to 2.04 V p-p differential, with 1.7 V p-p differential being the default. Differential Input Configurations There are several ways to drive theAD9695, either actively or passively. Optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 69 and Table 9) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9695. For low to midrange frequencies, a double balun or double transformer network (see Figure 69 and Table 9) is recommended for optimum performance of the AD9695. For higher frequencies in the second or third Nyquist zones, it is recommended to remove some of the front-end passive components to ensure wideband operation (see Table 9). Rev. 0 | Page 27 of 135 AD9695 Data Sheet C2 R1 R3 C3 R2 MARKI BAL-0006 C4 C2 ADC R3 C3 15547-050 R1 200Ω C1 R2 NOTES: 1. SEE TABLE 9 FOR COMPONENT VALUES Figure 69. Differential Transformer-Coupled Configuration for the AD9695 Table 10. Differential Transformer-Coupled Input Configuration Component Values Speed Grade AD9695-625 AD9695-1300 Transformer BAL-0006/BAL-0006SMG BAL-0006/BAL-0006SMG R1 25 Ω 25 Ω R2 25 Ω 25 Ω R3 10 Ω 10 Ω C1 0.1 μF 0.1 μF C2 0.1 μF 0.1 μF C3 DNI1 DNI1 C4 DNI1 DNI1 DNI means do not insert. The analog inputs of the AD9695 are internally biased to the common mode, as shown in Figure 71. For dc-coupled applications, the recommended operation procedure is to export the common-mode voltage to the VREF pin using the SPI writes listed in this section. The common-mode voltage must be set by the exported value to ensure proper ADC operation. Disconnect the internal common-mode buffer from the analog input using Register 0x1908. When performing SPI writes for dc coupling operation, use the following register settings, in order: 1. 2. 3. 4. 5. Set Register 0x1908, Bit 2 to 1 to disconnect the internal common-mode buffer from the analog input. Set Register 0x18A6 to 0x00 to turn off the voltage reference. Set Register 0x18E6 to 0x00 to turn off the temperature diode export. Set Register 0x18E3, Bit 6 to 0x01 to turn on the VCM export. Set Register 0x18E3, Bits[5:0] to the buffer current setting (copy the buffer current setting from Register 0x1A4C and Register 0x1A4D to improve the accuracy of the commonmode export). Figure 70 shows the block diagram representation of a dccoupled application. ADC ADC AMP A VOCM VREF VOCM ADC AMP B VCM EXPORT SELECT SPI REGISTERS 0x1908, 0x18A6, 0x18E3, 0x18E6) 15660-041 Input Common Mode Figure 70. DC-Coupled Application Using the AD9695 Analog Input Buffer Controls and SFDR Optimization The AD9695 input buffer offers flexible controls for the analog inputs, such as, buffer current, and input full-scale adjustment. All the available controls are shown in Figure 71. AVDD3 AVDD3 VIN+ 3.5pF 100Ω AVDD3 100Ω AVDD3 VIN– REG (0x0008, 0x1908) AVDD3 3.5pF REG (0x0008, 0x1A4C, 0x1A4D, 0x1910) Figure 71. Analog Input Controls Rev. 0 | Page 28 of 135 15660-042 1 Frequency Range <2 GHz <2 GHz Data Sheet AD9695 Using Register 0x1A4C and Register 0x1A4D, the buffer behavior on each channel can be adjusted to optimize the SFDR over various input frequencies and bandwidths of interest. Use Register 0x1910 to change the internal reference voltage. Changing the internal reference voltage results in a change in the input full-scale voltage. When the input buffer current in Register 0x1A4C and Register 0x1A4D is set, the amount of current required by the AVDD3 supply changes. This relationship is shown in Figure 72. For a complete list of buffer current settings, see Table 11. 85 80 IAVDD3 (mA) 75 70 65 Table 11 shows the recommended values for the buffer current for various Nyquist zones. Absolute Maximum Input Swing The absolute maximum input swing allowed at the inputs of the AD9695 is 5.6 V p-p differential. Signals operating near or at this level can cause permanent damage to the ADC. Dither The AD9695 has internal on-chip dither circuitry that improves the ADC linearity and SFDR, particularly at smaller signal levels. A known but random amount of white noise is injected into the input of theAD9695. This dither improves the small signal linearity within the ADC transfer function and is precisely subtracted out digitally. The dither is turned on by default and does not reduce the ADC input dynamic range. The data sheet specifications and limits are obtained with the dither turned on. The dither is on by default. It is not recommended to turn it off. 60 50 300 350 400 450 BUFFER CURRENT SETTING (µA) 15660-369 55 Figure 72. AVDD3 Current (IAVDD3) vs. Buffer Current Setting (Buffer Control 1 Setting in Register 0x1A4C and Buffer Control 2 Setting in Register 0x1A4D) Table 11. SFDR Optimization for Input Frequencies AD9695-1300 Frequency DC to 650 MHz 650 MHz to 1250 MHz >1250 MHz All AIN frequencies Register 0x1A4C and Register 0x1A4D 160 μA 300 μA 400 μA 300 μA Register 0x1B03 0x00 0x00 0x02 0x02 Register 0x1B08 0x01 0x01 0xC1 0xC1 VIN+A/VIN+B VIN–A/VIN–B INTERNAL 0.5V REFERENCE GENERATOR VFS ADJUST ADC CORE INPUT FULL SCALE RANGE ADJUST SPI REGISTER (0x1910) VREF VREF PIN CONTROL SPI REGISTER (0x18A6) Figure 73. Internal Reference Configuration and Controls Rev. 0 | Page 29 of 135 15660-044 Speed Grade AD9695-625 Register 0x1B10 0x00 0x00 0x1C 0x00 AD9695 Data Sheet INTERNAL 0.5V REFERENCE GENERATOR ADR130 NC NC ADC GND SET INPUT VFS ADJUST VREF VIN VOUT 0.1µF 0.1µF 15660-045 VREF PIN AND VFS CONTROL Figure 74. External Reference Using the ADR130 VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9695. This internal 0.5 V reference sets the full-scale input range of the ADC. The full-scale input range can be adjusted via the ADC input full-scale control register (Register 0x1910). For more information on adjusting the input swing, see Table 47. Figure 73 shows the block diagram of the internal 0.5 V reference controls. The SPI Register 0x18A6 enables the user to either use this internal 0.5 V reference, or to provide an external 0.5 V reference. When using an external voltage reference, provide a 0.5 V reference. The full-scale adjustment is made using the SPI, irrespective of the reference voltage. For more information on adjusting the full-scale level of the AD9695, refer to the Memory Map section. The SPI writes required to use the external voltage reference, in order, are as follows: 1. 2. Set Register 0x18E3 to 0x00 to turn off the VCM export. Set Register 0x18E6 to 0x00 to turn off the temperature diode export. Set Register 0x18A6 to 0x01 to turn on the external voltage reference. 3. The use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 75 shows the typical drift characteristics of the internal 0.5 V reference. The external reference must be a stable 0.5 V reference. The ADR130 is a sufficient option for providing the 0.5 V reference. Figure 74 shows how the ADR130 can be used to provide the external 0.5 V reference to the AD9695. The dashed lines show unused blocks within the AD9695 while using the ADR130 to provide the external reference. DC OFFSET CALIBRATION The AD9695 contains a digital filter to remove the dc offset from the output of the ADC. For ac-coupled applications, this filter can be enabled by setting Register 0x0701, Bit 7 to 0x1 and setting Register 0x73B, Bit 7 to 0x0. The filter computes the average dc signal and it is digitally subtracted from the ADC output. As a result, the dc offset is improved to better than 70 dBFS at the output. Because the filter does not distinguish between the source of dc signals, this feature can be used when the signal content at dc is not of interest. The filter corrects dc up to ±512 codes and saturates beyond that. CLOCK INPUT CONSIDERATIONS For optimum performance, drive the AD9695 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or clock drivers. These pins are biased internally and require no additional biasing. Figure 76 shows a preferred method for clocking the AD9695. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. 0.503 CLK+ 0.501 100Ω 1:2Z ADC CLK– 0.500 Figure 76. Transformer Coupled Differential Clock 0.499 0.498 0.497 0.496 0.495 –40 –20 0 20 40 60 JUNCTION TEMPERATURE (°C) 80 100 Figure 75. Typical VREF Drift Rev. 0 | Page 30 of 135 15660-047 CLOCK INPUT 15660-046 BANDGAP VOLTAGE (V) 0.502 Data Sheet AD9695 Another option is to ac couple a differential CML or LVDS signal to the sample clock input pins, as shown in Figure 77 and Figure 78. 150Ω ADC CLOCK INPUT CLK– 15660-048 LVDS DRIVER 150Ω The AD9695 contains an input clock divider with the ability to divide the input clock by 1, 2, or 4. Select the divider ratios using Register 0x0108 (see Figure 80). The maximum frequency at the CLK± inputs is 1.28 GHz, which is the limit of the divider. In applications where the clock input is a multiple of the sample clock, take care to program the appropriate divider ratio into the clock divider before applying the clock signal; this ensures that the current transients during device startup are controlled. CLK+ 100Ω DIFFERENTIAL 100Ω TRACE Input Clock Divider Figure 77. Differential LVPECL Sample Clock REG 0x011C, 0x011E CLK+ CLK+ ADC CLOCK INPUT CLK– CLK– DIFFERENTIAL TRACE REG 0x0108 Figure 78. Differential CML Sample Clock Figure 80. Clock Divider Circuit The AD9695 clock divider can be synchronized using the external SYSREF± input. A valid SYSREF± signal causes the clock divider to reset to a programmable state. This synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. See the Memory Map Register section for more information. DAC CLOCK INPUT 100Ω CLKOUT– CLK+ ADC CLOCK INPUT CLK– 15660-050 ADC CLKOUT+ ÷2 ÷4 15660-051 100Ω 15660-049 CML DRIVER Figure 79. Clock Output Clocking the AD9695 Clock Duty Cycle Considerations Input Clock Divider ½ Period Delay Adjust Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. The AD9695 contains an internal clock divider and a duty cycle stabilizer comprised of Duty Cycle Stabilizer 1 (DCS1) and Duty Cycle Stabilizer 2 (DCS2). The input clock divider inside the AD9695 provides phase delay in increments of ½ the input clock cycle. Register 0x10C can be programmed to enable this delay independently for each channel. Changing this register does not affect the stability of the JESD204B link. For the AD9695 625 MSPS speed grade, the DCS is disabled by default. In applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock along with the usage of the clock divider is recommended. Clock Fine Delay and Superfine Delay Adjust In the AD9695 625 MSPS speed grade, when it is not possible to provide a higher frequency clock, it is recommended to turn on DCSx using Register 0x011C and Register 0x011E. Figure 80 shows the different controls to the AD9695 clock inputs. The output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal ADC. In the AD9695 1300 MSPS speed grade, the DCS is enabled by default. It is recommended to keep DCS on inrespective of clock divide ratio in the AD9695. See the Memory Map section for more details on using this feature. Adjust the AD9695 sampling edge instant by writing to Register 0x0110, Register 0x0111, and Register 0x0112. Bits[2:0] of Register 0x0110 enable the selection of the fine delay, or the fine delay with superfine delay. The fine delay allows the user to delay the clock edges with 16 step or 192 step delay options. The superfine delay is an unsigned control to adjust the clock delay in superfine steps of 0.25 ps each. Register 0x0112, Bits[7:0] offer the user the option to delay the clock in 192 delay steps. Register 0x0111, Bits[7:0] offer the user the option to delay the clock in 128 superfine steps. These values can be programmed individually for each channel. To use the superfine delay option, set the clock delay control in Register 0x0110, Bits[2:0] to 0x2 or 0x6. Figure 81 shows the controls available to the clock dividers within AD9695. It is recommended to apply the same delay settings to the digital delay circuits as are applied to the analog delay circuits to maintain sample accuracy through the pipe. Rev. 0 | Page 31 of 135 AD9695 Data Sheet 130 CHANNEL A 12.5fS 25fS 50fS 100fS 200fS 400fS 800fS 120 110 PHASE CH. A CLK_DIV SNR (dB) PHASE CH. B 0x0108 FINE DELAY 0x0110, 0x0111, 0x0112 70 50 CHANNEL B 40 30 10 Figure 81. Clock Divider Phase and Delay Controls The clock delay adjustment takes effect immediately when it is enabled via SPI writes. Enabling the clock fine delay adjust in Register 0x0110 causes a datapath reset. However, the contents of Register 0x0111 and Register 0x0112 can be changed without affecting the stability of the JESD204B link. Clock Coupling Considerations The AD9695 has many different domains within the analog supply that control various aspects of the data conversion. The clock domain is supplied by Pin 49 and Pin 64 on the analog supply (AVDD1). To minimize coupling between the clock supply domain and the other analog domains, it is recommended to add a supply Q factor reduction circuitry (de-Q) for Pin 49 and Pin 64, as shown in Figure 82. FERRITE BEAD 220Ω AT 100MHz DCR ≤ 0.5Ω 80 60 15660-052 0x0109 90 100 1000 10000 ANALOG INPUT FREQUENCY (MHz) 15660-054 CLK INPUT 100 Figure 83. Ideal SNR vs. Input Frequency and Jitter Treat the clock input as an analog signal when aperture jitter may affect the dynamic range of the AD9695. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. If the clock is generated from another type of source (by gating, dividing, or other methods), retime the clock by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in depth information about jitter performance as it relates to ADCs. Figure 84 shows the estimated SNR of the AD9695 across input frequency for different clock induced jitter values. Estimate the SNR by using the following equation: SNR JITTER SNR ADC 10 10 10 SNR (dBFS) = −10log10 10 PIN 49 100nF 10Ω 70 AVDD1 PLANE 65 10Ω 60 55 Figure 82. De-Q Network Recommendation for the Clock Domain Supply 50 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. Calculate the degradation in SNR at a given input frequency (fIN) due only to aperture jitter (tJ) by 45 10 25fS 50fS 75fS 100fS 125fS 150fS 175fS 100 INPUT FREQUENCY (MHz) 1000 15660-484 100nF PIN 64 15660-053 220Ω AT 100MHz DCR ≤ 0.5Ω SNR (dBFS) FERRITE BEAD Figure 84. Estimated SNR Degradation for the AD9695 vs. Analog Input Frequency and RMS Jitter SNRJITTER = −20 × log10 (2 × π × fIN × tJ) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 83). Rev. 0 | Page 32 of 135 Data Sheet AD9695 The AD9695 has a PDWN/STBY pin that configure the device in power-down or standby mode. The default operation is PDWN. The PDWN/STBY pin is a logic high pin. When in power-down mode, the JESD204B link is disrupted. The power-down option can also be set via Register 0x003F and Register 0x0040. In standby mode, the JESD204B link is not disrupted and transmits zeros for all converter samples. Change this transmission using Register 0x0571, Bit 7 to select /K/ characters. The SPI writes required to export the central temperature diode are as follows (see the Memory Map section for more information): 4. 5. 6. Set Register 0x0008 to 0x03 to select both channels. Set Register 0x18E3 to 0x00 to turn off VCM export. Set Register 0x18A6 to 0x00 to turn off voltage reference export. Set Register 0x18E6 to 0x01 to turn on voltage export of the central 1× temperature diode. The typical voltage response of the temperature diode is shown in Figure 87. Although this voltage represents the die temperature, it is recommended to take measurements from a pair of diodes for improved accuracy. The following step explains how to enable the 20× diode. Set Register 0x18E6 to 0x02 to turn on the second central temperature diode of the pair, which is 20× the size of the first. For the method using two diodes simultaneously to achieve a more accurate result, see the AN-1432 Application Note, Practical Thermal Modeling and Measurements in High Power ICs. 7. TEMPERATURE DIODE ADC ADC B DIGITAL JESD204B DRIVER TEMPERATURE DIODE LOCATIONS CHANNEL A, CENTRAL, CHANNEL B 0.75 0.70 0.65 0.60 0.55 0.50 –40 –20 0 40 60 80 100 Figure 87. Typical Voltage Response of the 1× Temperature Diode The relationship between the measured delta voltage (ΔV) and the junction temperature in degrees Celcius is shown in Figure 88. 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 –10 –20 –30 –40 60 TJ (°C) The temperature diode voltages can be exported to the VREF pin using the SPI. Use Register 0x18E6 to enable or disable diodes. It is important to note that other voltages may be exported to the VREF pin at the same time, which can result in undefined behavior. To ensure a proper readout, switch off all other voltage exporting circuits as described in this section. Figure 86 shows the block diagram of the controls that are required to enable the diode voltage readout. VREF PIN CONTROL SPI REGISTER (0x18A6) VREF 20 JUNCTION TEMPERATURE (°C) Figure 85. Temperature Diode Locations in the Die CHANNEL A CENTRAL TEMPERATURE DIODE LOCATION SELECT SPI REGISTER (0x18E6) 15660-057 CHANNEL B 65 70 75 80 85 90 95 100 105 110 DELTA VOLTAGE (mV) Figure 88. Junction Temperature (TJ) vs. Delta Voltage (ΔV) Figure 86. Register Controls to Output Temperature Diode Voltage on the VREF Pin Rev. 0 | Page 33 of 135 15660-059 VREF 0.80 15660-056 ADC A 8. TEMPERATURE DIODE VOLTAGE (V) The AD9695 contains diode-based temperature sensors. The diodes output voltages commensurate to the temperature of the silicon. There are multiple diodes on the die, but the results established using the temperature diode at the central location of the die can be regarded as representative of the entire die. However, in applications where only one channel is used (the other channel being in a power-down state), it is recommended to read the temperature diode corresponding to the channel that is on. Figure 85 shows the locations of the diodes in the AD9695 with voltages that can be output to the VREF pin. In each location, there is a pair of diodes, one of which is 20× the size of the other. It is recommended to use both diodes in a location to obtain an accurate estimate of the die temperature. For more information, see the AN-1432 Application Note, Practical Thermal Modeling and Measurements in High Power ICs. 15660-058 POWER-DOWN/STANDBY MODE AD9695 Data Sheet ADC OVERRANGE AND FAST DETECT The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 89. In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overrange bit in the JESD204B outputs provides information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, the latency of this function is of major concern. Highly pipelined converters can have significant latency. The AD9695 contains fast detect circuitry for individual channels to monitor the threshold and assert the FD_A and FD_B pins. The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located at Register 0x0247 and Register 0x0248. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 28 clock cycles (maximum). The approximate upper threshold magnitude is defined by Upper Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) ADC OVERRANGE The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, located at Register 0x0249 and Register 0x024A. The fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency, but is accurate in terms of converter resolution. The lower threshold magnitude is defined by The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange indicator can be embedded within the JESD204B link as a control bit (when CSB > 0). The latency of this overrange indicator matches the sample latency. The AD9695 also records any overrange condition in any of the eight virtual converters. For more information on the virtual converters, refer to Figure 90. The overrange status of each virtual converter is registered as a sticky bit in Register 0x563. The contents of Register 0x563 can be cleared using Register 0x562, by toggling the bits corresponding to the virtual converter to set and reset position. Lower Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) For example, to set an upper threshold of −6 dBFS, write 0xFFF to Register 0x0247 and Register 0x0248. To set a lower threshold of −10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A. FAST THRESHOLD DETECTION (FD_A AND FD_B) The fast detect bit is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit is only cleared when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. This feature provides hysteresis and prevents the FD bit from excessively toggling. The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located at Register 0x24B and Register 0x024C. See the Memory Map section (Register 0x0040, and Register 0x0245 to Register 0x024C in Table 47) for more details. UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD DWELL TIME FD_A OR FD_B Figure 89. Threshold Settings for FD_A and FD_B Signals Rev. 0 | Page 34 of 135 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 15660-060 MIDSCALE LOWER THRESHOLD Data Sheet AD9695 ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING Table 12 shows the number of virtual converters required and the transport layer mapping when channel swapping is disabled. Figure 62 shows the virtual converters and their relationship to the DDC outputs when complex outputs are used. The AD9695 contains a configurable signal path that allows different features to be enabled for different applications. These features are controlled using the chip application mode register, Register 0x0200. The chip operating mode is controlled by Bits[3:0] in this register, and the chip Q ignore is controlled by Bit 5. Each DDC channel outputs either two sample streams (I/Q) for the complex data components (real + imaginary), or one sample stream for real (I) data. The AD9695 can be configured to use up to eight virtual converters, depending on the DDC configuration. The AD9695 contains the following modes: Full bandwidth mode: two 14-bit ADC cores running at the full sample rate. DDC mode: up to four digital downconverter (DDC) channels. The I/Q samples are always mapped in pairs with the I samples mapped to the first virtual converter and the Q samples mapped to the second virtual converter. With this transport layer mapping, the number of virtual converters are the same whether a single real converter is used along with a digital downconverter block producing I/Q outputs, or whether an analog downconversion is used with two real converters producing I/Q outputs. After the chip application mode is selected, the output decimation ratio is set using the chip decimation ratio in Register 0x0201, Bits[3:0]. The output sample rate = ADC sample rate/the chip decimation ratio. To support the different application layer modes, the AD9695 treats each sample stream (real, I, or Q) as originating from separate virtual converters. Figure 63 shows a block diagram of the two scenarios described for I/Q transport layer mapping. Table 12. Virtual Converter Mapping 1 2 2 4 4 8 Chip Operating Mode (Reg. 0x0200, Bits[3:0]) Full bandwidth mode (0x0) One DDC mode (0x1) One DDC mode (0x1) Two DDC mode (0x2) Two DDC mode (0x2) Four DDC mode (0x3) Four DDC mode (0x3) Virtual Converter Mapping Chip Q Ignore (0x0200, Bit 5) Real or complex (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) REAL/I 0 ADC A samples DDC0 I samples DDC0 I samples DDC0 I samples DDC0 I samples DDC0 I samples DDC0 I samples 1 ADC B samples Unused 2 Unused 3 Unused 4 Unused 5 Unused 6 Unused 7 Unused Unused Unused Unused Unused Unused Unused DDC0 Q samples DDC1 I samples DDC0 Q samples DDC1 I samples DDC0 Q samples Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused DDC1 I samples DDC2 I samples DDC1 I samples DDC1 Q samples DDC3 I samples DDC1 Q samples Unused Unused Unused Unused Unused Unused Unused Unused DDC2 I samples DDC2 Q samples DDC3 I samples DDC3 Q samples REAL/I ADC A SAMPLING AT fS REAL/Q REAL/I I/Q CROSSBAR MUX REAL/Q REAL/I REAL/Q REAL/Q ADC B SAMPLING AT fS REAL/I REAL/Q DDC 0 I REAL/I CONVERTER 0 Q Q CONVERTER 1 I Q DDC 1 I REAL/I CONVERTER 2 Q Q CONVERTER 3 I Q DDC 2 I Q DDC 3 I Q REAL/I CONVERTER 6 Q Q CONVERTER 7 I Figure 90. DDCs and Virtual Converter Mapping Rev. 0 | Page 35 of 135 OUTPUT INTERFACE REAL/I I CONVERTER 4 Q Q CONVERTER 5 15660-061 Number of Virtual Converters Supported 1 to 2 AD9695 Data Sheet DIGITAL DOWNCONVERSION M=2 I CONVERTER 0 ADC REAL I REAL DIGITAL DOWNCONVERSION Q CONVERTER 1 L LANES JESD204B Tx L LANES I/Q ANALOG MIXING M=2 I CONVERTER 0 ADC 90° PHASE Q JESD204B Tx ADC Q CONVERTER 1 Figure 91. I/Q Transport Layer Mapping Rev. 0 | Page 36 of 135 15660-062 REAL Data Sheet AD9695 PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS SUPPORTED MODES The AD9695 supports the following modes of operation (the asterisk symbol (*) denotes convolution): PROGRAMMABLE FILTER (PFILT) I (REAL) ADC A CORE DINI [n] 48-TAP FIR FILTER xyI [n] DOUTI [n] I′ (REAL) SIGNAL PROCESSING BLOCKS Q (IMAG) ADC B CORE DINQ [n] 48-TAP FIR FILTER xyQ [n] DOUTQ [n] JESD204B INTERFACE Q′ (IMAG) 15660-063 Real 48-tap filter for each I/Q channel (see Figure 92) DOUT_I[n] = DIN_I[n] * XY_I[n] DOUT_Q[n] = DIN_Q[n] * XY_Q[n] Real 96-tap filter for on either I or Q channel (see Figure 93) DOUT_I[n] = DIN_I[n] * XY_I_XY_Q[n] DOUT_Q[n] = DIN_Q[n] Real set of two cascaded 24-tap filters for each I/Q channel (see Figure 94) DOUT_I[n] = DIN_I[n] * X_I[n] * Y_I[n] DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n] Figure 92. Real 48-Tap Filter Configuration PROGRAMMABLE FILTER (PFILT) I (REAL) ADC A CORE DINI [n] 96-TAP FIR FILTER xIyIxQyQ [n] DOUTI [n] I′ (REAL) SIGNAL PROCESSING BLOCKS Q (IMAG) ADC B CORE DINQ [n] DOUTQ [n] Q′ (IMAG) Figure 93. Real 96-Tap Filter Configuration Rev. 0 | Page 37 of 135 JESD204B INTERFACE 15660-064 Half complex filter using two real 48-tap filters for the I/Q channels (see Figure 95) DOUT_I[n] = DIN_I[n] DOUT_Q[n] = DIN_Q[n] * XY_Q[n] + DIN_I[n] * XY_I[n] Full complex filter using four real 24-tap filters for the I/Q channels (see Figure 96) DOUT_I[n] = DIN_I[n] * X_I[n] + DIN_Q[n] * Y_Q[n] DOUT_Q[n] = DIN_Q[n] * X_Q[n] + DIN_I[n] * Y_I[n] AD9695 Data Sheet PROGRAMMABLE FILTER (PFILT) I (REAL) ADC A CORE DINI [n] 24-TAP FIR FILTER xI [n] DOUTI [n] 24-TAP FIR FILTER yI [n] I′ (REAL) SIGNAL PROCESSING BLOCKS JESD204B INTERFACE 24-TAP FIR FILTER yQ [n] ADC B CORE DINQ [n] 24-TAP FIR FILTER xQ [n] DOUTQ [n] Q′ (IMAG) 15660-065 Q (IMAG) Figure 94. Real, Two Cascaded, 24-Tap Filter Configuration PROGRAMMABLE FILTER (PFILT) I (REAL) ADC A CORE DINI [n] DOUTI [n] 0 TO 47 DELAY TAPS 48-TAP FIR FILTER xyI [n] I′ (REAL) SIGNAL PROCESSING BLOCKS JESD204B INTERFACE + ADC B CORE DINQ [n] 48-TAP FIR FILTER xyQ [n] + DOUTQ [n] Q′ (IMAG) 15660-066 Q (IMAG) Figure 95. 48-Tap Half Complex Filter Configuration PROGRAMMABLE FILTER (PFILT) I (REAL) ADC A CORE DINI [n] 24-TAP FIR FILTER xI [n] DOUTI [n] + I′ (REAL) + 24-TAP FIR FILTER yI [n] SIGNAL PROCESSING BLOCKS JESD204B INTERFACE 24-TAP FIR FILTER yQ [n] ADC B CORE DINQ [n] 24-TAP FIR FILTER xQ [n] + DOUTQ [n] Q′ (IMAG) Figure 96. 24-Tap Full Complex Filter Configuration. Rev. 0 | Page 38 of 135 15660-067 + Q (IMAG) Data Sheet AD9695 PROGRAMMING INSTRUCTIONS Table 12. Register 0x0DF8 Definition Use the following procedure to set up the programmable FIR filter: Bits [7:3] [2:0] 1. 2. 3. 4. 5. 6. 7. Enable the sample clock to the device. Configure the mode registers as follows: a. Set the device index to Channel A (I path) (Register 0x0008 = 0x01). b. Set the I path mode (I mode) and gain in Register 0x0DF8 and Register 0x0DF9 (see Table 12 and Table 13). c. Set the device index to Channel B (Q path) (Register 0x0008 = 0x02). d. Set the Q path mode (Q mode) and gain in Register 0x0DF8 and Register 0x0DF9. Wait at least 5 μs to allow the programmable filter to power up. Program the I path coefficients to the internal shadow registers as follows: a. Set the device index to Channel A (I path) (Register 0x0008 = 0x01). b. Program the XI coefficients in Register 0x0E00 to Register 0x0E2F (see Table 14 and Table 15). c. Program the YI coefficients in Register 0x0F00 to Register 0x0F2F (see Table 14 and Table 15). d. Program the tapped delay in Register 0x0F30 (note that this step is optional). Program the Q path coefficients to the internal shadow registers as follows: a. Set the device index to Channel B (Q path) (Register 0x0008 = 0x02). b. Set the Q path mode and gain in Register 0x0DF8 and Register 0x0DF9 (see Table 12 and Table 13). c. Program the XQ coefficients in Register 0x0E00 to Register 0x0E2F (see Table 14 and Table 15). d. Program the YQ coefficients in Register 0x0F00 to Register 0x0F2F (see Table 14 and Table 15) e. Program the tapped delay in Register 0x0F30 (note that this step is optional). Set the chip transfer bit using either of the following methods (note that setting the chip transfer bit applies the programmed shadow coefficients to the filter): a. Via the register map by setting the chip transfer bit (Register 0x000F = 0x01). b. Via a GPIO pin, as follows: i. Configure one of the GPIO pins as the chip transfer bit in Register 0x0040 to Register 0x0042. ii. Toggle the GPIO pin to initiate the chip transfer (the rising edge is triggered). When the I or Q path mode register changes in Register 0x0DF8, all coefficients must be reprogrammed. Description Reserved Filter mode (I mode or Q mode) 000: filters bypassed 001: real 24-tap filter (X only) 010: real 48-tap filter (X and Y together) 100: real set of two cascaded 24-tap filters (X then Y cascaded) 101: full complex filter using four real 24-tap filters for the A/B channels (opposite channel must also be set to 101) 110: half complex filter using two real 48-tap filters + 48-tap delay line (X and Y together) (opposite channel must also be set to 010) 111: real 96-tap filter (XI, YI, XQ, and YQ together) (opposite channel must be set to 000) Table 13. Register 0x0DF9 Definition Bits 7 [6:4] 3 [2:0] Description Reserved Y filter gain 110: −12 dB loss 111: −6 dB loss 000: 0 dB gain 001: 6 dB gain 010: 12 dB gain Reserved X filter gain 110: −12 dB loss 111: −6 dB loss 000: 0 dB gain 001: 6 dB gain 010: 12 dB gain Table 14 and Table 15 show the coefficient tables in Register 0x0E00 to Register 0x0F30. All coefficients are Q1.15 format (sign bit + 15 fractional bits). Rev. 0 | Page 39 of 135 AD9695 Data Sheet Table 14. I Coefficient Table (Device Selection = 0x1)1 Addr. 0x0E00 0x0E01 0x0E02 0x0E03 … 0x0E2E 0x0E2F 0x0F00 0x0F01 0x0F02 0x0F03 … 0x0F2E 0x0F2F 0x0F30 Single 24-Tap Filter (I Mode [2:0] = 0x1) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] Unused Unused Unused Unused … Unused Unused Unused Single 48-Tap Filter (I Mode [2:0] = 0x2) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C24 [7:0] YI C24 [15:8] YI C25 [7:0] YI C25 [15:8] … YI C47 [7:0] YI C47 [15:0] Unused Two Cascaded 24-Tap Filters (I Mode [2:0] = 0x4) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C0 [7:0] YI C0 [15:8] YI C1 [7:0] YI C1 [15:8] … YI C23 [7:0] YI C23 [15:0] Unused Full Complex 24-Tap Filters (I Mode [2:0] = 0x5 and Q Mode [2:0] = 0x5) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C0 [7:0] YI C0 [15:8] YI C1 [7:0] YI C1 [15:8] … YI C23 [7:0] YI C23 [15:0] Unused 1 Half Complex 48-Tap Filters (I Mode [2:0] = 0x6 and Q Mode [2:0] = 0x2)2 XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C24 [7:0] YI C24 [15:8] YI C25 [7:0] YI C25 [15:8] … YI C47 [7:0] YI C47 [15:0] I path tapped delay 0: 0 tapped delay (matches C0 in the filter) 1: 1 tapped delays … 47: 47 tapped delays XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n. When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode. 3 When using the I path in 96-tap filter mode, the Q path must be in bypass mode. 2 Rev. 0 | Page 40 of 135 I Path 96-Tap Filter (I Mode[2:0] = 0x7 and Q Mode [2:0] = 0x0)3 XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C24 [7:0] YI C24 [15:8] YI C25 [7:0] YI C25 [15:8] … YI C47 [7:0] YI C47 [15:0] Unused Q Path 96-Tap Filter (I Mode [2:0] = 0x0 and Q Mode [2:0] = 0x7)3 XQ C48 [7:0] XQ C48 [15:8] XQ C49 [7:0] XQ C49 [15:8] … XQ C71 [7:0] XQ C71 [15:0] YQ C72 [7:0] YQ C72 [15:8] YQ C73 [7:0] YQ C73 [15:8] … YQ C95 [7:0] YQ C95 [15:0] Unused Data Sheet AD9695 Table 15. Q Coefficient Table (Device Selection = 0x2)1 Addr. 0x0E00 0x0E01 0x0E02 0x0E03 … 0x0E2E 0x0E2F 0x0F00 0x0F01 0x0F02 0x0F03 … 0x0F2E 0x0F2F 0x0F30 1 2 3 Single 24-Tap Filter (Q Mode [2:0] = 0x1) XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] Unused Unused Unused Unused … Unused Unused Unused Single 48-Tap Filter (Q Mode [2:0] = 0x2) XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C24 [7:0] YQ C24 [15:8] YQ C25 [7:0] YQ C25 [15:8] … YQ C47 [7:0] YQ C47 [15:0] Unused Two Cascaded 24-Tap Filters (Q Mode [2:0] = 0x4) XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C0 [7:0] YQ C0 [15:8] YQ C1 [7:0] YQ C1 [15:8] … YQ C23 [7:0] YQ C23 [15:0] Unused Full Complex 24-Tap Filters (Q Mode [2:0] = 0x5 and I Mode [2:0] = 0x5) XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C0 [7:0] YQ C0 [15:8] YQ C1 [7:0] YQ C1 [15:8] … YQ C23 [7:0] YQ C23 [15:0] Unused Half Complex 48-Tap Filters (Q Mode [2:0] = 0x6 and I Mode [2:0] = 0x2)2 XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C24 [7:0] YQ C24 [15:8] YQ C25 [7:0] YQ C25 [15:8] … YQ C47 [7:0] YQ C47 [15:0] Q path tapped delay 0: 0 tapped delay (matches C0 in the filter) 1: 1 tapped delays … 47: 47 tapped delays XQ Cn means Q Path X Coefficient n. YQ Cn means Q Path Y Coefficient n. When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode. When using the I path in 96-tap filter mode, the Q path must be in bypass mode. Rev. 0 | Page 41 of 135 I Path 96-Tap Filter (Q Mode [2:0] = 0x0 and I Mode [2:0] = 0x7)3 XI C48 [7:0] XI C48 [15:8] XI C49 [7:0] XI C49 [15:8] … XI C71 [7:0] XI C71 [15:0] YI C72 [7:0] YI C72 [15:8] YI C73 [7:0] YI C73 [15:8] … YI C95 [7:0] YI C95 [15:0] Unused Q Path 96-Tap Filter (Q Mode [2:0] = 0x7 and I Mode [2:0] = 0x0)3 XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C24 [7:0] YQ C24 [15:8] YQ C25 [7:0] YQ C25 [15:8] … YQ C47 [7:0] YQ C47 [15:0] Unused AD9695 Data Sheet DIGITAL DOWNCONVERTER (DDC) The AD9695 includes four digital downconverters (DDC 0 to DDC 3) that provide filtering and reduce the output data rate. This digital processing section includes an NCO, multiple decimating FIR filters, a gain stage, and a complex to real conversion stage. Each of these processing blocks has control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverter can be configured to output either real data or complex output data. to use both DDC Output Port I and DDC Output Port Q. For more information, see Figure 130. The DDCs output a 16-bit stream. To enable this operation, the converter number of bits, N, is set to a default value of 16, even though the analog core only outputs 14 bits. In full bandwidth operation, the ADC outputs are the 14-bit word followed by two zeros, unless the tail bits are enabled. Each DDC block contains the following signal processing stages: DDC I/Q INPUT SELECTION DDC GENERAL DESCRIPTION The four DDC blocks extract a portion of the full digital spectrum captured by the ADC(s). They are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. Frequency translation stage (optional) Filtering stage Gain stage (optional) Complex to real conversion stage (optional) Frequency Translation Stage (Optional) The AD9695 has two ADC channels and four DDC channels. Each DDC channel has two input ports that can be paired to support both real and complex inputs through the I/Q crossbar mux. For real signals, both DDC input ports must select the same ADC channel (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel A). For complex signals, each DDC input port must select different ADC channels (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel B). The inputs to each DDC are controlled by the DDC input selection registers (Register 0x0311, Register 0x0331, Register 0x0351 and Register 0x0371). See Table 47 for information on how to configure the DDCs. DDC I/Q OUTPUT SELECTION This stage consists of a phase coherent NCO and quadrature mixers that can be used for frequency translation of both real or complex input signals. The phase coherent NCO allows an infinite number of frequency hops that are all referenced back to a single synchronization event. It also includes 16 shadow registers for fast switching applications. This stage shifts a portion of the available digital spectrum down to baseband. Filtering Stage After shifting down to baseband, this stage decimates the frequency spectrum using multiple low pass finite impulse response (FIR) filters for rate conversion. The decimation process lowers the output data rate, which in turn reduces the output interface rate. Gain Stage (Optional) Each DDC channel has two output ports that can be paired to support both real and complex outputs. For real output signals, only the DDC Output Port I is used (the DDC Output Port Q is invalid). For complex I/Q output signals, both DDC Output Port I and DDC Output Port Q are used. The I/Q outputs to each DDC channel are controlled by the DDC complex to real enable bit, Bit 3, in the DDC control registers (Register 0x0310, Register 0x0330, Register 0x0350 and Register 0x370). The chip Q ignore bit in the chip mode register (Register 0x0200, Bit 5) controls the chip output muxing of all the DDC channels. When all DDC channels use real outputs, set this bit high to ignore all DDC Q output ports. When any of the DDC channels are set to use complex I/Q outputs, the user must clear this bit Due to losses associated with mixing a real input signal down to baseband, this stage compensates by adding an additional 0 dB or 6 dB of gain. Complex to Real Conversion Stage (Optional) When real outputs are necessary, this stage converts the complex outputs back to real by performing an fS/4 mixing operation plus a filter to remove the complex component of the signal. Figure 97 shows the detailed block diagram of the DDCs implemented in the AD9695. Figure 98 shows an example usage of one of the four DDC channels with a real input signal and four half-band filters (HB4 + HB3 + HB2 + HB1) used. It shows both complex (decimate by 16) and real (decimate by 8) output options. Rev. 0 | Page 42 of 135 Data Sheet AD9695 COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) REAL/I CONVERTER 2 Q CONVERTER 3 I DECIMATION FILTERS Q REAL/I CONVERTER 4 JESD204B TRANSMIT INTERFACE DECIMATION FILTERS Q ADC B SAMPLING AT fS L JESD204B LANES AT UP TO 16Gbps Q CONVERTER 5 DDC 3 I NCO + MIXER (OPTIONAL) REAL/I DECIMATION FILTERS Q SYSREF± REAL/I CONVERTER 6 Q CONVERTER 7 SYSREF DCM = DECIMATION 15660-068 NCO CHANNEL SELECTION CIRCUITS COMPLEX TO REAL CONVERSION (OPTIONAL) REAL/I REAL/I GPIO PINS Q CONVERTER 1 DDC 2 REAL/I REGISTER MAP CONTROLS COMPLEX TO REAL CONVERSION (OPTIONAL) I/Q CROSSBAR MUX REAL/I NCO + MIXER (OPTIONAL) SYNCHRONIZATION CONTROL CIRCUITS GAIN = 0 OR +6dB I NCO + MIXER (OPTIONAL) SYSREF PIN REAL/I CONVERTER 0 DDC 1 REAL/I REAL/Q DECIMATION FILTERS Q ADC A SAMPLING AT fS REAL/I GAIN = 0 OR +6dB I NCO + MIXER (OPTIONAL) REAL/I GAIN = 0 OR +6dB REAL/I GAIN = 0 OR +6dB DDC 0 NCO CHANNEL SELECTION Figure 97. DDC Detailed Block Diagram Rev. 0 | Page 43 of 135 AD9695 Data Sheet ADC –fS/2 –fS/3 ADC SAMPLING AT fS REAL REAL INPUT—SAMPLED AT fS BANDWIDTH OF INTEREST IMAGE –fS/4 REAL BANDWIDTH OF INTEREST –fS/32 fS/32 DC –fS/16 fS/16 –fS/8 fS/8 fS/4 fS/3 fS/2 FREQUENCY TRANSLATION STAGE (OPTIONAL) I DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND ((fS/3)/fS × 248) = +9.382513 (0x5555_5555_5555) NCO TUNES CENTER OF BANDWIDTH OF INTEREST TO BASEBAND cos(ωt) REAL 48-BIT NCO 90° 0° –sin(ωt) Q DIGITAL FILTER RESPONSE –fS/3 –fS/4 –fS/32 fS/32 DC –fS/16 fS/16 –fS/8 FILTERING STAGE HB4 FIR 4 DIGITAL HALF-BAND FILTERS (HB4 + HB3 + HB2 + HB1) I HALFBAND FILTER Q HALFBAND FILTER HB3 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB4 FIR fS/8 HB2 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB3 FIR fS/4 fS/3 fS/2 HB1 FIR 2 HB2 FIR HALFBAND FILTER I HB1 FIR 2 HALFBAND FILTER Q 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS DIGITAL FILTER RESPONSE 0dB OR 6dB GAIN I GAIN STAGE (OPTIONAL) Q 0dB OR 6dB GAIN COMPLEX TO REAL CONVERSION STAGE (OPTIONAL) –fS/32 fS/32 DC –fS/16 fS/16 –fS/8 COMPLEX (I/Q) OUTPUTS DECIMATE BY 16 GAIN STAGE (OPTIONAL) fS/8 fS/4 MIXING + COMPLEX FILTER TO REMOVE Q 2 +6dB 2 +6dB I Q –fS/32 fS/32 DC –fS/16 fS/16 DOWNSAMPLE BY 2 I REAL (I) OUTPUTS +6dB I DECIMATE BY 8 Q +6dB Q COMPLEX REAL/I TO REAL 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS –fS/8 –fS/32 fS/32 DC –fS/16 fS/16 fS/8 Figure 98. DDC Theory of Operation Example (Real Input) Rev. 0 | Page 44 of 135 15660-069 –fS/2 BANDWIDTH OF INTEREST IMAGE (–6dB LOSS DUE TO NCO + MIXER) BANDWIDTH OF INTEREST (–6dB LOSS DUE TO NCO + MIXER) Data Sheet AD9695 DDC FREQUENCY TRANSLATION Variable IF Mode DDC Frequency Translation General Description NCO and mixers are enabled. NCO output frequency can be used to digitally tune the IF frequency. Frequency translation is accomplished by using a 48-bit complex NCO with a digital quadrature mixer. This stage translates either a real or complex input signal from an IF to a baseband complex digital output (carrier frequency = 0 Hz). 0 Hz IF (ZIF) Mode The mixers are bypassed, and the NCO is disabled. fS/4 Hz IF Mode The frequency translation stage of each DDC can be controlled individually and supports four different IF modes using Bits[5:4] of the DDC control registers (Register 0x0310, Register 0x0330, Register 0x0350, and Register 0x0370). These IF modes are as follows: Test Mode Input samples are forced to 0.999 to positive full scale. The NCO is enabled. This test mode allows the NCOs to directly drive the decimation filters. Variable IF mode 0 Hz IF or zero IF (ZIF) mode fS/4 Hz IF mode Test mode Figure 99 and Figure 100 show examples of the frequency translation stage for both real and complex inputs. NCO FREQUENCY TUNING WORD (FTW) SELECTION 48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 I ADC + DIGITAL MIXER + NCO REAL INPUT—SAMPLED AT fS REAL cos(ωt) ADC SAMPLING AT fS REAL 48-BIT NCO 90° 0° COMPLEX –sin(ωt) Q BANDWIDTH OF INTEREST BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 –fS/8 fS/32 –fS/32 DC –fS/16 fS/16 fS/8 fS/4 fS/3 fS/2 –6dB LOSS DUE TO NCO + MIXER 48-BIT NCO FTW = ROUND ((fS/3)/fS × 248) = +9.382513 (0x5555_5555_5555) POSITIVE FTW VALUES –fS/32 DC fS/32 48-BIT NCO FTW = ROUND ((fS/3)/fS × 248) = –9.382513 (0xAAAA_AAAA_AAAA) NEGATIVE FTW VALUES –fS/32 DC fS/32 Figure 99. DDC NCO Frequency Tuning Word Selection—Real Inputs Rev. 0 | Page 45 of 135 15660-070 The mixers and the NCO are enabled in special downmixing by fS/4 mode to save power. AD9695 Data Sheet NCO FREQUENCY TUNING WORD (FTW) SELECTION 48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 248 QUADRATURE ANALOG MIXER + 2 ADCs + QUADRATURE DIGITAL MIXER + NCO QUADRATURE MIXER ADC SAMPLING AT fS I + I I Q Q REAL 90° PHASE 48-BIT NCO 90° 0° COMPLEX INPUT—SAMPLED AT fS Q Q ADC SAMPLING AT fS Q Q I I – –sin(ωt) I I + COMPLEX Q + BANDWIDTH OF INTEREST IMAGE DUE TO ANALOG I/Q MISMATCH –fS/3 –fS/4 –fS/8 fS/32 –fS/32 –fS/16 fS/16 DC fS/8 fS/4 fS/3 fS/2 48-BIT NCO FTW = ROUND ((fS/3)/fS × 248) = +9.382513 (0x5555_5555_5555) POSITIVE FTW VALUES –fS/32 fS/32 DC Figure 100. DDC NCO Frequency Tuning Word Selection—Complex Inputs Rev. 0 | Page 46 of 135 15660-071 –fS/2 Data Sheet AD9695 DDC NCO Description DDC NCO Coherent Mode Each DDC contains one NCO. Each NCO enables the frequency translation process by creating a complex exponential frequency (e-jωct), which can be mixed with the input spectrum to translate the desired frequency band of interest to dc, where it can be filtered by the subsequent low-pass filter blocks to prevent aliasing. This mode allows an infinite number of frequency hops where the phase is referenced to a single synchronization event at time 0. This mode is useful when phase coherency must be maintained when switching between different frequency bands. In this mode, the user can switch to any tuning frequency without the need to reset the NCO. Although only one FTW is required, the NCO contains 16 shadow registers for fast-switching applications. Selection of the shadow registers is controlled by the CMOS GPIO pins or through the register map of the SPI. In this mode, the NCO can be set up by providing the following: When placed in variable IF mode, the NCO supports two different additional modes. DDC NCO Programmable Modulus Mode This mode supports >48-bit frequency tuning accuracy for applications that require exact rational (M/N) frequency synthesis at a single carrier frequency. In this mode, the NCO is set up by providing the following: Figure 73 shows a block diagram of one NCO and its connection to the rest of the design. The coherent phase accumulator block contains the logic that allows an infinite number of frequency hops. 48-bit frequency tuning word (FTW) 48-bit Modulus A word (MAW) 48-bit Modulus B word (MBW) 48-bit phase offset word (POW) NCO NCO CHANNEL SELECTION FTW/POW WRITE INDEX SYNCHRONIZATION CONTROL CIRCUITS I/O CROSSBAR MUX 0 48-BIT FTW/POW 0 1 48-BIT FTW/POW 1 48-BIT FTW/POW 15 15 COHERENT PHASE ACCUMULATOR BLOCK COS/SIN GENERATOR SYSREF I I Q Q DIGITAL QUADRATURE MIXER FTW = FREQUENCY TUNING WORD POW = PHASE OFFSET WORD MAW = MODULUS A WORD (NUMERATOR) MBW = MODULUS B WORD (DENOMINATOR) Figure 101. NCO + Mixer Block Diagram Rev. 0 | Page 47 of 135 DECIMATION FILTERS 15660-072 FTW/POW REGISTER MAP MODULUS ERROR 48-BIT MAW/MBW –sin(x) MAW/MBW cos(x) NCO CHANNEL SELECTION CIRCUITS Up to sixteen 48-bit FTWs. Up to sixteen 48-bit POWs. The 48-bit MAW must be set to zero in coherent mode. AD9695 Data Sheet NCO FTW/POW/MAW/MAB Description The NCO frequency value is determined by the following settings: 48-bit twos complement number entered in the FTW 48-bit unsigned number entered in the MAW 48-bit unsigned number entered in the MBW M and N are integers reduced to their lowest terms. MAW and MBW are integers reduced to their lowest terms. When MAW is set to zero, the programmable modulus logic is automatically disabled. Frequencies between −fS/2 and +fS/2 (fS/2 excluded) are represented using the following values: Equation 1 to Equation 4 apply to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). FTW = 0x8000_0000_0000 and MAW = 0x0000_0000_0000 represents a frequency of –fS/2. FTW = 0x0000_0000_0000 and MAW = 0x0000_0000_0000 represents dc (frequency is 0 Hz). FTW = 0x7FFF_FFFF_FFFF and MAW = 0x0000_0000_0000 represents a frequency of +fS/2. For example, if the ADC sampling frequency (fS) is 625 MSPS and the carrier frequency (fC) is 208.6 MHz, then, 2089 M mod 417 . 8 ,1300 1300 6250 N mod2417.8,1300 FTW floor 248 1300 = 0x5590_C0AD_03D9 NCO FTW/POW/MAW/MAB Programmable Modulus Mode MAW = mod(248 × 2089, 6250) = 0x0000_0000_1117 For programmable modulus mode, the MAW must be set to a nonzero value (not equal to 0x0000_0000_0000). This mode is only needed when frequency accuracy of >48 bits is required. One example of a rational frequency synthesis requirement that requires >48 bits of accuracy is a carrier frequency of 1/3 the sample rate. When frequency accuracy of ≤48 bits is required, coherent mode must be used (see the NCO FTW/POW/MAW/ MAB Coherent Mode section). MBW = 0x0000_0000_186A The actual carrier frequency can be calculated based on the following equation: f C _ ACTUAL FTW floor(248 FTW 2 MAW MBW 48 mod( fc , f s ) fs ) (1) (2) MAW = mod(248 × M, N) (3) MBW = N (4) where: fC is the desired carrier frequency. fS is the ADC sampling frequency. M is the integer representing the rational numerator of the frequency ratio. N is the integer representing the rational denominator of the frequency ratio. FTW is the 48-bit twos complement number representing the NCO FTW. MAW is the 48-bit unsigned number representing the NCO MAW (must be <247). MBW is the 48-bit unsigned number representing the NCO MBW. mod(x) is a remainder function. For example mod(110,100) = 10 and for negative numbers, mod(–32,10)= –2. floor(x) is defined as the largest integer less than or equal to x. For example, floor(3.6) = 3. MAW f MBW S 2 48 For the previous example, the actual carrier frequency (fC_ACTUAL) is fC _ ACTUAL In programmable modulus mode, the FTW, MAW, and MBW must satisfy the following four equations (for a detailed description of the programmable modulus feature, see the DDS architecture described in the AN-953 Application Note): mod( f c , f s ) M fs N FTW 0x5590_C0AD_03D9 417.8MHz 2 48 0x0000_0000_1117 0x0000_0000_186A 1300 MHz A 48-bit POW is available for each NCO to create a known phase relationship between multiple chips or individual DDC channels inside the chip. While in programmable modulus mode, the FTW and POW registers can be updated at any time while still maintaining deterministic phase results in the NCO. However, the following procedure must be followed to update the MAW and/or MBW registers to ensure proper operation of the NCO: 1. 2. Rev. 0 | Page 48 of 135 Write to the MAW and MBW registers for all the DDCs. Synchronize the NCOs either through the DDC soft reset bit accessible through the SPI or through the assertion of the SYSREF± pin (see the Memory Map section). Data Sheet AD9695 For the previous example, the actual carrier frequency (fC_ACTUAL) is NCO FTW/POW/MAW/MAB Coherent Mode For coherent mode, the NCO MAW must be set to zero (0x0000_0000_0000). In this mode, the NCO FTW can be calculated by the following equation: FTW round(2 48 mod( f c , f s ) ) fs fC_ACTUAL = (5) where: FTW is the 48-bit twos complement number representing the NCO FTW. fS is the ADC sampling frequency. fC is the desired carrier frequency. mod() is a remainder function. For example mod(110,100) = 10 and for negative numbers, mod(–32,10) = –2. round() is a rounding function. For example round(3.6) = 4 and for negative numbers, round(–3.4)= –3. Note that Equation 5 applies to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). The MAW must be set to zero to use coherent mode. When MAW is zero, the programmable modulus logic is automatically disabled. For example, if the ADC sampling frequency (fS) is 1300 MSPS and the carrier frequency (fC) is 417.3333 MHz, then, mod(417.33331300 NCO_FTW = round 2 48 = 1300 0x5578_49CE_E73F 0x5578_49C E_E73F 1300 248 A 48-bit POW is available for each NCO to create a known phase relationship between multiple chips or individual DDC channels inside the chip. While in coherent mode, the FTW and POW registers can be updated at any time while still maintaining deterministic phase results in the NCO. NCO Channel Selection When configured in coherent mode, only one FTW is required in the NCO. In this mode, the user can switch to any tuning frequency without the need to reset the NCO by writing to the FTW directly. However, for fast switching applications, where either all FTWs are known beforehand or it is possible to queue up the next set of FTWs, the NCO contains 16 additional shadow registers (see Figure 73). These shadow registers are hereafter referred to as the NCO channels. Figure 71 shows a simplified block diagram of the NCO channel selection block. Only one NCO channel is active at a time, and NCO channel selection is controlled either by the CMOS GPIO pins or through the register map. Each NCO channel selector supports three different modes, as described in the following sections. The actual carrier frequency can be calculated based on the following equation: FTW f S 2 48 NCO CHANNEL SELECTION IN GPIO CMOS PINS IN [3:0] IN IN MUX REGISTER MAP [0] GPIO SELECTION COUNTER INC NCO CHANNEL SELECTION NCO REGISTER MAP NCO CHANNEL SELECTION 0x0314, 0x0334, 0x0354, 0x0374 NCO CHANNEL MODE 15660-073 f C _ ACTUAL = 417.33 MHz Figure 71. NCO Channel Selection Block Rev. 0 | Page 49 of 135 AD9695 Data Sheet The following procedure must be followed to use GPIO edge control for NCO channel selection: GPIO Level Control Mode The GPIO pins determine the exact NCO channel selected. The following procedure must be followed to use GPIO level control for NCO channel selection: 1. 2. 3. Configure one or more GPIO pins as NCO channel selection inputs. GPIO pins not configured as NCO channel selection are internally tied low. a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to 0x6 and Bits[3:0] in Register 0x0041 to 0x0. b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to 0x6 and Bits [7:4] in Register 0x0041 to 0x0. Configure the NCO channel selector in GPIO level control mode by setting Bits[7:4] in the NCO control registers (Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374) to 0x1 through 0x6, depending on the desired GPIO pin ordering. Select the desired NCO channel through the GPIO pins. 1. 2. 3. Configure one or more GPIO pins as NCO channel selection inputs. a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to 0x6 and Bits[3:0] in Register 0x0041 to 0x0. b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to 0x6 and Bits[7:4] in Register 0x0041 to 0x0. Configure the NCO channel selector in GPIO edge control mode by setting Bits[7:4] in the NCO control registers (Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374) to 0x8 through 0xB, depending on the desired GPIO Pin. Configure the wrap point for the NCO channel selection by setting Bits[3:0] in the NCO control registers (Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374). A value of 4 causes the channel selection to wrap at Channel 4 (0, 1, 2, 3, 4, 0, 1, 2, 3, 4, and so on). Transition the selected GPIO pin from low to high to increment the NCO channel selection. GPIO Edge Control Mode 4. Low to high transition on a single GPIO pin determines the exact NCO channel selected. The internal channel selection counter is reset by either SYSREF± or the DDC soft reset. Register Map Mode NCO channel selection is controlled directly through the register map. Rev. 0 | Page 50 of 135 Data Sheet AD9695 f0 f1 f2 ACTIVE DDC NCO CHANNEL 0 CARRIER FREQUENCY 0 (ACTIVE) NCO CHANNEL 1 CARRIER FREQUENCY 1 (STANDBY) NCO CHANNEL 2 CARRIER FREQUENCY 2 (STANDBY) fS/2 15660-074 DC B2 B1 B0 Figure 72. NCO Coherent Mode with Three NCO Channels (B0 Selected) Figure 72 shows an example use case for coherent mode utilizing three NCO channels. In this example, NCO Channel 0 is actively downconverting bandwidth 0 (B0) while NCO Channel 1 and Channel 2 are in standby and tuned to Bandwidth 1 and Bandwidth 2 (B1 and B2), respectively. The phase coherent NCO switching feature allows an infinite number of frequency hops that are all phase coherent. The initial phase of the NCO is established at time t0 from SYSREF± synchronization. Switching the NCO FTW does not affect the phase. With this feature, only one FTW is required; however, the user may want to use all 16 channels to queue up the next hop. After SYSREF± synchronization at start-up, all NCOs across multiple chips are inherently synchronized. Setting Up the Multichannel NCO Feature The first step to configure the multichannel NCO is to program the FTWs. The AD9695 memory map has a FTW index register for each DDC. This index determines which NCO channel receives the FTW from the register map. The following sequence describes the method for programming the FTWs. 1. 2. 3. Write the FTW index register with the desired DDC channel. Write the FTW with the desired value. This value is applied to the NCO channel index mentioned in Step 1. Repeat Step 1 and Step 2 for other NCO channels. After setting the FTWs, the user must then select an active NCO channel. This selection can be done either through the SPI registers or through the external GPIO pins. The following sequence describes the method for selecting the active NCO channel using SPI. 1. 2. The following sequence describes the method for selecting the active NCO channel using GPIO CMOS pins. 1. 2. 3. Set NCO channel selection mode (Bits[7:4]) in Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374 to a nonzero value to enable GPIO pin selection. Configure the GPIO pins as NCO channel selection inputs by writing to Register 0x0040, Register 0x0041, and Register 0x0042. NCO switching is done by externally controlling the GPIO CMOS pins. NCO Synchronization Each NCO contains a separate phase accumulator word (PAW). The initial reset value of each PAW is set to zero and increments every clock cycle. The instantaneous phase of the NCO is calculated using the PAW, FTW, MAW, MBW, and POW. Due to this architecture, the FTW and POW registers can be updated at any time while still maintaining deterministic phase results in the PAW of the NCO. Two methods can be used to synchronize multiple PAWs within the chip: Set the NCO channel selection mode (Bits[7:4]) in Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374 to 0x0 to enable SPI selection. Choose the active NCO channel (Bits[3:0]) in Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374. Rev. 0 | Page 51 of 135 Using the SPI. Use the DDC soft reset bit in the DDC synchronization control register (Register 0x0300, Bit 4) to reset all the PAWs in the chip. This reset is accomplished by setting the DDC soft reset bit high, and then setting this bit low. Note that this method can only be used to synchronize DDC channels within the same chip. Using the SYSREF± pin. When the SYSREF± pin is enabled in the SYSREF control registers (Register 0x0120 and Register 0x0121), and the DDC synchronization is enabled in the DDC synchronization control register (Register 0x0300, Bits[1:0]), any subsequent SYSREF± event resets all the PAWs in the chip. Note that this method can be used to synchronize DDC channels within the same chip or DDC channels within separate chips. AD9695 Data Sheet NCO Multichip Synchronization MNTO ADC DEVICE 0 (MASTER) In some applications, it is necessary to synchronize all the NCOs and local multiframe clocks (LMFCs) within multiple devices in a system. For applications requiring multiple NCO tuning frequencies in the system, a designer likely needs to generate a single SYSREF± pulse at all devices simultaneously. For many systems, generating or receiving a single-shot SYSREF± pulse at all devices is challenging because of the following factors: ADC DEVICE 1 (SLAVE) SNTI Enabling or disabling the SYSREF± pulse is often an asynchronous event. Not all clock generation chips support this feature. SNTI For these reasons, the AD9695 contains a synchronization triggering mechanism that allows the following: Multichip synchronization of all NCOs and LMFCs at system startup. Multichip synchronization of all NCOs after applying new tuning frequencies during normal operation. The synchronization triggering mechanism uses a master/slave arrangement, as shown in Figure 104. ADC DEVICE 2 (SLAVE) ADC DEVICE 3 (SLAVE) 1 LINK, L LANES 1 LINK, L LANES 1 LINK, L LANES SYSREF± DEVICE_CLOCK± CLOCK GENERATION MNTO = MASTER NEXT TRIGGER OUTPUT (CMOS) SNTI = SLAVE NEXT TRIGGER INPUT (CMOS) 15660-075 SNTI 1 LINK, L LANES Figure 104. System Using Master/Slave Synchronization Triggering Each device has an internal next synchronization trigger enable (NSTE) signal that controls whether the next SYSREF± signal causes a synchronization event. Slave ADC devices must source their NSTE from an external slave next trigger input (SNTI) pin. Master devices can either use an external master next trigger output (MNTO) pin (default setting), or use an external SNTI pin. See Table 47 (Register 0x0041 and Register 0x0042) to configure the FD/GPIO pins for this operation. NCO Multichip Synchronization at Startup Figure 105 shows a timing diagram along with the required sequence of events for NCO multichip synchronization using triggering and SYSREF± at startup. Using this startup sequence synchronizes all the NCOs and LMFCs in the system at once. NCO Multichip Synchronization During Normal Operation See the NCO Multichip Synchronization section. Rev. 0 | Page 52 of 135 Data Sheet CONFIGURE MASTER AND SLAVE DEVICES AD9695 ENABLE TRIGGER IN MASTER DEVICES MNTO SET HIGH SYSTEM SYNCHRONIZATION ACHIEVED SNTI SET HIGH SYSREF IGNORED DEVICE CLOCK SYSREF MNTO BOARD PROPAGATION DELAY SNTI INPUT DELAY NSTE LMFCs DON’T CARE NCOs DON’T CARE LMFC SYNCHRONIZED NCO SYNCHRONIZED 15660-076 MNTO = MASTER NEXT TRIGGER OUTPUT (CMOS) SNTI = SLAVE NEXT TRIGGER INPUT (CMOS) NSTE = NEXT SYNCHRONIZATION TRIGGER ENABLE LMFC = LOCAL MULTIFRAME CLOCK NCO = NUMERICALLY CONTROLLED OSCILLATOR Figure 105. NCO Multichip Synchronization at Startup (Using Triggering and SYSREF) DDC Mixer Description When not bypassed (Register 0x0200 ≠ 0x00), the digital quadrature mixer performs a similar operation to an analog quadrature mixer. It performs the downconversion of input signals (real or complex) by using the NCO frequency as a local oscillator. For real input signals, a real mixer operation (with two multipliers) is performed. For complex input signals, a complex mixer operation (with four multipliers and two adders) is performed. The selection of real or complex inputs can be controlled individually for each DDC block using Bit 7 of the DDC control registers (Register 0x0310, Register 0x0330, Register 0x0350, and Register 0x0370). DDC NCO + Mixer Loss and SFDR When mixing a real input signal down to baseband, −6 dB of loss is introduced in the signal due to filtering of the negative image. An additional −0.05 dB of loss is introduced by the NCO. The total loss of a real input signal mixed down to baseband is −6.05 dB. For this reason, it is recommended that the user compensate for this loss by enabling the 6 dB of gain in the gain stage of the DDC to recenter the dynamic range of the signal within the full scale of the output bits (see the DDC Gain Stage section for more information). When mixing a complex input signal (where I and Q DDC inputs come from the different ADCs) down to baseband, the maximum value each I/Q sample can reach is 1.414 × full-scale after it passes through the complex mixer. To avoid overrange of the I/Q samples and to keep the data bit widths aligned with real mixing, −3.06 dB of loss is introduced in the mixer for complex signals. An additional −0.05 dB of loss is introduced by the NCO. The total loss of a complex input signal mixed down to baseband is −3.11 dB. The worst case spurious signal from the NCO is greater than 102 dBc SFDR for all output frequencies. DDC DECIMATION FILTERS After the frequency translation stage, there are multiple decimation filter stages used to reduce the output data rate. After the carrier of interest is tuned down to dc (carrier frequency = 0 Hz), these filters efficiently lower the sample rate, while providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. Figure 73 shows a simplified block diagram of the decimation filter stage, and Table 16 describes the filter characteristics of the different FIR filter blocks. Table 17 and Table 18 show the different filter configurations selectable by including different filters. In all cases, the DDC filtering stage provides 80% of the available output bandwidth, <±0.005 dB of pass-band ripple, and >100 dB of stop band alias rejection. Rev. 0 | Page 53 of 135 AD9695 Data Sheet DCM = 3 DECIMATION FILTERS I DCM = 2 DCM = 3 TB2 FIR DCM = 2 HB3 FIR HB2 FIR I DCM = 2 FB2 FIR I I Q Q DCM = 5 Q FB2 FIR I I Q TB2 FIR DCM = 3 Q Q HB3 FIR HB4 FIR DCM = 2 HB2 FIR DCM = 2 I HB1 FIR DCM = 5 I NCO AND MIXERS (OPTIONAL) HB4 FIR DCM = 2 DCM = 2 COMPLEX TO REAL CONVERSION (OPTIONAL) I GAIN = 0dB OR +6dB I TB1 FIR HB1 FIR DCM = 2 Q Q Q TB1 FIR Q DCM = 3 15660-077 FIR = FINITE IMPULSE RESPONSE FILTER DCM = DECIMATION NOTES 1. TB1 IS ONLY SUPPORTED IN DDC0 AND DDC1 Figure 73. DDC Decimation Filter Block Diagram Table 16. DDC Decimation Filter Characteristics Filter Name HB4 HB3 HB2 HB1 TB2 TB11 FB2 1 Filter Type FIR low-pass FIR low-pass FIR low-pass FIR low-pass FIR low-pass FIR low-pass FIR low-pass Decimation Ratio 2 2 2 2 3 3 5 Pass Band (rad/sec) 0.1 x π/2 0.2 x π/2 0.4 x π/2 0.8 x π/2 0.4 x π/3 0.8 x π/3 0.4 x π/5 Stop Band (rad/sec) 1.9 x π/2 1.8 x π/2 1.6 x π/2 1.2 x π/2 1.6 x π/3 1.2 x π/3 1.6 x π/5 TB1 is only supported in DDC0 and DDC1. Rev. 0 | Page 54 of 135 Pass-Band Ripple (dB) <±0.001 <±0.001 <±0.001 <±0.001 <±0.002 <±0.005 <±0.001 Stop-Band Attenuation (dB) >100 >100 >100 >100 >100 >100 >100 Data Sheet AD9695 Table 17. DDC Filter Configurations1 ADC Sample Rate fS fS fS fS fS fS fS fS fS fS fS fS fS fS DDC Filter Configuration HB1 TB13 HB2 + HB1 TB2 + HB1 HB3 + HB2 + HB1 FB2 + HB1 TB2 + HB2 + HB1 FB2 + TB13 HB4 + HB3 + HB2 + HB1 FB2 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 HB2 + FB2 + TB13 FB2 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 Real (I) Output Decimation Sample Ratio Rate 1 fS N/A N/A 2 fS/2 3 fS/3 4 fS/4 5 fS/5 6 fS/6 N/A N/A 8 fS/8 10 fS/10 12 fS/12 N/A N/A 20 fS/20 24 fS/24 Complex (I/Q) Outputs Decimation Ratio Sample Rate 2 fS/2 (I) + fS/2 (Q) 3 f fS/3 (I) + fS/3 (Q) 4 fS/4 (I) + fS/4 (Q) 6 fS/6 (I) + fS/6 (Q) 8 fS/8 (I) + fS/8 (Q) 10 fS/10 (I) + fS/10 (Q) 12 fS/12 (I) + fS/12 (Q) 15 fS/15 (I) + fS/15 (Q) 16 fS/16 (I) + fS/16 (Q) 20 fS/20 (I) + fS/20 (Q) 24 fS/24 (I) + fS/24 (Q) 30 fS/30 (I) + fS/30 (Q) 40 fS/40 (I) + fS/40 (Q) 48 fS/48 (I) + fS/48 (Q) Alias Protected Bandwidth fS/2 × 80% fS/3 × 80% fS/4 × 80% fS/6 × 80% fS/8 × 80% fS/10 × 80% fS/12 × 80% fS/15 × 80% fS/16 × 80% fS/20 × 80% fS/24 × 80% fS/30 × 80% fS/40 × 80% fS/48 × 80% Ideal SNR Improvement (dB)2 1 2.7 4 5.7 7 8 8.8 9.7 10 11 11.8 12.7 14 14.8 1 N/A means not applicable. Ideal SNR improvement due to oversampling + filtering > 10log(bandwidth/fS/2). 3 TB1 is only supported in DDC0 and DDC1. 2 Table 18. DDC Filter Configurations (fS = 1300 MSPS)1 ADC Sample Rate (MSPS) 1300 1300 DDC Filter Configuration HB1 TB12 Real (I) Output Decimation Sample Rate Ratio (MSPS) 1 1300 N/A N/A 1300 1300 HB2 + HB1 TB2 + HB1 2 3 650 433.33 1300 1300 1300 HB3 + HB2 + HB1 FB2 + HB1 TB2 + HB2 + HB1 4 5 6 325 260 216.67 1300 1300 1300 1300 1300 1300 1300 FB2 + TB12 HB4 + HB3 + HB2 + HB1 FB2 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 HB2 + FB2 + TB12 FB2 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 N/A 8 10 12 N/A 20 24 N/A 162.5 130 108.33 N/A 65 54.16 1 2 N/A means not applicable. TB1 is only supported in DDC0 and DDC1. Rev. 0 | Page 55 of 135 Complex (I/Q) Outputs Decimation Sample Rate Ratio (MSPS) 2 650 (I) + 650 (Q) 3 433.33 (I) + 433.33 (Q) 4 325 (I) + 325 (Q) 6 216.67 (I) + 216.67 (Q) 8 162.5 (I) + 162.5 (Q) 10 130 (I) + 130 (Q) 12 108.33 (I) + 108.33 (Q) 15 86.67 (I) + 86.67 (Q) 16 81.25 (I) + 81.25 (Q) 20 65 (I) + 65 (Q) 24 54.16 (I) + 54.16 (Q) 30 43.44 (I) + 43.44 (Q) 40 32.5 (I) + 32.5 (Q) 48 27.08 (I) + 27.08 (Q) Alias-Protected Bandwidth (MHz) 520 346.67 260 173.33 130 104 86.67 69.33 65 52 43.33 34.67 26 21.67 AD9695 Data Sheet Table 18. DDC Filter Configurations (fS = 625 MSPS)1 ADC Sample Rate (MSPS) 625 625 DDC Filter Configuration HB1 TB12 Real (I) Output Decimation Sample Rate Ratio (MSPS) 1 625 N/A N/A 625 HB2 + HB1 2 312.5 625 TB2 + HB1 3 208.33 625 HB3 + HB2 + HB1 4 156.25 625 625 625 625 625 625 625 625 FB2 + HB1 TB2 + HB2 + HB1 FB2 + TB12 HB4 + HB3 + HB2 + HB1 FB2 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 HB2 + FB2 + TB12 FB2 + HB3 + HB2 + HB1 5 6 N/A 8 10 12 N/A 20 125 104.17 N/A 78.125 62.5 52.08 N/A 31.25 625 TB2 + HB4 + HB3 + HB2 + HB1 24 26.04 1 2 Complex (I/Q) Outputs Decimation Sample Rate Ratio (MSPS) 2 312.5 (I) + 312.5 (Q) 3 208.33 (I) + 208.33 (Q) 4 156.25 (I) + 156.25 (Q) 6 104.17 (I) + 104.17 (Q) 8 78.125 (I) + 78.125 (Q) 10 62.5 (I) + 62.5 (Q) 12 52.08 (I) + 52.08 (Q) 15 41.67 (I) + 41.67 (Q) 16 39.06 (I) + 39.06 (Q) 20 31.25 (I) + 31.25 (Q) 24 26.04 (I) + 26.04 (Q) 30 20.83 (I) + 20.83 (Q) 40 15.625 (I) + 15.625 (Q) 48 13.02 (I) + 13.02 (Q) Alias-Protected Bandwidth (MHz) 250 166.67 125 83.33 62.5 50 41.67 33.33 31.25 25 20.83 16.67 12.5 10.42 N/A means not applicable. TB1 is only supported in DDC0 and DDC1. 20 HB4 Filter Description 0 –20 MAGNITUDE (dB) The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB4 filter is only used when complex outputs (decimate by 16) or real outputs (decimate by 8) are enabled; otherwise, it is bypassed. Table 21 and Figure 107 show the coefficients and response of the HB4 filter. –80 –100 Decimal Coefficient (15-Bit) +99 0 −809 0 +4806 +8192 Rev. 0 | Page 56 of 135 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) Figure 107. HB4 Filter Response 0.9 1.0 15660-078 Normalized Coefficient +0.006042 0 −0.049377 0 +0.293335 +0.5 –60 –120 Table 21. HB4 Filter Coefficients HB4 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 –40 Data Sheet AD9695 HB3 Filter Description Table 23. HB2 Filter Coefficients The second decimate by 2, half-band, low-pass, FIR filter (HB3) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB3 filter is only used when complex outputs (decimate by 8 or 16) or real outputs (decimate by 4 or 8) are enabled; otherwise, it is bypassed. Table 22 and Figure 108 show the coefficients and response of the HB3 filter. HB2 Coefficient Number C1, C19 C2, C18 C3, C17 C4, C16 C5, C15 C6, C14 C7, C13 C8, C12 C9, C11 C10 HB3 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Normalized Coefficient +0.006638 0 −0.051056 0 +0.294418 +0.500000 Decimal Coefficient (17-Bit) +435 0 −3346 0 +19,295 +32,768 20 0 0 –20 –40 –60 –80 –100 –40 –120 –60 –140 –80 –160 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) –120 Figure 109. HB2 Filter Response –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) 0.9 1.0 15660-079 –140 Figure 108. HB3 Filter Response HB2 Filter Description The third decimate by 2, half-band, low-pass, FIR filter (HB2) uses a 19-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB2 filter is only used when complex or real outputs (decimate by 4, 8, or 16) is enabled; otherwise, it is bypassed. Table 23 and Figure 109 show the coefficients and response of the HB2 filter. Rev. 0 | Page 57 of 135 0.9 1.0 15660-080 MAGNITUDE (dB) –20 Decimal Coefficient (18-Bit) +88 0 −698 0 +2981 0 −9723 0 +40120 +65536 20 MAGNITUDE (dB) Table 22. HB3 Filter Coefficients Normalized Coefficient +0.000671 0 −0.005325 0 +0.022743 0 −0.074181 0 +0.306091 +0.5 AD9695 Data Sheet 20 HB1 Filter Description 0 –20 MAGNITUDE (dB) Table 24. HB1 Filter Coefficients Decimal Coefficient (20-Bit) −10 0 +38 0 −102 0 +232 0 −467 0 +862 0 −1489 0 +2440 0 −3833 0 +5831 0 −8679 0 12803 0 −19086 0 +29814 0 −53421 0 +166138 +262144 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED FREQUENCY (× Π RAD/s) Figure 110. HB1 Filter Response TB2 Filter Description The TB2 uses a 26-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The TB2 filter is only used when decimation ratios of 6, 12, or 24 are required. Table 25 and Figure 111 show the coefficients and response of the TB2 filter. Table 25. TB2 Filter Coefficients TB2 Coefficient Number C1, C26 C2, C25 C3, C24 C4, C23 C5, C22 C6, C21 C7, C20 C8, C19 C9, C18 C10, C17 C11, C16 C12, C15 C13, C14 Normalized Coefficient −0.000191 −0.000793 −0.001137 +0.000916 +0.006290 +0.009823 +0.000916 −0.023483 −0.043152 −0.019318 +0.071327 +0.201172 +0.297756 Decimal Coefficient (19-Bit) −50 +208 −298 +240 +1649 +2575 +240 −6156 −11312 −5064 +18698 +52736 +78055 20 0 –20 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) Figure 111. TB2 Filter Response Rev. 0 | Page 58 of 135 0.9 1.0 15660-082 Normalized Coefficient −0.000019 0 +0.000072 0 −0.000195 0 +0.000443 0 −0.000891 0 +0.001644 0 −0.002840 0 +0.004654 0 −0.007311 0 +0.011122 0 −0.016554 0 0.024420 0 −0.036404 0 +0.056866 0 −0.101892 0 +0.316883 +0.5 MAGNITUDE (dB) HB1 Coefficient Number C1, C63 C2, C62 C3, C61 C4, C60 C5, C59 C6, C58 C7, C57 C8, C56 C9, C55 C10, C54 C11, C53 C12, C52 C13, C51 C14, C50 C15, C49 C16, C48 C17, C47 C18, C46 C19, C45 C20, C44 C21, C43 C22, C42 C23, C41 C24, C40 C25, C39 C26, C38 C27, C37 C28, C36 C29, C35 C30, C34 C31, C33 C32 –40 15660-081 The fourth and final decimate by 2, half-band, low-pass, FIR filter (HB1) uses a 63-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB1 filter is always enabled and cannot be bypassed. Table 24 and Figure 110 show the coefficients and response of the HB1 filter. Data Sheet AD9695 20 TB1 Filter Description TB1 Coefficient Number 1, 76 2, 75 3, 74 4, 73 5, 72 6, 71 7, 70 8, 69 9, 68 10, 67 11, 66 12, 65 13, 64 14, 63 15, 62 16, 61 17, 60 18, 59 19, 58 20, 57 21, 56 22, 55 23, 54 24, 53 25, 52 26, 51 27, 50 28, 49 29, 48 30, 47 31, 46 32, 45 33, 44 34, 43 35, 42 36, 41 37, 40 38, 39 Normalized Coefficient −0.000023 −0.000053 −0.000037 +0.000090 +0.000291 +0.000366 +0.000095 −0.000463 −0.000822 −0.000412 +0.000739 +0.001665 +0.001132 −0.000981 −0.002961 −0.002438 +0.001087 +0.004833 +0.004614 −0.000871 −0.007410 −0.008039 +0.000053 +0.010874 +0.013313 +0.001817 −0.015579 −0.021590 −0.005603 +0.022451 +0.035774 +0.013541 −0.034655 −0.066549 −0.035213 +0.071220 +0.210777 +0.309200 Decimal Coefficient (22-Bit) −96 −224 −156 +379 +1220 +1534 +398 −1940 −3448 −1729 +3100 +6984 +4748 −4114 −12418 −10226 +4560 +20272 +19352 −3652 −31080 −33718 +222 +45608 +55840 +7620 −65344 −90556 −23502 +94167 +150046 +56796 −145352 −279128 −147694 +298720 +884064 +1296880 –20 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) Figure 112. TB1 Filter Response Rev. 0 | Page 59 of 135 0.9 1.0 15660-083 Table 26. TB1 Filter Coefficients 0 MAGNITUDE (dB) The TB1 decimate by 3, low-pass, FIR filter uses a 76-tap, symmetrical, fixed coefficient filter implementation. Table 26 shows the TB1 filter coefficients, and Figure 112 shows the TB1 filter response. TB1 is only supported in DDC0 and DDC1. AD9695 Data Sheet 20 FB2 Filter Description FB2 Coefficient Number 1, 48 2, 47 3, 46 4, 45 5, 44 6, 43 7, 42 8, 41 9, 40 10, 39 11, 38 12, 37 13, 36 14, 35 15, 34 16, 33 17, 32 18, 31 19, 30 20, 29 21, 28 22, 27 23, 26 24, 25 Normalized Coefficient +0.000007 −0.000004 −0.000069 −0.000244 −0.000544 −0.000870 −0.000962 −0.000448 +0.000977 +0.003237 +0.005614 +0.006714 +0.004871 −0.001011 −0.010456 −0.020729 −0.026978 −0.023453 −0.005608 +0.027681 +0.072720 +0.121223 +0.162346 +0.185959 Decimal Coefficient (21-Bit) 7 −4 −72 −256 −570 −912 −1009 −470 +1024 +3394 +5887 +7040 +5108 −1060 −10964 −21736 −28288 −24592 −5880 +29026 +76252 +127112 +170232 +194992 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) 0.9 1.0 15660-084 Table 27. FB2 Filter Coefficients 0 –20 MAGNITUDE (dB) The FB2 decimate by 5, low-pass, FIR filter uses a 48-tap, symmetrical, fixed coefficient filter implementation. Table 27 shows the FB2 filter coefficients, and Figure 113 shows the FB2 filter response. Figure 113. FB2 Filter Response DDC GAIN STAGE Each DDC contains an independently controlled gain stage. The gain is selectable as either 0 dB or 6 dB. When mixing a real input signal down to baseband, it is recommended that the user enable the 6 dB of gain to recenter the dynamic range of the signal within the full scale of the output bits. When mixing a complex input signal down to baseband, the mixer has already recentered the dynamic range of the signal within the full scale of the output bits, and no additional gain is necessary. However, the optional 6 dB gain compensates for low signal strengths. The downsample by 2 portion of the HB1 FIR filter is bypassed when using the complex to real conversion stage. The TB1 filter does not have the 6 dB gain stage. Rev. 0 | Page 60 of 135 Data Sheet AD9695 the signal, the Q portion of the complex mixer is no longer needed and is dropped. The TB1 filter does not support complex to real conversion. DDC COMPLEX TO REAL CONVERSION Each DDC contains an independently controlled complex to real conversion block. The complex to real conversion block reuses the last filter (HB1 FIR) in the filtering stage along with an fS/4 complex mixer to upconvert the signal. After upconverting HB1 FIR Figure 114 shows a simplified block diagram of the complex to real conversion. GAIN STAGE COMPLEX TO REAL ENABLE LOW-PASS FILTER I 2 0dB OR 6dB I 0 I/REAL 1 COMPLEX TO REAL CONVERSION 0dB OR 6dB I cos(wt) + REAL 90° fS/4 0° – LOW-PASS FILTER 2 0dB OR 6dB Q 0dB OR 6dB Q Q 15660-085 Q sin(wt) HB1 FIR Figure 114. Complex to Real Conversion Block Rev. 0 | Page 61 of 135 AD9695 Data Sheet DDC MIXED DECIMATION SETTINGS The AD9695 also supports DDCs with different decimation rates. In this scenario, the chip decimation ratio must be set to the lowest decimation ratio of all the DDC channels. Samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Only mixed decimation ratios that are integer multiples of 2 are supported. For example, decimate by 1, 2, 4, 8, or 16 can be mixed together, decimate by 3, 6, 12, 24, or 48 can be mixed together, or decimate by 5, 10, 20, or 40 can be mixed together. Table 26 shows the DDC sample mapping when the chip decimation ratio is different than the DDC decimation ratio. For example, if the chip decimation ratio is set to decimate by 4, DDC0 is set to use the HB2 + HB1 filters (complex outputs, decimate by 4) and DDC1 is set to use the HB4 + HB3 + HB2 + HB1 filters (real outputs, decimate by 8), then DDC1 repeats its output data 2 times for every one DDC0 output. The resulting output samples are shown in Table 27. Table 26. Sample Mapping when Chip Decimation Ratio (DCM) Does Not Match DDC DCM Sample Index 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DDC DCM = Chip DCM N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 N + 24 N + 25 N + 26 N + 27 N + 28 N + 29 N + 30 N + 31 DDC DCM = 2 × Chip DCM N N N+1 N+1 N+2 N+2 N+3 N+3 N+4 N+4 N+5 N+5 N+6 N+6 N+7 N+7 N+8 N+8 N+9 N+9 N + 10 N + 10 N + 11 N + 11 N + 12 N + 12 N + 13 N + 13 N + 14 N + 14 N + 15 N + 15 DDC DCM = 4 × Chip DCM N N N N N+1 N+1 N+1 N+1 N+2 N+2 N+2 N+2 N+3 N+3 N+3 N+3 N+4 N+4 N+4 N+4 N+5 N+5 N+5 N+5 N+6 N+6 N+6 N+6 N+7 N+7 N+7 N+7 Rev. 0 | Page 62 of 135 DDC DCM = 8 × Chip DCM N N N N N N N N N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+3 N+3 N+3 N+3 N+3 N+3 N+3 N+3 Data Sheet AD9695 Table 27. Chip DCM = 4, DDC0 DCM = 4 (Complex), and DDC1 DCM = 8 (Real)1 DDC Input Samples N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 1 Output Port I I0[N] I0[N] I0[N] I0[N] I0[N + 1] I0[N + 1] I0[N + 1] I0[N + 1] I0[N + 2] I0[N + 2] I0[N + 2] I0[N + 2] I0[N + 3] I0[N + 3] I0[N + 3] I0[N + 3] DDC0 Output Port Q Q0[N] Q0[N] Q0[N] Q0[N] Q0[N + 1] Q0[N + 1] Q0[N + 1] Q0[N + 1] Q0[N + 2] Q0[N + 2] Q0[N + 2] Q0[N + 2] Q0[N + 3] Q0[N + 3] Q0[N + 3] Q0[N + 3] DCM means decimation. Rev. 0 | Page 63 of 135 Output Port I I1[N] I1[N] I1[N] I1[N] I1[N] I1[N] I1[N] I1[N] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] DDC1 Output Port Q Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable AD9695 Data Sheet DDC EXAMPLE CONFIGURATIONS Table 28 describes the register settings for multiple DDC example configurations. Bandwidths listed are with <−0.005 dB of pass-band ripple and >100 dB of stop band alias rejection. Table 28. DDC Example Configurations (per ADC Channel Pair) Chip Application Layer One DDC Chip Decimation Ratio 2 DDC Input Type Complex DDC Output Type Complex Bandwidth Per DDC1 40% × fS No. of Virtual Converters Required 2 Two DDCs 4 Complex Complex 20% × fS 4 Two DDCs 4 Complex Real 10% × fS 2 Two DDCs 4 Real Real 10% × fS 2 Rev. 0 | Page 64 of 135 Register Settings 0x0200 = 0x01 (one DDC; I/Q selected) 0x0201 = 0x01 (chip decimate by 2) 0x0310 = 0x83 (complex mixer; 0 dB gain; variable IF; complex outputs; HB1 filter) 0x0311 = 0x04 (DDC I Input = ADC Channel A; DDC Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0200 = 0x02 (two DDCs; I/Q selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x80 (complex mixer; 0 dB gain; variable IF; complex outputs; HB2+HB1 filters) 0x0311, 0x0331 = 0x04 (DDC I input = ADC Channel A; DDC Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x89 (complex mixer; 0 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x0311, 0x0331 = 0x04 (DDC I Input = ADC Channel A; DDC Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 Data Sheet AD9695 Chip Application Layer Two DDCs Chip Decimation Ratio 4 DDC Input Type Real DDC Output Type Complex Bandwidth Per DDC1 20% × fS No. of Virtual Converters Required 4 Two DDCs 8 Real Real 5% × fS 2 Four DDCs 8 Real Complex 10% × fS 8 Rev. 0 | Page 65 of 135 Register Settings 0x0200 = 0x02 (two DDCs; I/Q selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x40 (real mixer; 6 dB gain; variable IF; complex output; HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0200 = 0x03 (four DDCs; I/Q selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330, 0x0350, 0x0370 = 0x41 (real mixer; 6 dB gain; variable IF; complex output; HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC3 AD9695 Data Sheet Chip Application Layer Four DDCs Chip Decimation Ratio 8 DDC Input Type Real DDC Output Type Real Bandwidth Per DDC1 5% × fS No. of Virtual Converters Required 4 Four DDCs 16 Real Complex 5% × fS 8 1 fS is the ADC sample rate. Rev. 0 | Page 66 of 135 Register Settings 0x0200 = 0x23 (four DDCs; I only selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330, 0x0350, 0x0370 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC3 0x0200 = 0x03 (four DDCs; I/Q selected) 0x0201 = 0x04 (chip decimate by 16) 0x0310, 0x0330, 0x0350, 0x0370 = 0x42 (real mixer; 6 dB gain; variable IF; complex output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC3 Data Sheet AD9695 SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The results of the signal monitor block can be obtained either by reading back the internal values from the SPI port or by embedding the signal monitoring information into the JESD204B interface as special control bits. A global, 24-bit programmable period controls the duration of the measurement. Figure 82 shows the simplified block diagram of the signal monitor block. FROM MEMORY MAP SIGNAL MONITOR PERIOD REGISTER (SMPR) 0x0271, 00x272, 0x0273 DOWN COUNTER IS COUNT = 1? LOAD FROM INPUT LOAD LOAD SIGNAL MONITOR HOLDING REGISTER TO SPORT OVER JESD204B AND MEMORY MAP 15660-086 CLEAR MAGNITUDE STORAGE REGISTER COMPARE A>B Figure 82. Signal Monitor Block The peak detector captures the largest signal within the observation period. The detector only observes the magnitude of the signal. The resolution of the peak detector is a 13-bit value, and the observation period is 24 bits and represents converter output samples. The peak magnitude can be derived by using the following equation: The magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal monitor period register (SMPR). The peak detector function is enabled by setting Bit 1 of Register 0x0270 in the signal monitor control register. The 24-bit SMPR must be programmed before activating this mode. After enabling peak detection mode, the value in the SMPR is loaded into a monitor period timer, which decrements at the decimated clock rate. The magnitude of the input signal is compared with the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the SPORT over the JESD204B interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown restarts. In addition, the magnitude of the first input sample is updated in the magnitude storage register, and the comparison and update procedure, as explained previously, continues. Peak Magnitude (dBFS) = 20log(Peak Detector Value/213) Rev. 0 | Page 67 of 135 AD9695 Data Sheet significant control bit is used (see Example Configuration 1 and Example Configuration 2 in Figure 83). To select the SPORT over JESD204B option, program Register 0x0559, Register 0x055A, and Register 0x058F. See Table 47 for more information on setting these bits. SPORT OVER JESD204B The signal monitor data can also be serialized and sent over the JESD204B interface as control bits. These control bits must be deserialized from the samples to reconstruct the statistical data. The signal control monitor function is enabled by setting Bits[1:0] of Register 0x0279 and Bit 1 of Register 0x027A. Figure 83 shows two different example configurations for the signal monitor control bit locations inside the JESD204B samples. A maximum of three control bits can be inserted into the JESD204B samples; however, only one control bit is required for the signal monitor. Control bits are inserted from MSB to LSB. If only one control bit is to be inserted (CS = 1), only the most Figure 84 shows the 25-bit frame data that encapsulates the peak detector value. The frame data is transmitted MSB first with five 5-bit subframes. Each subframe contains a start bit that can be used by a receiver to validate the deserialized data. Figure 85 shows the SPORT over JESD204B signal monitor data with a monitor period timer set to 80 samples. 16-BIT JESD204B SAMPLE SIZE (N' = 16) EXAMPLE CONFIGURATION 1 (N' = 16, N = 15, CS = 1) 1-BIT CONTROL BIT (CS = 1) 15-BIT CONVERTER RESOLUTION (N = 15) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S[14] X S[13] X S[12] X S[11] X S[10] X S[9] X S[8] X S[7] X S[6] X S[5] X S[4] X S[3] X S[2] X S[1] X S[0] X CTRL [BIT 2] X SERIALIZED SIGNAL MONITOR FRAME DATA 16-BIT JESD204B SAMPLE SIZE (N' = 16) 15 S[13] X 14 13 S[12] X S[11] X 12 S[10] X 11 10 S[9] X 9 S[8] X 8 S[7] X 7 S[6] X 6 S[5] X 5 S[4] X 4 S[3] X S[2] X 3 S[1] X 2 1 0 S[0] X CTRL [BIT 2] X TAIL X SERIALIZED SIGNAL MONITOR FRAME DATA Figure 83. Signal Monitor Control Bit Locations 5-BIT SUBFRAMES 5-BIT IDLE SUBFRAME (OPTIONAL) 25-BIT FRAME IDLE 1 IDLE 1 IDLE 1 IDLE 1 IDLE 1 5-BIT IDENTIFIER START 0 SUBFRAME ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 5-BIT DATA MSB SUBFRAME START 0 P[12] P[11] P[10] P[9] 5-BIT DATA SUBFRAME START 0 P[8] P[7] P[6] P5] 5-BIT DATA SUBFRAME START 0 P[4] P[3] P[2] P1] 5-BIT DATA LSB SUBFRAME START 0 P[0] 0 0 0 P[x] = PEAK MAGNITUDE VALUE Figure 84. SPORT over JESD204B Signal Monitor Frame Data Rev. 0 | Page 68 of 135 15660-088 EXAMPLE CONFIGURATION 2 (N' = 16, N = 14, CS = 1) 15660-087 1 CONTROL 1 TAIL BIT BIT (CS = 1) 14-BIT CONVERTER RESOLUTION (N = 14) Data Sheet AD9695 SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00) 80 SAMPLE PERIOD PAYLOAD 25-BIT FRAME (N) IDENT. DATA MSB DATA DATA LSB DATA IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD PAYLOAD 25-BIT FRAME (N + 1) IDENT. DATA MSB DATA DATA LSB DATA IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE Figure 85. SPORT over JESD204B Signal Monitor Example Rev. 0 | Page 69 of 135 15660-089 PAYLOAD 25-BIT FRAME (N + 2) AD9695 Data Sheet DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE The AD9695 digital outputs are designed to the JEDEC standard JESD204B, serial interface for data converters. JESD204B is a protocol to link the AD9695 to a digital processing device over a serial interface with lane rates of up to 16 Gbps. The benefits of the JESD204B interface over LVDS include a reduction in required board area for data interface routing, and an ability to enable smaller packages for converter and logic devices. JESD204B OVERVIEW K is the number of frames per multiframe (AD9695 value = 4, 8, 12, 16, 20, 24, 28, or 32 ) S is the samples transmitted/single converter/frame cycle (AD9695 value = set automatically based on L, M, F, and N΄) HD is the high density mode (AD9695 = set automatically based on L, M, F, and N΄) CF is the number of control words/frame clock cycle/converter device (AD9695 value = 0) The JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8-bit/10-bit encoding as well as optional scrambling to form serial output data. Lane synchronization is supported through the use of special control characters during the initial establishment of the link. Additional control characters are embedded in the data stream to maintain synchronization thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, refer to the JESD204B standard. Figure 119 shows a simplified block diagram of the AD9695 JESD204B link. By default, the AD9695 is configured to use two converters and four lanes. Converter A data is output to SERDOUT0± and/or SERDOUT1±, and Converter B is output to SERDOUT2± and/or SERDOUT3±. The AD9695 allows other configurations, such as combining the outputs of both converters onto a single lane, or changing the mapping of the A and B digital output paths. These modes are customizable, and can be set up via the SPI. Refer to the Memory Map section for more details. The AD9695 JESD204B data transmit block maps up to two physical ADCs or up to eight virtual converters (when DDCs are enabled) over a link. A link can be configured to use one, two, or four JESD204B lanes. The JESD204B specification refers to a number of parameters to define the link, and these parameters must match between the JESD204B transmitter (the AD9695 output) and the JESD204B receiver (the logic device input). By default in the AD9695, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF±, or fast detect output. The JESD204B link is described according to the following parameters: The two resulting octets can be scrambled. Scrambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. The scrambler uses a self-synchronizing, polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver is a self synchronizing version of the scrambler polynomial. L is the number of lanes/converter device (lanes/link) (AD9695 value = 1, 2, or 4) M is the number of converters/converter device (virtual converters/link) (AD9695 value = 1, 2, 4, or 8) F is the octets/frame (AD9695 value = 1, 2, 4, 8, or 16) N΄ is the number of bits per sample (JESD204B word size) (AD9695 value = 8 or 16) N is the converter resolution (AD9695 value = 7 to 16) CS is the number of control bits/sample (AD9695 value = 0, 1, 2, or 3) The two octets are then encoded with an 8-bit/10-bit encoder. The 8-bit/10-bit encoder works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. Figure 119 shows how the 14-bit data is taken from the ADC, how the tail bits are added, how the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. Figure 120 shows the default data format. CONVERTER 0 CONVERTER A INPUT ADC A MUX/ FORMAT (SPI REGISTERS 0x0561, 0x0564) CONVERTER B INPUT JESD204B LINK CONTROL (L, M, F) (SPI REGISTER 0x058B, 0x058E, 0x058C) ADC B LANE MUX AND MAPPING (SPI REGISTERS 0x05B0, 0x05B2, 0x05B3, 0x05B5, 0x05B6) SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± CONVERTER 1 15660-090 SYSREF± SYNCINB± Figure 119. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00) Rev. 0 | Page 70 of 135 Data Sheet AD9695 JESD204B DATA LINK LAYER TEST PATTERNS 0x0574[2:0] JESD204B INTERFACE TEST PATTERN (0x0573, 0x0551 TO 0x0558) MSB A13 A12 A11 A10 A9 A8 ADC A7 A6 A5 A4 A3 A2 A1 LSB A0 OCTET1 TAIL BITS 0x0571[6] OCTET0 JESD204B SAMPLE CONSTRUCTION MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 A5 A4 A3 A2 A1 A0 C2 T SCRAMBLER 1 + x14 + x15 (OPTIONAL) MSB S7 S6 S5 S4 S3 S2 S1 LSB S0 S7 S6 S5 S4 S3 S2 S1 S0 SERIALIZER 8-BIT/ 10-BIT ENCODER a b i j a b SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± i j SYMBOL0 SYMBOL1 a b c d e f g h i j a b c d e f g h i j C2 C1 C0 15660-091 CONTROL BITS FRAME CONSTRUCTION OCTET1 ADC TEST PATTERNS (0x0550, 0x0551 TO 0x0558) OCTET0 JESD204B LONG TRANSPORT TEST PATTERN 0x0571[5] Figure 120. ADC Output Datapath Showing Data Framing TRANSPORT LAYER SAMPLE CONSTRUCTION FRAME CONSTRUCTION SCRAMBLER ALIGNMENT CHARACTER GENERATION 8-BIT/10-BIT ENCODER PHYSICAL LAYER CROSSBAR MUX SERIALIZER Tx OUTPUT 15660-092 PROCESSED SAMPLES FROM ADC DATA LINK LAYER SYSREF± SYNCINB± Figure 121. Data Flow FUNCTIONAL OVERVIEW Data Link Layer The block diagram in Figure 121 shows the flow of data through the JESD204B hardware from the sample input to the physical output. The processing can be divided into layers that are derived from the open source initiative (OSI) model, widely used to describe the abstraction layers of communications systems. These layers are the transport layer, data link layer, and physical layer (serializer and output driver). The data link layer is responsible for the low level functions of passing data across the link. These include optionally scrambling the data, inserting control characters during the initial lane alignment sequence (ILAS) and for frame and multiframe synchronization monitoring, and encoding 8-bit octets into 10-bit symbols. The data link layer is also responsible for sending the ILAS, which contains the link configuration data used by the receiver to verify the settings in the transport layer. Transport Layer The transport layer handles packing the data (consisting of samples and optional control bits) into JESD204B frames that are mapped to 8-bit octets. The packing of samples into frames are determined by the JESD204B configuration parameters for number of lanes (L), number of converters (M), the number of octets per lane per frame (F), the number of samples per converter per frame (S), and the number of bits in a nibble group (sometimes called the JESD204 word size − N’). Samples are mapped in order starting from Converter 0, then Converter 1, and so on until Converter M − 1. If S > 1, each sample from the converter is mapped before mapping the samples from the next converter. Each sample is mapped into words formed by appending converter control bits, if enabled, to the LSBs of each sample. The words are then padded with tail bits, if necessary, to form nibble groups (NGs) of the appropriate size as determined by the N’ parameter. The following equation can be used to determine the number of tail bits within a nibble group (JESD204B word): T = N΄ − N − CS Physical Layer The physical layer consists of the high speed circuitry clocked at the serial clock rate. In this layer, parallel data is converted into one, two, or four lanes of high speed differential serial data. JESD204B LINK ESTABLISHMENT The AD9695 JESD204B transmitter (Tx) interface operates in Subclass 0 or Sunclass 1 as defined in the JEDEC Standard JESD204B (July 2011 specification). The link establishment process is divided into the following steps: code group synchronization, initial lane alignment sequence, and user data and error correction. Code Group Synchronization (CGS) CGS is the process by which the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit block transmits /K/ characters (/K28.5/ symbols). The receiver must locate the /K/ characters in its input data stream using clock and data recovery (CDR) techniques. Rev. 0 | Page 71 of 135 AD9695 Data Sheet The receiver issues a synchronization request by asserting the SYNCINB± pin of the AD9695 low. The JESD204B Tx then begins sending /K/ characters. Once the receiver has synchronized, it waits for the correct reception of at least four consecutive /K/ symbols. It then deasserts SYNCINB±. The AD9695 then transmits an ILAS on the following local multiframe clock (LMFC) boundary. User Data and Error Detection After the initial lane alignment sequence is complete, the user data (ADC samples) is sent. During transmission of the user data, a mechanism called character replacement monitors the frame clock and multiframe clock alignment. This mechanism replaces the last octet of a frame or multiframe with an /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is enabled by default, but it can be disabled using the SPI. For more information on the code group synchronization phase, refer to the JEDEC Standard JESD204B, July 2011, Section 5.3.3.1. The SYNCINB± pin operation can also be controlled by the SPI. The SYNCINB± signal is a differential dc-coupled LVDS mode signal by default, but it can also be driven single-ended. For more information on configuring the SYNCINB± pin operation, refer to Register 0x572. For scrambled data, any 0xFC character at the end of a frame is replaced by an /F/, and any 0x7C character at the end of a multiframe is replaced with an /A/. The JESD204B receiver (Rx) checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver handles the situation by using dynamic realignment or asserting the SYNCINB± signal for more than four frames to initiate a resynchronization. For unscrambled data, if the final octet of two subsequent frames are equal, the second octet is replaced with an /F/ symbol if it is at the end of a frame, and an /A/ symbol if it is at the end of a multiframe. The SYNCINB± pins can also be configured to run in CMOS (single-ended) mode by setting Bit 4 in Register 0x572. When running SYNCINB± in CMOS mode, connect the CMOS SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20 (SYNCINB−) disconnected. Initial Lane Alignment Sequence (ILAS) The ILAS phase follows the CGS phase and begins on the next LMFC boundary after SYNCINB± deassertion. The ILAS consists of four mulitframes, with an /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by 0 to 255 ramp data for one multiframe. On the second multiframe, the link configuration data is sent, starting with the third character. The second character is a /Q/ character to confirm that the link configuration data follows. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. Insertion of alignment characters can be modified using SPI. The frame alignment character insertion (FACI) is enabled by default. More information on the link controls is available in the Memory Map section, Register 0x571. 8-Bit/10-Bit Encoder The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 31. The 8-bit/10-bit encoding ensures that the signal is dc balanced by using the same number of ones and zeros across multiple symbols. The ILAS sequence construction is shown in Figure 122. The four multiframes include the following: Multiframe 1 begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 2 begins with an /R/ character followed by a /Q/ character (/K28.4/), followed by link configuration parameters over 14 configuration octets (see Table 31) and ends with an /A/ character. Many of the parameter values are of the value – 1 notation. Multiframe 3 begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). K K R D ●●● D A R Q C ●●● C D ●●● The 8-bit/10-bit interface has options that can be controlled via the SPI. These operations include bypass and invert. These options are troubleshooting tools for the verification of the digital front end (DFE). Refer to the Memory Map section, Register 0x572, Bits[2:1] for information on configuring the 8-bit/10-bit encoder. D A R D ●●● D A R D ●●● D A D END OF MULTIFRAME ●●● START OF ILAS ●●● ●●● ●●● START OF LINK CONFIGURATION DATA ●●● START OF USER DATA Figure 122. Initial Lane Alignment Sequence Rev. 0 | Page 72 of 135 15660-093 Multiframe 4 begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Data Sheet AD9695 Table 31. AD9695 Control Characters Used in JESD204B Abbreviation /R/ /A/ /Q/ /K/ /F/ 1 Control Symbol /K28.0/ /K28.3/ /K28.4/ /K28.5/ /K28.7/ 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value, RD1 = −1 001111 0100 001111 0011 001111 0100 001111 1010 001111 1000 10-Bit Value, RD1 = +1 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment RD means running disparity. DRVDD1 SERDOUTx+ 0.1µF 100Ω DIFFERENTIAL TRACE PAIR 100Ω 0.1µF RECEIVER SERDOUTx– 15660-094 OUTPUT SWING = 0.85 × DRVDD1 V p-p DIFFERENTIAL ADJUSTABLE TO 1 × DRVDD1, 0.75 × DRVDD1 Figure 123. AC-Coupled Digital Output Termination Example PHYSICAL LAYER (DRIVER) OUTPUTS The AD9695 physical layer consists of drivers that are defined in the JEDEC Standard JESD204B, July 2011. The differential digital outputs are powered up by default. The drivers use a dynamic 100 Ω internal termination to reduce unwanted reflections. 15660-095 Digital Outputs, Timing, and Controls Figure 124. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps If there is no far end receiver termination, or if there is poor differential trace routing, timing errors can result. To avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. Figure 125. Digital Outputs Jitter Histogram, External 100 Ω Terminations at 16 Gbps 15660-097 The AD9695 digital outputs can interface with custom ASICs and field programmable gate array (FPGA) receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a single differential 100 Ω termination resistor placed as close to the receiver inputs as possible. 15660-096 Place a 100 Ω differential termination resistor at each receiver input to result in a nominal 0.85 × DRVDD1 V p-p swing at the receiver (see Figure 123). The swing is adjustable through the SPI registers. AC coupling is recommended to connect to the receiver. See the Memory Map section (Register 0x05C0 to Register 0x05C3 in Table 47) for more details. Figure 126. Digital Outputs Bathtub Curve, External 100 Ω Terminations at 16 Gbps Figure 124 to Figure 126 show an example of the digital output data eye, jitter histogram, and bathtub curve for one AD9695 lane running at 16 Gbps. The format of the output data is twos complement by default. To change the output data format, see the Memory Map section (Register 0x0561). Rev. 0 | Page 73 of 135 AD9695 Data Sheet Deemphasis Table 33. AD9695 JESD204B Initialization Deemphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. Use the deemphasis feature only when the receiver is unable to recover the clock due to excessive insertion loss. Under normal conditions, it is disabled to conserve power. Additionally, enabling and setting too high a deemphasis value on a short link can cause the receiver eye diagram to fail. Use the deemphasis setting with caution because it can increase electromagnetic interference (EMI). See the Memory Map section (Register 0x05C4 to Register 0x05CA in Table 47) for more details. Register 0x1228 0x1228 0x1222 0x1222 0x1222 0x1262 0x1262 Phase-Locked Loop (PLL) The PLL generates the serializer clock, which operates at the JESD204B lane rate. The status of the PLL lock can be checked in the PLL locked status bit (Register 0x056F, Bit 7). This read only bit notifies the user if the PLL achieved a lock for the specific setup. Register 0x056F also has a loss of lock (LOL) sticky bit (Bit 3) that notifies the user that a loss of lock is detected. The sticky bit can be reset by issuing a JESD204B link restart (Register 0x0571, Bit 0 = 0x1, followed by Register 0x0571, Bit 0 = 0x0). Refer to Table 33 for the reinitialization of the link following a link power cycle. The JESD204B lane rate control, Bits[7:4] of Register 0x056E, must be set to correspond with the lane rate. Table 32 shows the lane rates supported by the AD9695 using Register 0x056E. Table 32. AD9695 Register 0x056E Supported Lane Rates Value 0x00 0x10 0x30 0x50 Lane Rate Lane rate = 6.75 Gbps to 13.5 Lane rate = 3.375 Gbps to 6.75 Gbps (default) Lane rate = 13.5 Gbps to 16 Gbps Lane rate = 1.6875 Gbps to 3.375 Gbps The initialization SPI writes are as shown in Table 33. Number of lanes per link (L) Number of converters per link (M) Number of octets per frame (F) If the internal DDCs are used for on-chip digital processing, M represents the number of virtual converters. The virtual converter mapping setup is shown in Table 11. By default in the AD9695, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF±, or fast detect output. Control bits are filled and inserted MSB first such that enabling CS = 1 activates Control Bit 2, enabling CS = 2 activates Control Bit 2 and Control Bit 1, and enabling CS = 3 activates Control Bit 2, Control Bit 1, and Control Bit 0. The maximum lane rate allowed by the AD9695 is 16 Gbps. The lane rate is related to the JESD204B parameters using the following equation: To ensure proper operation of the AD9695 at startup, some SPI writes are required to initialize the link. Additionally, these registers must be written every time the ADC is reset. Any one of the following resets warrants the initialization routine for the digital interface: Hard reset, as with power-up. Power-up using the PDWN pin. Power-up using the SPI via Register 0x0002, Bits[1:0]. SPI soft reset by setting Register 0x0000 = 0x81. Datapath soft reset by setting Register 0x0001 = 0x02. JESD204B link power cycle by setting Register 0x0571, Bit 0 = 0x1, then 0x0. Comment Reset JESD204B start-up circuit JESD204B start-up circuit in normal operation JESD204B PLL force normal operation Reset JESD204B PLL calibration JESD204B PLL normal operation Clear loss of lock bit Loss of lock bit normal operation The AD9695 has one JESD204B link. The serial outputs (SERDOUT0± to SERDOUT3±) are considered to be part of one JESD204B link. The basic parameters that determine the link setup are SETTING UP THE AD9695 DIGITAL INTERFACE Value 0x4F 0x0F 0x00 0x04 0x00 0x08 0x00 10 M N ' f OUT 8 Lane Rate = L where fOUT = f ADC _ CLOCK Decimation Ratio The decimation ratio (DCM) is the parameter programmed in Register 0x0201. Use the following procedure to configure the output: 1. 2. 3. 4. 5. 6. 7. Rev. 0 | Page 74 of 135 Power down the link. Select the JESD204B link configuration options. Configure the detailed options. Set output lane mapping (optional). Set additional driver configuration options (optional). Power up the link. Initialize the JESD204B link by issuing the commands described in Table 33. Data Sheet AD9695 Register 0x056E must be programmed according to the lane rate calculated. Refer to the Phase-Locked Loop (PLL) section for more details. Table 34 and Table 35 show the JESD204B output configurations supported for both N΄ = 16, N’=12, and N΄ = 8 for a given number of virtual converters. Take care to ensure that the serial lane rate for a given configuration is within the supported range of 1.6875 Gbps to 16 Gbps. Table 34. JESD204B Output Configurations for N΄ = 161 Number of Virtual Converters Supported (Same as M) 1 2 4 8 Supported Decimation Rates JESD204B Serial Lane Rate2 20 × fOUT Lane Rate = 1.6875 Gbps to 3.375 Gbps 2, 4, 5, 6 Lane Rate = 3.375 Gbps to 6.75 Gbps 1, 2, 3 Lane Rate = 6.75 Gbps to 13.5 Gbps 1 Lane Rate = 13.5 Gbps to 16 Gbps N/A L 1 M 1 F 2 S 1 HD 0 N 8 to 16 N' 16 CS 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 1 1 4 2 0 8 to 16 16 0 to 3 10 × fOUT 1, 2, 3 1, N/A N/A 2 1 1 1 1 8 to 16 16 0 to 3 10 × fOUT 1, 2, 3 1 N/A N/A 2 1 2 2 0 8 to 16 16 0 to 3 5 × fOUT 1 N/A N/A N/A 4 1 1 2 1 8 to 16 16 0 to 3 5 × fOUT 1 N/A N/A N/A 4 1 2 4 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 5, 6 1, 2, 3 1 1 2 4 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 5, 6 1, 2, 3 1 1 2 8 2 0 8 to 16 16 0 to 3 20 × fOUT 4, 5, 6 1, 2, 3 1 N/A 2 2 2 1 0 8 to 16 16 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 2 2 4 2 0 8 to 16 16 0 to 3 10 × fOUT 1, 2, 3 1 N/A N/A 4 2 1 1 1 8 to 16 16 0 to 3 10 × fOUT 1, 2, 3 1 N/A N/A 4 2 2 2 0 8 to 16 16 0 to 3 80 × fOUT 8, 16, 20, 24 4, 8, 10, 12 2, 4, 6 2 1 4 8 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 5, 6 1, 2, 3 1 2 4 4 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 5, 6 1, 2, 3 1 2 4 8 2 0 8 to 16 16 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 4 4 2 1 0 8 to 16 16 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 4 4 4 2 0 8 to 16 16 0 to 3 160 × fOUT 16, 40, 48 8, 16, 20, 24 4, 8, 12 4 1 8 16 1 0 8 to 16 16 0 to 3 80 × fOUT 8, 16, 20, 24 4, 8, 10, 12 2, 4, 6 2 2 8 8 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 6 2 N/A 4 8 4 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 6 2 N/A 4 8 8 2 0 8 to 16 16 0 to 3 1 JESD204B Transport Layer Settings3 K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 3 fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 16 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤ 16,000 Mbps and > 13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13,500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32. 2 Rev. 0 | Page 75 of 135 AD9695 Data Sheet Table 35. JESD204B Output Configurations (N' = 12)1 No. of Virtual Converters Supported (Same Value as M) 1 2 4 8 JESD204B Transport Layer Settings3 Supported Decimation Rates Serial Lane Rate2 15 × fOUT Lane Rate = 1.6875 Gbps to 3.375 Gbps 3 Lane Rate = 3.375 Gbps to 6.75 Gbps N/A Lane Rate = 6.75 Gbps to 13.5 Gbps N/A Lane Rate = 13.5 Gbps to 16 Gbps N/A L 1 M 1 F 3 S 2 HD 0 N 8 to 12 N' 12 L 0 to 3 7.5 × fOUT N/A N/A N/A N/A 2 1 3 4 1 8 to 12 12 0 to 3 7.5 × fOUT N/A N/A N/A N/A 2 1 6 8 0 8 to 12 12 0 to 3 5 × fOUT 1 N/A N/A N/A 3 1 1 2 1 8 to 12 12 0 to 3 30 × fOUT 3, 6 3 N/A N/A 1 2 3 1 0 8 to 12 12 0 to 3 15 × fOUT 3 N/A N/A N/A 2 2 3 2 0 8 to 12 12 0 to 3 10 × fOUT 1, 2, 3 1 N/A N/A 3 2 1 1 1 8 to 12 12 0 to 3 7.5 × fOUT N/A N/A N/A N/A 4 2 3 4 0 8 to 12 12 0 to 3 60 × fOUT 6, 12 3, 6 3 N/A 1 4 6 1 0 8 to 12 12 0 to 3 30 × fOUT 3, 6 3 N/A N/A 2 4 3 1 0 8 to 12 12 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 3 4 2 1 1 8 to 12 12 0 to 3 15 × fOUT 3 N/A N/A N/A 4 4 3 2 0 8 to 12 12 0 to 3 60 × fOUT 6, 12 6 N/A N/A 2 8 6 1 0 8 to 12 12 0 to 3 30 × fOUT 6 N/A N/A N/A 4 8 3 1 0 8 to 12 12 0 to 3 1 K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 16 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤ 16,000 Mbps and > 13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13,500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50. 3 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32. 2 Rev. 0 | Page 76 of 135 Data Sheet AD9695 Table 32. JESD204B Output Configurations for N΄ = 81 JESD204B Transport Layer Settings3 Supported decimation rates No. of Virtual Converters Supported (Same Value as M) 1 Serial Lane Rate2 10 × fOUT Lane Rate = 1.6875 Gbps to 3.375 Gbps 1, 2, 3 Lane Rate = 3.375 Gbps to 6.75 Gbps 1 Lane Rate = 6.75 Gbps to 13.5 Gbps N/A Lane Rate = 13.5 Gbps to 16 Gbps N/A L 1 M 1 F 1 S 1 HD 0 N 7 to 8 N' 8 CS 0 to 1 1 10 × fOUT 1, 2, 3 1 N/A N/A 1 1 2 2 0 7 to 8 8 0 to 1 1 5 × fOUT 1 N/A N/A N/A 2 1 1 2 0 7 to 8 8 0 to 1 1 5 × fOUT 1 N/A N/A N/A 2 1 2 4 0 7 to 8 8 0 to 1 1 5 × fOUT 1 N/A N/A N/A 2 1 4 8 0 7 to 8 8 0 to 1 1 2.5 × fOUT N/A N/A N/A N/A 4 1 1 4 0 7 to 8 8 0 to 1 1 2.5 × fOUT N/A N/A N/A N/A 4 1 2 8 0 7 to 8 8 0 to 1 2 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 1 2 2 1 0 7 to 8 8 0 to 1 2 10 × fOUT 1, 2, 3 1 N/A N/A 2 2 1 1 0 7 to 8 8 0 to 1 2 10 × fOUT 1, 2, 3 1 N/A N/A 2 2 2 2 0 7 to 8 8 0 to 1 2 5 × fOUT 1 N/A N/A N/A 4 2 1 2 0 7 to 8 8 0 to 1 2 5 × fOUT 1 N/A N/A N/A 4 2 2 4 0 7 to 8 8 0 to 1 2 5 × fOUT 1 N/A N/A N/A 4 2 4 8 0 7 to 8 8 0 to 1 1 K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 16 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤ 16,000 Mbps and > 13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13,500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50. 3 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32. 2 Rev. 0 | Page 77 of 135 AD9695 Data Sheet Example Setup 1—Full Bandwidth Mode 1300MSPS 13GBit/sec SYNC~ F=1 VIN_B REAL 14-BIT ADC CORE 14-BIT ADC CORE L0 M0 L1 M1 JESD204B LINK (L = 4, M = 2, F = 1, S = 2, N' = 16, N = 16, CS = 0, HD = 1) L2 L3 I = REAL COMPONENT Q = QUADRATURE COMPONENT DCM = DECIMATION C2R = COMPLEX TO REAL MX = VIRTUAL CONVERTER X LY = LANE Y SZ = SAMPLE Z INSIDE A JESD204B FRAME C = CONTROL BIT (OVERRANGE, AMONG OTHERS) T = TAIL BIT M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0] 15660-098 VIN_A REAL Figure 127. Full Bandwidth Mode The AD9695 is set up as shown in Figure 127, with the following configurations: The JESD204B supported output configurations are as follows (see Table 34): Two 14-bit converters at 1300 MSPS. Full bandwidth application layer mode. Decimation filters bypassed. The JESD204B output configuration is as follows: Two virtual converters required (see Table 34). Output sample rate (fOUT) = 1300/1 = 1300 MSPS. Rev. 0 | Page 78 of 135 N΄ = 16 bits. N = 14 bits. L = 4, M = 2, and F = 1. CS = 0. K = 32. Output serial lane rate: 13 Gbps per lane (L = 4). PLL control register: Register 0x056E is set to 0x00 (L = 4). Data Sheet AD9695 Example Setup 2—ADC with DDC Option (Two ADCs Plus Two DDCs) Fs (MHz) FOUT = Fs / 4 (MHz) 40 x FOUT MbPS SYNCAB~ 14-BIT ADC CORE DDC0 (REAL INPUT, DCM = 4 C2R = BYPASS) JESD204B LINK (L = 2 M=4 F = 4, S = 1, N' = 16, N = 16, CS = 0, HD =0) M1(Q) HB2_HB1 USED VIN_B REAL 14-BIT ADC CORE DDC1 (REAL INPUT, DCM = 4 C2R = BYPASS) M2(I) LAB0 LAB1 M3(Q) M2(I)S0[15:8] M2(I)S0[7:0] M3(Q)S0[15:8] M3(Q)S0[7:0] VIN_A REAL M0(I)S0[15:8] M0(I)S0[7:0] M1(Q)S0[15:8] M1(Q)S0[7:0] F=4 M0(I) LEGEND 15660-099 I = REAL COMPONENT Q = QUADRATURE COMPONENT DCM = DECIMATION C2R = COMPLEX TO REAL MX= VIRTUAL CONVERTER X LY = LINK LANE Y SZ = SAMPLE Z INSIDE A JESD204B FRAME C = CONTROL BIT (OVER-RANGE, ETC.) T = TAIL BIT Figure 128. Two ADCs Plus Two DDCs Mode (L = 4, M = 4, F = 2, S = 1) This example shows the flexibility in the digital and lane configurations for the AD9695. The sample rate is 1300 MSPS; whereas the outputs are all combined in a combination of either two, four, or eight lanes, depending on the input/output speed capability of the receiving device. The AD9695 is set up as shown in Figure 128, with the following configuration: Two 14-bit converters at 1300 MSPS. Two DDC application layer mode with complex outputs (I/Q). Chip decimation ratio = 4. DDC decimation ratio = 4 (see the Memory Map section). The JESD204B output configuration is as follows: Four virtual converters required (see Table 34). Output sample rate (fOUT) = 1300 MSPS/4 = 325 MSPS. The JESD204B supported output configurations are as follows (see Table 34): N΄ = 16 bits. N = 14 bits. L = 2, M = 4, and F = 4, or L = 4, M = 4, and F = 4. CS = 0. K = 32. Output serial lane rate = 6.5 Gbps per lane (L = 4), 13 Gbps per lane (L = 2) For L = 2, set the PLL control register, Register 0x056E, to 0x00. For L = 4, set the PLL control register, Register 0x056E, to 0x10. Rev. 0 | Page 79 of 135 AD9695 Data Sheet DETERMINISTIC LATENCY Both ends of the JESD204B link contain various clock domains distributed throughout each system. Data traversing from one clock domain to a different clock domain can lead to ambiguous delays in the JESD204B link. These ambiguities lead to nonrepeatable latencies across the link from one power cycle or link reset to the next. Section 6 of the JESD204B specification addresses the issue of deterministic latency with mechanisms defined as Subclass 1 and Subclass 2. boundaries and buffering to achieve consistent latency across lanes (or even multiple devices), and to achieve a fixed latency between power cycles and link reset conditions. Deterministic Latency Requirements Several key factors are required for achieving deterministic latency in a JESD204B Subclass 1 system: The AD9695 supports JESD204B Subclass 0 and Subclass 1 operation. Register 0x0590, Bit 5 sets the subclass mode for the AD9695; the default mode is the Subclass 1 operating mode (Register 0x0590, Bit 5 = 1). If deterministic latency is not a system requirement, Subclass 0 operation is recommended and the SYSREF± signal may not be required. Even in Subclass 0 mode, the SYSREF± signal may be required in an application where multiple AD9695 devices must be synchronized with each other. This topic is addressed in the Timestamp Mode section. SYSREF± signal distribution skew within the system must be less than the desired uncertainty for the system. SYSREF± setup and hold time requirements must be met for each device in the system. The total latency variation across all lanes, links, and devices must be ≤1 LMFC period (see Figure 129). This includes both variable delays and the variation in fixed delays from lane to lane, link to link, and device to device in the system. Setting Deterministic Latency registers SUBCLASS 0 OPERATION The JESD204B receive buffer in the logic device buffers data starting on the LMFC boundary. If the total link latency in the system is near an integer multiple of the LMFC period, it is possible that from one power cycle to the next, the data arrival time at the receive buffer may straddle an LMFC boundary. To ensure deterministic latency in this case, a phase adjustment of the LMFC at either the transmitter or receiver must be performed. Typically, adjustments to accommodate the receive buffer are made to the LMFC of the receiver. In the AD9695, this adjustment can be made using the LMFC offset bits (Register 0x578, Bits[4:0]). These bits delay the LMFC in frame clock increments, depending on the F parameter, which is the number of octets per lane per frame). For F = 1, every fourth setting (0, 4, 8, …, and so on) results in a one frame clock shift. For F = 2, every other setting (0, 2, 4, …, and so on) results in a 1-frame clock shift. For all other values of F, each setting results in a 1-frame clock shift. If there is no requirement for multichip synchronization while operating in Subclass 0 mode (Register 0x0590, Bit 5 = 0), the SYSREF± input can be left disconnected. In this mode, the relationship of the JESD204B clocks between the JESD204B transmitter and receiver are arbitrary but does not affect the ability of the receiver to capture and align the lanes within the link. SUBCLASS 1 OPERATION The JESD204B protocol organizes data samples into octets, frames, and multiframes as described in the Transport Layer section. The LMFC is synchronous with the beginnings of these multiframes. In Subclass 1 operation, the SYSREF± signal synchronizes the LMFCs for each device in a link or across multiple links (within the AD9695, SYSREF± also synchronizes the internal sample dividers). This synchronization is shown in Figure 129. The JESD204B receiver uses the multiframe SYSREF DEVICE CLOCK SYSREF-ALIGNED GLOBAL LMFC SYSREF TO LMFC DELAY ALL LMFCs DATA ILAS Figure 129. SYSREF± and LMFC Rev. 0 | Page 80 of 135 DATA 15660-100 POWER CYCLE VARIATION (MUST BE < tLMFC) Data Sheet AD9695 Figure 130 shows that, in the case where the link latency is near an LMFC boundary, the local LMFC of the AD9695 can be delayed to in turn delay the data arrival time at the receiver. Figure 131 shows how the LMFC of the receiver is delayed to accommodate the receive buffer timing. Refer to the applicable JESD204B receiver user guide for details on making this adjustment. If the total latency in the system is not near an integer multiple of the LMFC period, or if the appropriate adjustments are made to the LMFC phase at the clock source, it is still possible to have variable latency from one power cycle to the next. In this case, check for the possibility that the setup and hold time requirements for the SYSREF± signal are not being met. Perform this check by reading the SYSREF± setup and hold monitor register (Register 0x0128). This function is described in the SYSREF± Setup/Hold Window Monitor section. If reading Register 0x0128 indicates a timing problem, there are adjustments that can made in the AD9695. Changing the SYSREF± level used for alignment is possible using the SYSREF± transition select bit (Register 0x0120, Bit 4). Also, changing which edge of the clock is used to capture SYSREF± can be performed using the clock edge select bit (Register 0x0120, Bit 3). Both of these options are described in the SYREF± Control Features section. If neither of these measures help achieve an acceptable setup and hold time, adjusting the phase of SYSREF± and/or the device clock (CLK±) may be required. POWER CYCLE VARIATION LMFCTX DELAY TIME SYSREF-ALIGNED GLOBAL LMFC Tx LOCAL LMFC ILAS DATA (AT Rx INPUT) DATA ILAS DATA Tx LMFC MOVED (DELAYING THE ARRIVAL OF DATA RELATIVE TO THE GLOBAL LMFC) SO THE RECIEVE BUFFER RELEASE TIME IS ALWAYS REFERENCED TO THE SAME LMFC EDGE 15660-101 DATA (AT Tx INPUT) Figure 130. Adjusting the JESD204B Tx LMFC in the AD9695 LMFCRX DELAY TIME POWER CYCLE VARIATION SYSREF-ALIGNED GLOBAL LMFC DATA (AT Tx INPUT) DATA (AT Rx INPUT) DATA ILAS ILAS ILAS DATA Rx LMFC MOVED SO THE RECEIVE BUFFER RELEASE TIME IS ALWAYS REFERENCED TO THE SAME LMFC EDGE Figure 131. Adjusting the JESD204B Rx LMFC in the Logic Device Rev. 0 | Page 81 of 135 15660-102 Rx LOCAL LMFC AD9695 Data Sheet MULTICHIP SYNCHRONIZATION The flowchart shown in Figure 133 describes the internal mechanism for multichip synchronization in the AD9695. There are two methods by which multichip synchronization can take place, as determined by the chip synchronization mode bit (Register 0x1FF , Bit 0). Each method involves different applications of the SYSREF± signal. timestamp method is used for synchronization of multiple channels and/or devices. In timestamp mode, the clocks are not reset but instead, the coinciding sample is time stamped using the JESD204B control bits of that sample. To operate in timestamp mode, the following additional settings are necessary: Continuous or N-shot SYSREF enabled (Register 0x0120, Bits[2:1] = 1 or 2). At least one control bit must be enabled (CS > 0, Register 0x058F, Bits[7:6] = 1, 2, or 3). Set the function for one of the control bits to SYSREF: Register 0x0559, Bits[2:0] = 5 if using Control Bit 0. Register 0x0559, Bits[6:4] = 5 if using Control Bit 1. Register 0x055A, Bits[2:0] = 5 if using Control Bit 2. NORMAL MODE The default sate of the chip synchronization mode bit is 0, which configures the AD9695 for normal chip synchronization. The JESD204B standard specifies the use of SYSREF± to provide deterministic latency within a single link. This same concept, when applied to a system with multiple converters and logic devices, can also provide multichip synchronization. In Figure 133, this is referred to as normal mode. Following the process outlined in the flowchart ensures that the AD9695 is configured appropriately. Consult the logic devices user intellectual property (IP) guide to ensure that the JESD204B receivers are configured appropriately. TIMESTAMP MODE For all AD9695 full bandwidth operating modes, the SYSREF± input can also be used to timestamp samples. This is another method by which multiple channels and multiple devices can achieve synchronization. This is especially effective when synchronizing multiple devices to one or more logic devices. The logic devices buffer the data streams, identify the time stamped samples, and align them. When the chip synchronization mode bit (Register 0x1FF, Bit 0) is set to 1, the Enable control bits MSB first. In other words, if only using one control bit (CS = 1), then Control Bit 2 must be enabled. If two control bits are used, then Control Bits[2:1] must be enabled. Figure 132 shows how the input sample coincident with SYSREF± is time stamped and ultimately output of the ADC. In this example, there are two control bits and Control Bit 1 is the bit indicating which sample was coincident with the SYSREF rising edge. Note that the pipeline latencies for each channel are identical. If so desired, the SYSREF timestamp delay register (Register 0x0123) can be used to adjust the timing of which sample is time stamped. Note that time stamping is not supported by any AD9695 operating modes that use decimation. 14-BIT SAMPLES OUT N–1 N+1 N+2 N+3 N – 1 00 N CONTROL BIT 0 USED TO TIME STAMP SAMPLE N ENCODE CLK SYSREF AINB 01 N + 1 00 N + 2 00 N + 3 00 CHANNEL A N–1 N CHANNEL B N+1 N+2 N – 1 00 N 01 N + 1 00 N + 2 00 N + 3 00 N+3 2 CONTROL BITS 15660-103 AINA N Figure 132. AD9695 Timestamping—CS = 2 (Register 0x058F, Bits[7:6] = 2), Control Bit 1 is SYSREF± (Register 0x0559, Bits[6:4] = 5) Rev. 0 | Page 82 of 135 Data Sheet AD9695 INCREMENT SYSREF IGNORE COUNTER START NO NO RESET SYSREF IGNORE COUNTER NO SYSREF ENABLED? (0x0120) YES SYSREF ASSERTED? SYSREF MODE (0x0120) YES SYSREF IGNORE COUNTER EXPIRED? (0x0121) N-SHOT MODE YES CONTINUOUS MODE CLEAR SYSREF IGNORE COUNTER AND DISABLE SYSREF (CLEAR BIT 2 IN 0x0120) UPDATE SETUP/HOLD DETECTOR STATUS (0x0128) ALIGN CLOCK DIVIDER PHASE TO SYSREF YES INPUT CLOCK DIVIDER ALIGNMENT REQUIRED? NO SYNCHRONIZATION MODE? (0x01FF) TIMESTAMP MODE SYSREF TIMESTAMP DELAY (0x0123) YES CLOCK DIVIDER AUTO ADJUST ENABLED? CLOCK DIVIDER >1? (0x010B) YES NO INCREMENT SYSREF COUNTER (0x012A) NO SYSREF ENABLED IN CONTROL BITS? (0x0559, 0x055A, 0x058F) SYSREF INSERTED IN JESD204B CONTROL BITS YES NO RAMP TEST MODE ENABLED? (0x0550) NORMAL MODE SYSREF RESETS RAMP TEST MODE GENERATOR YES BACK TO START NO JESD204B LMFC ALIGNMENT REQUIRED? YES ALIGN PHASE OF ALL INTERNAL CLOCKS (INCLUDING LMFC) TO SYSREF SEND INVALID 8-BIT/ 10-BIT CHARACTERS (ALL 0s) SYNC~ ASSERTED NO NO SEND K28.5 CHARACTERS NORMAL JESD204B INITIALIZATION NO YES ALIGN SIGNAL MONITOR COUNTERS DDC NCO ALIGNMENT ENABLED? (0x0300) YES ALIGN DDC NCO PHASE ACCUMULATOR BACK TO START NO 15660-104 SIGNAL MONITOR ALIGNMENT ENABLED? (0x026F) YES Figure 133. SYSREF± Capture Scenarios and Multichip Synchronization Rev. 0 | Page 83 of 135 AD9695 Data Sheet SETUP REQUIREMENT –70ps HOLD REQUIREMENT 120ps SYSREF KEEP OUT WINDOW The input clock divider, DDCs, signal monitor block, and JESD204B link are all synchronized using the SYSREF± input when in normal synchronization mode (Register 0x01FF, Bits[1:0] = 0). The SYSREF± input can also be used to time stamp an ADC sample to provide a mechanism for synchronizing multiple AD9695 devices in a system. For the highest level of timing accuracy, SYSREF± must meet the setup and hold requirements relative to the CLK± input. There are several features in the AD9695 to ensure these requirements are met (see the SYREF± Control Features section). SYREF± Control Features SYSREF± is used, along with the input clock (CLK±), as part of a source synchronous timing interface and requires setup and hold timing requirements of 117 ps and −96 ps, relative to the input clock (see Figure 134). The AD9695 has several features to meet these requirements. First, the SYSREF± sample event can be defined as either a synchronous low to high transition or synchronous high to low transition. Second, the AD9695 allows the SYSREF± signal to be sampled using either the rising edge or falling edge of the input clock. Figure 134, Figure 135, Figure 136, and Figure 137 show all four possible combinations. 15660-105 CLK Figure 134. SYSREF± Setup and Hold Time Requirements; SYSREF± Low to High Transition Using the Rising Edge Clock (Default) SETUP REQUIREMENT –70ps LMFC = ADC Clock/S × K HOLD REQUIREMENT 120ps SYSREF SAMPLE POINT CLK 15660-106 where: S is the the JESD204B parameter for number of samples per converter. K is JESD204B parameter for number of frames per multiframe. SYSREF SAMPLE POINT SYSREF Figure 135. SYSREF± Low to High Transition Using Falling Edge Clock Capture (Register 0x0120, Bit 4 = 1’b0 and Register 0x0120, Bit 3 = 1’b1) SETUP REQUIREMENT –70ps HOLD REQUIREMENT 120ps SYSREF SAMPLE POINT CLK 15660-107 The SYSREF± input signal is used as a high accuracy system reference for deterministic latency and multichip synchronization. The AD9695 accepts a single-shot or periodic input signal. The SYSREF± mode select bits (Register 0x0120, Bits[2:1]) select the input signal type and also arm the SYSREF± state machine when set. If in single- (or N) shot mode (Register 0x0120, Bits[2:1] = 2), the SYSREF± mode select bit self clears after the appropriate SYSREF± transition is detected. The pulse width must have a minimum width of two CLK± periods. If the clock divider (Register 0x010B, Bits[2:0]) is set to a value other than divide by 1, then multiply this minimum pulse width requirement by the divide ratio (for emample, if set to divide by 8, the minimum pulse width is 16 CLK± cycles). When using a continuous SYSREF± signal (Register 0x0120, Bits[2:1] = 1), the period of the SYSREF± signal must be an integer multiple of the LMFC. Derive the LMFC using the following formula: labeled as N-shot mode. The AD9695 is able to ignore N SYSREF± events, which is useful to handle periodic SYSREF± signals that require time to settle after startup. Ignoring SYSREF± until the clocks in the system have settled avoids an inaccurate SYSREF± trigger. Figure 138 shows an example of the SYSREF± ignore feature when ignoring three SYSREF± events. SYSREF Figure 136. SYSREF± High to Low Transition Using Rising Edge Clock Capture (Register 0x0120, Bit 4 = 1’b1 and Register 0x0120, Bit 3 = 1’b0) SETUP REQUIREMENT –70ps HOLD REQUIREMENT 120ps SYSREF SAMPLE POINT CLK SYSREF Figure 137. SYSREF± High to Low Transition Using Falling Edge Clock Capture (Register 0x0120, Bit 4= 1’b1 and Register 0x0120, Bit 3 = 1’b1) The third SYSREF± related feature available is the ability to ignore a programmable number (up to 16) of SYSREF± events. The SYSREF± ignore feature is enabled by setting the SYSREF± mode register (Register 0x0120, Bits[2:1]) to 2’b10, which is Rev. 0 | Page 84 of 135 15660-108 SYSREF± INPUT Data Sheet AD9695 SYSREF SAMPLE PART 1 SYSREF SAMPLE PART 2 SYSREF SAMPLE PART 3 SYSREF SAMPLE PART 4 SYSREF SAMPLE PART 5 CLK 15660-109 SYSREF SAMPLE THE FOURTH SYSREF IGNORE FIRST THREE SYSREFs Figure 138. SYSREF± Ignore Example; SYSREF± Ignore Count Bits (Register 0x0121, Bits[3:0]) = 3 SYSREF SKEW WINDOW = ±3 SYSREF SKEW WINDOW = ±2 SYSREF SKEW WINDOW = ±1 SYSREF SKEW WINDOW = 0 15660-110 SAMPLE CLOCK SYSREF Figure 139. SYSREF± Skew Window When in continuous SYSREF± mode (Register 0x0120, Bits[2:1] = 1), the AD9695 monitors the placement of the SYSREF± leading edge compared to the internal LMFC. If the SYSREF± edge is captured with a clock edge other than the one that is aligned with LMFC, the AD9695 initiates a resynchronization of the link. Because the input clock rates for the AD9695 can be up to 4 GHz, the AD9695 provides another SYSREF± related feature that makes it possible to accommodate periodic SYSREF± signals where cycle accurate capture is not feasible or not required. For these scenarios, the AD9695 has a programmable SYSREF± skew window that allows the internal dividers to remain undisturbed, unless SYSREF± occurs outside the skew window. The resolution of the SYSREF± skew window is set in sample clock cycles. If the SYSREF± negative skew window is 1 and the positive skew window is 1, then the total skew window is ±1 sample clock cycles, meaning that, as long as SYSREF± is captured within ±1 sample clock cycle of the clock that is aligned with LMFC, the link continues to operate normally. If the SYSREF± has jitter, which can cause a misalignment between SYSREF± and the LMFC, the system continues to run without a resynchronization, while still allowing the device to monitor for larger errors not caused by jitter. For the AD9695, the positive and negative skew window is controlled by the SYSREF± window negative bits (Register 0x0122, Bits[3:2]) and the SYSREF± window positive bits (Register 0x0122, Bits[1:0]). Figure 139 shows information on the location of the skew window settings relative to Phase 0 of the internal dividers. Negative skew is defined as occurring before the internal dividers reach Phase 0 and positive skew is defined after the internal dividers reach Phase 0. Rev. 0 | Page 85 of 135 AD9695 Data Sheet SYSREF± SETUP/HOLD WINDOW MONITOR To ensure a valid SYSREF± signal capture, the AD9695 has a SYSREF± setup/hold window monitor. This feature allows the system designer to determine the location of the SYSREF± signals relative to the CLK± signals by reading back the amount of setup/hold margin on the interface through the memory map. Figure 140 and Figure 141 show the setup and hold status values for different phases of SYSREF±. The setup detector returns the status of the SYSREF± signal before the CLK± edge, and the hold detector returns the status of the SYSREF signal after the CLK± edge. Register 0x0128 stores the status of SYSREF± and lets the user know if the SYSREF± signal is captured by the ADC. Table 37 describes the contents of Register 0x0128 and how to interpret them. 0xF 0xE 0xD 0xC 0xB 0xA 0x9 REG 0x0128[3:0] 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 CLK± INPUT VALID SYSREF± INPUT FLIP-FLOP HOLD (MIN) FLIP-FLOP HOLD (MIN) Figure 140. SYSREF± Setup Detector Rev. 0 | Page 86 of 135 15660-111 FLIP-FLOP SETUP (MIN) Data Sheet AD9695 0xF 0xE 0xD 0xC 0xB 0xA 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 REG 0x0128[7:4] 0x0 CLK± INPUT SYSREF± INPUT FLIP-FLOP SETUP (MIN) FLIP-FLOP HOLD (MIN) FLIP-FLOP HOLD (MIN) 15660-112 VALID Figure 141. SYSREF± Hold Detector Table 37. SYSREF± Setup/Hold Monitor, Register 0x0128 Register 0x0128, Bits[7:4] Hold Status 0x0 0x0 to 0x8 0x8 0x8 0x9 to 0xF 0x0 Register 0x0128, Bits[3:0] Setup Status 0x0 to 0x7 0x8 0x9 to 0xF 0x0 0x0 0x0 Description Possible setup error. The smaller this number, the smaller the setup margin. No setup or hold error (best hold margin). No setup or hold error (best setup and hold margin). No setup or hold error (best setup margin). Possible hold error. The larger this number, the smaller the hold margin. Possible setup or hold error. Rev. 0 | Page 87 of 135 AD9695 Data Sheet LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS Total latency in the AD9695 is dependent on the chip application mode and the JESD204B configuration. For any given combination of these parameters, the latency is deterministic, however, the value of this deterministic latency must be calculated as described in the Example Latency Calculations section. Example Configuration 1 is as follows: Table 38 shows the combined latency through the ADC and DSP for the different chip application modes supported by the AD9695. Table 37 shows the latency through the JESD204B block for each application mode based on the M/L ratio. For both tables, latency is typical and is in units of the encode clock. The latency through the JESD204B block does not depend on the output data type (real or complex). Therefore, data type is not included in Table 37. To determine the total latency, select the appropriate ADC + DSP latency from Table 34 and add it to the appropriate JESD204B latency from Table 35. Example calculations are provided in the following section. ADC application mode = full bandwidth Real outputs L = 4, M = 2, F = 1, S = 1 (JESD204B mode) M/L = 0.5 Latency = 31 + 25 = 56 encode clocks Example Configuration 2 is as follows: ADC application mode = DCM4 Complex outputs L = 2, M = 2, F = 2, S = 1 (JESD204B mode) M/L = 1 Latency = 162 + 50 = 212 encode clocks LMFC REFERENCED LATENCY Some FPGA vendors may require the end user to know LMFC referenced latency to make appropriate deterministic latency adjustments. If they are required, the latency values in Table 38 and Table 39 can be used for the analog input to LMFC and LMFC to data output latency values, respectively. Rev. 0 | Page 88 of 135 Data Sheet AD9695 Table 38. Latency Through the ADC + DSP Blocks (Number of Sample Clocks)1 Chip Application Mode Full Bandwidth DCM1 (Real) DCM2 (Complex) DCM3 (Complex) DCM2 (Real) DCM4 (Complex) DCM3 (Real) DCM6 (Complex) DCM4 (Real) DCM8 (Complex) DCM5 (Real) DCM10 (Complex) DCM6 (Real) DCM12 (Complex) DCM15 (Real) DCM8 (Real) DCM16 (Complex) DCM10 (Real) DCM20 (Complex) DCM12 (Real) DCM24 (Complex) DCM30 (Complex) DCM20 (Real) DCM40 (Complex) DCM24 (Real) DCM48 (Complex) 1 Enabled Filters Not applicable HB1 HB1 TB1 HB2 + HB1 HB2 + HB1 TB2 + HB1 TB2 + HB1 HB3 +HB2 + HB1 HB3 +HB2 + HB1 FB2 + HB1 FB2 + HB1 TB2 + HB2 + HB1 TB2 + HB2 + HB1 FB2 + TB1 HB4 + HB3 + HB2 + HB1 HB4 + HB3 + HB2 + HB1 FB2 + HB2 + HB1 FB2 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 HB2 + FB2 + TB1 FB2 + HB3 + HB2 + HB1 FB2 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 ADC + DSP Latency 31 90 90 102 162 162 212 212 292 292 380 380 424 424 500 552 552 694 694 814 814 836 1420 1420 1594 1594 DCMx indicates the decimation ratio. Table 39. Latency Through JESD204B Block (Number of Sample Clocks)1 Chip Application Mode Full Bandwidth DCM1 DCM2 DCM3 DCM4 DCM5 DCM6 DCM8 DCM10 DCM12 DCM15 DCM16 DCM20 DCM24 DCM30 DCM40 DCM48 0.125 82 82 160 237 315 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.25 44 44 84 124 164 2033 243 323 N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.5 25 25 46 67 88 1093 130 172 213 255 3184 3394 N/A N/A N/A N/A N/A 1 M/L Ratio2 1 14 14 27 39 50 623 73 96 119 142 1764 1884 233 279 3484 N/A N/A N/A means not applicable and indicates that the application mode is not supported at the M/L ratio listed. M/L ratio is the number of converters divided by the number of lanes for the configuration. 3 The application mode at the M/L ratio listed is only supported in real output mode. 4 The application mode at the M/L ratio listed is only supported in complex output mode. 2 Rev. 0 | Page 89 of 135 2 7 7 14 21 27 433 39 50 62 73 904 964 119 142 1764 2334 2794 4 9 N/A 7 11 14 N/A 21 27 33 39 474 504 62 73 904 1194 1424 8 3 N/A N/A N/A 9 N/A 14 18 22 27 334 354 43 51 624 824 974 AD9695 Data Sheet TEST MODES If the application mode is set to select a DDC mode of operation, the test modes must be enabled for each DDC enabled. The test patterns can be enabled via Bit 2 and Bit 0 of Register 0x0327, Register 0x0347, and Register 0x0367, depending on which DDC(s) are selected. The (I) data uses the test patterns selected for Channel A, and the (Q) data uses the test patterns selected for Channel B. For DDC3 only, the (I) data uses the test patterns from Channel A, and the (Q) data does not output test patterns. Bit 0 of Register 0x0387 selects the Channel A test patterns to be used for the (I) data. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. ADC TEST MODES The AD9695 has various test options that aid in the system level implementation. The AD9695 has ADC test modes that are available in Register 0x0550. These test modes are described in Table 36. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks, and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting and some are not. The pseudorandom number (PN) generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0550. These tests can be performed with or without an analog signal (if present, the analog signal is ignored); however, they do require an encode clock. JESD204B INTERFACE TEST PATTERN (REG 0x573, REG 0x551 TO REG 0x558) JESD204B LONG TRANSPORT TEST PATTERN REG 0x571[5] SERIALIZER MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 A5 A4 A3 A2 A1 A0 C2 T MSB S7 S6 S5 S4 S3 S2 S1 LSB S0 S7 S6 S5 S4 S3 S2 S1 S0 8-BIT/10-BIT ENCODER a b c d e f g h i j a b SERDOUT0± SERDOUT1± i j a b SYMBOL0 i j SYMBOL1 a b c d e f g h i j 15660-214 TAIL BITS 0x571[6] SCRAMBLER 1 + x14 + x15 (OPTIONAL) OCTET 1 JESD204B SAMPLE CONSTRUCTION MSB A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 LSB A0 OCTET 1 OCTET 0 FRAME CONSTRUCTION OCTET 0 ADC TEST PATTERNS (RE0x550, REG 0x551 TO REG 0x558) ADC JESD204B DATA LINK LAYER TEST PATTERNS REG 0x574[2:0] C2 CONTROL BITS C1 C0 Figure 142. ADC Output Datapath Showing Data Framing Table 36. ADC Test Modes1 Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 Pattern Name Off (default) Midscale short Positive full-scale short Negative full-scale short Checkerboard PN sequence long PN sequence short One-/zero-word toggle User input Expression N/A 0000 0000 0000 01 1111 1111 1111 10 0000 0000 0000 10 1010 1010 1010 x23 + x18 + 1 x9 + x5 + 1 11 1111 1111 1111 Register 0x0551 to Register 0x0558 1111 Ramp output (x) % 214 1 Default/ Seed Value N/A N/A N/A N/A N/A 0x3AFF 0x0092 N/A N/A N/A N/A means not applicable. Rev. 0 | Page 90 of 135 Sample (N, N + 1, N + 2, …) N/A N/A N/A N/A 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6 0x125B, 0x3C9A, 0x2660, 0x0C65, 0x0697 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000 User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2] … for repeat mode. User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], 0x0000 … for single mode. (x) % 214, (x +1) % 214, (x +2) % 214, (x +3) % 214 Data Sheet AD9695 JESD204B BLOCK TEST MODES In addition to the ADC pipeline test modes, the AD9695 also has flexible test modes in the JESD204B block. These test modes are listed in Register 0x0573 and Register 0x0574. These test patterns can be injected at various points along the output datapath. These test injection points are shown in Figure 142. Table 37 describes the various test modes available in the JESD204B block. For the AD9695, a transition from test modes (Register 0x0573 ≠ 0x00) to normal mode (Register 0x0573 = 0x00) requires an SPI soft reset. This is done by writing 0x81 to Register 0x0000 (self cleared). Transport Layer Sample Test Mode The transport layer samples are implemented in the AD9695 as defined by Section 5.1.6.3 in the JEDEC JESD204B specification. These tests are shown in Register 0x0571, Bit 5. The test pattern is equivalent to the raw samples from the ADC. Interface Test Modes The interface test modes are described in Register 0x0573, Bits[3:0]. These test modes are also explained in Table 37. The interface tests can be injected at various points along the data. See Figure 142 for more information on the test injection points. Register 0x0573, Bits[5:4] show where these tests are injected. Table 38, Table 39, and Table 40 show examples of some of the test modes when injected at the JESD sample input, PHY 10-bit input, and scrambler 8-bit input. UPx in the tables represent the user pattern control bits from the customer register map. Table 37. JESD204B Interface Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1110 1111 Pattern Name Off (default) Alternating checker board 1/0 word toggle 31-bit PN sequence 23-bit PN sequence 15-bit PN sequence 9-bit PN sequence 7-bit PN sequence Ramp output Continuous/repeat user test Single user test Expression Not applicable 0x5555, 0xAAAA, 0x5555, … 0x0000, 0xFFFF, 0x0000, … x31 + x28 + 1 x23 + x18 + 1 x15 + x14 + 1 x9 + x5 + 1 x7 + x6 + 1 (x) % 216 Register 0x0551 to Register 0x0558 Register 0x0551 to Register 0x0558 Default Not applicable Not applicable Not applicable 0x0003AFFF 0x003AFF 0x03AF 0x092 0x07 Ramp size depends on test injection point User Pattern 1 to User Pattern 4, then repeat User Pattern 1 to User Pattern 4, then zeros Table 38. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00) Frame Number 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 Converter Number 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Sample Number 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Alternating Checkerboard 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 1/0 Word Toggle 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 Ramp (x) % 216 (x) % 216 (x) % 216 (x) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 (x +4) % 216 (x +4) % 216 (x +4) % 216 (x +4) % 216 Rev. 0 | Page 91 of 135 PN9 0x496F 0x496F 0x496F 0x496F 0xC9A9 0xC9A9 0xC9A9 0xC9A9 0x980C 0x980C 0x980C 0x980C 0x651A 0x651A 0x651A 0x651A 0x5FD1 0x5FD1 0x5FD1 0x5FD1 PN23 0xFF5C 0xFF5C 0xFF5C 0xFF5C 0x0029 0x0029 0x0029 0x0029 0xB80A 0xB80A 0xB80A 0xB80A 0x3D72 0x3D72 0x3D72 0x3D72 0x9B26 0x9B26 0x9B26 0x9B26 User Repeat UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] User Single UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] 0x0000 0x0000 0x0000 0x0000 AD9695 Data Sheet Table 39. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 'b01) 10-Bit Symbol Number 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 1/0 Word Toggle 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF Ramp (x) % 210 (x + 1) % 210 (x + 2) % 210 (x + 3) % 210 (x + 4) % 210 (x + 5) % 210 (x + 6) % 210 (x + 7) % 210 (x + 8) % 210 (x + 9) % 210 (x + 10) % 210 (x + 11) % 210 PN9 0x125 0x2FC 0x26A 0x198 0x031 0x251 0x297 0x3D1 0x18E 0x2CB 0x0F1 0x3DD PN23 0x3FD 0x1C0 0x00A 0x1B8 0x028 0x3D7 0x0A6 0x326 0x10F 0x3FD 0x31E 0x008 User Repeat UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] User Single UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 Table 40. Scrambler 8-Bit Input (Register 0x0573, Bits[5:4] = 'b10) 8-Bit Octet Number 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 1/0 Word Toggle 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF Ramp (x) % 28 (x + 1) % 28 (x + 2) % 28 (x + 3) % 28 (x + 4) % 28 (x + 5) % 28 (x + 6) % 28 (x + 7) % 28 (x + 8) % 28 (x + 9) % 28 (x + 10) % 28 (x + 11) % 28 Data Link Layer Test Modes The data link layer test modes are implemented in the AD9695 as defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification. These tests are shown in Register 0x0574, PN9 0x49 0x6F 0xC9 0xA9 0x98 0x0C 0x65 0x1A 0x5F 0xD1 0x63 0xAC PN23 0xFF 0x5C 0x00 0x29 0xB8 0x0A 0x3D 0x72 0x9B 0x26 0x43 0xFF User Repeat UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] User Single UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Bits[2:0]. Test patterns inserted at this point are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINB± by writing 0xC0 to Register 0x0572. Rev. 0 | Page 92 of 135 Data Sheet AD9695 SERIAL PORT INTERFACE (SPI) The AD9695 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the Serial Control Interface Standard (Rev. 1.0). CONFIGURATION USING THE SPI Three pins define the SPI of the AD9695 ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 41). The SCLK (serial clock) pin is used to synchronize the read and write data presented to and from the ADC. The SDIO (serial data input/ output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 41. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input that is used to synchronize serial interface, reads, and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 4 and Table 5. Other modes involving the CSB pin are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued, which allows the SDIO pin to change direction from an input to an output. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the Serial Control Interface Standard (Rev. 1.0). HARDWARE INTERFACE The pins described in Table 41 comprise the physical interface between the user programming device and the serial port of the AD9695. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. Do not activate the SPI port during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9695 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SPI ACCESSIBLE FEATURES Table 42 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the Serial Control Interface Standard (Rev. 1.0). The AD9695 device specific features are described in the Memory Map section. Table 42. Features Accessible Using the SPI Feature Name Mode Clock DDC Test Input/Output Output Mode SERDES Output Setup Description Allows the user to set either power-down mode or standby mode. Allows the user to access the clock divider via the SPI. Allows the user to set up decimation filters for different applications. Allows the user to set test modes to have known data on output bits. Allows the user to set up outputs. Allows the user to vary SERDES settings such as swing and emphasis. Rev. 0 | Page 93 of 135 AD9695 Data Sheet MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Default Values Each row in the memory map register table has eight bit locations. The memory map is divided into the following sections: After the AD9695 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 47. Logic Levels Analog Devices SPI registers (Register 0x0000 to Register 0x000F) Clock/SYSREF/chip power-down pin control registers (Register 0x003F to Register 0x0201) Fast detect and signal monitor control registers (Register 0x0245 to Register 0x027A) DDC function registers (Register 0x0300 to Register 0x03CD) Digital outputs and test modes registers (Register 0x0550 to Register 0x05CB) Programmable filter control and coefficients registers (Register 0x0DF8 to Register 0x0F7F) VREF/analog input control registers (Register 0x18A6 to Register 0x1A4D) Table 47 (see the Memory Map Register Details section) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x0561, the output sample mode register, has a hexadecimal default value of 0x01, which means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see Table 47. Open and Reserved Locations An explanation of logic level terminology follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” X denotes a don’t care bit. Channel Specific Registers Some channel setup functions, such as the input buffer control register (Register 0x1A4C), can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 47 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x0008. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an SPI read cycle, the device returns the value for Channel A. Registers and bits designated as global in Table 47 affect the entire device and the channel features for which independent settings are not allowed between channels. The settings in Register 0x0005 do not affect the global registers and bits. SPI Soft Reset All address and bit locations that are not included in Table 47 are not currently supported for this device. Write unused bits of a valid address location with 0s unless the default value is set otherwise. Writing to these locations is required only when part of an address location is unassigned (for example, Address 0x0561). If the entire address location is open (for example, Address 0x0013), do not write to this address location. After issuing a soft reset by programming 0x81 to Register 0x0000, the AD9695 requires 5 ms to recover. When programming the AD9695 for application setup, ensure that an adequate delay is programmed into the firmware after asserting the soft reset and before starting the device setup. Rev. 0 | Page 94 of 135 Data Sheet AD9695 MEMORY MAP REGISTERS All address locations that are not included in Table 47 are not currently supported for this device and must not be written. Table 47. Memory Map Registers Address Name Analog Devices SPI Registers 0x0000 SPI Configuration A Bits Bit Name Settings 7 Soft reset mirror (self clearing) 0 1 6 LSB first mirror 1 0 5 Address ascension mirror 0 1 [4:3] 2 Reserved Address ascension 0 1 1 LSB first 1 0 0 Soft reset (self clearing) 0 1 0x0001 0x0002 SPI Configuration B Chip configuration (local) [7:2] 1 Reserved Datapath soft reset (self clearing) 0 [7:2] [1:0] Reserved Reserved Channel power mode 0 1 00 10 11 0x0003 Chip type [7:0] Chip type 0x3 0x0004 Chip ID LSB [7:0] Chip ID LSB [7:0] 0xDE 0x0005 Chip ID MSB [7:0] Chip ID MSB [15:8] Rev. 0 | Page 95 of 135 Description Reset Access Whenever a soft reset is issued, the user must wait 5 ms before writing to any other register; this provides sufficient time for the boot loader to complete. Do nothing. Reset the SPI and registers (self clearing). Least significant bit shifted first for all SPI operations. Most significant bit shifted first for all SPI operations. Multibyte SPI operations cause addresses to auto decrement. Multibyte SPI operations cause addresses to auto increment. Reserved. Multibyte SPI operations cause addresses to auto decrement. Multibyte SPI operations cause addresses to auto increment. Least significant bit shifted first for all SPI operations. Most significant bit shifted first for all SPI operations. Whenever a soft reset is issued, the user must wait 5 ms before writing to any other register; this provides sufficient time for the boot loader to complete. Do nothing. Reset the SPI and registers (self clearing). Reserved. Normal operation. 0x0 R/WC 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/WC 0x0 0x0 R R/WC 0x0 0x0 0x0 R R R/W 0x3 R Datapth soft reset (self clearing). Reserved. Reserved. Channel power modes. Normal mode (power-up). Standby mode. Digital datapath clocks disabled; JESD204B interface enabled. Power-down mode. Digital datapath clocks disabled; digital datapath held in reset; JESD204B interface disabled. Chip type. High speed ADC. Chip ID. AD9695. Chip ID. R 0x0 R AD9695 Address 0x0006 Data Sheet Name Chip grade Bits [7:4] Bit Name Chip speed grade Settings 0x00 0x01 0x0008 Device index [3:0] [7:2] 1 Reserved Reserved Channel B 0 1 0 Channel A 0 1 0x000A Scratch pad [7:0] Scratch pad 0x000B SPI revision [7:0] SPI revision 0x01 00000001 0x000C 0x000D 0x000F Vendor ID LSB Vendor ID MSB Transfer [7:0] [7:0] [7:1] 0 Reserved Chip transfer 0 1 Clock/SYSREF/Chip Power-Down Pin Control Registers 0x003F 7 Chip powerLocal chip powerdown pin (local) down pin disable 0 1 [6:0] Reserved Rev. 0 | Page 96 of 135 Description Chip speed grade. 625 MSPS. 1300 MSPS. Reserved. Reserved. ADC Core B does not receive the next SPI command. ADC Core B receives the next SPI command. ADC Core A does not receive the next SPI command. ADC Core A receives the next SPI command. Chip scratch pad register. This register provides a consistent memory location for software debug. SPI revision register. Revision 1.0. Revision 1.0. Vendor ID [7:0]. Vendor ID [15:8]. Reserved. Self clearing chip transfer bit. This bit is used to update the DDC phase increment and phase offset registers when the DDC phase update mode bit (Register 0x0300, Bit 7) = 1. This setting makes it possible to synchronously update the DDC mixer frequencies. It is also used to update the coefficients for the programmable filter (PFILT). Do nothing. This bit it is only cleared after the transfer completes. Self clearing bit used to synchronize the transfer of data from master to slave registers. Function is determined by Register 0x0040, Bits[7:6]. Power-down pin (PDWN/STBY) enabled (default). Power-down pin (PDWN/STBY) disabled/ignored. Reserved. Reset 0x0 Access R DNC 0x0 0x1 R R R/W 0x1 R/W 0x0 R/W 0x1 R 0x56 0x04 0x0 0x0 R R R R/W 0x0 R/W 0x0 R Data Sheet Address 0x0040 Name Chip Pin Control 1 AD9695 Bits [7:6] Bit Name Global chip powerdown pin functionality Settings 00 01 10 [5:3] Chip FD_B/GPIO_B0 pin functionality 000 001 110 111 [2:0] Chip FD_A/GPIO_A0 pin functionality 000 001 110 111 0x0041 Chip Pin Control 2 [7:4] Chip FD_B/GPIO_B0 pin secondary functionality 0000 0001 1000 1001 [3:0] Chip FD_A/GPIO_A0 pin secondary functionality 0000 0001 1000 1001 Rev. 0 | Page 97 of 135 Description External power-down pin functionality. Assertion of the external power-down pin (PDWN/STBY) has higher priority than the channel power mode control bits (Register 0x0002, Bits[1:0]). The PDWN/STBY pin is only used when Register 0x0040, Bits[7:6] = 00 or 01. Power-down pin (default). Assertion of the external power-down pin (PDWN/STBY) causes the chip to enter full power-down mode. Standby-pin. Assertion of the external power-down pin (PDWN/STBY) causes the chip to enter standby mode. Pin disabled. Power-down pin (PDWN/STBY) is ignored. Fast Detect B/GPIO B0 pin functionality. Fast Detect B output. JESD204B LMFC output. Pin functionality determined by Register 0x0041, Bits[7:4]. Disabled. Configured as input with weak pull-down (default). Fast Detect A/GPIO A0 pin functionality. Fast Detect A output. JESD204B LMFC output. Pin functionality determined by Regiser 0x0041, Bits[3:0]. Disabled. Configured as input with weak pull-down. (default) Fast Detect B/GPIO B0 pin secondary functionality. Only used when Register 0x0040, Bits[5:3] = 110. Chip GPIO B0 input (NCO channel selection). Chip transfer input. Master next trigger output (MNTO). Slave next trigger input (SNTI). Fast Detect A/GPIO B0 pin secondary functionality. Only used when Register 0x0040, Bits[2:0] = 110. Chip GPIO A0 input (NCO channel selection). Chip transfer input. Master next trigger output (MNTO). Slave next trigger input (SNTI). Reset 0x0 Access R/W 0x7 R/W 0x7 R/W 0x0 R/W 0x0 R/W AD9695 Address 0x0042 Data Sheet Name Chip Pin Control 3 Bits [7:4] Bit Name Chip GPIO_B1 pin functionality Settings 0000 1000 1001 1111 [3:0] Chip GPIO_A1 pin functionality 0000 1000 1001 1111 0x0108 0x0109 Clock divider control [7:3] [2:0] Reserved Input clock divider (CLK± pins) Clock divider phase (local) [7:4] [3:0] Reserved Clock divider phase offset 00 01 11 0000 0001 0010 1110 1111 0x010A Clock divider and SYSREF control 7 Clock divider autophase adjust enable 0 1 [6:4] [3:2] Reserved Clock divider negative skew window 0 1 10 11 Rev. 0 | Page 98 of 135 Description GPIO_B1 pin functionality. Chip GPIO B1 input (NCO channel selection). Master next trigger output (MNTO). Slave next trigger input (SNTI). Disabled (configured as an input with a weak pull down). GPIO_A1 pin functionality. Chip GPIO A1 input (NCO channel selection). Master next trigger output (MNTO). Slave next trigger input (SNTI). Disabled (configured as an input with a weak pull down). Reserved. Divide by 1. Divide by 2. Divide by 4. Reserved. 0 input clock cycles delayed. 1/2 input clock cycles delayed (invert clock). 1 input clock cycles delayed. … 7 input clock cycles delayed. 7 1/2 input clock cycles delayed. Clock divider autophase adjust enable. When enabled, Register 0x0129, Bits[3:0] contain the phase of the divider when SYSREF occurred. The actual divider phase offset = Register 0x0129, Bits[3:0] + Register 0x0109, Bits[3:0]. Clock divider phase is not changed by SYSREF± (disabled). Clock divider phase is automatically adjusted by SYSREF± (enabled). Reserved. Clock divider negative skew window (measured in 1/2 input device clocks). Number of 1/2 clock cycles before the input device clock by which captured SYSREF± transitions are ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]; this allows some uncertainty in the sampling of SYSREF± without disturbing the input clock divider. Also, SYSREF± must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. No negative skew. SYSREF± must be captured accurately. 1/2 device clock of negative skew. 1 device clocks of negative skew. 1 1/2 device clocks of negative skew. Reset 0x0 Access R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W Data Sheet Address Name AD9695 Bits [1:0] Bit Name Clock divider positive skew window Settings 0 1 10 11 0x010B Clock divider SYSREF status [7:4] [3:0] Reserved Clock divider SYSREF± offset 0x0110 Clock delay control [7:3] [2:0] Reserved Clock delay mode select 000 010 011 100 110 0x0111 Clock super fine delay (local) [7:0] Clock super fine delay adjust Rev. 0 | Page 99 of 135 Description Clock divider positive skew window (measured in 1/2 input device clocks). Number of clock cycles after the input device clock by which captured SYSREF± transitions aree ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]; this allows some uncertainty in the sampling of SYSREF± without disturbing the input clock divider. Also, SYSREF± must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. No positive skew. SYSREF± must be captured accurately. 1/2 device clock of positive skew. 1 device clocks of positive skew. 1 1/2 device clocks of positive skew. Reserved Clock divider phase status (measured in 1/2 clock cycles). Internal clock divider phase of the captured SYSREF± signal applied to the phase offset. Only used when Register 0x010A, Bit 7 = 1. When Register 0x010A, Bit 7 = 1, Register 0x010A, Bits[3:2] = 0, and Register 0x010A, Bits[1:0] = 0, clock divider SYSREF± offset = Register 0x0129, Bits[3:0]. Reserved. Clock delay mode select. Used in conjunction with Register 0x0111 and Register 0x0112. No clock delay. Fine delay. Only Delay Step 0 to Delay Step 16 are valid. Fine delay (lowest jitter). Only Delay Step 0 to Delay Step 16 are valid. Fine delay. All 192 delay steps valid. Fine delay enabled (all 192 delay steps valid). Super fine delay enabled (all 128 delay steps valid). Clock super fine delay adjust. This is an unsigned control to adjust the super fine sample clock delay in 0.25 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 010 or 110. 0x00 = 0 delay steps. … 0x08 = 8 delay steps. … 0x80 = 128 delay steps. Reset 0x0 Access R/W 0x0 0x0 R R 0x0 0x0 R R/W 0x0 R/W AD9695 Data Sheet Address 0x0112 Name Clock fine delay (local) Bits [7:0] Bit Name Set clock fine delay 0x0113 Digital clock super fine delay [7:0] Digital clock super fine delay adjust 0x0114 Digital clock fine delay [7:0] Set digital clock fine delay 0x011A Clock detection control [7:5] [4:3] Reserved Clock detection threshold 0x011B Clock status [2:0] [7:1] 0 Settings 01 11 Reserved Reserved Input clock detect 0 1 Rev. 0 | Page 100 of 135 Description Clock fine delay adjust. This is an unsigned control to adjust the fine sample clock skew in 1.725 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6. 0x00 = 0 delay steps. … 0x08 = 8 delay steps. … 0xC0 = 192 delay steps. Minimum = 0. Maximum = 192. Increment = 1. Unit = delay steps. Digital clock super fine delay adjust. This is an unsigned control to adjust the super fine sample clock delay in 0.25ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 010 or 110. 0x00 = 0 delay steps. … 0x08 = 8 delay steps. … 0x80 = 128 delay steps. Digital clock fine delay adjust. This is an unsigned control to adjust the fine sample clock skew in 1.725 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4 or 0x6. 0x00 = 0 delay steps. … 0x08 = 8 delay steps. … 0xC0 = 192 delay steps. Minimum = 0. Maximum = 192. Increment = 1. Unit = delay steps. Reserved. Clock detection threshold. Threshold 1 for sample rate ≥ 300 MSPS. Threshold 2 for sample rate <300 MSPS. Reserved Reserved. Clock detection status. Input clock not detected. Input clock detected/locked. Reset 0xC0 Access R/W 0x0 R/W 0xC0 R/W 0x0 0x1 R/W R/W 0x6 0x0 0x0 R/W R R Data Sheet Address 0x011C Name Clock Duty Cycle Stabilizer 1 (DCS1) control (local) AD9695 Bits [7:2] 1 Bit Name Reserved DCS1 enable Settings 0 1 0 DCS1 power-up 0 1 0x011E Clock Duty Cycle Stabilizer 2 (DCS2) control [7:2] 1 Reserved DCS2 enable 0 1 0 DCS2 power-up 0 1 0x0120 SYSREF± Control 1 7 6 Reserved SYSREF± flag reset 5 4 Reserved SYSREF± transition select 0 1 0 1 0x0121 SYSREF± Control 2 3 CLK± edge select [2:1] SYSREF± mode select 0 [7:4] [3:0] Reserved Reserved SYSREF± N-shot ignore counter select 0 1 0 1 10 0000 0001 0010 0011 1110 1111 Rev. 0 | Page 101 of 135 Description Reserved Clock DCS1 enable. DCS1 bypassed. DCS1 enabled. Clock DCS1 power-up. DCS1 powered down. DCS1 powered up. Reserved. Clock DCS2 enable. DCS2 bypassed. DCS2 enabled. Clock DCS2 power-up. DCS2 powered down. DCS2 powered up. Reserved. Normal flag operation. SYSREF flags held in reset (setup/hold error flags cleared). Reserved. SYSREF is valid on low to high transitions using the selected CLK± edge. When changing this setting, SYSREF± mode select must be set to disabled. SYSREF is valid on high to low transitions using the selected CLK± edge. When changing this setting, SYSREF± mode select must be set to disabled. Captured on rising edge of CLK± input. Captured on falling edge of CLK± input. Disabled. Continuous. N-shot. Reserved. Reserved. Next SYSREF only (do not ignore). Ignore the first SYSREF± transition. Ignore the first two SYSREF± transitions. Ignore the first three SYSREF± transitions. … Ignore the first 14 SYSREF± transitions. Ignore the first 15 SYSREF± transitions. Reset 0x0 0x1 Access R/W R/W 0x1 R/W 0x0 0x1 R/W R/W 0x1 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 0x0 R R R/W AD9695 Address 0x0122 Data Sheet Name SYSREF± Control 3 Bits [7:4] [3:2] Bit Name Reserved SYSREF± window negative Settings 00 01 10 11 [1:0] SYSREF± window negative 00 01 10 11 0x0123 SYSREF Control 4 7 [6:0] Reserved SYSREF± timestamp delay 0x0128 SYSREF Status 1 0x0129 SYSREF Status 2 [7:4] [3:0] [7:4] [3:0] SYSREF± hold status SYSREF± setup status Reserved Clock divider phase when SYSREF± is captured 0x012A SYSREF Status 3 [7:0] SYSREF± counter, Bits[7:0] increments when a SYSREF±is captured Rev. 0 | Page 102 of 135 Description Reserved Negative skew window (measured in sample clocks). Number of clock cycles before the sample clock by which captured SYSREF± transitions are ignored. No negative skew. SYSREF± must be captured accurately. One sample clock of negative skew. Two sample clocks of negative skew. Three sample clocks of negative skew. Positive skew window (measured in sample clocks). Number of clock cycles before the sample clock by which captured SYSREF± transitions are ignored. No positive skew. SYSREF± must be captured accurately. One sample clock of positive skew. Two sample clocks of positive skew. Three sample clocks of positive skew. Reserved. SYSREF± timestamp delay (in converter sample clock cycles). 0: 0 sample clock cycle delay. 1: 1 sample clock cycle delay. … 127: 127 sample clock cycle delay. SYSREF± hold status. SYSREF± setup status. Reserved. SYSREF divider phase. These bits represent the phase of the divider when SYSREF± is captured. 0000 = in phase. 0001 = SYSREF± is ½ cycle delayed from clock. 0010 = SYSREF± is 1 cycle delayed from clock. 0011 = 1½ input clock cycles delayed. 0100 = 2 input clock cycles delayed. 0101 = 2½ input clock cycles delayed. … 1111 = 7½ input clock cycles delayed. SYSREF± count. Running counter that increments whenever a SYSREF event is captured. Reset by Register 0x0120, Bit 6. Wraps around at 255. Only read these bits while Register 0x0120, Bits[2:1] are set to disabled. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x40 R R/W 0x0 0x0 0x0 0x0 R R R R 0x0 R Data Sheet Address 0x01FF Name Chip sync mode AD9695 Bits [7:1] 0 Bit Name Reserved Synchronization mode Settings 0x0 0x1 Chip Operating Mode Control Registers 0x0200 Chip mode [7:6] 5 Reserved Chip Q ignore 0 1 4 [3:0] Reserved Chip application mode 0000 0001 0010 0011 0x0201 Chip decimation ratio [7:4] [3:0] Reserved Chip decimation ratio 0000 0001 1000 0010 0101 1001 0011 0110 1010 0111 0100 1101 1011 1110 1111 1100 Rev. 0 | Page 103 of 135 Description Reserved. JESD204B synchronization mode. The SYSREF± signal resets all internal clock dividers. Use this mode when synchro-nizing multiple chips as specified in the JESD204B standard. If the phase of any of the dividers must change, the JESD204B link goes down. Timestamp mode. The SYSREF± signal does not reset the internal clock dividers. In this mode, the JESD204B link and the signal monitor are not affected by the SYSREF± signal. The SYSREF± signal simply time stamps a sample as it passes through the ADC and is used as a control bit in the JESD204B output word. Reset 0x0 0x0 Access R R/W Reserved. Chip real (I) only selection. Both real (I) and complex (Q) selected. Only real (I) selected. Complex (Q) is ignored. Reserved. Full bandwidth mode. (default). One DDC mode (DDC 0 only). Two DDC mode (DDC 0 and DDC 1 only). Four DDC mode (DDC 0, DDC 1, DDC 2, and DDC 3). Reserved. Chip decimation ratio. Full sample rate (decimate by 1, DDCs are bypassed). Decimate by 2. Decimate by 3. Decimate by 4. Decimate by 5. Decimate by 6. Decimate by 8. Decimate by 10. Decimate by 12. Decimate by 15. Decimate by 16. Decimate by 20. Decimate by 24. Decimate by 30. Decimate by 40. Decimate by 48. 0x0 0x0 R/W R/W 0x0 0x0 R R/W 0x0 0x0 R R/W AD9695 Data Sheet Address Name Bits Bit Name Fast Detect and Signal Monitor Control Registers 0x0245 [7:4] Reserved Fast detect control (local) 3 Force FD A/FD B pins 2 Force value of FD_A/FD_B pins 1 0 Reserved Enable fast detect output 0x0247 Fast detect uppper LSB (local) [7:0] Fast detect upper threshold 0x0248 Fast detect upper MSB (local) [7:5] [4:0] Reserved Fast detect upper threshold 0x0249 Fast detect low LSB (local) [7:0] Fast detect lower threshold 0x024A Fast detect low MSB (local) [7:5] [4:0] Reserved Fast detect lower threshold 0x024B Fast detect dwell LSB (local) [7:0] Fast detect dwell time 0x024C FAST detect dwell MSB (local) [7:0] Fast detect dwell time 0x026F SIgnal monitor sync control [7:2] 1 Reserved Signal monitor next synchronization mode Settings 0 1 0 1 0 1 Rev. 0 | Page 104 of 135 Description Reset Access Reserved. Normal operation of fast detect pin. Force a value on fast detect pin (see Bit 2 in this register). The fast detect output pin for this channel is set to this value when the output is forced. Reserved. Fast detect disabled. Fast detect enabled. LSBs of fast detect upper threshold. Eight LSBs of the programmable 13-bit upper threshold compared to the fine ADC magnitude Reserved. LSBs of fast detect upper threshold. Eight LSBs of the programmable 13-bit upper threshold compared to the fine ADC magnitude. LSBs of the fast detect lower threshold. Eight LSBs of the programmable 13-bit lower threshold compared to the fine ADC magnitude. Reserved. LSBs of fast detect lower threshold. Eight LSBs of the programmable 13-bit lower threshold compared to the fine ADC magnitude. LSBs of fast detect dwell time counter target. This is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FD_x pins are reset to 0. LSBs of fast detect dwell time counter target. This is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FD_x pins are reset to 0. Reserved. Signal monitor next synchronization mode. Continuous mode. Next synchronization mode. Only the next valid edge of SYSREF± pin synchronizes the signal monitor block. Subsequent edges of the SYSREF± pin are ignored. After the next SYSREF is found, Register 0x026F, Bit 0 is cleared. The SYSREF± pin must be an integer multiple of the signal monitor period for this function to operate correctly in continuous mode. 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W Data Sheet Address 0x0270 Name Signal monitor control (local) 0x0271 Signal Monitor Period 0 (local) 0x0272 Signal Monitor Period 1 (local) Signal Monitor Period 2 (local) Signal monitor status control (local) 0x0273 0x0274 AD9695 Bits 0 Bit Name Signal monitor synchronization mode Reserved Peak detector 0 [7:0] Reserved Signal monitor period [7:0] [7:0] [7:5] 4 Signal monitor period [15:8] Signal monitor period [23:16] Reserved Result update 1 3 [2:0] Reserved Result selection 001 [7:0] 0 1 Signal Monitor Status 0 (local) [7:0] Signal monitor result [7:0] 0x0276 Signal Monitor Status 1 (local) Signal Monitor Status 2 (local) [7:0] Signal monitor status frame counter (local) Signal monitor serial framer control (local) [7:0] Signal monitor result [15:8] Reserved Signal monitor result [19:16] Period count result [7:2] [1:0] Reserved Signal monitor SPORT over JESD204B enable SPORT over JESD204B input selection (local) [7:6] 1 Reserved SPORT over JESD204B input selection 0x0278 0x0279 0x027A 0 1 [7:2] 1 0x0275 0x0277 Settings [7:4] [3:0] 00 11 0 1 0 Reserved Rev. 0 | Page 105 of 135 Description Signal monitor synchronization enable. Synchronization disabled. If Register 0x026F, Bit 1 = 1, only the next valid edge of the SYSREF± pin is used to synchronize the signal monitor block. Subsequent edges of the SYSREF± pin are ignored. After the next SYSREF± isreceived, this bit is cleared. The SYSREF± input pin must be enabled to synchronize the signal monitor blocks. Reserved. Peak detector disabled. Peak detector enabled. Reserved. This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Only even values are supported. Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 0x80 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/WC 0x0 0x1 R R/W 0x0 R 0x0 R Reserved. Signal monitor status result. 0x0 0x0 R R Signal monitor frame counter status bits. The frame counter increments whenever the period counter expires. Reserved. Disabled. Enabled. Reserved. Signal monitor serial framer input selection. When each individual bit is a 1, the corresponding signal statistics information is sent within the frame. Disabled. Peak detector data inserted in serial frame. Reserved 0x0 R 0x0 0x0 R R/W 0x0 0x1 R R/W 0x0 R Reserved. Update signal monitor status, Register 0x0275 to Register 0x0278. Self clearing. Reserved. Peak detector placed on status readback signals. Signal monitor status result. This 20-bit value contains the status result calculated by the signal monitor block. Signal monitor status result. AD9695 Data Sheet Address Name Bits Bit Name Settings DDC Function Registers (See the Digital Downconverter (DDC) Section) 0x0300 DDC sync control 7 DDC FTW/POW/MAW/ MBW update mode 0 1 [6:5] 4 Reserved DDC NCO soft reset 0 1 [3:2] 1 Reserved DDC next sync 0 1 0 DDC synchronization mode 0 1 0x0310 DDC 0 control 7 DDC 0 mixer select 0 1 6 DDC 0 gain select 0 1 Rev. 0 | Page 106 of 135 Description Reset Access Select DDC FTW/POW/MAW/MBW update mode. Instantaneous/continuous update. The FTW/POW/MAW/MBW values are updated immediately. The FTW/POW/MAW/MBW values are updated synchronously when the chip transfer bit (Register 0x000F, Bit 0) is set. Reserved. This bit can be used to synchronize all the NCOs inside the DDC blocks. Normal operation. DDC held in reset. Reserved. Continuous mode. The SYSREF± frequency must be an integer multiple of the NCO frequencyr for this function to operate correctly in continuous mode. Only the next valid edge of the SYSREF± pin is used to synchronize the NCO in the DDC block. Subsequent edges of the SYSREF± pin are ignored. After the next SYSREF is found, the DDC synchronization enable bit (Register 0x0300, Bit 0) is cleared. The SYSREF± input pin must be enabled to synchronize the DDCs. Synchronization disabled. If the DDC next sync bit (Register 0x0300, Bit 1) = 1, only the next valid edge of the SYSREF± pin is used to synchronize the NCO in the DDC block. Subsequent edges of the SYSREF± pin are ignored. After the next SYSREF± is received, this bit is cleared. Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate, real and imaginary quadrature ADC receive channels; analog demodulator). Gain can be used to compensate for the 6 dB loss associated with mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Address Name AD9695 Bits [5:4] Bit Name DDC 0 intermediate frequency (IF) mode 3 DDC 0 complex to real enable Settings 00 01 10 11 0 1 [2:0] DDC 0 decimation rate select 000 001 010 011 100 101 110 111 0x0311 DDC 0 input select [7:4] DDC 0 decimation rate select 0 10 11 100 Rev. 0 | Page 107 of 135 Description Variable IF mode. 0 Hz IF mode. fS/4 Hz IF mode. Test mode. Complex (I and Q) outputs contain valid data. Real (I) output only. Complex to real enabled. Uses extra fS /4 mixing to convert to real. Decimation filter selection. HB1 + HB2 filter selection: decimate by 2 (complex to real enabled), or decimate by 4 (complex to real disabled). HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real enabled), or decimate by 8 (complex to real disabled). HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to real enabled), or decimate by 16 (complex to real disabled). HB1 filter selection: decimate by 1 (complex to real enabled), or decimate by 2 (complex to real disabled). HB1 + TB2 filter selection: decimate by 3 (complex to real enabled), or decimate by 6 (complex to real disabled). HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real enabled), or decimate by 12 (complex to real disabled). HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to real enabled), or decimate by 24 (complex to real disabled). Decimation determined by Register 0x0311, Bits[7:4]. Only valid when Register 0x0310, Bits[2:0] = 3'b111. TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48 (complex to real disabled), or decimate by 24 (complex to real enabled). FB2 + HB1 filter selection: decimate by 10 (complex to real disabled) or decimate by 5 (complex to real enabled). FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real disabled), or decimate by 10 (complex to real enabled). FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to real disabled), or decimate by 20 (complex to real enabled). Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9695 Address Data Sheet Name Bits Bit Name Settings 111 1000 1001 0x0314 DDC 0 NCO control 3 2 Reserved DDC 0 Q input select 1 0 Reserved DDC 0 I input select [7:4] DDC 0 NCO channel select mode 0 1 0 1 0 1 1000 1010 [3:0] DDC 0 NCO register map channel select 0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 0x0315 DDC 0 phase control [7:4] [3:0] Reserved DDC 0 phase update index 0000 0001 0010 0011 0x0316 DDC 0 Phase Increment 0 [7:0] DDC 0 phase increment [7:0] Rev. 0 | Page 108 of 135 Description TB1 filter selection: decimate by 3 (decimate by 1.5 not supported). FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not supported). HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by 15 not supported). Reserved. Channel A. Channel B. Reserved. Channel A. Channel B. For edge control, the internal counter wraps after the Register 0x0314, Bits[3:0] value is reached. Use Register 0x0314, Bits[3:0]. 2'b0, GPIO B0, GPIO A0. Increment internal counter on rising edge of the GPIO A0 pin. Increment internal counter on rising edge of the GPIO B0 pin. NCO channel select register map control. Select NCO Channel 0. Select NCO Channel 1. Select NCO Channel 2. Select NCO Channel 3. Select NCO Channel 4. Select NCO Channel 5. Select NCO Channel 6. Select NCO Channel 7. Select NCO Channel 8. Select NCO Channel 9. Select NCO Channel 10. Select NCO Channel 11. Select NCO Channel 12. Select NCO Channel 13. Select NCO Channel 14. Select NCO Channel 15. Reserved. Indexes the NCO channel whose phase and offset gets updated. The update method is based on the DDC pyhase update mode, which may be continuous or require chip transfer. Update NCO Channel 0. Update NCO Channel 1. Update NCO Channel 2. Update NCO Channel 3. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. Reset Access 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W Data Sheet AD9695 Address 0x0317 Name DDC 0 Phase Increment 1 Bits [7:0] Bit Name DDC 0 phase increment [15:8] 0x0318 DDC 0 Phase Increment 2 [7:0] DDC 0 phase increment [23:16] 0x0319 DDC 0 Phase Increment 3 [7:0] DDC 0 phase increment [31:24] 0x031A DDC 0 Phase Increment 4 [7:0] DDC 0 phase increment [39:32] 0x031B DDC 0 Phase Increment 5 [7:0] DDC 0 phase increment [47:40] 0x031D DDC 0 Phase Offset 0 DDC 0 Phase Offset 1 DDC 0 Phase Offset 2 DDC 0 Phase Offset 3 DDC 0 Phase Offset 4 DDC 0 Phase Offset 5 DDC 0 test enable [7:0] DDC 0 phase offset [7:0] DDC 0 phase offset [15:8] DDC 0 phase offset [23:16] DDC 0 phase offset [31:24] DDC 0 phase offset [39:32] DDC 0 phase offset [47:40] Reserved DDC 0 Q output test mode enable 0x031E 0x031F 0x0320 0x0321 0x0322 0x0327 [7:0] [7:0] [7:0] [7:0] [7:0] [7:3] 2 Settings 0 1 1 0 0x0330 DDC 1 control 7 Reserved DDC 0 I output test mode enable DDC 1 mixer select 0 1 0 1 6 DDC 1 gain select 0 1 Rev. 0 | Page 109 of 135 Description FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Reserved. Q samples always use the Test Mode B block. The test mode is selected using the channel dependent bits (Register 0x0550, Bits[3:0]). Test mode disabled. Test mode enabled. Reserved. I samples always use the Test Mode A block. The test mode is selected using the channel dependent bits (Register 0x0550, Bits[3:0]). Test mode disabled. Test mode enabled. Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate, real and imaginary quadrature ADC receive channels; analog demodulator). Gain can be used to compensate for the 6 dB loss associated with mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W AD9695 Address Data Sheet Name Bits [5:4] Bit Name DDC 1 intermediate frequency (IF) mode 3 DDC 1 Complex to real enable Settings 00 01 10 11 0 1 [2:0] DDC 1 decimation rate select 000 001 010 011 100 101 110 111 Rev. 0 | Page 110 of 135 Description Variable IF mode. 0 Hz IF mode. fS/4 Hz IF mode. Test mode. Complex (I and Q) outputs contain valid data. Real (I) output only. Complex to real enabled. Uses extra fS/4 mixing to convert to real. Decimation filter selection. HB1 + HB2 filter selection: decimate by 2 (complex to real enabled), or decimate by 4 (complex to real disabled). HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real enabled), or decimate by 8 (complex to real disabled). HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to real enabled), or decimate by 16 (complex to real disabled). HB1 filter selection: decimate by 1 (complex to real enabled), or decimate by 2 (complex to real disabled). HB1 + TB2 filter selection: decimate by 3 (complex to real enabled), or decimate by 6 (complex to real disabled). HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real enabled), or decimate by 12 (complex to real disabled). HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to real enabled), or decimate by 24 (complex to real disabled). Decimation determined by Register 0x0331, Bits[7:4]. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W Data Sheet Address 0x0331 Name DDC 1 input select AD9695 Bits [7:4] Bit Name DDC 1 decimation rate select Settings 0 10 11 100 111 1000 1001 0x0334 DDC 1 NCO control 3 2 Reserved DDC 1 Q input select 1 0 Reserved DDC 1 I input select [7:4] DDC 1 NCO channel select mode 0 1 0 1 0 1 1000 1010 [3:0] DDC 1 NCO register map channel select 0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 Rev. 0 | Page 111 of 135 Description Only valid when Register 0x0310, Bits[2:0] = 3'b111. TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48 (complex to real disabled), or decimate by 24 (complex to real enabled). FB2 + HB1 filter selection: decimate by 10 (complex to real disabled), or decimate by 5 (complex to real enabled). FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real disabled), or decimate by 10 (complex to real enabled). FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to real disabled), or decimate by 20 (complex to real enabled). TB1 filter selection: decimate by 3 (decimate by 1.5 not supported). FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not supported). HB2 + FB2 + TB1 filter select: decim-ate by 30 (decimate by 15 not supported). Reserved. Channel A. Channel B. Reserved. Channel A. Channel B. For edge control, the internal counter wraps after the Register 0x0334, Bits[3:0] value is reached. Use Register 0x0314, Bits[3:0]. 2'b0, GPIO B0, GPIO A0. Increment internal counter when rising edge of the GPIO A0 pin. Increment internal counter when rising edge of the GPIO B0 pin. NCO channel select register map control. Select NCO Channel 0. Select NCO Channel 1. Select NCO Channel 2. Select NCO Channel 3. Select NCO Channel 4. Select NCO Channel 5. Select NCO Channel 6. Select NCO Channel 7. Select NCO Channel 8. Select NCO Channel 9. Select NCO Channel 10. Select NCO Channel 11. Select NCO Channel 12. Select NCO Channel 13. Select NCO Channel 14. Select NCO Channel 15. Reset 0x0 Access R/W 0x0 0x1 R R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W AD9695 Address 0x0335 Data Sheet Name DDC 1 phase control Bits [7:4] [3:0] Bit Name Reserved DDC 1 phase update index Settings 0000 0001 0010 0011 0x0336 DDC 1 Phase Increment 0 [7:0] DDC 1 phase increment [7:0] 0x0337 DDC 1 Phase Increment 1 [7:0] DDC 1 phase increment [15:8] 0x0338 DDC 1 Phase Increment 2 [7:0] DDC 1 phase increment [23:16] 0x0339 DDC 1 Phase Increment 3 [7:0] DDC 1 phase increment [31:24] 0x033A DDC 1 Phase Increment 4 [7:0] DDC 1 phase increment [39:32] 0x033B DDC 1 Phase Increment 5 [7:0] DDC 1 phase increment [47:40] 0x033D DDC 1 Phase Offset 0 DDC 1 Phase Offset 1 DDC 1 Phase Offset 2 DDC 1 Phase Offset 3 DDC 1 Phase Offset 4 DDC 1 Phase Offset 5 [7:0] DDC 1 phase offset [7:0] DDC 1 phase offset [15:8] DDC 1 phase offset [23:16] DDC 1 phase offset [31:24] DDC 1 phase offset [39:32] DDC 1 phase offset [47:40] 0x033E 0x033F 0x0340 0x0341 0x0342 [7:0] [7:0] [7:0] [7:0] [7:0] Rev. 0 | Page 112 of 135 Description Reserved. Indexes the NCO channel whose phase and offset gets updated. The update method is based on the DDC pyhase update mode, which may be continuous or require chip transfer. Update NCO Channel 0. Update NCO Channel 1. Update NCO Channel 2. Update NCO Channel 3. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Address 0x0347 Name DDC 1 test enable AD9695 Bits [7:3] 2 Bit Name Reserved DDC 1 Q output test mode enable Settings 0 1 1 0 0x0350 DDC 2 control 7 Reserved DDC 1 I output test mode enable DDC 2 mixer select 0 1 0 1 6 DDC 2 gain select [5:4] DDC 2 intermediate frequency (IF) mode 3 DDC 2 complex to real enable 0 1 00 01 10 11 0 1 [2:0] DDC 2 decimation rate select 000 001 010 011 100 Rev. 0 | Page 113 of 135 Description Reserved. Q Samples always use the Test Mode B block. The test mode is selected using the channel dependent bits, Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Reserved. I samples always use the Test Mode A block. The test mode is selected using the channel dependent bits, Register 0x0550, Bits[3:0] bits. Test mode disabled. Test mode enabled. Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate, real and imaginary quadrature ADC receive channels; analog demodulator). Gain can be used to compensate for the 6 dB loss associated with mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). Variable IF mode. 0 Hz IF mode. fS/4 Hz IF mode. Test mode. Complex (I and Q) outputs contain valid data. Real (I) output only. Complex to real enabled. Uses extra fS/4 mixing to convert to real. Decimation filter selection. HB1 + HB2 filter selection: decimate by 2 (complex to real enabled), or decimate by 4 (complex to real disabled). HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real enabled), or decimate by 8 (complex to real disabled). HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to real enabled), or decimate by 16 (complex to real disabled). HB1 filter selection: decimate by 1 (complex to real enabled), or decimate by 2 (complex to real disabled). HB1 + TB2 filter selection: decimate by 3 (complex to real enabled), or decimate by 6 (complex to real disabled). Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9695 Address Data Sheet Name Bits Bit Name Settings 101 110 111 0x0351 DDC 2 input select [7:4] DDC 2 decimation rate select 0 10 11 100 0x0354 DDC 2 NCO control 3 2 Reserved DDC 2 Q input select 1 0 Reserved DDC 2 I input select [7:4] DDC 2 NCO channel select mode 0 1 0 1 0 1 1000 1010 [3:0] DDC 2 NCO register map channel select 0 1 10 11 100 101 110 111 1000 1001 1010 1011 Rev. 0 | Page 114 of 135 Description HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real enabled), or decimate by 12 (complex to real disabled). HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to real enabled), or decimate by 24 (complex to real disabled). Decimation determined by Register 0x0351, Bits[7:4]. Only valid when Register 0x0310, Bits[2:0] = 3'b111. TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48 (complex to real disabled), or decimate by 24 (complex to real enabled). FB2 + HB1 filter selection: decimate by 10 (complex to real disabled), or decimate by 5 (complex to real enabled). FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real disabled), or decimate by 10 (complex to real enabled). FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to real disabled), or decimate by 20 (complex to real enabled). Reserved. Channel A. Channel B. Reserved. Channel A. Channel B. For edge control, the internal counter wraps after the Register 0x0354, Bits[3:0] value is reached. Use Register 0x0314, Bits[3:0]. 2'b0, GPIO B0, GPIO A0. Increment internal counter when rising edge of the GPIO A0 pin. Increment internal counter when rising edge of the GPIO B0 pin. NCO channel select register map control. Select NCO Channel 0. Select NCO Channel 1. Select NCO Channel 2. Select NCO Channel 3. Select NCO Channel 4. Select NCO Channel 5. Select NCO Channel 6. Select NCO Channel 7. Select NCO Channel 8. Select NCO Channel 9. Select NCO Channel 10. Select NCO Channel 11. Reset Access 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W Data Sheet AD9695 Address Name Bits Bit Name Settings 1100 1101 1110 1111 0x0355 DDC 2 phase control [7:4] [3:0] Reserved DDC 2 phase update index 0000 0001 0010 0011 0x0356 DDC 2 Phase Increment 0 [7:0] DDC 2 phase increment [7:0] 0x0357 DDC 2 Phase Increment 1 [7:0] DDC 2 phase increment [15:8] 0x0358 DDC 2 Phase Increment 2 [7:0] DDC 2 phase increment [23:16] 0x0359 DDC 2 Phase Increment 3 [7:0] DDC 2 phase increment [31:24] 0x035A DDC 2 Phase Increment 4 [7:0] DDC 2 phase increment [39:32] 0x035B DDC 2 Phase Increment 5 [7:0] DDC 2 phase increment [47:40] 0x035D DDC 2 Phase Offset 0 DDC 2 Phase Offset 1 DDC 2 Phase Offset 2 DDC 2 Phase Offset 3 DDC 2 Phase Offset 4 DDC 2 Phase Offset 5 [7:0] DDC 2 phase offset [7:0] DDC 2 phase offset [15:8] DDC 2 phase offset [23:16] DDC 2 phase offset [31:24] DDC 2 phase offset [39:32] DDC 2 phase offset [47:40] 0x035E 0x035F 0x0360 0x0361 0x0362 [7:0] [7:0] [7:0] [7:0] [7:0] Rev. 0 | Page 115 of 135 Description Select NCO Channel 12. Select NCO Channel 13. Select NCO Channel 14. Select NCO Channel 15. Reserved. Indexes the NCO channel whose phase and offset gets updated. The update method is based on the DDC pyhase update mode, which may be continuous or require chip transfer. Update NCO Channel 0. Update NCO Channel 1. Update NCO Channel 2. Update NCO Channel 3. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Reset Access 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9695 Address 0x0367 Data Sheet Name DDC 2 test enable Bits [7:3] 2 Bit Name Reserved DDC 2 Q output test mode enable Settings 0 1 1 0 0x0370 DDC 3 control 7 Reserved DDC 2 I output test mode enable DDC 3 mixer select 0 1 0 1 6 DDC 3 gain select [5:4] DDC 3 intermediate frequency (IF) mode 3 DDC 3 complex to real enable 0 1 00 01 10 11 0 1 [2:0] DDC 3 decimation rate select 000 001 010 011 100 Rev. 0 | Page 116 of 135 Description Reserved. Q samples always use the Test Mode B block. The test mode is selected using the channel dependent bits, Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Reserved. I samples always use the Test Mode A block. The test mode is selected using the channel dependent bits, Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate, real and imaginary quadrature ADC receive channels; analog demodulator). Gain can be used to compensate for the 6 dB loss associated with mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). Variable IF mode. 0 Hz IF mode. fS/4 Hz IF mode. Test mode. Complex (I and Q) outputs contain valid data. Real (I) output only. Complex to real enabled. Uses extra fS/4 mixing to convert to real. Decimation filter selection. HB1 + HB2 filter selection: decimate by 2 (complex to real enabled), or decimate by 4 (complex to real disabled). HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real enabled), or decimate by 8 (complex to real disabled). HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to real enabled), or decimate by 16 (complex to real disabled). HB1 filter selection: decimate by 1 (complex to real enabled), or decimate by 2 (complex to real disabled). HB1 + TB2 filter selection: decimate by 3 (complex to real enabled), or decimate by 6 (complex to real disabled). Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Address Name AD9695 Bits Bit Name Settings 101 110 111 0x0371 DDC 3 input select [7:4] DDC 3 decimation rate select 0 10 11 100 0x0374 DDC 3 NCO control 3 2 Reserved DDC 3 Q input select 1 0 Reserved DDC 3 I input select [7:4] DDC 3 NCO channel select mode 0 1 0 1 0 1 1000 1010 [3:0] DDC 3 NCO register map channel select 0 1 10 11 100 101 110 111 1000 1001 1010 1011 Rev. 0 | Page 117 of 135 Description HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real enabled), or decimate by 12 (complex to real disabled). HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to real enabled), or decimate by 24 (complex to real disabled). Decimation determined by Register 0x0371, Bits[7:4]. Only valid when Register 0x0310, Bits[2:0] = 3'b111. TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48 (complex to real disabled), or decimate by 24 (complex to real enabled). FB2 + HB1 filter selection: decimate by 10 (complex to real disabled), or decimate by 5 (complex to real enabled) FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real disabled), or decimate by 10 (complex to real enabled) FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to real disabled), or decimate by 20 (complex to real enabled) Reserved. Channel A. Channel B. Reserved. Channel A. Channel B. For edge control, the internal counter wraps after the Register 0x0374, Bits[3:0] value is reached. Use Register 0x0314, Bits[3:0]. 2'b0, GPIO B0, GPIO A0. Increment internal counter when rising edge of the GPIO A0 pin. Increment internal counter when rising edge of the GPIO B0 pin. NCO channel select register map control. Select NCO Channel 0. Select NCO Channel 1. Select NCO Channel 2. Select NCO Channel 3. Select NCO Channel 4. Select NCO Channel 5. Select NCO Channel 6. Select NCO Channel 7. Select NCO Channel 8. Select NCO Channel 9. Select NCO Channel 10. Select NCO Channel 11. Reset Access 0x0 R/W 0x0 0x1 R R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W AD9695 Data Sheet Address Name Bits Bit Name Settings 1100 1101 1110 1111 0x0375 DDC 3 phase control [7:4] [3:0] Reserved DDC 3 phase update index 0000 0001 0010 0011 0x0376 DDC 3 Phase Increment 0 [7:0] DDC 3 phase increment [7:0] 0x0377 DDC 3 Phase Increment 1 [7:0] DDC 3 phase increment [15:8] 0x0378 DDC 3 Phase Increment 2 [7:0] DDC 3 phase increment [23:16] 0x0379 DDC 3 Phase Increment 3 [7:0] DDC 3 phase increment [31:24] 0x037A DDC 3 Phase Increment 4 [7:0] DDC 3 phase increment [39:32] 0x037B DDC 3 Phase Increment 5 [7:0] DDC 3 phase increment [47:40] 0x037D DDC 3 Phase Offset 0 DDC 3 Phase Offset 1 DDC 3 Phase Offset 2 DDC 3 Phase Offset 3 DDC 3 Phase Offset 4 DDC 3 Phase Offset 5 [7:0] DDC 3 phase offset [7:0] [7:0] DDC 3 phase offset [15:8] DDC 3 phase offset [23:16] DDC 3 phase offset [31:24] DDC 3 phase offset [39:32] DDC 3 phase offset [47:40] 0x037E 0x037F 0x0380 0x0381 0x0382 [7:0] [7:0] [7:0] [7:0] Rev. 0 | Page 118 of 135 Description Select NCO Channel 12. Select NCO Channel 13. Select NCO Channel 14. Select NCO Channel 15. Reserved. Indexes the NCO channel whose phase and offset gets updated. The update method is based on the DDC phase update mode, which may be continuous or require chip transfer. Update NCO Channel 0. Update NCO Channel 1. Update NCO Channel 2. Update NCO Channel 3. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC_PHASE_INC × fS)/248. Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Twos complement phase offset value for the NCO (POW). Reset Access 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Address 0x0387 Name DDC 3 test enable AD9695 Bits [7:3] 2 Bit Name Reserved DDC 3 Q output test mode enable Settings 0 1 1 0 Reserved DDC 3 I output test mode enable 0 1 0x0390 0x0391 0x0392 0x0393 0x0394 0x0395 0x0398 0x0399 0x039A 0x039B 0x039C 0x039D 0x03A0 0x5C00x03A1 DDC 0 Phase Increment Fractional A0 DDC 0 Phase Increment Fractional A1 DDC 0 Phase Increment Fractional A2 DDC 0 Phase Increment Fractional A3 DDC 0 Phase Increment Fractional A4 DDC 0 Phase Increment Fractional A5 DDC 0 Phase Increment Fractional B0 DDC 0 Phase Increment Fractional B1 DDC 0 Phase Increment Fractional B2 DDC 0 Phase Increment Fractional B3 DDC 0 Phase Increment Fractional B4 DDC 0 Phase Increment Fractional B5 DDC 1 Phase Increment Fractional A0 DDC 1 Phase Increment Fractional A1 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] DDC 0 Phase Increment Fractional A [7:0] DDC 0 Phase Increment Fractional A [15:8] DDC 0 Phase Increment Fractional A [23:16] DDC 0 Phase Increment Fractional A [31:24] DDC 0 Phase Increment Fractional A [39:32] DDC 0 Phase Increment Fractional A [47:40] DDC 0 Phase Increment Fractional B [7:0] DDC 0 Phase Increment Fractional B [15:8] DDC 0 Phase Increment Fractional B [23:16] DDC 0 Phase Increment Fractional B [31:24] DDC 0 Phase Increment Fractional B [39:32] DDC 0 Phase Increment Fractional B [47:40] DDC 1 Phase Increment Fractional A [7:0] DDC 1 Phase Increment Fractional A [15:8] Rev. 0 | Page 119 of 135 Description Reserved. Q samples always use the Test Mode B block. The test mode is selected using the channel dependent bit, Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Reserved. I samples always use the Test Mode A block. The test mode is selected using the channel dependent bits, Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Numerator correction term for the modulus phase accumulator (MAW). Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W 0x0 R/W Numerator correction term for the MAW. 0x0 R/W Numerator correction term for the MAW. 0x0 R/W Numerator correction term for the MAW. 0x0 R/W Numerator correction term for the MAW. 0x0 R/W Numerator correction term for the MAW. 0x0 R/W Denominator correction term for the modulus phase accumulator (MBW). 0x0 R/W Denominator correction term for the MBW. 0x0 R/W Denominator correction term for the MBW. 0x0 R/W Denominator correction term for the MBW. 0x0 R/W Denominator correction term for the MBW. 0x0 R/W Denominator correction term for the MBW. 0x0 R/W Numerator correction term for the modulus phase accumulator (MAW). 0x0 R/W Numerator correction term for the MAW. 0x0 R/W AD9695 Address 0x03A2 0x03A3 0x03A4 0x03A5 0x03A8 0x03A9 0x03AA 0x03AB 0x03AC 0x03AD 0x03B0 0x03B1 0x03B2 0x03B3 0x03B4 0x03B5 0x03B8 0x03B9 0x03BA Data Sheet Name DDC 1 Phase Increment Fractional A2 DDC 1 Phase Increment Fractional A3 DDC 1 Phase Increment Fractional A4 DDC 1 Phase Increment Fractional A5 DDC 1 Phase Increment Fractional B0 DDC 1 Phase Increment Fractional B1 DDC 1 Phase Increment Fractional B2 DDC 1 Phase Increment Fractional B3 DDC 1 Phase Increment Fractional B4 DDC 1 Phase Increment Fractional B5 DDC 2 Phase Increment Fractional A0 DDC 2 Phase Increment Fractional A1 DDC 2 Phase Increment Fractional A2 DDC 2 Phase Increment Fractional A3 DDC 2 Phase Increment Fractional A4 DDC 2 Phase Increment Fractional A5 DDC 2 Phase Increment Fractional B0 DDC 2 Phase Increment Fractional B1 DDC 2 Phase Increment Fractional B2 Bits [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name DDC 1 Phase Increment Fractional A [23:16] DDC 1 Phase Increment Fractional A [31:24] DDC 1 Phase Increment Fractional A [39:32] DDC 1 Phase Increment Fractional A [47:40] DDC 1 Phase Increment Fractional B [7:0] Settings Description Numerator correction term for the MAW. Reset 0x0 Access R/W Numerator correction term for the MAW. 0x0 R/W Numerator correction term for the MAW. 0x0 R/W Numerator correction term for the MAW. 0x0 R/W Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 1 Phase Increment Fractional B [15:8] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 1 Phase Increment Fractional B [23:16] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 1 Phase Increment Fractional B [31:24] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 1 Phase Increment Fractional B [39:32] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 1 Phase Increment Fractional B [47:40] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional A [7:0] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional A [15:8] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional A [23:16] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional A [31:24] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional A [39:32] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional A [47:40] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional B [7:0] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional B [15:8] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional B [23:16] Denominator correction term for the MBW. 0x0 R/W Rev. 0 | Page 120 of 135 Data Sheet Address 0x03BB 0x03BC 0x03BD 0x03C0 0x03C1 0x03C2 0x03C3 0x03C4 0x03C5 0x03C8 0x03C9 0x03CA 0x03CB 0x03CC Name DDC 2 Phase Increment Fractional B3 DDC 2 Phase Increment Fractional B4 DDC 2 Phase Increment Fractional B5 DDC 3 Phase Increment Fractional A0 DDC 3 Phase Increment Fractional A1 DDC 3 Phase Increment Fractional A2 DDC 3 Phase Increment Fractional A3 DDC 3 Phase Increment Fractional A4 DDC 3 Phase Increment Fractional A5 DDC 3 Phase Increment Fractional B0 DDC 3 Phase Increment Fractional B1 DDC 3 Phase Increment Fractional B2 DDC 3 Phase Increment Fractional B3 DDC 3 Phase Increment Fractional B4 AD9695 Bits [7:0] Bit Name DDC 2 Phase Increment Fractional B [31:24] [7:0] Settings Description Denominator correction term for the MBW. Reset 0x0 Access R/W DDC 2 Phase Increment Fractional B [39:32] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 2 Phase Increment Fractional B [47:40] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional A [7:0] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional A [15:8] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional A [23:16] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional A [31:24] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional A [39:32] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional A [47:40] Numerator correction term for the MAW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional B [7:0] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional B [15:8] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional B [23:16] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional B [31:24] Denominator correction term for the MBW. 0x0 R/W [7:0] DDC 3 Phase Increment Fractional B [39:32] Denominator correction term for the MBW. 0x0 R/W Rev. 0 | Page 121 of 135 AD9695 Data Sheet Address 0x03CD Name Bits [7:0] DDC 3 Phase Increment Fractional B5 Digital Outputs and Test Mode Registers 0x0550 7 ADC test mode control (local) Bit Name DDC 3 Phase Increment Fractional B [47:40] Settings User pattern selection 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W User Pattern 1 [7:0] User Pattern 1 [15:8] [7:0] User Pattern 2 [7:0] User Test Pattern 2 LSB. 6 5 Reserved Reset psuedorandom long generator 0 1 4 Reset psuedorandom short generator 0 1 [3:0] Test mode selection 0000 0001 0010 0011 0100 0101 0110 0111 1000 0x0553 Access R/W [7:0] [7:0] 1 User Pattern 1 LSB User Pattern 1 MSB User Pattern 2 LSB Reset 0x0 Test mode user pattern selection. These bits are only used when TMODE_GEN_SEL is in user input mode (TMODE_GEN_SEL = 1000). Otherwise, they are ignored. User Pattern 1 is found in the USR_PAT_ 1_MSB and USR_PAT_1_LSB registers. User Pattern 2 is found in the USR_ PAT_2_MSB and USR_PAT_2_LSB registers, and so on. Continuous/repeat pattern. Place each user pattern (User Pattern 1 through User Pattern 4) on the output for 1 clock cycle and then repeat. (Output User Pattern 1, User Pattern 2, User Pattern 3, User Pattern 4, User Pattern 1, User Pattern 2, User Pattern 3, User Pattern 4, User Pattern 1, User Pattern 2, User Pattern 3, User Pattern 4, and so on). Single Pattern. Place each User Pattern (User Pattern 1 through User Pattern 4) on the output for 1 clock cycle and then output all zeros. (Output User Pattern 1 through User Pattern 4, then output all zeros). Reserved. Test mode long psuedorandom number test generator reset. Long psuedorandom enabled. Long psuedorandom held in reset. Test mode short psuedorandom number Test generator reset. Short psuedorandom enabled. Short psuedorandom held in reset. Test mode generation selection. Off; normal operation. Midscale short. Positive full scale. Negative full scale. Alternating checker board. Psuedorandom sequence, long. Psuedorandom sequence, short. 1/0 word toggle. User pattern test mode (used with TMODE_USR_PAT_SEL and the User Pattern 1 through User Pattern 4 registers). 1111: ramp output. User Test Pattern 1 LSB. User Test Pattern 1 LSB. 0 0x0551 0x0552 Description Denominator correction term for the MBW. Rev. 0 | Page 122 of 135 Data Sheet Address 0x0554 0x0555 0x0556 0x0557 0x0558 0x0559 0x055A 0x0561 0x0562 Name User Pattern 2 MSB User Pattern 3 LSB User Pattern 3 MSB User Pattern 4 LSB User Pattern 4 MSB Output Mode Control 1 AD9695 Description User Test Pattern 2 LSB. Reset 0x0 Access R/W User Pattern 3 [7:0] User Pattern 3 [15:8] User Test Pattern 3 LSB. User Test Pattern 3 LSB. 0x0 0x0 R/W R/W [7:0] [7:0] User Pattern 4 [7:0] User Pattern 4 [15:8] User Test Pattern 4 LSB. User Test Pattern 4 LSB. 0x0 0x0 R/W R/W [7:4] Converter control Bit 1 selection 0x0 R/W [3:0] Converter control Bit 0 selection 0x0 R/W Output Mode Control 2 [7:4] [3:0] Reserved Converter control Bit 2 selection 0x0 0x1 R R/W Output sample mode [7:3] 2 Reserved Sample invert 0x0 0x0 R/W R/W [1:0] Data format select 0x1 R/W [7:0] Data format overrange clear Tie low (1'b0). Overrange bit. Signal monitor bit. Fast detect (FD) bit. SYSREF±. Tie low (1'b0). Overrange bit. Signal monitor bit. Fast detect (FD) bit. SYSREF±. Reserved. Tie low (1'b0). Overrange bit. Signal monitor bit. Fast detect (FD) bit. SYSREF±. Reserved. ADC sample data is not inverted. ADC sample data is inverted. Offset binary. Twos complement (default). Overrange clear bits (one bit for each virtual converter). Overrange bit enabled. Overrange bit cleared. Writing a 1 to the overrange clear bit clears the corresponding overrange sticky bit. Overrange sticky bit status (one bit for each virtual converter). No overrange occurred Overrange occurred. Writing a 1 to the overrange clear bit clears the corresponding overrange sticky bit. Reserved. Normal channel ordering. Channel swap enabled. Depending on the application mode selected in Register 0x0200, enabling the channel swap bit (Register 0x0564, Bit 0) swaps the A/B or I/Q converters. Lane rate = 13.5 Gbps to 16 Gbps. Lane rate = 6.75 Gbps to 13.5 Gbps. Lane rate = 3.375 Gbps to 6.75 Gbps. Lane rate = 1.6875 Gbps to 3.375 Gbps. Reserved. 0x0 R/W 0x0 R 0x0 0x0 R R/W 0x3 R/W 0x0 R Output overrange clear Bits [7:0] Bit Name User Pattern 2 [15:8] [7:0] [7:0] Settings 0000 0001 0010 0011 0101 0000 0001 0010 0011 0101 0000 0001 0010 0011 0101 0 1 00 01 0 1 0x0563 Output overrange status [7:0] Data format overrange 0 1 0x0564 0x056E Output channel select [7:1] 0 Reserved Converter channel swap control PLL control [7:4] JESD204B lane rate control [3:0] Reserved 0 1 0011 0000 0001 0101 Rev. 0 | Page 123 of 135 AD9695 Address 0x056F Data Sheet Name PLL status Bits 7 Bit Name PLL lock status [6:4] 3 Reserved PLL loss of lock Settings 0 1 1 0x0571 JESD204B Link Control 1 [2:0] 7 Reserved Standby mode 0 1 6 Tail bit (t) PN 5 Long transport layer test 4 Lane synchronization [3:2] ILAS sequence mode 0 1 0 1 0 1 00 01 11 1 FACI 0 1 0 Link control 0 1 0x0572 JESD204B Link Control 2 [7:6] SYNCINB± pin control 5 SYNCINB± pin invert 4 SYNCINB± pin type 3 2 Reserved 8-bit/10-bit bypass 1 8-bit/10-bit bit invert 0 Reserved 00 10 11 0 1 0 1 0 1 0 1 Rev. 0 | Page 124 of 135 Description Not locked. Locked. Reserved. Loss of lock sticky bit. Indicates a loss of lock occurred at some time; cleared by setting Register 0x0571, Bit 0. Reserved Standby mode forces zeros for all converter samples. Standby mode forces code group synchronization (K28.5 characters). Disable. Enable. JESD204B test samples disabled. JESD204B test samples enabled; long transport layer test sample sequence (as specified in JESD204B Section 5.1.6.3) sent on all link lanes. Disable FACI uses /K28.7/. Enable FACI uses /K28.3/ and /K28.7/. Initial lane alignment sequence disabled (JESD204B, Section 5.3.3.5). Initial lane alignment sequence enabled (JESD204B, Section 5.3.3.5). Initial lane alignment sequence always on test mode (JESD204B data link layer test mode) where repeated lane alignment sequence (as specified in JESD204B, Section 5.3.3.8.2) sent on all lanes. Frame alignment character insertion enabled (JESD204B, Section 5.3.3.4). Frame alignment character insertion disabled; for debug only (JESD204B, Section 5.3.3.4). JESD204B serial transmit link enabled. Transmission of the /K28.5/ characters for code group synchronization is controlled by the SYNCINB± pin. JESD204B serial transmit link powered down (held in reset and clock gated). Normal mode. Ignore SYNCINB± (force CGS). Ignore SYNCINB± (force ILAS/user data). SYNCINB± pin not inverted. SYNCINB± pin inverted. LVDS differential pair SYNC input. CMOS single-ended SYNC input. Reserved. 8-bit/10-bit enabled. 8-bit/10-bit bypassed (the most significant 2 bits are 0). Normal. Invert a, b, c, d, e, f, g, h, I, and j symbols. Reserved. Reset 0x0 Access R 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W Data Sheet Address 0x0573 Name JESD204B Link Contro 3 AD9695 Bits [7:6] Bit Name Checksum mode Settings 00 01 10 [5:4] 0x0574 JESD204B Link Control 4 Test injection point [3:0] JESD204B test mode patterns [7:4] ILAS delay 11 0 1 10 0 1 10 11 100 101 110 111 1000 1110 1111 0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 3 Reserved Rev. 0 | Page 125 of 135 Description Checksum is the sum of all 8-bit registers in the link configuration table. Checksum is the sum of all individual link configuration fields (LSB aligned). Checksum is disabled (set to zero). For test purposes only. Unused. N' sample input. 10 bit data at 8-bit/10-bit output (for PHY testing) 8-bit data at scrambler input. Normal operation (test mode disabled). Alternating checkerboard. 1/0 word toggle. 31-bit PN sequence (x31 + x28 + 1). 23-bit PN sequence (x23 + x18 + 1). 15-bit PN sequence (x15 + x14 + 1). 9-bit PN sequence (x9 + x5 + 1). 7-bit PN sequence (x7 + x6 + 1). Ramp output. Continuous/repeat user test. Single user test. Transmit ILAS on first LMFC after SYNCINB± deasserted. Transmit ILAS on second LMFC after SYNCINB± deasserted. Transmit ILAS on third LMFC after SYNCINB± deasserted. Transmit ILAS on fourth LMFC after SYNCINB± deasserted. Transmit ILAS on fifth LMFC after SYNCINB± deasserted. Transmit ILAS on sixth LMFC after SYNCINB± deasserted. Transmit ILAS on seventh LMFC after SYNCINB± deasserted. Transmit ILAS on eighth LMFC after SYNCINB± deasserted. Transmit ILAS on ninth LMFC after SYNCINB± deasserted. Transmit ILAS on tenth LMFC after SYNCINB± deasserted. Transmit ILAS on eleventh LMFC after SYNCINB± deasserted. Transmit ILAS on twelfth LMFC after SYNCINB± deasserted. Transmit ILAS on thirteenth LMFC after SYNCINB± deasserted. Transmit ILAS on fourteenth LMFC after SYNCINB± deasserted. Transmit ILAS on fifteenth LMFC after SYNCINB± deasserted. Transmit ILAS on sixteenth LMFC after SYNCINB± deasserted. Reserved. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R AD9695 Address Data Sheet Name Bits [2:0] Bit Name Link layer test mode Settings 000 001 010 011 100 101 110 111 Description Normal operation (link layer test mode disabled). Continuous sequence of /D21.5/ characters. Reserved. Reserved. Modified RPAT test sequence. JSPAT test sequence. JTSPAT test sequence. Reserved. Reserved. Local multiframe clock (LMFC) phase offset value. Reset value for the LMFC phase counter when SYSREF± is asserted. Used for deterministic delay applications. JESD204B serial DID number. Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 R/W 0x0578 JESD204B LMFC offset [7:5] [4:0] Reserved LMFC phase offset value 0x0580 JESD204B device identification (DID) configuration JESD204B bank identification (BID) configuration JESD204B Lane Identification 0 (LID0) configuration JESD204B LID1 configuration [7:0] JESD204B Tx DID value [7:4] [3:0] Reserved JESD204B Tx BID value Reserved. JESD204B serial BID number (extension to DID). 0x0 0x0 R R/W [7:5] [4:0] Reserved Lane 0 LID value Reserved. JESD204B serial LID number for Lane 0. 0x0 0x0 R R/W [7:5] [4:0] [7:5] [4:0] [7:5] [4:0] 7 Reserved Lane 1 LID value Reserved Lane 2 LID value Reserved Lane 3 LID value JESD204B scrambling (SCR) 0x0 0x1 0x0 0x2 0x0 0x3 0x1 R R/W R R/W R R/W R/W [6:5] [4:0] Reserved JESD204B lanes (L) 0x0 0x3 R R/W JESD204B link number of octets per frames (F) [7:0] JESD204B F configuration 0x0 R/W JESD204B link number of frames per multiframe (K) [7:5] [4:0] Reserved. JESD204B serial LID number for Lane 1. Reserved. JESD204B serial LID number for Lane 2. Reserved. JESD204B serial LID number for Lane 3. JESD204B scrambler disabled (SCR = 0). JESD204B scrambler enabled (SCR = 1). Reserved. One lane per link (L = 1). Two lanes per link (L = 2). Four lanes per link (L = 4). JESD204B number of octets per frame (F = JESD204B_F_CONFIG + 1). F = 1. F = 2. F = 3. F = 4. F = 6. F = 8. F = 16. Reserved. JESD204B number of frames per multiframe (K = JESD204B_K_CONFIG + 1). Only values where F × K which are divisible by 4 can be used. 0x0 0x1F R R/W 0x0581 0x0583 0x0584 0x0585 JESD204B LID2 configuration 0x0586 JESD204B LID3 configuration 0x058B JESD204B scrambling and number of lanes (L) configuration 0x058C 0x058D 0 1 0x0 0x1 0x3 0 1 10 11 101 111 1111 Reserved JESD204B K configuration Rev. 0 | Page 126 of 135 Data Sheet Address 0x058E Name JESD204B link number of converters (M) AD9695 Bits [7:0] Bit Name JESD204B M configuration Settings 0 1 11 111 0x058F 0x0590 JESD204B number Of control bits (CS) and ADC resolution (N) JESD204B SCV NP configuration [7:6] Number of control bits (CS) per sample 0 1 10 11 5 [4:0] Reserved ADC converter resolution (N) [7:5] Subclass support [4:0] ADC number of bits per sample (N') Reserved Samples per converter frame cycle (S) HD value 0x0591 JESD204B JV S configuration [7:5] [4:0] 0x0592 JESD204B HD CF configuration 7 [6:5] [4:0] 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 001 00111 01111 0 1 Reserved Control words per frame clock cycle per link (CF) Checksum 0 value for SERDOUT0± 0x05A0 JESD204B Checksum 0 configuration [7:0] 0x05A1 JESD204B Checksum 1 configuration [7:0] Checksum 1 value for SERDOUT1± 0x05A2 JESD204B Checksum 2 configuration [7:0] Checksum 2 value for SERDOUT2± 0x05A3 JESD204B Checksum 3 configuration [7:0] Checksum 3 value for SERDOUT3± Rev. 0 | Page 127 of 135 Description JESD204B number of converters per link/device (M = JESD204B_M_CFG). Link connected to one virtual converter (M = 1). Link connected to two virtual converters (M = 2). Link connected to four virtual converters (M = 4). Link connected to eight virtual converters (M = 8). No control bits (CS = 0) 1 control bit (CS = 1), Control Bit 2 only. 2 control bits (CS = 2), Control Bit 2 and Control Bit 1only. 3 control bits (CS = 3), all control bits (2, 1,and 0). Reserved. N = 7-bit resolution. N = 8-bit resolution. N = 9-bit resolution. N = 10-bit resolution. N = 11-bit resolution. N = 12-bit resolution. N = 13-bit resolution. N = 14-bit resolution. N = 15-bit resolution. N = 16-bit resolution. Subclass 0. Subclass 1. N' = 8. N' = 16. Reserved. Samples per converter frame cycle (S = Register 0x0591, Bits[4:0]+1) High density format disabled. High density format enabled. Reserved. Number of control words per frame clock cycle per link (CF = Register 0x0592, Bits[4:0]). Serial Checksum Value for Lane 0. Automatically calculated for each lane. Sum(all link configuration parameters for Lane 0) mod 256. Serial Checksum Value for Lane 1. Automatically calculated for each lane. Sum(all link configuration parameters for Lane 1) mod 256. Serial Checksum Value for Lane 2. Automatically calculated for each lane. Sum(all link configuration parameters for each lane) mod 256. Serial Checksum Value for Lane 3. Automatically calculated for each lane. Sum(all link configuration parameters for Lane 3) mod 256. Reset 0x1 Access R/W 0x0 R/W 0x0 0xF R R/W 0x1 R/W 0xF R/W 0x1 0x0 R R 0x0 R 0x0 0x0 R R 0xC3 R 0xC4 R 0xC5 R 0xC6 R AD9695 Address 0x05B0 Data Sheet Name JESD204B lane power-down Bits 7 6 5 4 3 2 1 0 0x05B2 0x05B3 0x05B5 0x05B6 0x05BF JESD204B Lane Assignment 1 JESD204B Lane Assignment 2 JESD204B Lane Assignment 3 JESD204B Lane Assignment 4 SERDOUTx± data invert [7:3] [2:0] [7:3] [2:0] [7:3] [2:0] [7:3] [2:0] 7 6 Bit Name Reserved JESD204B Lane 3 power-down Reserved JESD204B Lane 2 power-down Reserved JESD204B Lane 1 power-down Reserved JESD204B Lane 0 power-down Reserved SERDOUT0± lane assignment Reserved SERDOUT1± lane assignment Reserved SERDOUT2± lane assignment Reserved SERDOUT3± lane assignment Settings 0 1 10 11 0 1 10 11 0 1 10 11 0 1 10 11 Reserved Invert SERDOUT3± data 0 1 5 4 Reserved Invert SERDOUT2± data 0 1 3 2 Reserved Invert SERDOUT1± data 0 1 1 0 Reserved Invert SERDOUT0± data 0 1 Rev. 0 | Page 128 of 135 Description Reserved. Physical Lane 3 force power-down. Reset 0x0 0x0 Access R R/W Reserved. Physical Lane 2 force power-down. 0x0 0x0 R R/W Reserved. Physical Lane 1 force power-down. 0x0 0x0 R R/W Reserved. Physical Lane 0 force power-down. 0x0 0x0 R R/W Reserved. Physical Lane 0 assignment. Logical Lane 0. Logical Lane 1. Logical Lane 2. Logical Lane 3. Reserved. Physical Lane 1 assignment. Logical Lane 0. Logical Lane 1 Logical Lane 2 Logical Lane 3. Reserved. Physical Lane 2 assignment. Logical Lane 0. Logical Lane 1. Logical Lane 2. Logical Lane 3. Reserved. Physical Lane 3 assignment. Logical Lane 0. Logical Lane 1. Logical Lane 2. Logical Lane 3. Reserved. Invert SERDOUT3± data. Normal. Invert. Reserved. Invert SERDOUT2± data. Normal. Invert. Reserved. Invert SERDOUT1± data Normal. Invert. Reserved. Invert SERDOUT0± data. Normal. Invert. 0x0 0x0 R R/W 0x0 0x1 R R/W 0x0 0x2 R R/W 0x0 0x3 R R/W 0x0 0x0 R/W R/W 0x0 0x0 R/W R/W 0x0 0x0 R/W R/W 0x0 0x0 R/W R/W Data Sheet Address 0x05C0 0x05C1 0x05C2 0x05C3 0x05C4 Name JESD204B Swing Adjust 1 JESD204B Swing Adjust 2 JESD204B Swing Adjust 3 JESD204B Swing Adjust 4 SERDOUT0± preemphasis select AD9695 Bits [7:3] [2:0] [7:3] [2:0] [7:3] [2:0] [7:3] [2:0] 7 SERDOUT1± preemphasis select [3:0] 7 SERDOUT2± preemphasis select Reserved SERDOUT2± voltage swing adjust Reserved SERDOUT3± voltage swing adjust 0 1 2 0 1 2 0 1 2 0 1 2 Post tap enable Set post tap level for SERDOUT0± 000 001 010 011 100 Reserved Post tap enable 0 1 [6:4] 0x05C8 Reserved SERDOUT1± voltage swing adjust Settings 0 1 [6:4] 0x05C6 Bit Name Reserved SERDOUT0± voltage swing adjust [3:0] 7 Set post tap level for SERDOUT1 000 001 010 011 100 Reserved Post tap enable 0 1 [6:4] [3:0] Set post tap level for SERDOUT2 000 001 010 011 100 Reserved Rev. 0 | Page 129 of 135 Description Reserved. Output swing level for SERDOUT0±. 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. Output swing level for SERDOUT1±. 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. Output swing level for SERDOUT2±. 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. Output swing level for SERDOUT3±. 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Post tab enable. Disable. Enable. Set post tap level. 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Post tab enable. Disable. Enable. Set post tap level. 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Post tab enable. Disable. Enable. Set post tap level. 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Reset 0x0 0x1 Access R R/W 0x0 0x1 R R/W 0x0 0x1 R R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 R/W AD9695 Address 0x05CA Data Sheet Name SERDOUT3± preemphasis select Bits 7 Bit Name Post tap enable Settings 0 1 [6:4] Set post tap level for SERDOUT3± [3:0] Reserved Programmable Filter Control and Coefficients Registers 0x0DF8 [7:3] Reserved Programmable filter control [2:0] Programmable filter mode 000 001 010 011 100 000 001 010 100 101 0x0DF9 PFILT gain 7 [6:4] Reserved PFILT Y gain 3 [2:0] Reserved PFILT X gain Rev. 0 | Page 130 of 135 Description Post tab enable. Disabled Enabled. Set post tap level. 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Reserved. Programmable filter (PFILT) mode. Disabled (filters bypassed). Single filter (Filter X only). DOUT_I[n] = DIN_I[n] × X_I[n]. DOUT_Q[n] = DIN_Q[n] × X_Q[n]. Single filter (Filter X and Filter Y together). DOUT_I[n] = DIN_I[n] × XY_I[n]. DOUT_Q[n] = DIN_Q[n] × XY_Q[n]. Cascaded filters (Filter X to Filter Y). DOUT_I[n] = DIN_I[n] × X_I[n] × Y_I[n]. DOUT_Q[n] = DIN_Q[n] × X_Q[n] × Y_Q[n]. Complex filters. DOUT_I[n] = DIN_I[n] × X_I[n] + DIN_Q[n] × Y_Q[n]. DOUT_Q[n] = DIN_Q[n] × X_Q[n] + DIN_I[n] × Y_I[n]. Reserved. Programmable filter (PFILT) Y gain 100 = reserved. 101 = reserved. 110 = −12 dB loss. 111 = −6 dB loss. 000: 0 dB gain. 001: +6 dB gain. 010: +12 dB gain. 011: reserved. Reserved. Programmable filter (PFILT) X gain. 100 = reserved. 101 = reserved. 110 = −12 dB loss. 111 = −6 dB loss. 000: 0 dB gain. 001: +6 dB gain. 010: +12 dB gain. 011: reserved. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 0x0 R R/W Data Sheet AD9695 Address 0x0E00 to 0x0E7F Name Programmable Filter X Coefficient x Bits [7:0] Bit Name Programmable Filter X Coefficient 0 to Programmable Filter X Coefficient 127 0x0F00 to 0x0F7F Programmable Filter Y Coefficient x [7:0] Programmable Filter Y Coefficient 0 to Programmable Filter Y Coefficient 127 VREF/Analog Input Control Registers 0x0701 [7] DC Offset Calibration Control 1 (local) 0x073B 0x18A6 0x18E3 0x18E6 DC Offset Calibration Control 2 (local) VREF control External VCM buffer control Temperature diode export [6:0] [7] DC Offset Calibration Enable 1 Settings 0 1 Reserved DC Offset Calibration Enable 2 110 0 1 [6:0] [7:1] 0 Reserved Reserved VREF control 7 6 Reserved External VCM buffer [5:0] External VCM buffer [5:0] Temperature diode location select [7:0] 111111 0 1 0 1 0x00 0x01 0x02 0x03 0x40 0x41 0x42 0x43 0x50 0x51 0x52 0x53 0x1908 Analog input control (local) [7:3] 2 Reserved Enable dc coupling [1:0] Reserved 0 1 Rev. 0 | Page 131 of 135 Description Refer to the I coefficient table (Table 14) and the Q coefficient table (Table 15) in the Programmable Finite Impulse Response (FIR) Filters section for details. Coefficients are only applied after the chip transfer bit (Register 0x000F, Bit 0) is set. Refer to the I coefficient table (Table 14) and the Q coefficient table (Table 15) in the Programmable Finite Impulse Response (FIR) Filters section for details. Coefficients are only applied after the chip transfer bit (Register 0x000F, Bit 0) is set. Reset 0x0 Access R/W 0x0 R/W Disabled (must set to 0 when Register 0x073B, Bit 7 = 1). Enabled (must set to 1 when Register 0x073B, Bit 7 = 0). Reserved. Enabled (must set to 0 when Register 0x0701, Bit 7 = 1). Disabled (must set to 1 when Register 0x0701, Bit 7 = 0). Reserved. Reserved. Internal reference. External reference. Reserved. Disable. Enable. See the Input Common Mode section. 0x0 R/W 0x6 0x1 R R/W 0x3F 0x0 0x0 R R R/W 0x0 0x0 R R/W 0x0 R/W See the Temperature Diode section. 0x0 Central diode. VREF pin = high-Z. Central diode. VREF pin = 1× diode voltage output. Central diode. VREF pin = 20× diode voltage output. Central diode. VREF pin = GND. Channel A diode. VREF pin = high-Z. Channel A diode. VREF pin = 1× diode voltage output. Channel A diode. VREF pin = 20× diode voltage output. Channel A diode. VREF pin = GND. Channel B diode. VREF pin = high-Z. Channel B diode. VREF pin = 1× diode voltage output. Channel B diode. VREF pin = 20× diode voltage output. Channel B diode. VREF pin = GND. Reserved. 0x0 Analog input optimized for ac coupling. 0x0 Analog input optimized for dc coupling. Reserved. 0x0 R/W R R/W R AD9695 Address 0x1910 Data Sheet Name Input full-scale control (local) Bits [7:4] [3:0] Bit Name Reserved TRM VREF 1.8 V Settings 0 1010 1011 1100 1101 1110 1111 0x1A4C Buffer Control 1 (local) [7:6] [5:0] Reserved Buffer Control P 00110 01000 01010 01100 01110 10000 10010 10100 0x1A4D Buffer Control 2 (local) [7:6] [5:0] Reserved Buffer Control N 00110 01000 01010 01100 01110 10000 10010 10100 0x1B03 Buffer Control 3 (local) [7:0] Buffer Control 3 0x00 0x02 0x1B08 0x1B10 Buffer Control 4 (local) [7:0] Buffer Control 5 (local) [7:0] Buffer Control 4 0x01 0xC1 Buffer Control 5 0x00 0x1C Rev. 0 | Page 132 of 135 Description Reserved. Full-scale voltage setting. 2.04 V p-p differential. 1.36 V p-p differential. 1.47 V p-p differential. 1.59 V p-p differential. 1.70 V p-p differential. 1.81 V p-p differential. 1.93 V p-p differential. Reserved. Input buffer main current (P). Buffer current set to 120 μA. Buffer current set to 160 μA. Buffer current set to 200 μA. Buffer current set to 240 μA. Buffer current set to 280 μA. Buffer current set to 320 μA. Buffer current set to 360 μA. Buffer current set to 400 μA. Reserved. Input buffer main current (N). Buffer current set to 120 μA. Buffer current set to 160 μA. Buffer current set to 200 μA. Buffer current set to 240 μA. Buffer current set to 280 μA. Buffer current set to 320 μA. Buffer current set to 360 μA. Buffer current set to 400 μA. Buffer Control 3. Setting 1 Setting 2 Buffer Control 4. Setting 1 Setting 2 Buffer Control 5. Setting 1 Setting 2 Reset 0x0 0xD Access R R/W 0x0 0x1E R R/W 0x0 0x1E R R/W 0x00 R/W 0x01 R/W 0x00 R/W Data Sheet AD9695 APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS The power supplies required to power the AD9695 are shown in Table 44. Table 44. Typical Power Supplies for AD9695 Voltage (V) 0.95 0.95 0.95 0.95 1.8 1.8 1.8 2.5 Tolerance (%) ±2.5 ±2.5 ±2.5 ±2.5 ±5 ±5 ±5 ±2.5 For applications requiring an optimal high power efficiency and low noise performance, it is recommended that the ADP5054 quad switching regulator be used to convert the 6.0 V or 12 V input rails to intermediate rails (1.3 V, 2.4 V, and 3.0 V). These intermediate rails are then postregulated by very low noise, low dropout (LDO) regulators (ADP1763, ADP7159, and ADP151). Figure 143 shows the recommended power supply scheme for the AD9695. 6.0V TO 15.0V 1.3V ANALOG ADP5054 1.3V DIGITAL ADP1763 ADP1763 ADP7159 ADP151 ADP5054 ADP1763 1.3V DIGITAL AVDD1 0.95V AVDD1_SR 0.95V DVDD 0.95V SW3 DRVDD1 0.95V SW4 2.4V ADP7159 AVDD1_SR 0.95V OPTIONAL DVDD 0.95V AVDD2 1.8V SPIVDD 1.8V FERRITE BEAD LDO SWITCHER OPTIONAL PATH 3.0V ADP7159 AVDD3 2.5V NOTES 1. ALL VOLTAGES REFERENCED TO AGND. AVDD2 1.8V Figure 144. Simplified Power Solution for the AD9695 OPTIONAL DRVDD2 1.8V The user can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors must be located close to the point of entry at the PCB level and close to the devices, with minimal trace lengths. AVDD3 2.5V 15660-113 LDO SWITCHER OPTIONAL PATH REFERENCED TO AGND ADP7159 SW2 1.3V ANALOG DRVDD2 1.8V SPIVDD 1.8V 3.0V SW1 AVDD1 0.95V DRVDD1 0.95V 2.4V 12V FROM FMC OR 6.0V FROM WALL SUPPLY Figure 143. High Efficiency, Low Noise Power Solution for the AD9695 Rev. 0 | Page 133 of 135 15660-114 Domain AVDD1 AVDD1_SR DVDD DRVDD1 AVDD2 DRVDD2 SPIVDD AVDD3 It is not necessary to split all of these power domains in all cases. The recommended solution shown in Figure 143 provides the lowest noise, highest efficiency power delivery system for the AD9695. If only one 0.975 V supply is available, route to AVDD1 first and then tap it off and isolate it with a ferrite bead or a filter choke, preceded by decoupling capacitors for AVDD1_SR, DVDD, and DRVDD1, in that order. Figure 144 shows the simplified schematic. Alternatively, the LDOs can be bypassed altogether and the AD9695 can be driven directly from the dcto-dc converter. Note that this approach has risks in that there may be more power supply noise injected into the power supply domains of the ADC. To minimize noise, follow the layout guidelines of the dc-to-dc converter. AD9695 Data Sheet LAYOUT GUIDELINES The ADC evaluation board can be used as a guide to follow good layout practices. The evaluation board layout is set up in such a way as to Minimize coupling between the analog inputs (Channel A to Channel B and Channel B to Channel A). Minimize clock coupling to the analog inputs. Provide enough power and ground planes for the various supply domains while reducing cross coupling. Provide adequate thermal relief to the ADC. AVDD1_SR (PIN 57) AND AGND_SR (PIN 56 AND PIN 60) AVDD1_SR (Pin 57) and AGND_SR (Pin 56 and Pin 60) can be used to provide a separate power supply node to the SYSREF± circuits of AD9695. If running in Subclass 1, the AD9695 can support periodic one-shot or gapped signals. To minimize the coupling of this supply into the AVDD1 supply node, adequate supply bypassing is needed. Figure 145 shows the overall layout scheme used for the AD9695 evaluation board. CH.A EF SR SY ADC CH.B JESD204B LANES POWER Figure 145. Recommended PCB Layout for the AD9695 . Rev. 0 | Page 134 of 135 15660-115 CLK Data Sheet AD9695 OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.25 0.18 PIN 1 INDICATOR 49 PIN 1 INDICATOR 64 1 48 0.50 BSC EXPOSED PAD 6.30 6.20 SQ 6.10 33 PKG-004559 0.80 0.75 0.70 32 17 16 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE 0.20 MIN 7.50 REF COMPLIANT TO JEDEC STANDARDS MO-220-WMMD 06-06-2014-A TOP VIEW 0.45 0.40 0.35 Figure 146. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm × 9 mm Body and 0.75 mm Package Height (CP-64-17) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9695BCPZ-625 AD9695BCPZRL7-625 AD9695-625EBZ AD9695BCPZ-1300 AD9695BCPZRL7-1300 AD9695-1300EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP] 64-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board 64-Lead Lead Frame Chip Scale Package [LFCSP] 64-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15660-0-9/17(0) Rev. 0 | Page 135 of 135 Package Option CP-64-17 CP-64-17 CP-64-17 CP-64-17