Supertex inc. HV633 32-Channel, 128-Level Amplitude Gray-Shade Display Column Driver Features ►► HVCMOS® technology ►► 5.0V CMOS inputs ►► Capable of 128 levels of gray shading ►► Modulation voltage up to +80V ►► 24MHz data throughput rate ►► 32 outputs per device (can be cascaded) ►► Pin-programmable shift direction (DIR) ►► D/A conversion cycle time is 20µs ►► Diodes in output structure allow usage in energy recovery systems ►► Available in 3-sided 64-lead gull wing package Applications ►► Electroluminescent Displays ►► Polycholesteric Displays General Description The HV633 is a 32-channel driver IC for gray shade display use. It is designed to produce varying output voltages between 3.0 - 80V. This amplitude modulation at the output is facilitated by an external ramp voltage VR. See Theory of Operation for detailed explanation. This device consists of dual 16-bit shift registers, 32 data latches and comparators, and control logic to preform 128 levels of gray shading. There are 7 bits of data inputs. Data is shifted through the shift registers at both edges of the clock, resulting in a data transfer rate of twice that of the shift clock frequency. When the DIR pin is high, CSI/CSO is the input/ output for the chip select pulse. When DIR is low, CSI/CSO is the output/input for the chip select pulse. When the DIR pin is high, it allows the HV633 to shift data in the counter-clockwise direction when viewed from the top of the package. When the DIR pin is low, data is shifted in the clockwise direction. The output circuitry allows the energy which is stored in the output capacitance to be returned to VPP through the body diode of the output transistor. Functional Block Diagram VDD CSI LC Shift Register Latches Comparator Counter CC CSO DIR 7 32 Source Follower Output Buffer HVOUT1 ~ ~ HVOUT32 IBIAS Control VCTL Doc.# DSFP-HV633 C031414 VPP High Voltage Low Voltage SC D1 - D7 VR RCTL Supertex inc. www.supertex.com HV633 Pin Configuration Ordering Information Part Number Package Option Packing HV633PG-G 64-Lead PQFP 66/Tray 64 -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value Supply voltage, VDD -0.5V to +7.5V Supply voltage, VPP -0.5V to +90V Logic input levels 1 64-Lead PQFP -0.5V to VDD +0.5V Ground current1 (top view) 1.5A Operating temperature range Storage temperature range 0°C to +125°C -65°C to +150°C Continuous total power dissipation2 Product Marking 2.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Duty cycle is limited by the total power dissipated in the package. 2. For operation above 25°C ambient derate linearly to 125°C at 20mW/°C. L = Lot Number YY = Year Sealed WW = Week Sealed C = Country of Origin A = Assembler ID = “Green” Packaging Top Marking HV 6 3 3 P G LLLLLLLLLL Y Y WW CCCCCCCC AAA Package may or may not include the following marks: Si or 64-Lead PQFP Typical Thermal Resistance Package θja 64-Lead PQFP 41OC/W Recommended Operating Conditions Sym VDD Parameter Low-voltage digital supply voltage Low-voltage analog supply voltage Min Typ Max Units 4.5 5.0 5.5 V VIH High-level input voltage (analog & digital) VDD -1 - VDD V VIL Low-level input voltage (analog & digital) 0 - 1.0 V -2.0 0 - V - 0 2.0 V -0.3 - 80 V VBIAS IPP control circuit bias voltage VCTL IPP control circuit control voltage VPP High voltage supply VR Ramp voltage 0 - VPP -2 V fSC Shift clock operating frequency (at VDD = 5.5V) - - 12 MHz Doc.# DSFP-HV633 C031414 2 Supertex inc. www.supertex.com HV633 Electrical Characteristics (over recommended operating conditions at T = 25°C unless otherwise noted) A Low Voltage DC Characteristics (Digital) Sym Parameter Min Typ 1 Max Units Conditions IDD VDD supply current - 12 20 mA fSC = 12MHz, fCC = 12MHz IDDQ Quiescent VDD supply current - - 200 µA All VIN = 0V, VDD = 5.5V High-level input current - 1.0 50 µA VIH = VDD Low-level input current - -1.0 -50 µA VIL = 0V CIN Input capacitance (D1 ~ D7, LC, SC, CC) - - 15 pF VIN = 0V, f = 1.0MHz IOH High-level output current -2.0 - - mA VDD = 4.5V, VOH = 0.9VDD IOL Low-level output current 2.0 - - mA VDD = 4.5V, VOL = 0.1VDD IIH IIL 2 Notes: 1. All typical values are at VDD = 5.0V. 2. Guaranteed by design. Low Voltage DC Characteristics (Analog) IDD VDD supply current - - 500 µA fSC = 12MHz, fCC = 12MHz IDDQ Quiescent VDD supply current - - 200 µA All VIN = 0V, VDD = 5.5V 2.0 - mA Depending on external bias circuit, see Table 1. mA VPP = 80V. See Test Circuit mA VPP = 80V, VDD = 4.5V, VAO = 2.0V High Voltage Bias Circuit for Output Variation Control IPP VPP supply current for bias circuit - High Voltage DC Characteristics IAOH High-voltage analog output source current IAOL High-voltage analog output sink current ΔVO Maximum delta voltage between high voltage outputs of the same level AC Characteristics (V Logic Timing DD See performance curves See performance curves - - ±0.2 V At all gray levels = 5.5V, TA = 25°C) fSC Shift clock operating frequency - - 12 MHz --- fDIN Data-in frequency - - 24 MHz --- tSS CSI/CSO pulse to shift clock setup time - 40 - ns --- tHS CSI/CSO pulse to shift clock hold time - 0 - ns --- tWA CSI pulse width - 49 - ns --- tDS Data to shift clock setup time - 20 - ns --- tDH Data to shift clock hold time - 0 - ns --- tWD Data-in pulse width - 24 - ns --- tWLC Load count pulse width - 98 - ns --- tDLCR Load count to ramp delay 1.0 - - µs --- tDRCC3 Ramp to count clock delay 0.47 - - µs --- - 98 - ns --- tDSL Shift clock to load count delay time Doc.# DSFP-HV633 C031414 3 Supertex inc. www.supertex.com HV633 Logic Timing (cont.) Sym Parameter Min Typ Max Units Conditions tCSC Shift clock cycle time 98 - - ns --- tWSC Shift clock pulse width 49 - - ns --- tCCC Count clock cycle time 98 - - ns --- tWCC Count clock pulse width 49 - - ns --- 15 - - µs --- VR Timing tCR Cycle time of ramp signal tRR Ramp rise time 10.6 - - µs --- tHR4 Ramp hold time 2.0 - 15 µs --- tFR Ramp fall time 3.0 - - µs CLOAD = 1nF Notes: 3. Count clock starts counting after 0.47µs min. This is equivalent to a time duration for a linear ramp VR to ramp from 0 to 3.0V, assuming the minimum value of tRR, ramp size time of 12µs for VR = 80V. 4. The maximum ramp hold time may be longer than 15 µs, but the output voltage HVOUT will droop due to leakage. Table 1: Schemes to control IPP bias current, typical IPP Option 1 Option 2 VBIAS VCTL RCTL (kΩ) (mA) IPP VBIAS VCTL RCTL (kΩ) (mA) 0 0.1 56 2.0 -1.0 0 56 4.0 0 1.0 56 7.0 -2.0 0 56 5.5 (V) (V) (V) (V) IPP VCTL + VCTL HV633 RCTL RCTL + VBIAS Function Table Function In DIR Data (D1 - D7) Shift data from HVOUT1 to HVOUT32 H Data Shift data from HVOUT32 to HVOUT1 L Data Load shift register X X Load counter X X Counting/voltage conversion X X Notes: CSI CSO SC Output Output Pre-defined by 1 or 2 LC CC VR HVOUT L L L Data → HVOUT1 → ...→ HVOUT32 L L L Data → HVOUT32 → ...→ HVOUT1 L L L - L L - Initiates VR - L L L L = Low logic level H = High logic level = Low to high transition = Transition of both edges X = Don’t care Doc.# DSFP-HV633 C031414 4 Supertex inc. www.supertex.com HV633 Functional Block Diagram See Output Stage Detail 1 2 VCTL Dual 16-bit Shift Registers RCTL ● L/E Data Latches L/E Data Latches 7 Latches and Comparators Latches and Comparators 7 7 RS F/F Output Stage HVOUT1 RS F/F Output Stage HVOUT2 ● ● ● ● ● 31 32 ● ● ● ● ● ● ● ● ● ● ● ● L/E Data Latches L/E Data Latches SC SC DIR 7 GND VR VPP 7 7 7 RS F/F Output Stage HVOUT31 Latches and 7 Comparators RS F/F Output Stage HVOUT32 Latches and Comparators CC 7 Count Data In Buffers I/O Buffers I/O Buffers Shift Clock Buffer CSI CSO SC Counter Reset Counter Load Clear Pulse Generator D7 ●●●●●●● D1 Load Count Buffer Count Clock Buffer LC CC Note: SC = Shift Clock, LC = Load Count, CC = Count Clock, CSI = Chip Select Input, CSO = Chip Select Output *Data rate = 2x the SC frequency Input and Output Equivalent Circuits VDD VDD DATA OUT DATA IN LVGND LVGND Logic Data Output Logic Inputs Output Stage Detail VR VPP CH VCTL RCTL Doc.# DSFP-HV633 C031414 Internal Logic & Bias Circuit 5 Q1 HVOUT Q2 Supertex inc. www.supertex.com HV633 Test Circuit High-voltage Analog Output Source Current (IAOH). For gray shade #1 (000 0000). VR 70V + – HV633 Output Stage Logic 0V VPP = 80V HVOUT + 1.0kΩ VTST - LVGND 1. 2. 3. 4. 5. 10kΩ HVGND Set HVOUT = Low Apply VPP = 80V Apply a step voltage of 70V at VR (slew rate = 4.1V/µs) Measure voltage across the 1.0KΩ resistor Output source current can be calculated by using VTST /1.0KΩ Typical Panel Connections D1 ~ D7 DIR = LOW VR, VPP LVGND, HVGND, SC, LC, CC, CSO 32 1 32 1 32 1 1 32 Display Panel (Example) VR, VPP LVGND, HVGND, SC, LC, CC, CSI 1 32 1 32 DIR = HIGH D1 ~ D7 Doc.# DSFP-HV633 C031414 6 Supertex inc. www.supertex.com HV633 Timing Diagrams (a) Basic System Timing tCR tHR tRR VR Load First Device Chip Select Input (CSI) Load Second Device tFR Load Last Device Chip Select Output (CSO) Shift Clock (SC) ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ DATA IN (D1 - D7) ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ Data from Data Bus (See Detailed Timing) tDLCR Load Count* (LC) Count Clock (CC) ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 2 3 4 5 128 1 2 3 4 5 128 HVOUT *HVOUT will clear to zero with load count. (b) Detailed Device Timing LOADING LAST DEVICE tWA NEXT LOADING CYCLE Chip Select Input (CSI) tHS tSS Shift Clock (SC) Data (D1-D7) DATA SET 1 tDH Load Count (LC) tCSC SC1 DATA SET 2 tWSC SC2 DATA SET 3 SC 16 DATA SET 31 tWD SC 1 SC 16 DATA SET 1 DATA SET 32 tDSL DATA SET 31 tWLC tDS tWCC tCCC Count Clock (CC) Count Clock 1 tDRCC tDLCR VR Doc.# DSFP-HV633 C031414 0V 7 Count Clock 128 3V Supertex inc. www.supertex.com HV633 Gray Shade Decoding Scheme Shade Number D7 D6 D5 D4 Gray Scale Voltage D3 D2 D1 1 1 1 1 1 1 1 127 1 1 1 1 1 1 0 126 1 1 1 1 1 0 1 125 1 1 1 1 1 0 0 124 1 1 1 1 0 1 1 123 1 1 1 1 0 1 0 122 1 1 1 1 0 0 1 121 1 1 1 1 0 0 0 • • • • • • • • • • • • • • • • • • • • • • • • 7 0 0 0 0 1 1 0 6 0 0 0 0 1 0 1 5 0 0 0 0 1 0 0 4 0 0 0 0 0 1 1 3 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 VR HVOUT HVOUT HVOUT HVOUT (111 1111) 01 2 ● ● ● 127 Gray Scale Voltage 128 (000 0000) HVOUT Clock Cycle Typical Performance Curves Source Output Characteristics 15 12 IO (milliamperes) IO (milliamperes) 12 9 6 3 1 Sink Output Characteristics 15 9 6 3 0 1 2 3 4 5 6 7 0 8 VGS Volts Doc.# DSFP-HV633 C031414 0 1 2 3 4 5 6 7 8 VGS Volts 8 Supertex inc. www.supertex.com HV633 Theory of Operation When data has been loaded into all 32 outputs of all chips (top and bottom of the display panel), the load count pin is pulsed. On its rising transition, all output levels are reset to zero and all the data in the input latches is transferred to a like number of comparator latches, (thus leaving the data latches ready to receive new data during the following operations). After the transfer, the load count pin is brought low. This transition begins the events that convert the binary data into a gray-shade level. The HV633 has two primary functions: 1) Loading data from the data bus and, 2) Gray-shade conversion(converting latched data to output voltages). Since the device was developed initially for flat panel displays, the operation will be described in terms that pertain to that technology. As shown by the Typical Panel Connections, several HV633 packages are mounted at the top and bottom of a display panel. Data exists on a 7-bit bus (adjacent PC board traces) at top and bottom. The D1 through D7 inputs of each chip take data from the bus when either a CSI or CSO pulse is present at the chip. These pulses therefore act as a combination CHIP SELECT and LOCATION STROBE. Because of the way the chip HVOUT pins are sequenced, data on the bus at the bottom of the display panel will be entered into the left-most chip as HVOUT1, HVOUT2, etc. up to HVOUT32. The CSI pulse will accomplish this with DIR = High. Gray-shade Conversion 1) The COUNT CLOCK is started. An external signal is applied to the COUNT CLOCK pin, causing the counter on each chip to increment from binary 000 0000 to 111 1111 (0 to 127). 2) At the same time, the VR voltage is applied to all chips, via charging transistors, causing the HOLD CAPACITOR (CH) on each output to experience a rise in voltage. 3) The logic control compares the count in the comparator latch to the count clock. The gate voltage of Q1 and the output voltage HVOUT will ramp up at the same rate as VR. Loading Data from Data Bus Here is the full data-entry sequence: 4) Once VR has reached the maximum voltage, then all the pixels will be at the final value. (See Gray Scale Voltage.) 1) The micro controller puts data on the bus (7 bits) Output Voltage Variation 2) To enter the data into the 32 sets of 7 latches on the first chip, the shift clock rises. This positive transition is combined with the CSI pulse and is generated only once to strobe the data into the first set of latches. (These latches eventually send data to the HVOUT1). The data on the bus then changes, the shift clock falls, and this negative transition is combined with the CSI pulse, which is now propagated internally, to strobe the new data into the next set of 7 latches (which will end up as HVOUT2). This internal CSI pulse therefore runs at twice the shift clock rate. The output voltage of the HV633 is determined by the logic and the ramp voltage VR. It is possible that the output voltage may be coupled to an unacceptable level due to its adjacent outputs through the panel. In order to solve this problem, internal logic (refer to Output Stage Detail) is integrated in the IC to minimize the effect. Two external pins VCTL and RCTL allow the feasibility to control the current flowing through Q2. The VCTL pin is connected to a voltage source and the RCTL pin is connected to ground through a resistor (2.0V and 56KΩ are used for a particular panel). The internal bias circuit will drive the resistor to a voltage level that is equal to the VCTL voltage at steady state through an operational amplifier. The current flowing through Q1 and Q2 will be limited to VCTL/RCTL. This combination of VCTL and RCTL will reduce the output voltage variation to less than ±0.2V of delta voltage for each gray shade, independent of its adjacent output voltages. 3) When the last set of 7 latches in the first chip has been loaded (HVOUT32), the CSI pulse leaves chip 1 and enters chip 2. The exit pin is called CSO and the chip 2 entry pin is CSI. For chips at the top of the panel things are reversed: DIR is low, entry pins are CSO and exit pins are CSI, because the data-into-latches sequence is in descending order, HVOUT32 down to HVOUT1. 4) The buses may of course be separate, and data can be strobed in on an interleaved basis, etc., but those complications will be left to systems designers. Doc.# DSFP-HV633 C031414 9 Supertex inc. www.supertex.com HV633 Pin Descriptions Pin # Function 1 HVOUT1 2 HVOUT2 3 HVOUT3 4 HVOUT4 5 HVOUT5 6 HVOUT6 7 HVOUT7 8 HVOUT8 9 HVOUT9 10 HVOUT10 11 HVOUT11 12 HVOUT12 13 HVOUT13 14 HVOUT14 15 HVOUT15 16 HVOUT16 17 HVGND This is ground for the high-voltage (output) section. HVGND and LVGND should be connected together externally. 18 VR High voltage ramp input for charging the output stage hold capacitors (CH). This input can be linear or non-linear as desired. 19 VPP This input biases the output source followers. 20 NC No connect. 21 VDD (analog)* 22 CSI Input pin for the chip select pulse (when DIR is high). Output pin for the chip select pulse (when DIR is low). 23 NC No connect. 24 VCTL 25 RCTL 26 SC (shift clock) 27 LVGND 28 DIR 29 VDD (digital)* Description High-voltage outputs Low-voltage analog supply voltage. Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (VCTL = 2.0V for a particular panel). The combination of VCTL and RCTL will reduce the output voltage variation to less than ±0.2V of delta voltage between high voltage outputs of the same level at all gray levels. Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs (RCTL = 56KΩ for a particular panel). See VCTL function above. Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock rate (data rate = 20MHz if clock rate = 10MHz). This is ground for the logic section. HVGND and LVGND should be connected together externally. When this pin is connected to VDD, input data is shifted in ascending order, i.e., corresponding to HVOUT1 to HVOUT32. When connected to LVGND, input data is shifted in descending order, i.e., corresponding to HVOUT32 to HVOUT1. Low-voltage digital supply voltage. * Analog VDD and digital VDD may be connected seperately for better noise immunity. Doc.# DSFP-HV633 C031414 10 Supertex inc. www.supertex.com HV633 Pin Descriptions (cont.) Pin # Function 30 D7 31 D6 32 D5 33 D4 34 D3 35 D2 36 D1 37 NC 38 LVGND 39 NC 40 LC (Load Count) Description Inputs for binary-format parallel data. No connect. This is ground for the logic section. HVGND and LVGND should be connected together externally. No connect. Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches, and whose falling edge initiates the conversion of this binary data to an output level (D-to-A). Also, the HVOUT will clear to zero after the load count is initiated. 41 NC 42 CC (Count Clock) 43 CSO 44 NC No connect. 45 VPP This input biases the output source followers. 46 NC No connect. 47 VR 48 HVGND 49 HVOUT17 50 HVOUT18 51 HVOUT19 52 HVOUT20 53 HVOUT21 54 HVOUT22 55 HVOUT23 56 HVOUT24 57 HVOUT25 58 HVOUT26 59 HVOUT27 60 HVOUT28 61 HVOUT29 62 HVOUT30 63 HVOUT31 64 HVOUT32 Doc.# DSFP-HV633 C031414 No connect. Input to the count clock generator whose increments are compared to the data in the comparator latches. Input pin for the chip select pulse (when DIR is low). Output pin for the chip select pulse (when DIR is high). High-voltage ramp input for charging the output stage hold capacitors (CH).This input can be linear or non-linear as desired. This is ground for the high-voltage (output) section. HVGND and LVGND should be connected together externally. High-voltage outputs 11 Supertex inc. www.supertex.com HV633 64-Lead PQFP (3-Sided) Package Outline (PG) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint D L3 D1 64 E1 E Note 1 (Index Area D1/4 x E1/4) 1 Note 2 e b θ1 Top View View B A A2 Seating Plane A1 L L1 L2 Gauge Plane θ Seating Plane View B Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. The leads on this side are trimmed. Symbol Dimension (mm) A A1 A2 b D D1 E E1 MIN 2.80 0.25 2.55 0.30 22.25 19.80 17.65 13.80 NOM - - 2.80 - 22.50 20.00 17.90 14.00 MAX 3.40 0.50 3.05 0.45 e L L1 0.73 L2 L3 θ θ1 0 5O O 0.80 1.95 0.25 0.55 0.88 3.5O BSC REF BSC REF 22.75 20.20 18.15 14.20 1.03 7O 16O Drawings not to scale. Supertex Doc. #: DSPD-64PQFPPG, Version NR090608. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV633 C031414 12 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com