MPQ4431 36V, 1A, Low Quiescent Current, Synchronous, Step-Down Converter AEC-Q100 Qualified DESCRIPTION FEATURES The MPQ4431 is a frequency-programmable (350kHz to 2.5MHz), synchronous, step-down switching regulator with integrated, internal, high-side and low-side power MOSFETs. It provides up to 1A of highly efficient output current with current mode control for fast loop response. The wide 3.3V to 36V input range accommodates a variety of step-down applications in automotive input environments and is ideal for batterypowered applications due to its extremely low quiescent current. The MPQ4431 employs advanced asynchronous mode (AAM), which helps achieve high efficiency in light-load condition by scaling down the switching frequency to reduce switching and gate driving losses. Wide 3.3V to 36V Operating Input Range 1A Continuous Output Current 1μA Low Shutdown Mode Current 10μA Sleep Mode Quiescent Current Internal 90mΩ High-Side and 80mΩ LowSide MOSFETs 350kHz to 2.5MHz Programmable Switching Frequency Fixed Output Options: 3.3V, 3.8V, 5V Synchronize to External Clock Selectable In-Phase or 180° Out-of-Phase Power Good (PG) Indicator Programmable Soft-Start (SS) Time 80ns Minimum On Time Selectable Forced CCM or AAM Low Dropout Mode Over-Current Protection (OCP) with ValleyCurrent Detection and Hiccup Available in a QFN-16 (3mmx4mm) Package Available with Wettable Flank AEC-Q100 Grade-1 Standard features include soft start (SS), external clock synchronization, enable (EN) control, and a power good (PG) indicator. Highduty cycle and low dropout mode are provided for automotive cold-crank condition. Over-current protection (OCP) with valleycurrent detection is employed to prevent the inductor current from running away. Hiccup mode reduces the average current in shortcircuit condition greatly. Thermal shutdown provides reliable and fault-tolerant operation. APPLICATIONS Automotive Systems Industrial Power Systems All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. The MPQ4431 is available in a QFN-16 (3mmx4mm) package. TYPICAL APPLICATION VIN 3.3 to 36V VIN BST VOUT SW GND FB MPQ4431 Rev. 1.0 3/21/2017 EN SYNC MPQ4431 PHASE FREQ VCC PG BIAS SS www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 1 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 ORDERING INFORMATION Part Number* MPQ4431GL** MPQ4431GL-AEC1** MPQ4431GLE-AEC1*** Package QFN-16 (3mmx4mm) QFN-16 (3mmx4mm) QFN-16 (3mmx4mm) Top Marking See Below See Below See Below * For Tape & Reel, add suffix –Z (e.g. MPQ4431GL–Z) ** Under qualification *** Under qualification, wettable flank TOP MARKING (MPQ4431GL & MPQ4431GL-AEC1) MP: MPS prefix Y: Year code WW: Week code 4431: First four digits of the part number LLL: Lot number TOP MARKING (FOR MPQ4431GLE-AEC1) MP: MPS prefix Y: Year code WW: Week code 4431: First four digits of the part number LLL: Lot number E: Wettable lead flank MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 2 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 PACKAGE REFERENCE TOP VIEW FREQ 16 FB SS AGND 15 14 13 PHASE 1 12 VCC VIN 2 11 BST SW 3 10 SW PGND 4 9 5 EN 6 SYNC 7 PG PGND 8 BIAS QFN-16 (3mmx4mm) ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (3) Supply voltage (VIN) ...................... -0.3V to 40V Switch voltage (VSW) ........... -0.3V to VIN + 0.3V BST voltage (VBST) ............................VSW + 6.5V EN voltage (VEN) ............................ -0.3V to 40V BIAS voltage (VBIAS) ....................... -0.3V to 20V All other pins .................................... -0.3V to 6V Continuous power dissipation (TA = +25°C) (2) QFN-16 (3mmx4mm) .................................2.6W Operating junction temperature................ 150°C Lead temperature .................................... 260°C Storage temperature .................. -65°C to 150°C NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Measured on JESD51-7, 4-layer PCB. θJA θJC QFN-16 (3mmx4mm) ............ 48 ....... 11 ... °C/W Recommended Operating Conditions Supply voltage (VIN) ....................... 3.3V to 36V Operating junction temp. (TJ) ... -40°C to +125°C MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 3 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 ELECTRICAL CHARACTERISTICS VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, unless otherwise noted. Typical values at TJ = +25°C. Parameter Symbol VIN quiescent current IQ VIN shutdown current ISHDN VIN under-voltage lockout threshold rising VIN under-voltage lockout threshold hysteresis Condition Min VFB = 0.85V, no load, no switching, TJ = +25°C VFB = 0.85V, no load, no switching, VEN = 0V INUVRISING 2.4 INUVHYS Feedback reference voltage VREF Switching frequency FSW Minimum on time (4) TON_MIN SYNC input low voltage VSYNC_LOW SYNC input high voltage VSYNC_HIGH Typ Max Units 10 18 µA 25 µA 1 5 µA 2.8 3.2 V 150 TJ = 25°C RFREQ = 180kΩ or from sync clock RFREQ = 82kΩ or from sync clock RFREQ = 27kΩ or from sync clock mV 784 800 816 mV 792 800 808 mV 400 475 550 kHz 850 2250 1000 2500 1150 2750 kHz kHz 80 ns 0.4 1.8 V V Current limit ILIMIT_HS Duty cycle = 40% 2.1 2.5 2.9 A Low-side valley current limit ILIMIT_LS VOUT = 3.3V, L = 4.7µH 1.1 1.35 1.6 A ZCD current IZCD Reverse current limit 50 mA ILIMIT_REVERSE 1.5 Switch leakage current ISW_LKG 0.01 1 µA HS switch on resistance RON_HS 90 155 mΩ LS switch on resistance RON_LS 80 145 mΩ 5 10 15 µA 0.9 1.05 1.2 V Soft-start current ISS EN rising threshold VSS = 0.8V VEN_RISING EN threshold hysteresis VEN_HYS PG rising threshold (VFB/VREF) PGRISING PG falling threshold (VFB/VREF) PGFALLING PG deglitch timer TPG_DEGLITCH PG output voltage low VPG_LOW VCC regulator 120 mV VFB rising 85 90 95 VFB falling 105 110 115 VFB falling 79 84 89 % VFB rising 113.5 118.5 123.5 % PG from low to high 30 PG from high to low 50 ISINK = 2mA 0.2 VCC VCC load regulation Thermal shutdown VBST - VSW = 5V A µs µs 0.4 5 ICC = 5mA (4) Thermal shutdown hysteresis (4) % V V 3 % TSD 170 °C TSD_HYS 20 °C NOTE: 4) Not tested in production, guaranteed by design and characterization. MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 4 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS VIN=12V, TA=-40°C to +125°C, unless otherwise noted MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 5 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, TA=-40°C to +125°C, unless otherwise noted MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 6 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, TA=-40°C to +125°C, unless otherwise noted MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 7 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN= 12V, VOUT= 3.3V, L= 10µH, FSW= 500kHz, AAM, TA=+25°C, unless otherwise noted MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 8 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN= 12V, VOUT= 3.3V, L= 10µH, FSW= 500kHz, AAM, TA=+25°C, unless otherwise noted MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 9 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN= 12V, VOUT= 3.3V, L= 10µH, FSW= 500kHz, AAM, TA=+25°C, unless otherwise noted MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 10 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN= 12V, VOUT= 3.3V, L= 10µH, FSW= 500kHz, AAM, TA=+25°C, unless otherwise noted MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 11 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN= 12V, VOUT= 3.3V, L= 10µH, FSW= 500kHz, AAM, TA=+25°C, unless otherwise noted MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 12 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 PIN FUNCTIONS Pin # Name 1 PHASE 2 VIN 3, 10 SW 4, 9 PGND 5 EN 6 SYNC 7 PG 8 BIAS 11 BST 12 VCC 13 AGND Switch node. SW is the output of the internal power switch. 14 SS 15 FB 16 FREQ MPQ4431 Rev. 1.0 3/21/2017 Description Selectable in-phase or 180° out-of-phase of SYNC input. Drive PHASE high to be in-phase. Drive PHASE low to be 180° out-of-phase. Input supply. VIN supplies power to all of the internal control circuitries and the power switch connected to SW. A decoupling capacitor to ground must be placed close to VIN to minimize switching spikes. Power ground. PGND is the reference ground of the power device and requires careful consideration during PCB layout. For best results, connect PGND with copper pours and vias. Enable. Pull EN below the specified threshold to shut the chip down. Pull EN above the specified threshold to enable the chip. Synchronize. Apply a 350kHz to 2.5MHz clock signal to SYNC to synchronize the internal oscillator frequency to the external clock. The external clock should be at least 250kHz larger than the RFREQ set frequency. SYNC can also be used to select forced continuous conduction mode (CCM) or advanced asynchronous mode (AAM). Drive SYNC high before the chip starts up to choose forced CCM. Drive SYNC low or leave SYNC floating to choose AAM. Power good indicator. The output of PG is an open drain and goes high if the output voltage is within ±10% of the nominal voltage. External power supply for the internal regulator. Connect BIAS to an external power supply (5V ≤ VBIAS ≤ 18V) to reduce power dissipation and increase efficiency. Float BIAS or connect BIAS to ground if not used. Bootstrap. BST is the positive power supply for the high-side MOSFET driver connected to SW. Connect a bypass capacitor between BST and SW. Internal bias supply. VCC supplies power to the internal control circuit and gate drivers. A ≥1µF decoupling capacitor to ground is required close to VCC. Analog ground. AGND is the reference ground of the logic circuit. Soft-start input. Place an external capacitor from SS to AGND to set the soft-start period. The MPQ4431 sources 10µA from SS to the soft-start capacitor during startup. As the SS voltage rises, the feedback threshold voltage increases to limit inrush current during start-up. Feedback input. Connect FB to the tap of an external resistor divider from the output to AGND to set the output voltage. The feedback threshold voltage is 0.8V. Place the resistor divider as close to FB as possible. Avoid placing vias on the FB traces. Switching frequency program. Connect a resistor from FREQ to ground to set the switching frequency. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 13 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 BLOCK DIAGRAM BIAS VCC VCC VCC Regulator VIN VCC EN Vref Reference FREQ BST Oscillator PLL SYNC ISW PHASE PG Logic + - VFB 110%xVREF + - 90%xVREF VFB Error Amplifier VREF SS FB VFB + + - Control Logic, OCP, OTP, BST Refresh SW VCC VC R1 460kΩ C1 52pF C2 0.2pF Ireverse PGND AGND Figure 1: Functional Block Diagram MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 14 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TIMING SEQUENCE VIN 0 SW 0 EN EN Threshold 0 VCC VCC Threshol d 0 118.5% Vref 90% Vref 50% REF 84% Vref Vo 110% Vref SS 0 I L=I Li mit IL 0 PG 30µs 50µs 30µs 50µs 30µs 0 Start-Up N o r m al N o r m al OCP OV N o r m al EN Shutdown OC Release Figure 2: Time Sequence MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 15 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 OPERATION The MPQ4431 is a high-frequency, synchronous, rectified, step-down, switch-mode converter with integrated, internal, high-side and low-side power MOSFETs. The MPQ4431 offers a very compact solution that achieves 1A of continuous output current with excellent load and line regulation over a wide 3.3V to 36V input supply range. The MPQ4431 features a switching frequency programmable from 350kHz to 2.5MHz, external soft start, power good indication, and precision current limit. Its very low operational quiescent current makes it suitable for batterypowered applications. Pulse-Width Modulation (PWM) Control At moderate to high output current, the MPQ4431 operates in a fixed-frequency, peakcurrent-control mode to regulate the output voltage. An internal clock initiates a pulse-width modulation (PWM) cycle. At the rising edge of the clock, the high-side power MOSFET (HSFET) is turned on, and the inductor current rises linearly to provide energy to the load. The HSFET remains on until its current reaches the value set by the COMP voltage (VCOMP), which is the output of the internal error amplifier. If the current in the HS-FET does not reach VCOMP in one PWM period, the HS-FET remains on, saving a turn-off operation. When the HS-FET is off, it remains off until the next clock cycle begins. The low-side MOSFET (LS-FET) is turned on immediately while the inductor current flows through it. To prevent shoot-through, a dead time is inserted to prevent the HS-FET and LS-FET from being on at the same time. For each turnon and -off in a switching cycle, the HS-FET turns on or off with a minimum on and off time limit. Forced CCM and AAM The MPQ4431 has selectable forced continuous conduction mode (CCM) and advanced asynchronous mode (AAM) (see Figure 3). Driving SYNC higher than its specified threshold before the chip starts up forces the device into CCM with a fixed frequency, regardless of the output load current. MPQ4431 Rev. 1.0 3/21/2017 Connect SYNC to VCC if there is no additional power supply available to pull SYNC high before the chip starts up. Once the device is in CCM, the pull-up at SYNC can be removed, and SYNC can be used to synchronize switching. The advantage of CCM is the controllable frequency and smaller output ripple, but it also has low efficiency at light load. Driving SYNC below its specified threshold or leaving SYNC floating before the chip starts up enables AAM power-save mode. The MPQ4431 first enters non-synchronous operation for as long as the inductor current approaches zero at light load. If the load is further decreased or is at no load, then VCOMP is below the internally set AAM value (VAAM). The MPQ4431 then enters sleep mode, which consumes very low quiescent current to further improve light-load efficiency. In sleep mode, the internal clock is blocked first, so the MPQ4431 skips some pulses. Since the FB voltage (VFB) is lower than the internal 0.8V reference (VREF) at this time, VCOMP ramps up until it crosses over VAAM. Then the internal clock is reset and the crossover time is taken as the benchmark of the next clock. This control scheme helps achieve high efficiency by scaling down the frequency to reduce the switching and gate driver losses during light-load or no-load conditions. When the output current increases from lightload condition, VCOMP becomes larger, and the switching frequency increases. If the DC value of VCOMP exceeds VAAM, the operation mode resumes discontinuous conduction mode (DCM) or CCM, which have a constant switching frequency. Inductor Current Inductor Current Forced CCM AAM t t Load Decreased Load t Decreased t t t Figure 3: Forced CCM and AAM www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 16 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 Error Amplifier (EA) The error amplifier (EA) compares VFB with VREF and outputs a current proportional to the difference between the two. This output current then charges or discharges the internal compensation network to form VCOMP, which controls the power MOSFET current. The optimized internal compensation network minimizes the external component count and simplifies the control loop design. Internal Regulator and BIAS Most of the internal circuitry is powered on by the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN exceeds 5V, the output of the regulator is in full regulation. When VIN falls below 5V, the output decreases following VIN. A decoupling ceramic capacitor ≥1µF is needed close to VCC. For better thermal performance, connect BIAS to an external power supply between 5V and 18V. The BIAS supply overrides VIN to power the internal regulator. Using the BIAS supply allows VCC to be derived from a high-efficiency external source, such as VOUT. Float BIAS or connect BIAS to ground if it is not being used. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The UVLO comparator monitors the output voltage of the internal regulator (VCC). The UVLO rising threshold is about 2.8V with a 150mV hysteresis. Enable (EN) Control EN is a digital control pin that turns the regulator on and off. When EN is pulled below its threshold voltage, the chip is put into the lowest shutdown current mode. Pulling EN above its threshold voltage turns on the part. Do not float EN. Power Good (PG) Indicator The MPQ4431 has a power good (PG) indicator. PG is the open drain of a MOSFET and should be connected to VCC or another voltage source through a resistor (e.g.: 100kΩ). In the presence of an input voltage, the MOSFET turns on so that PG is pulled low before SS is ready. When the regulator output MPQ4431 Rev. 1.0 3/21/2017 PRELIMINARY SPEC is within ±10% of its nominal output, the PG output is pulled high after a delay, typically 30μs. When the output voltage moves outside of this range with a hysteresis, the PG output is pulled low with a 50μs delay to indicate a failure output status. Programmable Frequency The oscillating frequency of the MPQ4431 can be programmed either by an external frequency resistor (RFREQ) or by a logic level synchronous clock. The frequency resistor should be located between FREQ and ground as close as to the device as possible. The value of RFREQ can be estimated with Equation (1): RFREQ (kΩ) 170000 fSW1.11(kHz) (1) The calculated resistance may need fine-tuning during the bench test. FREQ is not allowed to be floated, even if an external SYNC clock is added. SYNC and PHASE The internal oscillator frequency can be synchronized to an external clock ranging from 350kHz up to 2.5MHz through SYNC. The external clock should be at least 250kHz larger than the RFREQ set frequency. Ensure that the high amplitude of the SYNC clock is higher than 1.8V, and the low amplitude is lower than 0.4V. There is no pulse width requirement, but there is always parasitic capacitance of the pad, so if the pulse width is too short, a clear rising and falling edge may not be seen due to the parasitic capacitance. A pulse longer than 100ns is recommended in application. PHASE is used when two or more MPQ4431 devices are in parallel with the same SYNC clock. Pulling PHASE high forces the device to operate in-phase of the SYNC clock. Pulling PHASE low forces the device to be 180° out-ofphase of the SYNC clock. By setting different voltages for PHASE, two devices can operate 180° out-of-phase to reduce the total input current ripple so a smaller input bypass capacitor can be used (see Figure 4). The PHASE rising threshold is about 2.5V with a 400mV hysteresis. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 17 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 SW1: Phase high SW2: Phase low SW1, 2 has a 180o phase shift SYNC CLK SW1 SW2 t Figure 4: In-Phase and 180° Out-of-Phase Soft Start (SS) Soft start (SS) is implemented to prevent the converter output voltage from overshooting during start-up. When the chip starts up, an internal current source begins charging the external soft-start capacitor. When the soft-start voltage (VSS) is lower than the internal reference (VREF), VSS overrides VREF, so the error amplifier uses VSS as the reference. When VSS is higher than VREF, the error amplifier uses VREF as the reference. The soft-start time (tSS) set by the external SS capacitor can be calculated with Equation (2): t SS (ms) CSS (nF) VREF (V) ISS (A) (2) Where CSS is the external SS capacitor, VREF is 0.8V, and ISS is the internal 10μA SS charge current. SS can be used for tracking and sequencing. Pre-Bias Start-Up At start-up, if VFB is higher than VSS, which means the output has a pre-bias voltage, neither the HS-FET nor the LS-FET are turned on until VSS is higher than VFB. Over-Current Protection (OCP) and Hiccup The MPQ4431 has cycle-by-cycle peak currentlimit protection with valley-current detection and hiccup mode. The power MOSFET current is accurately sensed via a current sense MOSFET. It is then fed to the high-speed current comparator for current-mode control purposes. During the HSFET on state, if the sensed current exceeds the peak current limit value set by the COMP highclamp voltage, the HS-FET turns off MPQ4431 Rev. 1.0 3/21/2017 PRELIMINARY SPEC immediately. Then the LS-FET turns on to discharge the energy, and the inductor current decreases. The HS-FET remains off unless the inductor valley current is lower than a certain current threshold (valley current limit), even though the internal clock pulses high. If the inductor current does not drop below the valley current limit when the internal clock pulses high, the HS-FET misses the clock, and the switching frequency decreases to half the nominal value. Both the peak and valley current limits assist in keeping the inductor current from running away during an overload or short-circuit condition. When the output is shorted to ground, causing the output voltage to drop below 55% of its nominal output, the peak current limit is kicked, and the device considers this to be an output dead short and triggers hiccup mode immediately to restart the part periodically. In hiccup mode, the MPQ4431 disables its output power stage and discharges the softstart capacitor slowly. The MPQ4431 restarts with a full soft start when the soft-start capacitor is fully discharged. If the short-circuit condition still remains after the soft start ends, the device repeats this operation until the fault is removed and output returns to the regulation level. This protection mode reduces the average short circuit current greatly to alleviate thermal issues and protect the regulator. Floating Driver and Bootstrap Charging A 0.1μF to 1μF external, ceramic, bootstrap capacitor powers the floating power MOSFET driver. The floating driver has its own UVLO protection with a rising threshold of 2.5V and hysteresis of 200mV. The bootstrap capacitor voltage is charged to ~5V from VCC through a PMOS pass transistor when the LS-FET is on. At a high duty cycle operation or sleep mode condition, the time period available to the bootstrap charging is less, so the bootstrap capacitor may not be charged sufficiently. In case the external circuit does not have sufficient voltage or time to charge the bootstrap capacitor, extra external circuitry can be used to ensure that the bootstrap voltage is in the normal operation region. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 18 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 PRELIMINARY SPEC BST Refresh To improve dropout, the MPQ4431 is designed to operate at close to 100% duty cycle for as long as the BST to SW voltage is greater than 2.5V. When the voltage from BST to SW drops below 2.5V, the HS-FET is turned off using a UVLO circuit, which forces the LS-FET on to refresh the charge on the BST capacitor. Since the supply current sourced from the BST capacitor is low, the HS-FET can remain on for more switching cycles than are required to refresh the capacitor, making the effective duty cycle of the switching regulator high. The effective duty cycle during the dropout of the regulator is mainly influenced by the voltage drops across the HS-FET, LS-FET, inductor resistance, and printed circuit board resistance. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from running away thermally. When the silicon die temperature exceeds its upper threshold, the power MOSFETs shut down. When the temperature drops below its lower threshold, the chip is enabled again. MPQ4431 Rev. 1.0 3/21/2017 Start-Up and Shutdown If both VIN and EN exceed their appropriate thresholds, the chip starts up. The reference block starts first, generating a stable reference voltage and current, and then the internal regulator is enabled. The regulator provides a stable supply for the rest of the circuitries. While the internal supply rail is up, an internal timer holds the power MOSFET off for about 50µs to blank start-up glitches. When the softstart block is enabled, it first holds its SS output low to ensure that the rest of the circuitries are ready and slowly ramps up. Three events can shut down the chip: VIN low, EN low, and thermal shutdown. During the shutdown procedure, the signaling path is blocked first to avoid any fault triggering. VCOMP and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command, but its charging path is disabled. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 19 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 APPLICATION INFORMATION Setting the Output Voltage The external resistor divider connected to FB sets the output voltage (see Figure 5). Since CIN absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (4): ICIN ILOAD MPQ4431 RFB1 FB ICIN Figure 5: Feedback Network Choose RFB1 to be around 40kΩ. Then calculate RFB2 with Equation (3): R FB1 VOUT 1 0.8V (3) Table 1 lists the recommended feedback resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages VOUT (V) RFB1 (kΩ) RFB2 (kΩ) 3.3 41.2 (1%) 13 (1%) 5 68.1 (1%) 13 (1%) Selecting the Input Capacitor The input current to the step-down converter is discontinuous and therefore requires a capacitor to supply AC current to the converter while maintaining the DC input voltage. For the best performance, use low ESR capacitors. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, use a 4.7µF to 10µF capacitor. It is strongly recommended to use another lower value capacitor (e.g.: 0.1µF) with a small package size (0603) to absorb highfrequency switching noise. Place the smaller capacitor as close to VIN and GND as possible. MPQ4431 Rev. 1.0 3/21/2017 (4) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (5): Vout RFB2 R FB2 VOUT V (1 OUT ) VIN VIN ILOAD 2 (5) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high-quality ceramic capacitor (e.g.: 0.1μF) as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent excessive voltage ripple at the input. The input voltage ripple caused by the capacitance can be estimated with Equation (6): VIN ILOAD V V OUT (1 OUT ) fSW CIN VIN VIN (6) Selecting the Output Capacitor The output capacitor maintains the DC output voltage. Use ceramic, tantalum, or low ESR electrolytic capacitors. For best results, use low ESR capacitors to keep the output voltage ripple low. The output voltage ripple can be estimated with Equation (7): VOUT VOUT V 1 (1 OUT ) (RESR ) (7) fSW L VIN 8fSW COUT Where L is the inductor value, and RESR is the equivalent series resistance (ESR) value of the output capacitor. For ceramic capacitors, the capacitance dominates the impedance at the switching frequency and causes the majority of the output voltage ripple. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 20 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 For simplification, the output voltage ripple can be estimated with Equation (8): VOUT VOUT V (1 OUT ) (8) 8 fSW L COUT VIN 2 PRELIMINARY SPEC higher UVLO point, an external resistor divider between VIN and EN can be used to achieve a higher equivalent UVLO threshold (see Figure 6). VIN For tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (9): VOUT VOUT V (1 OUT ) RESR fSW L VIN (10) Choose the inductor ripple current to be approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (11): ILP (11) VIN UVLO Setting The MPQ4431 has an internal, fixed, undervoltage lockout (UVLO) threshold. The rising threshold is 2.8V, while the falling threshold is about 2.65V. For applications that need a MPQ4431 Rev. 1.0 3/21/2017 RDOWN The UVLO threshold can be calculated with Equation (12) and Equation (13): INUVRISING (1 RUP ) VEN_RISING RDOWN (12) INUVFALLING (1 RUP ) VEN_FALLING RDOWN (13) Where VEN_RISING is 1.05V, and VEN_FALLING is 0.93V. External BST Diode and Resistor An external BST diode can enhance the efficiency of the regulator when the duty cycle is high. A power supply between 2.5V and 5V can be used to power the external bootstrap diode. VCC or VOUT is recommended to be this power supply in the circuit (see Figure 7). VCC RBST Where ∆IL is the peak-to-peak inductor ripple current. VOUT V ILOAD (1 OUT ) 2fSW L VIN EN Figure 6: Adjustable UVLO Using EN Divider Selecting the Inductor A 1µH to 10µH inductor with a DC current rating at least 25% higher than the maximum load current is recommended for most applications. For higher efficiency, choose an inductor with a lower DC resistance. A larger-value inductor results in less ripple current and a lower output ripple voltage, but also has a larger physical size, higher series resistance, and lower saturation current. A good rule for determining the inductor value is to allow the inductor ripple current to be approximately 30% of the maximum load current. The inductance value can then be calculated with Equation (10): VOUT V (1 OUT ) fSW IL VIN R UP (9) The characteristics of the output capacitor also affect the stability of the regulation system. The MPQ4431 can be optimized for a wide range of capacitance and ESR values. L VIN External BST diode IN4148 BST VCC / VOUT CBST L VOUT SW COUT Figure 7: External Bootstrap Diode and Resistor The recommended external BST diode is IN4148, and the recommended BST capacitor value is 0.1µF to 1μF. A resistor in series with the BST capacitor (RBST) can reduce the SW rising rate and voltage spikes. This helps enhance EMI performance and reduce voltage stress at a high VIN. A higher resistance is better for SW spike reduction but compromises efficiency. To make a tradeoff between EMI and efficiency, a ≤20Ω RBST is recommended. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 21 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 PCB Layout Guidelines (6) Efficient PCB layout, especially for the input capacitor placement, is critical for stable operation. A four-layer layout is strongly recommended to achieve better thermal performance. For best results, refer to Figure 8 and follow the guidelines below. 1. Use a large ground plane to connect to PGND directly. 2. Add vias near PGND if the bottom layer is a ground plane. 3. Ensure that the high-current paths at GND and VIN have short, direct, and wide traces. 4. Place the ceramic input capacitor, especially the small package size (0603) input bypass capacitor, as close to VIN and PGND as possible to minimize high-frequency noise. 5. Keep the connection of the input capacitor and VIN as short and wide as possible. 6. Place the VCC capacitor as close to VCC and GND as possible. 7. Route SW and BST away from sensitive analog areas, such as FB. 8. Place the feedback resistors close to the chip to ensure that the trace which connects to FB is as short as possible. 9. Use multiple vias to connect the power planes to the internal layers. NOTE: 6) The recommended PCB layout is based on Figure 9 through Figure 16. Top Layer Inner Layer 1 Inner Layer 2 Bottom Layer Figure 8: Recommended PCB Layout MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 22 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL APPLICATION CIRCUITS U1 3.3V-36V VIN 2 C1A 10μF R1 100kΩ GND C1B 10μF C1C C1D 0.1μF 0.1μF 5 EN VIN BST 11 C5 0.1μF L1 MPQ4431 EN SW 3, 10 3.3V/1A 10μH R3 1MΩ 12 R5 100kΩ VCC FB C4 1μF GND 15 PG SS 14 C3 4.7nF 6 SYNC VOUT R4 316kΩ 7 PG C6 5pF C2A C2B 22μF 22μF SYNC FREQ R6 NS 16 R2 169kΩ BIAS PGND AGND 13 PHASE 4, 9 1 PHASE 8 C7 NS Figure 9: VOUT = 3.3V, IOUT = 1A, FSW = 500kHz U1 VIN 3.3V-36V GND 2 C1A 10μF R1 100kΩ C1B 10μF C1C C1D 0.1μF 0.1μF 5 EN VIN BST 11 C5 0.1μF L1 MPQ4431 EN SW 3, 10 R3 41.2kΩ 12 R5 100kΩ PG VCC FB C4 1μF C6 10pF C2A C2B 22μF 22μF VOUT GND 15 R4 13kΩ 7 PG SS 14 C3 4.7nF SYNC 3.3V/1A 10μH 6 SYNC FREQ R6 NS 16 R2 169kΩ PHASE BIAS PGND AGND 13 1 4, 9 PHASE 8 C7 NS Figure 10: VOUT = 3.3V, FSW = 500kHz for <100kΩ FB Divider Application MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. 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All Rights Reserved. 23 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL APPLICATION CIRCUITS (continued) U1 VIN 3.3V-36V 2 C1B 10μF C1A 10μF R1 100kΩ GND C1C C1D 0.1μF 0.1μF 5 EN VIN 11 BST C5 0.1μF L1 MPQ4431 EN 3, 10 SW 5V/1A 10μH R3 1MΩ 12 VCC PG 14 SS C3 4.7nF 6 SYNC GND R4 191kΩ 7 PG VOUT 15 FB C4 1μF R5 100kΩ C6 5pF C2A C2B 22μF 22μF SYNC R6 10Ω 16 FREQ R2 169kΩ 8 BIAS PGND AGND 13 PHASE 4, 9 1 PHASE C7 0.1µF Figure 11: VOUT = 5V, FSW = 500kHz U1 VIN 3.3V-36V GND 2 C1A 10μF R1 100kΩ C1B 10μF C1C C1D 0.1μF 0.1μF 5 EN VIN BST 11 C5 0.1μF L1 MPQ4431 EN SW 3, 10 R3 68.1kΩ 12 R5 100kΩ PG VCC FB C4 1μF C6 10pF C2A C2B 22μF 22μF VOUT GND 15 R4 13kΩ 7 PG SS 14 C3 4.7nF SYNC 5V/1A 10μH 6 SYNC FREQ R6 10Ω 16 R2 169kΩ PHASE BIAS PGND AGND 13 1 4, 9 PHASE 8 C7 0.1µF Figure 12: VOUT = 5V, FSW = 500kHz for <100kΩ FB Divider Application MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. 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All Rights Reserved. 24 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL APPLICATION CIRCUITS (continued) U1 VIN 3.3V-36V 2 C1A 10μF R1 100kΩ GND C1B 10μF VIN C1C C1D 0.1μF 0.1μF C5 0.1μF L1 MPQ4431 5 EN 11 BST EN 3, 10 SW 3.3V/1A 2.2μH R3 1MΩ 12 R5 100kΩ VCC FB C4 1μF GND 15 PG 14 SS C3 4.7nF 6 SYNC C6 10pF VOUT R4 316kΩ 7 PG C2A C2B 22μF 22μF SYNC FREQ R6 NS 16 R2 33kΩ 1 8 BIAS PGND AGND 13 PHASE 4, 9 PHASE C7 NS Figure 13: VOUT = 3.3V, FSW = 2.2MHz U1 VIN 3.3V-36V GND 2 C1A 10μF R1 100kΩ C1B 10μF C1C C1D 0.1μF 0.1μF 5 EN VIN BST 11 C5 0.1μF L1 MPQ4431 EN SW 3, 10 R3 41.2kΩ 12 R5 100kΩ PG VCC FB C4 1μF C6 10pF C2A C2B 22μF 22μF VOUT GND 15 R4 13kΩ 7 PG SS 14 C3 4.7nF SYNC 3.3V/1A 2.2μH 6 SYNC FREQ R6 NS 16 R2 33kΩ PHASE BIAS PGND AGND 13 1 4, 9 PHASE 8 C7 NS Figure 14: VOUT = 3.3V, FSW = 2.2MHz for <100kΩ FB Divider Application MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. 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All Rights Reserved. 25 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 TYPICAL APPLICATION CIRCUITS (continued) U1 VIN 3.3V-36V 2 C1A 10μF R1 100kΩ GND C1B 10μF VIN C1C C1D 0.1μF 0.1μF C5 0.1μF L1 MPQ4431 5 EN 11 BST EN 3, 10 SW 5V/1A 2.2μH R3 1MΩ 12 R5 100kΩ VCC FB C4 1μF GND 15 PG 14 SS C3 4.7nF 6 SYNC C6 10pF VOUT R4 191kΩ 7 PG C2A C2B 22μF 22μF SYNC FREQ R6 10Ω 16 R2 33kΩ 1 8 BIAS PGND AGND 13 PHASE 4, 9 PHASE C7 0.1µF Figure 15: VOUT = 5V, FSW = 2.2MHz U1 VIN 3.3V-36V GND 2 C1A 10μF R1 100kΩ C1B 10μF C1C C1D 0.1μF 0.1μF 5 EN VIN BST 11 C5 0.1μF L1 MPQ4431 EN SW 3, 10 R3 68.1kΩ 12 R5 100kΩ PG VCC FB C4 1μF C6 10pF C2A C2B 22μF 22μF VOUT GND 15 R4 13kΩ 7 PG SS 14 C3 4.7nF SYNC 5V/1A 2.2μH 6 SYNC FREQ R6 10Ω 16 R2 33kΩ PHASE BIAS PGND AGND 13 1 4, 9 PHASE 8 C7 0.1µF Figure 16: VOUT = 5V, FSW = 2.2MHz for <100kΩ FB Divider Application MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 26 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 PRELIMINARY SPEC PACKAGE INFORMATION QFN-16 (3mmx4mm) Non-Wettable Flank PIN 1 ID MARKING PIN 1 ID 0.15x45°TYP. PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW SIDE VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 3) JEDEC REFERENCE IS MO-220. 4) DRAWING IS NOT TO SCALE. 0.15x45° RECOMMENDED LAND PATTERN MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 27 MPQ4431 – 36V, 1A, LOW IQ, SYNC, STEP-DOWN CONVERTER, AEC-Q100 PACKAGE INFORMATION (continued) QFN-16 (3mmx4mm) Wettable Flank PIN 1 ID MARKING PIN 1 ID 0.15x45°TYP. PIN 1 ID INDEX AREA TOP VIEW BOTTOM VIEW SIDE VIEW SECTION A-A NOTE: 1) THE LEAD SIDE IS WETTABLE. 2) ALL DIMENSIONS ARE IN MILLIMETERS. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. 0.15x45° RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ4431 Rev. 1.0 3/21/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 28