TI1 LMH6514SQNOPB Lmh6514 600 mhz, digital controlled, variable gain amplifier Datasheet

LMH6514
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LMH6514 600 MHz, Digital Controlled, Variable Gain Amplifier
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FEATURES
DESCRIPTION
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The LMH6514 is a high performance, digitally
controlled variable gain amplifier (DVGA). It combines
precision gain control with a low noise, ultra-linear,
differential amplifier. Typically, the LMH6514 drives a
high performance ADC in a broad range of mixed
signal and digital communication applications such as
mobile radio and cellular base stations where
automatic gain control (AGC) is required to increase
system dynamic range. When used in conjunction
with a high speed ADC, system dynamic range can
be extended by up to 42 dB.
1
2
Adjustable Gain with a 42 dB Range
Precise 6.02 dB Gain Steps
Parallel 3 Bit Gain Control
On Chip Register Gain Setting
Fully Differential Signal Path
Single Ended to Differential Capable
200Ω Input Impedance
Small Footprint (4 mm x 4 mm) WQFN Package
APPLICATIONS
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Cellular Base Stations
IF Sampling Receivers
Instrumentation
Modems
Imaging
Differential Line Receiver
KEY SPECIFICATIONS
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600 MHz bandwidth at 100Ω load
39 dBm OIP3 at 75 MHz, 200Ω load
26 dB to 38 dB maximum gain
Selectable output impedance of 200Ω or 400Ω.
8.3 dB noise figure
5 ns gain step switching time
100 mA supply current
The LMH6514 has a differential input and output
allowing large signal swings on a single 5V supply. It
is designed to accept signals from RF elements and
maintain a terminated impedance environment. The
input impedance is 200Ω resistive. The output
impedance is either 200Ω or 400Ω and is user
selectable. A unique internal architecture allows use
with both single ended and differential input signals.
Input signals to the LMH6514 are scaled by a highly
linear, digitally controlled attenuator with seven
accurate 6 dB steps. The attenuator output provides
the input signal for a high gain, ultra linear differential
transconductor. The transconductor differential output
current can be converted into a voltage by using the
on-chip 200Ω or 400Ω loads. The transconductance
gain is 0.1 Amp/Volt resulting in a maximum voltage
gain of +32 dB when driving a 200Ω load, or 38 dB
when driving the 400Ω load. On chip digital latches
are provided for local storage of the gain setting. The
gain step settling time is 5 ns and care has been
taken to reduce the sensitivity of bandwidth and
phase to gain setting.
The LMH6514 operates over the industrial
temperature range of −40°C to +85°C. The LMH6514
is available in a 16-Pin, thermally enhanced, WQFN
package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Typical Application
VCC
LO
RLOAD
RF
ROUT
200
LMH6514
ADC14155
3
GAIN
LATCH
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
ESD Tolerance
(3)
Human Body Model
2 kV
Machine Model
150V
Positive Supply Voltage (Pin 3)
−0.6V to 5.5V
Output Voltage (Pin 14,15)
−0.6V to 6.8V
Differential Voltage between Any Two Grounds
<200 mV
Analog Input Voltage Range
−0.6V to VCC
Digital Input Voltage Range
−0.6V to 3.6V
Output Short Circuit Duration
(one pin to ground)
Infinite
Junction Temperature
+150°C
−65°C to +150°C
Storage Temperature Range
Soldering Information
Infrared or Convection (20 sec)
235°C
Wave Soldering (10 sec)
260°C
(1)
(2)
(3)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Operating Ratings (1)
Supply Voltage (Pin 3)
4V to 5.25V
Output Voltage Range (Pin 14, 15)
1.4V to 6.4V
Differential Voltage Between Any Two Grounds
<10 mV
Analog Input Voltage Range,
AC Coupled
Temperature Range
±1.4V
(2)
−40°C to +85°C
Package Thermal Resistance (θJA)
16-Pin WQFN
(1)
(2)
47°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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5V Electrical Characteristics (1) (2)
The following specifications apply for single supply with VCC = 5V, Maximum Gain , RL = 100Ω (200Ω external || 200Ω
internal), VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes.
Symbol
Parameter
Conditions
Min
(3)
Typ
(4)
Max
(3)
Units
Dynamic Performance
−3 dB Bandwidth
SSBW
Average of all Gain Settings
600
f = 75 MHz, V OUT = 2 VPP
−70
f = 150 MHz, V OUT = 2 VPP
−66
f = 250 MHz, V OUT = 2 VPP
−60
f = 450 MHz, V OUT = 2 VPP
−52
f = 75 MHz, V OUT = 2 VPP,
Tone Spacing = 0.5 MHz
35
f = 150 MHz, V OUT = 2 VPP,
Tone Spacing = 2 MHz
33
f = 250 MHz, V OUT = 2 VPP,
Tone Spacing = 2 MHz
31
f = 75 MHz, RL= 200Ω, V OUT = 2 VPP
Tone Spacing = 0.5 MHz
39
f = 150 MHz, RL = 200Ω, V OUT = 2 VPP,
Tone Spacing = 2 MHz
37
f = 250 MHz, RL = 200Ω, V OUT = 2 VPP,
Tone Spacing = 2 MHz
34
MHz
Noise and Distortion
Third Order Intermodulation
Products
OIP3
Output Third Order Intercept Point
P1 dB
Output Level for 1 dB Gain
Compression
f = 75 MHz, R L = 200Ω
16.7
f = 250 MHz, R L = 200Ω
14.7
f = 75 MHz
14.5
dBc
dBm
dBm
f = 450 MHz
13.2
VNI
Input Noise Voltage
Maximum Gain, f = 40 MHz
1.8
nV/√Hz
VNO
Output Noise Voltage
Maximum Gain, f = 40 MHz
36
nV/√Hz
NF
Noise Figure
Maximum Gain
8.3
dB
Analog I/O
Differential Input Resistance
165
158
188
220
230
Ω
Input Common Mode Resistance
825
785
955
1120
1160
Ω
Differential Output Resistance
(1)
(2)
(3)
(4)
4
Low Gain Option
186
High Gain Option
330
325
370
420
425
Internal Load Resistors
Between Pins 13, 14 and Pins 15, 16
165
158
187
215
225
Input Signal Level (AC Coupled)
Max Gain, VO = 2 VPP, RL = 1 kΩ
63
Maximum Differential Input Signal
AC Coupled
5.6
Input Common Mode Voltage
Self Biased
Input Common Mode Voltage
Range
Driven Externally
Minimum Input Voltage
DC
1.3
1.1
1.4
Ω
Ω
mVPP
VPP
1.5
1.7
V
0.9 to 2.0
V
0
V
Electrical Table values apply only for factory testing conditions at the temperature indicated. No specification of parametric performance
is indicated in the electrical tables under conditions different than those tested
Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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5V Electrical Characteristics(1)(2) (continued)
The following specifications apply for single supply with VCC = 5V, Maximum Gain , RL = 100Ω (200Ω external || 200Ω
internal), VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes.
Symbol
Parameter
Conditions
Min
(3)
Typ
(4)
Max
(3)
Units
Maximum Input Voltage
DC
3.3
V
Maximum Differential Output
Voltage Swing
VCC = 5V, Output Common Mode = 5V
5.5
VPP
VOS
Output Offset Voltage
All Gain Settings
−21
mV
CMRR
Common Mode Rejection Ratio
Maximum Gain
81
dB
PSRR
Power Supply Rejection Ratio
Maximum Gain
63
61
81
dB
Gain Parameters
Maximum Gain
DC, Internal RL = 186Ω,
External RL = 1280Ω
29.3
28.7
30
30.3
30.9
dB
Minimum Gain
DC, Internal RL = 186Ω,
External RL = 1280Ω
−12.75
−13.15
−12
−11.85
−11.45
dB
Gain Step Size
DC
6.02
Gain Step Error
DC
0.02
f = 150 MHz
0.07
Cumulative Gain Step Error
DC, Gain Step 7 to Gain Step 0
−0.35
−0.50
Gain Step Switching Time
0.02
dB
dB
0.30
0.45
5
dB
ns
Digital Inputs/Timing
Logic Compatibility
CMOS Logic
3.3
V
VIL
Logic Input Low Voltage
0.8
V
VIH
Logic Input High Voltage
IIH
Logic Input High Input Current (5)
40
μA
TSU
Setup Time
3
ns
THOLD
Hold Time
3
ns
TPW
Minimum Latch Pulse Width
10
ns
2.0
Digital Input Voltage = 3.3V
V
33
Power Requirements
ICC
(5)
Total Supply Current
VOUT = 0V Differential, VOUT Common
Mode = 5V
107
124
134
mA
Amplifier Supply Current
Pin 3 Only
56
66
74
mA
Output Stage Bias Currents
Pins 13, 14 and Pins 15, 16;
VOUT Common Mode = 5 V
51
58
60
mA
Negative input current implies current flowing out of the device.
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NC
V+
LATCH
NC
4
3
2
1
Connection Diagram
GND
5
16
LOAD-
IN+
6
15
OUT-
IN-
7
14
OUT+
GND
8
13
LOAD+
9
10
11
12
GAIN_2
GAIN_1
GAIN_0
NC
GND
Figure 1. 16-Pin WQFN (Top View)
Gain Control Pins
Pin Number
Pin Name
Gain Step Size
11
GAIN_0
6.02 dB
10
GAIN_1
12.04 dB
9
GAIN_2
24.08 dB
spacer
6
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PIN DESCRIPTIONS
Pin Number
Symbol
Description
6
IN+
Non-inverting analog input. Internally biased to 1.4V. Input voltage should not exceed VCC or
go below GND by more than 0.5V.
7
IN−
Inverting analog input. Internally biased to 1.4V. Input voltage should not exceed VCC or go
below GND by more than 0.5V. If using amplifier single ended this input should be capacitively
coupled to ground.
15
OUT−
Open collector inverting output. This pin is an output that also requires a power source. This
pin should be connected to 5V through either an RF choke or an appropriately sized inductor
that can form part of a filter. See Application Information for details.
14
OUT+
Open collector non-inverting output. This pin is an output that also requires a power source.
This pin should be connected to 5V through either an RF choke or an appropriately sized
inductor that can form part of a filter. See Application Information for details.
16
LOAD−
Internal 200Ω resistor connection to pin 15. This pin can be left floating for higher gain or
shorted to pin 13 for lower gain and lower effective output impedance. See Application
Information for details.
13
LOAD+
Internal 200Ω resistor connection to pin 14. This pin can be left floating for higher gain or
shorted to pin 16 for lower gain and lower effective output impedance. See Application
Information for details.
3
VCC
5V power supply pin. Use ceramic, low ESR bypass capacitors. This pin powers everything
except the output stage.
5,8
GND
Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is also a ground connection.
11,10,9
GAIN_0 to
GAIN_2
Gain setting pins. See above table for gain step sizes for each pin. These pins are 3.3V CMOS
logic compatible. 5V inputs may cause damage.
2
LATCH
This pin controls the function of the gain setting pins mentioned above. With LATCH in the
logic HIGH state the gain is fixed and will not change. With the LATCH in the logic LOW state
the gain is set by the state of the gain control pins. Any changes in gain made with the LATCH
pin in the LOW state will take effect immediately. This pin is 3.3V CMOS logic compatible. 5V
inputs may cause damage.
1,4,12
NC
These pins are not connected. They can be grounded or left floating.
Analog I/O
Power
Digital Inputs
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Typical Performance Characteristics
VCC = 5V
Frequency Response over Temperature, Maximum Gain
26
25
-40°C
GAIN (dB)
GAIN (dB)
Frequency Response All Gain Settings
26
23
20
17
14
11
8
5
2
-1
-4
-7
-10
-13
-16
-19 RL = 100:
-22
1
10
24
25°C
23
85°C
22
PIN = -16 dBm
RL = 100:
21
100
1000
100
10
FREQUENCY (MHz)
Figure 2.
Figure 3.
Frequency Response over Temperature, Minimum Gain
OIP3 High Gain Mode
40
-16
f = 75 MHz
38
36
-17
-40°C
f = 150 MHz
34
OIP3 (dBm)
GAIN (dB)
1000
FREQUENCY (MHz)
-18
25°C
-19
85°C
f = 250 MHz
32
30
INPUT CLIPPING
28
26
24
-20
PIN = 10 dBm
-21
VOUT = 2 VPP
22
RL = 100:
20
100
10
1000
RL = 200:
0
1
2
3
4
5
6
7
GAIN STEP (0 = MAXIMUM GAIN)
FREQUENCY (MHz)
Figure 4.
Figure 5.
OIP3 Low Gain Mode
OIP3 Over Temperature
40
45
f = 75 MHz
38
f = 150 MHz
36
40
75 MHz
OIP3 (dBm)
OIP3 (dBm)
34
32
30
f = 250 MHz
28
24
30
25
VOUT = 2 VPP
22
8
250 MHz
INPUT CLIPPING
26
20
150 MHz
35
RL = 100:
0
1
2
3
4
5
6
7
RL = 200:
20
-20
0
-40
20
40
GAIN STEP (0 = MAXIMUM GAIN)
TEMPERATURE (°C)
Figure 6.
Figure 7.
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80
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Typical Performance Characteristics (continued)
VCC = 5V
IMD3 Low Gain Mode
IMD3 High Gain Mode
-55
-40
VOUT = 2 VPP
VOUT = 2 VPP
RL = 100:
-45
-65
-50
INPUT CLIPPING
IMD3 (dBc)
IMD3 (dBc)
INPUT CLIPPING
RL = 200:
-60
-55
f = 250 MHz
-60
f = 250 MHz
-70
-75
f = 150 MHz
f = 150 MHz
-80
-65
f = 75 MHz
f = 75 MHz
-70
1
0
2
3
4
5
6
-85
0
7
1
GAIN STEP (0 = MAXIMUM GAIN)
4
5
Figure 9.
HD2
vs.
Frequency
HD3
vs.
Frequency
6
7
-30
RL = 100:
RL = 100:
-40
-40
DISTORTION (dBc)
2.8 VPP
-50
2 VPP
-60
-70
-80
1 VPP
2.8 VPP
-50
-60
2 VPP
-70
1 VPP
-80
-90
-100
-90
0
50
100 150 200 250 300 350 400
0
50
100 150 200 250 300 350 400
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10.
Figure 11.
HD2
vs.
Frequency
HD3
vs.
Frequency
-30
-30
RL = 200:
RL = 200:
-40
-40
-50
DISTORTION (dBc)
DISTORTION (dBc)
3
Figure 8.
-30
DISTORTION (dBc)
2
GAIN STEP (0 = MAXIMUM GAIN)
2.8 VPP
-60
2 VPP
-70
-80
1 VPP
-90
-50
2.8 VPP
-60
2 VPP
-70
-80
-100
1 VPP
-90
-110
0
50
100
150
200
250
300
0
50
100
150
200
250
300
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VCC = 5V
Noise Figure for All Gain Settings
Noise Figure vs. Frequency
55
13
MAXIMUM GAIN
50
12
f = 150 MHz
NOISE FIGURE (dB)
NOISE FIGURE (dB)
45
40
35
30
f = 75 MHz
25
20
11
10
15
9
10
5
0
1
2
3
4
5
6
8
7
0
100
GAIN SETTING (0 = MAXIMUM GAIN)
200
Figure 14.
Differential Output Noise
Maximum Gain vs. Supply Voltage
26
RL = 100:
PIN = -25 dBm
50
RL = 133:
MAXIMUM GAIN (dB)
OUTPUT NOISE (nV/ Hz)
f = 75 MHz
40
30
RL = 100:
20
25.5
f = 75 MHz
25
f = 150 MHz
24.5
f = 250 MHz
10
0
0
1
2
3
4
5
24
3.5
7
6
4
4.5
Figure 16.
Gain vs. External Load
Maximum Gain over Temperature
26
400: INTERNAL WITH 400:
EXTERNAL = 32 dB NET
INTERNAL LOAD
= 400:
30
INTERNAL LOAD =
200:
26
22
18
10
200: INTERNAL WITH 200:
EXTERNAL = 26 dB NET
MAXIMUM GAIN (dB)
25.5
34
5.5
Figure 17.
42
38
5
SUPPLY VOLTAGE (V)
GAIN SETTING (0 = MAXIMUM GAIN)
MAXIMUM GAIN (dB)
400
Figure 15.
60
f = 75 MHz
25
f = 150 MHz
24.5
f = 250 MHz
24
23.5
VOUT = 2 VPP
RL = 100:
100
1k
10k
100k
EXTERNAL DIFFERENTIAL LOAD (:)
Figure 18.
10
300
FREQUENCY (MHz)
23
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
Figure 19.
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Typical Performance Characteristics (continued)
VCC = 5V
Worst Case Gain Step Error
vs
Frequency
Gain Steps over Temperature
6.25
6.45
f = 150 MHz
VOUT = 1 VPP
6.40
RL = 100:
6.35
GAIN STEP SIZE (dB)
STEP SIZE (dB)
f = 250 MHz
6.30
f = 150 MHz
6.25
f = 75 MHz
6.20
6.15
6.10
6.20 VOUT = 2 VPP
RL = 100:
6.15
6.10
85°C
25°C
6.05
6.00
-40°C
6.05
5.95
6.00
IDEAL
5.95
1
2
3
HIGH
GAIN
4
5.90
5
6
1
7
LOW
GAIN
GAIN STEP
2
3
4
5
6
7
GAIN STEP (0 = MAXIMUM GAIN)
Figure 20.
Figure 21.
Worst Case Gain Step Error over Temperature
Input Impedance (S11) at Maximum Gain
0.4
350
RL = 100:
0.35
ERROR (dB)
0.3
0.25
85°C
0.2
0.15
25°C
0.1
INPUT IMPEDANCE (:)
300
250
|Z|
200
150
R
100
50
jX
-40°C
0.05
0
0
0
50
100
150
200
250
-50
50 100 150 200 250 300 350 400 450
300
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 22.
Figure 23.
Input Impedance (S11) at Minimum Gain
Output Impedance (S22) at Maximum Gain Low Gain Mode
350
350
300
300
INPUT IMPEDANCE (:)
INPUT IMPEDANCE (:)
|Z|
250
|Z|
200
150
R
100
50
jX
250
200
150
R
100
0
jX
50
0
-50
50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
-50
50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
VCC = 5V
Output Impedance (S22) at Maximum Gain High Gain Mode
Digital Crosstalk
350
40
300
30
250
|Z|
200
150
100
R
50
jX
0
20
10
0
-10
3
-20
-30
GAIN CONTROL SIGNALS (V)
DIFFERENTIAL OUTPUT (mV)
INPUT IMPEDANCE (:)
LATCH = 0
PINS 9, 10, 11,12
-40
-50
50 100 150 200 250 300 350 400 450
0
10 20 30 40 50 60 70 80 90 100
0
TIME (ns)
FREQUENCY (MHz)
Figure 26.
Figure 27.
Digital Crosstalk
Digital Pin to Output Isolation
40
-30
PIN = -10 dBm
LOAD = 200:
-40 MAX GAIN
10
0
-10
3
-20
-30
CROSSTALK (dBc)
20
GAIN CONTROL SIGNALS (V)
-50
LATCH
-60
-70
-80
GAIN 1
PINS 9, 10, 11,12
-40
0
0
10 20 30 40 50 60 70 80 90 100
-90
1
10
TIME (ns)
100
1000
FREQUENCY (MHz)
Figure 28.
Figure 29.
Minimum Gain to Maximum Gain Switching
Using Latch Pin
Maximum Gain to Minimum Gain Switching
Using Latch Pin
4
RL = 100:
4
RL = 100:
3
LATCH PIN
LATCH PIN
1
0
0.5
0
2
VOUT (V)
1
LATCH (V)
VOUT (V)
2
1.5
1.5
1
1
0
0.5
0
VOUT
-0.5
-1
-1
-1.5
-1.5
0
10
VOUT
-0.5
20
30
40
TIME (ns)
0
10
20
30
40
TIME (ns)
Figure 30.
12
3
LATCH (V)
DIFFERENTIAL OUTPUT (mV)
LATCH = 3.3V
30
Figure 31.
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Typical Performance Characteristics (continued)
VCC = 5V
24 dB Gain Step
4
3
3
GAIN BIT 2
1
1
0
0.5
0
VOUT (V)
1.5
2
GAIN BIT 2 (V)
1
1
0
0.5
0
VOUT
-1
-1
-1.5
-1.5
0
10
VOUT
-0.5
20
30
40
0
10
20
TIME (ns)
30
TIME (ns)
Figure 32.
Figure 33.
12 dB Gain Step
12 dB Gain Step
4
4
3
3
GAIN BIT 1
GAIN BIT 1
1
1
0
0.5
0
VOUT (V)
1.5
2
GAIN BIT 1 (V)
VOUT (V)
2
1.5
1
1
0
0.5
0
-0.5
-0.5
VOUT
VOUT
-1
-1
-1.5
-1.5
0
10
20
30
40
0
10
20
30
TIME (ns)
TIME (ns)
Figure 34.
Figure 35.
6 dB Gain Step
40
6 dB Gain Step
4
4
3
3
GAIN BIT 0
GAIN BIT 0
1
1
0
0.5
0
-0.5
VOUT (V)
1.5
2
GAIN BIT 0 (V)
2
VOUT (V)
40
GAIN BIT 1 (V)
-0.5
1.5
1.5
1
1
0
0.5
0
GAIN BIT 0 (V)
VOUT (V)
2
GAIN BIT 2 (V)
GAIN BIT 2
24 dB Gain Step
4
-0.5
-1
-1
VOUT
-1.5
VOUT
-1.5
0
10
20
30
40
0
10
20
TIME (ns)
TIME (ns)
Figure 36.
Figure 37.
30
40
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Typical Performance Characteristics (continued)
VCC = 5V
V
5
0.3
5
0.2
4
0.2
4
3
0.1
VOUT
0
2
-0.1
1
-0.2
0
20
25
VOUT (V)
0.3
-0.3 f = 250 MHz
ENVELOPE DISPLAYED
-0.4
0
5
10 15
-10 -5
3
0.1
VOUT
0
2
-0.1
1
-0.2
0
-0.3 f = 250 MHz
ENVELOPE DISPLAYED
-0.4
0
5
10 15
-10 -5
30
20
TIME (Ps)
TIME (Ps)
Figure 38.
Figure 39.
Power Off Timing, Maximum Gain
0.3
f = 250 MHz
ENVELOPE DISPLAYED 5
0.3
4
0.2
0.1
3
0
2
-0.1
1
0
-0.2
VOUT (V)
0.4
POWER SUPPLY (V)
6
VOUT
-0.4
-10
14
-5
0
5
10
15
4
VOUT
0.1
25
30
3
0
2
-0.1
1
0
-0.2
+
-0.3
20
30
6
f = 250 MHz
ENVELOPE DISPLAYED 5
+
V
-0.3
25
Power Off Timing, Minimum Gain
0.4
0.2
VOUT (V)
6
+
-0.4
-10
V
-5
0
5
10
15
TIME (Ps)
TIME (Ps)
Figure 40.
Figure 41.
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POWER SUPPLY (V)
+
0.4
POWER SUPPLY (V)
VOUT (V)
V
Power On Timing, Minimum Gain
6
POWER SUPPLY (V)
Power On Timing, Maximum Gain
0.4
20
25
30
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APPLICATION INFORMATION
The LMH6514 is a fully differential amplifier optimized for signal path applications up to 400 MHz. The LMH6514
has a 200Ω input. The absolute gain is load dependent, however the gain steps are always 6 dB. The LMH6514
output stage is a class A amplifier. This class A operation results in excellent distortion and linearity
characteristics. This makes the LMH6514 ideal for voltage amplification and an ideal ADC driver where high
linearity is necessary.
VCC
VCC
44.3 nH
VCM = VCC
200
200
LMH6514
ADC
10 pF
3
GAIN
LATCH
Figure 42. LMH6514 Typical Application
The LMH6514 output common mode should be set carefully. Using inductors to set the output common mode is
one preferred method and will give maximum output swing. AC coupling of the output is recommended. The
inductors mentioned above will shift the idling output common mode to the positive supply. Also, with the
inductors, the output voltage can exceed the supply voltage. Other options for setting the output common mode
require supply voltages above 5V. If using a supply higher than 5V care should be taken to make sure the output
common mode does not exceed the 5.25V supply rating.
It is also important to note the maximum voltage limits for the OUT+ and OUT− pins, which is 6.4V. When using
inductors these pins will experience voltage swings beyond the supply voltage. With a 5V output common mode
operating point this makes the effective maximum swing 5.6 VPP differential. System calibration and automatic
gain control algorithms should be tailored to avoid exceeding this limit. Figure 43 shows how output voltage and
output common mode add together and approach the maximum output voltage.
7
MAXIMUM OUTPUT VOLTAGE = 6.4V
OUT +
6
VOUT (V)
1.4 VP
5 COMMON MODE
= 5V
4
OUT -
3
VOUT = 5.6 VPP DIFFERENTIAL
2
0
1
2
3
4
5
6
PHASE (RADIANS)
Figure 43. Output Voltage with Respect to the Output Common Mode
In order to help with system design Texas Instruments offers the ADC14V155KDRB High IF Receiver reference
design board. This board combines the LMH6514 DVGA with the ADC14V155 ADC and provides a ready made
solution for many IF receiver applications. Using an IF frequency of 169 MHz it achieves a small signal SNR of
72 dBFS and an SFDR of greater than 90 dBFS. Large signal measurements show an SNR of 68 dBFS and an
SFDR of 77 dBFS. The High IF Receiver board also features the LMK03000 low-jitter precision clock conditioner.
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OUT-
13
200:
200:
OUT+
0 to -42 dB
6
400:
6dB STEP
VARIABLE
ATTENUATOR
200:
7
14
15
+38 dB
+IN
+
-
-IN
5, 8
Figure 44. LMH6514 Block Diagram
INPUT CHARACTERISTICS
The LMH6514 input impedance is set by internal resistors to a nominal 200Ω. Process variations will result in a
range of values as shown in the Electrical Characteristics table. At higher frequencies parasitics will start to
impact the impedance. This characteristic will also depend on board layout and should be verified on the
customer’s system board.
At maximum gain the digital attenuator is set to 0 dB and the input signal will be much smaller than the output. At
minimum gain the output is 4 dB or more smaller than the input. In this configuration the input signal size may
limit the amplifier output amplitude, depending on the output configuration and the desired output signal voltage.
The input signal cannot swing more than 0.5V below the negative supply voltage (normally 0V) nor should it
exceed the positive supply voltage. The input signal will clip and cause severe distortion if it is too large. Because
the input stage self biases to approximately 1.4V the lower supply voltage will impose the limit for input voltage
swing. To drive larger input signals the input common mode can be forced higher than 1.4V to allow for more
swing. An input common mode of 2.0V will allow an 8 VPP maximum input signal. The trade off for input signal
swing is that as the input common mode is shifted away from the 1.4V internal bias point the distortion
performance will suffer slightly.
5V
INTERNAL BIAS = 1.4V
R1
200
RIN = R1 || 200
LMH6514
C1
Vin
C2
3
GAIN
LATCH
Figure 45. Single Ended Input
(Note capacitor on grounded input)
At the frequencies where the LMH6514 is the most useful the input impedance is not 200 Ω and it may not be
purely resistive. For many AC coupled applications the impedance can be easily changed using LC circuits to
transform the actual impedance to the desired impedance.
16
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SOURCE IMPEDANCE = 50:
f = 100 MHz
5V
VIN
L1
ZIN
LMH6514
C1
ZAMP
C3
C2
5
C3 = 22 pF
L1 = 169 nH
GAIN 1-5
C1 = 1 nF
LATCH
C2 = 1 nF
ZAMP = (150 ± j0):
ZIN = (50 ± j1):
Figure 46. Single Ended Input with LC Matching
As shown in Figure 46 a single ended 50Ω source is matched to the LMH6514 input at 100 MHz. The loss in this
circuit is related to the parasitic resistance in the inductor and capacitor and the bandwidth is related to the
loaded Q of the circuit. Since the Q, at 1.4 is quite low, the bandwidth is very wide. (59 MHz 0.3 dB bandwidth).
The input match of this circuit is quite good. It converts the ZAMP of the amplifier, which is (150 +j0)Ω to (50+j1)Ω.
The benefit of LC matching circuits over a transformer is the ability to match ratios that are not commonly found
on transformers and also the ability to neutralize reactance to present a purely resistive load to the voltage
source.
SOURCE IMPEDANCE = 200:
f = 100 MHz
5V
VIN
ZIN
L1
C2
ZAMP
LMH6514
C1
L1 = 550 nH
5
C1 = 36 pF
C2 = 36 pF
GAIN 1-5
LATCH
ZAMP = (150 ± j0):
ZIN = (202 ± j0.5):
Figure 47. Differential 200Ω LC Conversion Circuit
In Figure 47 the input source resistance is 200Ω differential. Here the desired input impedance is higher than the
amplifier input impedance, and is differential as well. The amplifier impedance of (150–j0)Ω is increased to
(202–j0.5)Ω. For an easy way to calculate the L and C circuit values there are several options for online tools or
down-loadable programs. The following tool might be helpful.
http://www.circuitsage.com/matching/matcher2.html
Excel can also be used for simple circuits; however, the “Analysis ToolPak” add-in must be installed to calculate
complex numbers.
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OUTPUT CHARACTERISTICS
The LMH6514 has the option of two different output configurations. The LMH6514 is an open collector topology.
As shown in Figure 52 each output has an on chip 200Ω pull up resistor. In addition there is an internal 400Ω
resistor between the two outputs. This results in a 200Ω or a 400Ω differential load in parallel with the external
load. The 400Ω option is the high gain option and the 200Ω provides for less gain. The 200Ω configuration is
recommended unless more gain is required.
The output common mode of the LMH6514 must be set by external components. Most applications will benefit
from the use of inductors on the output stage. In particular, the 400Ω option as shown in Figure 53 will require
inductors in order to be able to develop an output voltage. The 200Ω option as shown in Figure 54 or Figure 55
will also require inductors since the voltage drop due to the on chip 200Ω resistors will saturate the output
transistors. It is also possible to use resistors and high voltage power supplies to set the output common mode.
This operation is not recommended, unless it is necessary to DC couple the output. If DC coupling is required the
input common mode and output common mode voltages must be taken into account.
Maximum bandwidth with the LMH6514 is achieved by using the low gain, low impedance output option and
using a low load resistance. With an effective load of 67Ω a bandwidth of nearly a 1 GHz can be realized. As the
effective resistance on the output stage goes up the capacitance of the board traces and amplifier output stage
limit bandwidth in a roughly linear fashion. At an output impedance of 100Ω the bandwidth is down to 600 MHz,
and at 200Ω the bandwidth is 260 MHz. For this reason driving very high impedance loads is not recommended.
Although bandwidth goes down with higher values of load resistance, the distortion performance improves and
gain increases. The LMH6514 has a common emitter Class A output stage and minimizing the amount of current
swing in the output devices improves distortion substantially.
The LMH6514 output stage is powered through the collectors of the output transistors. Power for the output
stage is fed through inductors and the reactance of the inductors allows the output voltage to develop. In
Figure 42 the inductors are shown with a value of 44.4 nH. The value of the inductors used will be different for
different applications. In Figure 42 the inductors have been chosen to resonate with the ADC and the load
capacitor to provide a weak band pass filter effect. For broad band applications higher value inductors will allow
for better low frequency operation. However, large valued inductors will reduce high frequency performance,
particularly inductors of small physical sizes like 0603 or smaller. Larger inductors will tend to perform better than
smaller ones of the same value even for narrow band applications. This is because the larger inductors will have
a lower DC resistance and less inter-winding capacitance and hence a higher Q and a higher self resonance
frequency. The self resonance frequency should be higher than any desired signal content by at least a factor of
2. Another consideration is that the power inductors and the filter inductors need to be placed on the circuit board
such that their magnetic fields do not cause coupling. Mutual coupling of inductors can compromise filter
characteristics and lead to unwanted distortion products.
1
0
NORMALIZED GAIN (dB)
1 PH
-1
-2
-3
470 nH
-4
-5
200 nH
-6
-7
-8
RL = 100: TOTAL
-9
1
10
100
1000
FREQUENCY (MHz)
Figure 48. Bandwidth Changes Due to Different Inductor Values
18
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5V
680 nH
AMP ROUT
390 nH
3 pF
41 pF
27 nH
200:
ADC CIN
390 nH
3 pF
200
680 nH
5V
Figure 49. Gain vs. External Load
DIGITAL CONTROL
The LMH6514 has eight gain settings covering a range of 42 dB. To avoid undesirable signal transients the
LMH6514 should be powered on at the minimum gain state (all logic input pins at 0V). The LMH6514 has a 3-bit
gain control bus as well as a Latch pin. When the Latch pin is low, data from the gain control pins is immediately
sent to the gain circuit (i.e. gain is changed immediately). When the Latch pin transitions high the current gain
state is held and subsequent changes to the gain set pins are ignored. To minimize gain change glitches multiple
gain control pins should not change while the latch pin is low. In order to achieve the very fast gain step
switching time of 5 ns the internal gain change circuit is very fast. Gain glitches could result from timing skew
between the gain set bits. This is especially the case when a small gain change requires a change in state of
three or more gain control pins. If continuous gain control is desired the Latch pin can be tied to ground. This
state is called transparent mode and the gain pins are always active. In this state the timing of the gain pin logic
transitions should be planned carefully to avoid undesirable transients.
The LMH6514 was designed to interface with 3.3V CMOS logic circuits. If operation with 5V logic is required a
simple voltage divider at each logic pin will allow for this. To properly terminate 100Ω transmission lines a divider
with a 66.5Ω resistor to ground and a 33.2Ω series resistor will properly terminate the line as well as give the
3.3V logic levels. Care should be taken not to exceed the 3.6V absolute maximum voltage rating of the logic
pins.
EXPOSED PAD WQFN PACKAGE
The LMH6514 is packaged in a thermally enhanced package. The exposed pad is connected to the GND pins. It
is recommended, but not necessary, that the exposed pad be connected to the supply ground plane. In any
case, the thermal dissipation of the device is largely dependent on the attachment of this pad. The exposed pad
should be attached to as much copper on the circuit board as possible, preferably external copper. However, it is
also very important to maintain good high speed layout practices when designing a system board. Please refer to
the LMH6514 evaluation board for suggested layout techniques.
Package information is available on the TI web site.
http://www.ti.com/packaging
INTERFACING TO ADC
The LMH6514 was designed to be used with high speed ADCs such as the ADC14155. As shown in the Typical
Application on page 1, AC coupling provides the best flexibility especially for IF sub-sampling applications. Any
resistive networks on the output will also cause a gain loss because the output signal is developed across the
output resistors. The chart Maximum Gain vs. External Load shows the change in gain when an external load is
added.
The inputs of the LMH6514 will self bias to the optimum voltage for normal operation. The internal bias voltage
for the inputs is approximately 1.4V. In most applications the LMH6514 input will need to be AC coupled.
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The output common mode voltage is not self biasing, it needs to be pulled up to the positive supply rail with
external inductors as shown in Figure 42. This gives the LMH6514 the capability for large signal swings with very
low distortion on a single 5V supply. The internal load resistors provide the LMH6514 with very consistent gain.
A unique internal architecture allows the LMH6514 to be driven by either a differential or single ended source. If
driving the LMH6514 single ended the unused input should be terminated to ground with a 0.01 µF capacitor.
Directly shorting the unused input to ground will disrupt the internal bias circuitry and will result in poor
performance.
5V
680 nH
AMP ROUT
390 nH
3 pF
41 pF
27 nH
200:
ADC CIN
390 nH
200
3 pF
680 nH
5V
Center Frequency is 140 MHz with a 20 MHz Bandwidth
Designed for 200Ω Impedance
Figure 50. Bandpass Filter
ADC Noise Filter
Below is a filter schematic and a table of values for some common IF frequencies. The filter shown below offers
a good compromise between bandwidth, noise rejection and cost. This filter topology is the same as is used on
the ADC14V155KDRB High IF Receiver reference design board. This filter topology works best with the 12 and
14 bit sub-sampling analog to digital converters shown in the Table 2 table.
Table 1. Filter Component Values
Filter Component Values
Components
20
Fc
75 MHz
140 MHz
170 MHz
250 MHz
BW
40 MHz
20 MHz
25 MHz
Narrow Band
L1, L2
10 µH
10 µH
10 µH
10 µH
L3, L4
390 nH
39 0nH
560 nH
—
C1, C2
10 pF
3 pF
1.4 pF
47 pF
C3
22 pF
41 pF
32 pF
11 pF
L5
220 nH
27 nH
30 nH
22 nH
R1, R2
100
200
100
499
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5V
L1
L3
AMP VOUT -
C1
L5
AMP VOUT +
L2
ADC ZIN
C2
L4
R1
C3
AMP ZOUT
R2
ADC VIN +
ADC VIN -
ADC VCM
5V
Figure 51. Sample Filter
POWER SUPPLIES
As shown in Figure 52, the LMH6514 has a number of options for power supply connections on the output pins.
Pin 3 (VCC) is always connected. The output stage can be connected as shown in Figure 53, Figure 54, and
Figure 55. The supply voltage range for VCC is 4V to 5.25V. A 5V supply provides the best performance while
lower supplies will result in less power consumption. Power supply regulation of 2.5% or better is advised.
Of special note is that the digital circuits are powered from an internal supply voltage of 3.3V. The logic pins
should not be driven above the absolute maximum value of 3.6V. See the DIGITAL CONTROL section for
details.
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LMH6514
VCC
LATCH
NC
2
1
NC
1
3
LATCH
2
NC
VCC
3
4
NC
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4
SNOSB06 – JANUARY 2008
5V
GND
5
16
LOAD-
IN+
6
15
OUT-
IN-
7
14
OUT+
GND
8
13
LOAD+
GND
5
16
NC
IN+
6
15
OUT-
IN-
7
14
OUT+
GND
8
13
NC
VOUT
11
12
NC
GAIN_2
NC
VCC
LATCH
NC
3
2
1
NC
1
5V
Figure 53. Using High Gain Mode (400Ω Load)
4
LATCH
2
GAIN_0
12
NC
VCC
3
10
11
GAIN_0
NC
4
Figure 52. Internal Load Resistors
GAIN_1
10
GAIN_1
9
9
GAIN_2
+
5V
GND
5
16
IN+
6
15
IN-
7
14
5V
-
OUT-
GND
5
16
IN+
6
15
VOUT
OUT+
IN-
7
14
GND
8
13
-
OUT-
VOUT
OUT+
+
GND
8
13
+
22
10
11
12
GAIN_0
NC
12
NC
Figure 54. Using Low Gain Mode (200Ω Load)
GAIN_1
11
GAIN_0
9
10
GAIN_1
5V
GAIN_2
9
GAIN_2
5V
Figure 55. Alternate Connection for Low Gain
Mode (200Ω Load)
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Table 2. Compatible High Speed Analog to Digital Converters
Product Number
Max Sampling Rate (MSPS)
Resolution
Channels
ADC12L063
62
12
SINGLE
ADC12DL065
65
12
DUAL
ADC12L066
66
12
SINGLE
ADC12DL066
66
12
DUAL
CLC5957
70
12
SINGLE
ADC12L080
80
12
SINGLE
ADC12DL080
80
12
DUAL
ADC12C080
80
12
SINGLE
ADC12C105
105
12
SINGLE
ADC12C170
170
12
SINGLE
ADC12V170
170
12
SINGLE
ADC14C080
80
14
SINGLE
ADC14C105
105
14
SINGLE
ADC14DS105
105
14
DUAL
ADC14155
155
14
SINGLE
ADC14V155
155
14
SINGLE
ADC08D500
500
8
DUAL
ADC08500
500
8
SINGLE
ADC08D1000
1000
8
DUAL
ADC081000
1000
8
SINGLE
ADC08D1500
1500
8
DUAL
ADC081500
1500
8
SINGLE
ADC08(B)3000
3000
8
SINGLE
ADC08L060
60
8
SINGLE
ADC08060
60
8
SINGLE
ADC10DL065
65
10
DUAL
ADC10065
65
10
SINGLE
ADC10080
80
10
SINGLE
ADC08100
100
8
SINGLE
ADCS9888
170
8
SINGLE
ADC08(B)200
200
8
SINGLE
ADC11C125
125
11
SINGLE
ADC11C170
170
11
SINGLE
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMH6514SQ/NOPB
ACTIVE
WQFN
RGH
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L6514SQ
LMH6514SQE/NOPB
ACTIVE
WQFN
RGH
16
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L6514SQ
LMH6514SQX/NOPB
ACTIVE
WQFN
RGH
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L6514SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMH6514SQ/NOPB
WQFN
RGH
16
LMH6514SQE/NOPB
WQFN
RGH
LMH6514SQX/NOPB
WQFN
RGH
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
16
250
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
16
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH6514SQ/NOPB
WQFN
RGH
16
1000
203.0
190.0
41.0
LMH6514SQE/NOPB
WQFN
RGH
16
250
203.0
190.0
41.0
LMH6514SQX/NOPB
WQFN
RGH
16
4500
358.0
343.0
63.0
Pack Materials-Page 2
MECHANICAL DATA
RGH0016A
SQA16A (Rev A)
www.ti.com
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