NCT7290 16 Channel ADC, 12 Channel DAC, Internal Temp Sensor with I2C & SPI Interface http://onsemi.com The NCT7290 is a serially programmable voltage and temperature monitor. It can monitor its on chip temperature via its local sensor, a remotely connected diode and 16 analog inputs. Two 12 bit DACs allow for voltage control on 12 pins. Eight GPIO pins allow digital control and monitoring. An ALERT output is also available to signal out-of-limit conditions. Communication with the NCT7290 is accomplished via an I2C interface which is compatible with industry standard protocols or a 4 wire SPI interface. Both interfaces are available on this device. Through these interfaces the NCT7290s internal registers may be accessed. These registers allow the user to read the current temperature and input voltages, change the configuration settings, adjust each channels limits and set set the output DAC voltages on each of the 12 channels available. The NCT7290 is available in a 56-lead QFN (8 × 8 × 0.5 mm) package and operates over a supply range of 5.0 V ±10% (digital supply range of 3 V to 3.6 V) and temperature range of –55 to +125°C. This makes the NCT7290 ideal for a wide variety of applications ranging from cellular base stations to servers and industrial controls. Features • • • • • • • • • On-chip Temperature Sensor (±2°C Accuracy) Remote Temperature Sensor 5.0 V ±10% Supply Range 16 Analog Voltage Inputs 12 DAC Output Channels 8 Digital GPIO Pins SPI and I2C Interface Package Type: 56 Lead QFN These Devices are Pb-Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 0 1 56 QFN−56 CASE 485BK MARKING DIAGRAM 1 XXXXXXXXX XXXXXXXXX AWLYYWWG XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package ORDERING INFORMATION Device Package Shipping† NCT7290MNTXG QFN−56 2000 Tape & Reel with MPQ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: NCT7290/D ADD0 ADD1 SDA SCL BUS_SEL 26 27 25 24 28 ON-CHIP TEMPERATURE SENSOR SCLK SDI 24 25 SDO CS 26 27 5 VDAC 32 Bank2DAC Shutdown NCT7290 29 34 DACGND I2C INTERFACE* SPI INTERFACE* 30 VOUT 1 D− 41 LIMIT COMPARATOR VIN1 43 VIN2 44 VIN3 45 DATA REGISTERS VIN4 46 LIMIT AND CONFIG REGISTERS VIN5 47 31 VOUT 2 12 bit DAC Bank1 D+ 42 5 VOUT 35 VOUT 4 36 VOUT 5 12 VOUT ANALOG MUX VIN8 50 7 DACGND 10 bit A-to-D CONVERTER 9 12 bit DAC Bank2 STATUS REGISTER VIN11 53 VIN12 54 VIN13 55 VIN14 56 5 VOUT 8 VOUT 9 6 VOUT 10 12 VOUT 23 39 13 14 15 16 17 18 19 20 21 40 22 4 12 DGND AGND GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 ALERT AVDD VDD 12 VDAC Bank1DAC Shutdown NCT7290 GPIO1 ADD Interface Selection GPIO BUS_SEL D1 DGND 1−2 CS DAC GND 1−2 SDI D+ VOUT5, 6, 11, 12 Voltage Outputs − 12 V VOUT1−4, 7−10 Voltage Outputs − 5 V NCT7290 SDO Remote Temperature Sensor 5 VDAC GPIO1−8 SCLK SPI Interface 5 VDAC 12 VDAC 5V 12 V 12 VDAC SDA 4.5 to 5.5 V SCL I2C Interface AVDD Figure 1. Functional Block Diagram of NCT7290 AGND 2 3.0 to 5.5 V VIN16 10 VOUT 8 GPIO CONTROL REGISTER VDD 1 5 VDAC 1 VOUT 7 VIN9 51 VIN10 52 VIN15 38 VOUT 6 37 12 VDAC VIN6 48 VIN7 49 33 VOUT 3 VIN1−16 Figure 2. Typical Application Circuit http://onsemi.com 2 System Voltages 5 VOUT 11 3 VOUT 12 VIN14 VIN13 VIN12 VIN11 VIN10 VIN9 VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 NCT7290 VIN15 1 42 D+ VIN16 2 41 D− VOUT6 3 40 AVDD 12 VDAC 4 39 AGND VOUT5 5 38 VOUT12 VOUT4 6 37 12 VDAC DAC GND 7 36 VOUT11 VOUT3 8 35 VOUT10 5 VDAC 9 34 DAC GND VOUT2 10 33 VOUT9 VOUT1 11 32 5 VDAC 12 31 VOUT8 13 30 VOUT7 14 29 BANK2DAC Shutdown 25 26 27 28 ADD0/SDO ADD1/CS BUS_SEL 23 DGND SDA/SDI 22 VDD 24 21 ALERT SCL/SCLK 20 18 GPIO6 GPIO8 17 GPIO5 19 16 GPIO4 GPIO7 15 GPIO2 GPIO3 BANK1DAC Shutdown GPIO1 NCT7290 Top View (Not to Scale) Note: GND Flag Located Underneath NCT7290 Figure 3. Pin Connections PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 VIN15 Analog Input. 0 V to 2.5 V. 2 VIN16 Analog Input. 0 V to 2.5 V. 3 VOUT6 Analog Output. 0 V to 12 V. 4 12VDAC Analog Supply. Analog supply pins for the DAC output amplifiers on VOUT5−6. 5 VOUT5 Analog Output. 0 V to 12 V. 6 VOUT4 Analog Output. 0 V to 5 V. 7 DACGND 8 VOUT3 Analog Output. 0 V to 5 V. 9 5VDAC Analog Supply. Analog supply pin for the DAC output amplifiers on VOUT1−4. 10 VOUT2 Analog Output. 0 V to 5 V. 11 VOUT1 Analog Output. 0 V to 5 V. 12 BANK1DAC Shutdown 13 GPIO1 Programmable general purpose digital input or output. Default = input. 14 GPIO2 Programmable general purpose digital input or output. Default = input. 15 GPIO3 Programmable general purpose digital input or output. Default = input. 16 GPIO4 Programmable general purpose digital input or output. Default = input. Ground pin for the DAC output amplifiers. Shutdown pin for Bank1 DAC outputs (VOUT1, VOUT2, VOUT3, VOUT4, VOUT5 and VOUT6). Active low input (i.e. tie low to shutdown the bank). Active low input. Pin cannot be left floating. http://onsemi.com 3 NCT7290 PIN FUNCTION DESCRIPTION (continued) Pin No. Pin Name 17 GPIO5 Programmable general purpose digital input or output. Default = input. Description 18 GPIO6 Programmable general purpose digital input or output. Default = input. 19 GPIO7 Programmable general purpose digital input or output. Default = input. 20 GPIO8 Programmable general purpose digital input or output. Default = input. 21 ALERT Open-Drain Logic Output Used as Interrupt or SMBus Alert. Active low output. 22 VDD Power Supply. Can be powered from a supply in the range 3.3 V or 5.0 V ±10% 23 DGND 24 SCL/SCLK Digital Ground. This is the ground pin for all the digital circuitry. 25 SDA/SDI 26 ADD0/SDO Address selection pin for I2C mode. Can be tied high, low or left floating to give multiple address options. Serial Data Out in SPI mode. 27 ADD1/CS Address selection pin for I2C mode. Can be tied high, low or left floating to give multiple address options. Chip Select. Slave transmit enable in SPI mode – active low. 28 BUS_SEL Selects I2C or SPI interface. BUS_SEL = DGND selects I2C; BUS_SEL = VDD selects SPI. 29 BANK2DAC Shutdown Shutdown pin for Bank1 DAC outputs (VOUT7, VOUT8, VOUT9, VOUT10, VOUT11 and VOUT12). Active low input (i.e. tie low to shutdown the bank). Active low input. Pin cannot be left floating. 30 VOUT7 Analog Output. 0 V to 5 V. 31 VOUT8 Analog Output. 0 V to 5 V. 32 5VDAC Analog Supply. Analog supply pin for the DAC output amplifiers on VOUT7−10. 33 VOUT9 Analog Output. 0 V to 5 V. 34 DACGND 35 VOUT10 Analog Output. 0 V to 5 V. 36 VOUT11 Analog Output. 0 V to 12 V. 37 12VDAC Analog Supply. Analog supply pins for the DAC output amplifiers on VOUT11−12. 38 VOUT12 Analog Output. 0 V to 12 V. 39 AGND Analog ground. This is the ground pin for all the analog circuitry. 40 AVDD Analog Power Supply. Can be powered from a supply in the range 5.0 V ±10%. 41 D− Negative Connection to Remote Temperature Sensor. 42 D+ Positive Connection to Remote Temperature Sensor. 43 VIN1 Analog Input. 0 V to 2.5 V. 44 VIN2 Analog Input. 0 V to 2.5 V. 45 VIN3 Analog Input. 0 V to 2.5 V. 46 VIN4 Analog Input. 0 V to 2.5 V. 47 VIN5 Analog Input. 0 V to 2.5 V. 48 VIN6 Analog Input. 0 V to 2.5 V. 49 VIN7 Analog Input. 0 V to 2.5 V. 50 VIN8 Analog Input. 0 V to 2.5 V. 51 VIN9 Analog Input. 0 V to 2.5 V. 52 VIN10 Analog Input. 0 V to 2.5 V. 53 VIN11 Analog Input. 0 V to 2.5 V. 54 VIN12 Analog Input. 0 V to 2.5 V. 55 VIN13 Analog Input. 0 V to 2.5 V. 56 VIN14 Analog Input. 0 V to 2.5 V. GND QFN GND flag located underneath package. Serial Clock Input for I2C and SPI interfaces Serial Data Input/Output in I2C mode. Serial Data Input in SPI mode. Ground pin for the DAC output amplifiers. http://onsemi.com 4 NCT7290 MAXIMUM RATINGS Symbol Value Unit Supply Voltage Rating AVDD 5.7 V Supply Voltage DVDD 5.7 V Input Voltage on SCL, SDA, A2, A1 and A0 −0.3 V to DVDD + 0.3 V V Voltage on All Other Pins Except 12 VDAC Outputs −0.3 V to AVDD + 0.3 V V 5 mA Input Current on All Other Pins Input Current on SDA, A2, A1 and A0 IIN −1 mA to +50 mA mA TJ(max) 150.7 °C Operating Temperature Range TOP −55 to 125 °C Storage Temperature Range TSTG −65 to 160 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V Maximum Junction Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC-Q100-002 (EIA/JESD22-A114) ESD Machine Model tested per AEC-Q100-003 (EIA/JESD22-A115) THERMAL CHARACTERISTICS Rating Symbol Value RqJA RYJB 25 4 Unit °C/W Thermal Characteristics, QFN-56 (Note 3) Thermal Resistance, Junction-to-Air (Note 4) Thermal Reference, Junction-to-Board (Note 4) 3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 4. As measured using a copper heat spreading area of 650 mm2 (or 1 in2), of 1 oz copper thickness. RECOMMENDED OPERATING RANGES Rating Operating Supply Voltage Symbol Min Typ Max Unit VDD 3.0 − 3.6 V AVDD 4.5 − 5.5 V 5 VDAC Supply 5VDAC − 5 5.5 V 12 VDAC supply 12VDAC − 12 13.2 V TA −55 − 125 °C Operating Ambient Temperature Range Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, AVDD = 5.0 V ±10%. All specifications for −55°C to +125°C, unless otherwise noted. Parameter Test Conditions Min Typ Max Unit TA = −40°C to +105°C, AVDD = 5 V − − ±3 °C TA = −55°C to +125°C, AVDD = 5 V − − ±3.5 °C − 0.25 − °C TA = −40°C to +105°C, AVDD = 5 V − − ±2 °C TA = −55°C to +125°C, AVDD = 5 V − − ±2.25 °C − 0.25 − °C TEMPERATURE SENSOR Local Sensor Accuracy AVDD = 5.0 V ±10% Local Temperature Resolution Remote Sensor Accuracy AVDD = 5.0 V ±10% Remote Temperature resolution http://onsemi.com 5 NCT7290 ELECTRICAL CHARACTERISTICS (continued) TA = TMIN to TMAX, AVDD = 5.0 V ±10%. All specifications for −55°C to +125°C, unless otherwise noted. Parameter Test Conditions Min Typ Max Unit High Level 1 − 240 − mA Low Level 1 − 30 − mA High Level 2 − 300 − mA Low Level 2 − 37.5 − mA Averaging On − 38 − ms Averaging Off − 25 − ms − 0.7 − V ADC Resolution − 10 − Bits Input Voltage Range 0 − 2.5 V − 1 − MW Input Capacitance − 15 − pF Input Leakage Current − ±1 − mA Integral Linearity − − ±1 LSB Differential Linearity − − ±1 LSB Offset Error − ±1 ±4 LSB Gain Error − − ±5 LSB 2 × 2.5 ms ADCs in Parallel − 5 − ms VOUT1−4, VOUT7−10 0 − 5.25* V VOUT5−6, VOUT11−12 0 − 12.5* V Fullscale Output − ±10 − mA − 12 − bits − ±1 ±2 LSB − − ±1 LSB Output: 0−5 V (200 mV to DAC Supply – 200 mV) − ±1 ±10 mV Output: 0−12 V (200 mV to DAC Supply – 200mV) − ±3 ±25 mV Output: 0−5 V (200 mV to DAC Supply – 200 mV) − ±5 ±15 LSB Output: 0−12 V (200 mV to DAC Supply – 200 mV) − ±5 ±25 LSB − ±10 − ppmFS/°C TEMPERATURE SENSOR Remote Sensor Current Temperature Conversion Time D− Voltage ADC Input Impedance Conversion Time Converting DAC Output Voltage Range Output Current Resolution Integral Linearity 200 mV to VDD – 200 mV Differential Linearity Offset Error Gain Error Gain Error Drift Settling Time Output = 1/4 to 3/4 of Fullscale, 2 kW // 200 pF Load − 3.5 10 ms Overshoot Output = 1/4 to 3/4 of Fullscale, 2 kW // 200 pF Load − 200 − mV Crosstalk Midscale Code − 1 − LSB Slew Rate Measure between 3/8 and 5/8 − 1500 − mV/ms Supply Voltage (AVDD) 4.5 5.0 5.5 V Supply Current (IAVDD) − 7.5 10 mA 3.0 3.3 3.6 V − 2 5 mA POWER REQUIREMENTS Digital Supply Voltage (VDD) Supply Current (IVDD) http://onsemi.com 6 NCT7290 ELECTRICAL CHARACTERISTICS (continued) TA = TMIN to TMAX, AVDD = 5.0 V ±10%. All specifications for −55°C to +125°C, unless otherwise noted. Parameter Test Conditions Min Typ Max Unit − − 8.0 mA OPEN DRAIN DIGITAL OUTPUT (SDA & ALERT) Current Sink IOL Output Low Voltage, VOL IOUT = −4.0 mA − − 0.6 V High Level Output Current, IOH VOUT = VDD − 0.1 20 mA Input High Voltage VIH 1.6 − VDD V Input Low Voltage, VIL 0 − 0.8 V Output Low Voltage, VOL − − 0.4 V Input Capacitance − 5 − pF GPIOs I2C INTERFACE INPUT (SCL) Input High Voltage VIH VDD = 3.3 V, IIH = 5 mA 2 − VDD + 0.3 V Input Low Voltage, VIL VDD = 3.3 V, IIL = −5 mA 0 − 0.8 V − 5 − pF V Input Capacitance SPI INTERFACE INPUT (SDI, SCLK, CS, BUS_SEL) Input High Voltage VIH VDD = 3.3 V, IIH = 5 mA 2 − VDD + 0.3 Input Low Voltage, VIL VDD = 3.3 V, IIL = −5 mA 0 − 0.8 V − 5 − pF Input Capacitance SPI INTERFACE OUTPUT (SDO) Output High Voltage, VOH VDD = 3.3 V, IOL = 3 mA 2.4 − VDD V Output Low Voltage, VOL VDD = 3.3 V, IOL = −3 mA 0 − 0.4 V SPI − − 5 MHz I2C FS Mode − − 400 kHz GENERAL INTERFACE INFORMATION Bit Rate Table 1. I2C TIMING Parameter (Note 6) Symbol Min Typ Max Unit Clock Frequency fSCLK 10 − 400 kHz Clock Period tSCLK 2.5 − − ms SCL High Time tHIGH 0.6 − − ms SCL Low Time tLOW 1.3 − − ms tSU;STA 0.6 − − ms Start Hold Time (Note 7) tHD;STA 0.6 − − ms Data Setup Time (Note 8) tSU;DAT 100 − − ns Data Hold Time (Note 9) tHD;DAT 0.3 − 0.9 ms SCL, SDA Rise Time tr − − 300 ns SCL, SDA Fall Time tf − − 300 ns Start Setup Time tSU;STO 0.6 − − ms Bus Free Time tBUF 1.3 − − ms Glitch Immunity tSW − 50 − ns Stop Setup Time 6. 7. 8. 9. Guaranteed by design, but not production tested Time from 10% of SDA to 90% of SCL Time for 10%or 90% of SDA to 10% of SCL A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. http://onsemi.com 7 NCT7290 tF t LOW t HD; STA tR SCLK t HD; STA t HIGH t HD; DAT t SU; STA t SU; DAT t SU; STO SDATA t BUF STOP START START STOP Figure 4. I2C Timing Diagram Table 2. SPI TIMING Parameter (Note 10) Symbol Min Max Unit SPI Clock Freq fSCLK − 5 MHz SPI Clock Period tSCLK 200 − ns CS Falling Edge to SCLK Falling Edge tDELAY 15 − ns SCLK Rising Edge to CS Rising Edge tQUIET 15 − ns CS Rising Edge to SDO Disabled tDIS − 110 ns tCS,DIS 250 − ns SCLK Low Pulse Width tS 0.4 × tSCLK − ns SCLK High Pulse Width tM 0.4 × tSCLK − ns tSDO − 100 ns SDI Valid before SCLK Rising Edge tSETUP 15 − ns SDI Valid after SCLK Rising Edge tHOLD 15 − ns CS Deassertion between SPI Communications SCLK Falling Edge to SDO Transition 10. Guaranteed by design, but not production tested CS SCLK 1 8 SDO SDI 9 1 1 25 8 8 25 9 25 9 Figure 5. SPI Timing Diagram http://onsemi.com 8 NCT7290 TYPICAL CHARACTERISTICS (TA = +25°C, VDD = +3.3 V, AVDD = 5 V, unless otherwise stated) DNL (5V DAC) 0.4 DNL (LSBs) 0.2 0 −0.2 −0.4 −0.6 −0.8 0 1024 2048 3072 4096 CODE Figure 6. DNL vs Code at 255C for 5 V DAC OUTPUT DNL (12V DAC) 0.4 0.3 DNL (LSBs) 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 1024 2048 3072 CODE Figure 7. DNL vs Code at 255C for 12 V DAC OUTPUT http://onsemi.com 9 4096 NCT7290 INL (5V DAC) 0.6 0.5 0.4 INL (LSBs) 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 1024 2048 3072 4096 CODE Figure 8. INL vs Code at 255C for 5 V DAC OUTPUT INL (12V DAC) 1.2 1 INL (LSBs) 0.8 0.6 0.4 0.2 0 −0.2 −0.4 0 1024 2048 3072 CODE Figure 9. INL vs Code at 255C for 12 V DAC OUTPUT http://onsemi.com 10 4096 NCT7290 Differential Non Linearity 1 0.8 0.6 DNL (LSBs) 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 28 228 428 628 828 1028 CODE Figure 10. ADC DNL vs Code at 255C Integral Non Linearity 1 0.8 0.6 INL (LSBs) 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 0 200 400 600 CODE Figure 11. ADC INL vs Code at 255C http://onsemi.com 11 800 1000 NCT7290 Supply Voltage AVDD vs Current AIDD Supply Current AIDD (mA) 10 9 8 7 6 5 4 3 2 1 4.5 4.7 4.9 5.1 5.3 5.5 AVDD (V) Figure 12. Supply Current vs Supply Voltage Supply Current AIDD vs Temperature Supply Current AIDD (mA) 10 9 8 7 6 5 4 3 2 1 0 −40 10 60 Temperature (5C) Figure 13. Supply Current vs Temperature http://onsemi.com 12 110 NCT7290 Local Sensor Temperature Accuracy 0.8 0.6 0.4 Error (5C) 0.2 0 −60 −40 −20 −0.2 0 20 40 60 80 100 120 −0.4 −0.6 −0.8 −1 −1.2 Temperature (5C) Figure 14. Local Temperature Error vs Temperature Remote Sensor Temperature Accuracy 0.6 0.4 0.2 Error (5C) 0 −80 −60 −40 −20 0 20 40 60 80 −0.2 −0.4 −0.6 −0.8 Temperature (5C) Figure 15. Remote Temperature Error vs Temperature http://onsemi.com 13 100 120 140 NCT7290 OVERVIEW NCT7290 encompasses full analog monitoring, local and remote temperature sensing along with general purpose I/Os. The operational details of these functions are discussed below. values specified in the datasheet. To avoid reset on the go AVDD, DVDD and DAC supplies must be within their specified range. Power On Reset NCT7290 has a power-on-reset circuitry that resets the device if the voltage level of power supplies goes below the ANALOG TO DIGITAL CONVERTERS The NCT7290 has three ADCs. These are all successive approximation ADCs used for the digitization of analog inputs and temperature information. 512C 8C 4C 2C C SAR ADC The ADCs are power successive approximation with a built in analog channel multiplexers and 10 bit resolution. The 10 bit resolution assures high noise immunity and fast digitization that makes this device suitable for medium to high speed applications. The device internal circuitry operates at speed higher than the conversion time of the device because of the binary algorithm used. The algorithm is based on approximating the input signal by comparing with successive analog signal generated from the builtin DAC. The value of each output bit is evaluated on the basis of output of the comparator. The converter requires N conversion periods to give N bit digital output of the input analog signal. The SAR register stores the digital equivalent bits of the input analog signal and can be read by the master device using an I2C interface. The main building block of the device are: • Digital to Analog Converter • Comparator • Digital Logic Vin Figure 16. The Acquisition Phase of the Typical ADC Conversion Phase: The conversion phase is administered by a two phase non overlapping clock with phases φ1 and φ2 respectively. During φ1 the bottom plates of all the capacitors are grounded i.e. the top plates of all the capacitors are now Vin times higher than the ground. As the conversion process starts the digital control sets all the bits zero except the MSB in the SAR register. During the φ2 the capacitors associated with MSB is connected to VREF while others are connected to ground. In this way the DAC generates analog voltage of magnitude VREF/2. The analog output of DAC is compared with the input analog signal. The digital control logic sets the MSB to 1 if comparator output is high and 0 otherwise. Thus the first step of SAR algorithm decides whether the input signal is greater or less than VREF/2. The approximation process is then run again with the MSB in its proven value and the next lower bit is set to 1. This gives a general direction path and the remaining approximations will converge the output in this direction. Digital to Analog Converter A charge scaling DAC is used due to its compatibility with the switch capacitor circuits. The DAC operation consists of two phases called acquisition phase and the conversion phase. The acquisition phase is analogous to sample and hold circuit while the conversion phase is the process of conversion of the internal digital word in to an analog output. Acquisition phase: The top plates of all the capacitors on the array are connected to the ground and the bottom plates are connected to the applied voltage Vin. Thus there is a charge proportional to input voltage on the capacitor array. After acquisition the top and bottom plates are disconnected from their respective connections. Vin 512C VREF φ2 φ1 φ2 8C 4C 2C φ1 φ2 φ1 φ2 φ1 C Figure 17. The Conversion Phase of the Typical ADC http://onsemi.com 14 NCT7290 Digital Logic The function of the digital logic is to generate the binary word to be compared with the input analog signal in each approximation cycle. The result of each approximation cycle is stored in the SAR register. In short the digital logic determines the value of each output bit in a sequential manner base don the output of the comparator. Comparator A switch capacitor comparator is used to alleviate the effects of input offset voltage. The issue of charge injection is controlled by using fully differential topology. ANALOG CHANNELS The analog inputs (VIN1−VIN16) are multiplexed into two on-chip successive approximation, analog-digital converters. Analog inputs VIN1−VIN8 are multiplexed on a 10 bit ADC1 whereas VIN9−VIN16 are multiplexed on a second 10 bit ADC2. The maximum input range of analog inputs is 0−2.5 V. The device generates an internal reference of 2.5 V which is used for the digitization of the analog input channel values. VOLTAGE & TEMPERATURE MONITORING Local Temp Remote Temp NCT7290 10 bit ADC Multiplexer 10 bit ADC 2N3904 NPN Data Register VIN9 VIN10 VIN11 VIN12 VIN13 VIN14 VIN15 VIN16 Substrate transistors are generally PNP types with the collector connected to the substrate. Discrete types can be either PNP or NPN transistors connected as a diode (base-shorted to the collector). If an NPN transistor is used, the collector and base are connected to D+ and the emitter is connected to D−. If a PNP transistor is used, the collector and base are connected to D− and the emitter is connected to D+. 10 bit ADC Multiplexer VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 Multiplexer The NCT7290 implements a simple round robin for gathering and converting voltage and temperature data. All inputs are divided into groups and then multiplexed into 3 separate ADCs. An internally generated reference of 2.5 V is used. D+ D− Figure 19. Discrete NPN Transistor as Remote Sensor NCT7290 Figure 18. Input Monitoring D+ VIN1−8 are implemented as one round robin sequence and multiplexed into ADC1. VIN9−16 are implemented as another separate round robin sequence and multiplexed into ADC2. Both local and remote temperature measurements are then multiplexed into the third ADC. The resulting outputs of each ADC is then stored in the appropriate register. 2N3906 PNP D− Figure 20. Discrete PNP Transistor as Remote Sensor Remote Sensing Diodes If a discrete transistor is used with the NCT7290, the best accuracy is obtained by choosing devices according to the following criteria: • Base-emitter voltage is greater than 0.25 V at 6 mA with the highest operating temperature • Base-emitter voltage is less than 0.95 V at 100 mA with the lowest operating temperature A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the base emitter voltage (VBE) of a transistor operated at constant current. However, this technique requires calibration to null the effect of the absolute value of VBE, which varies from device to device. The NCT7290 is designed to work with either substrate transistors built into processors or discrete transistors. http://onsemi.com 15 NCT7290 • Base resistance is less than 100 W • There is a small variation in hFE (for example, 50 to The data registers for storing local and remote temperature data are present at address 0x0E and 0x0F respectively. Only 10 bits are used which gives the temperature measurement a resolution of 0.25°C. 150) that indicates tight control of VBE characteristics Transistors such as 2N3904, 2N3906, or equivalents in SOT−23 packages are suitable devices to use. If alternative transistor is used the device operates as specified as long as the above condition are met. Table 3. TWO’S COMPLEMENT TEMPERATURE DATA FORMAT Temperature Digital Output (10-bit) Series Resistance Cancellation −55°C 1100 1001 00 Parasitic resistance to the D+ and D− inputs to the NCT7290, seen in series with the remote diode, is caused by a variety of factors, including PCB track resistance and track length. This series resistance appears as a temperature offset in the remote sensor temperature measurement. This error typically causes a 0.5°C offset per ohm of parasitic resistance in series with the remote diode. The NCT7290 automatically cancels out the effect of this series resistance on the temperature reading, providing a more accurate result, without the need for user characterization of this resistance. The NCT7290 is designed to automatically cancel typically up to 130 W of resistance per leg. By using an advanced temperature measurement method, this is transparent to the user. This feature allows resistances to be added to the sensor path to produce a filter, allowing the part to be used in noisy environments. The technique used in the NCT7290 measures the change in VBE when the device operates at four different currents. Previous devices used only two operating currents, but it is the use of a third and fourth current that allows automatic cancellation of resistances in series with the external temperature sensor. To measure DVBE, the operating current through the sensor is switched among four related currents. N1 × I , N2 × I and N3 × I are different multiples of the current, I. The currents through the temperature diode are switched between I and N1 × I, giving DVBE1; then between I and N2 × I, giving DVBE2 and then between I and N3 × I, giving DVBE3. The temperature is then calculated using the three DVBE measurements. This method also cancels the effect of any series resistance on the temperature measurement. The resulting DVBE waveforms are passed through a 65 kHz low-pass filter to remove noise and then to a chopper-stabilized amplifier. This amplifies and rectifies the waveform to produce a dc voltage proportional to DVBE. The ADC digitizes this voltage producing a temperature measurement. −40°C 1101 1000 00 −10°C 1111 0110 00 −1°C 1111 1111 00 −0.25°C 1111 1111 11 0°C 0000 0000 00 10.25°C 0000 1010 01 25°C 0001 1001 00 125°C 0111 1101 00 Table 4. 10-BIT ADC OUTPUT CODE VS VIN Input Voltage ADC Output 2.5 VIN Decimal Binary (10-bits) < 0.002441 0 00000000 00 0.002441 to 0.004883 1 00000000 01 0.004883 to 0.007324 2 00000000 10 0.007324 to 0.009776 3 00000000 11 0.009776 to 0.012207 4 00000001 00 0.012207 to 0.014648 5 00000001 01 − − − 0.625000 to 0.627441 256 01000000 00 − − − 1.25000 to 1.252441 512 10000000 00 − − − 1.875000 to 1.877441 768 11000000 00 − − − 2.485352 to 2.487793 1018 11111110 10 2.487793 to 2.490234 1019 11111110 11 2.490234 to 2.492676 1020 11111111 00 2.492676 to 2.495117 1021 11111111 01 2.495117 to 2.497559 1022 11111111 10 2.497559 to 2.5 1023 11111111 11 Reading Temperature The temperature measurement channels take longer to present the data to the ADC than voltage channels. This is due to the time it takes to measure the temperature before presenting the corresponding voltage to the ADC. Data is updated on every temperature round robin cycle. If averaging is enabled then 16 round robin cycles are required The results of the local and remote temperature measurements are stored in the temperature value registers in two’s complement format. The result in these registers is compared with limits programmed into the high and low limit registers. The high and low limits are also stored in 2’s complement format. http://onsemi.com 16 NCT7290 Signal conditioning and measurement of the internal temperature sensor are performed in the same manner. Switching from Averaging OFF to ON or vice versa requires a procedure. The user needs to stop monitoring, change the averaging status and re-start monitoring to avoid glitches. Alternatively, the user can discard the first reading after changing the averaging state. before data is updated. Until valid data is available the previous temperature stays in the temperature value register. Averaging To reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles for low conversion rates. The conversion rates for which averaging can be on are 1/16, 1/8, 1/4, 1/2, 1 and 2 conversions/second. At rates of 4, 8, 16 and 32 conversions/second, no digital averaging occurs. DAC OPERATION There are 12 DACs output that can be programmed with 12 bits resolution using an internal reference. This is a decoder type based Resistor String type converter where N bits are used to create 2N value output. (0x03). By default all DAC outputs are configured to operate as 5 V outputs. See Configuration Register 1 in the Register Map section for more information. DAC VOUT Register Resistor String DAC A resistor string in connected to a switch network. The switch network is connected like a tree. Depending on the switch selection there will be only one low impedance path between the resistor string and the input of the amplifier. Figure 21 shows the block diagram of resistor string DAC architecture. The resistor string consists of resistors, each with value R. The code loaded in the DAC output registers determines at which node on the string the voltage is tapped off to be fed into the output amplifier. Thus, the selection of switches is controlled by the bit selection in the DAC output registers from 0x2A to 0x35. Table 4 shows the DAC output values that can be achieved depending on the codes in the DAC output registers. Please the the Register Map section for more details R S2048 R S2047 R VOUT S2046 R S2045 Power Rails for DAC Outputs R Separate power rails of 5 V and 12 V are required to be connected to the device at pin 9 and 37 respectively. See typical application circuit Figure 2 for more details. The DAC powers-up with a default output of 0 V. Configuration of 12 V DAC Outputs R The device has 12 DAC outputs, 8 of them have 5 V output range while 4 have 12 V output range. The eight 5 V DAC outputs are available as VOUT1−4 and VOUT7−10. On the other hand four 5 V/12 V DAC outputs are available as VOUT5−6 and VOUT11−12 respectively. The 12 V DAC outputs can be configured to operate as 5 V outputs by setting the bit 7 of configuration Register 1 S0 Figure 21. DAC Register String Architecture http://onsemi.com 17 NCT7290 Table 5. 12 BIT REGISTER CODE VS DAC OUTPUT Register Value (12 Bits) Output Voltage Decimal Binary (12 Bits) 5.0 VOUT 12 VOUT 0 00000000 0000 < 0.00122 < 0.00293 1 00000000 0001 0.00122 to 0.00244 0.00293 to 0.00586 2 00000000 0010 0.00244 to 0.00366 0.00586 to 0.00879 3 00000000 0011 0.00366 to 0.00488 0.00879 to 0.01172 4 00000000 0100 0.00488 to 0.00611 0.01172 to 0.01465 5 00000000 0101 0.00611 to 0.00733 0.01465 to 0.01758 − − − − 256 00010000 0000 0.3126 to 0.3138 0.75018 to 0.75311 − − − − 512 00100000 0000 0.62515 to 0.6264 1.5004 to 1.50329 − − − − 768 00110000 0000 0.9377 to 0.9389 2.25055 to 2.25348 − − − − 1024 01000000 0000 1.2503 to 1.2515 3.0007 to 3.00367 − − − − 2048 10000000 0000 2.5006 to 2.5018 6.0015 to 6.00439 − − − − 4090 111111111010 4.9939 to 4.9951 11.9853 to 11.9883 4091 111111111011 4.9951 to 4.9963 11.9883 to 11.9912 4092 111111111100 4.9963 to 4.9976 11.9912 to 11.9941 4093 111111111101 4.9976 to 4.9988 11.9941 to 11.9971 4094 111111111110 4.9988 to 5 11.9971 to 12 4095 111111111111 5 12 Clearing of DACs DAC outputs can also be cleared by writing appropriately in the register DAC_CHANNEL_SHUTDOWN register at address 0xC. All the DACs are enabled by default however; individual DACs can be turned OFF by writing 0 to their corresponding bits. The clearing of any DAC output will just pull-down the output pin to ground while the corresponding VOUTx_DATA register retains its value. See Register Map section for more details. NCT7290 contains two external control lines, BANK1DACSHUTDOWN and BANK2DACSHUTDOWN pins to shutdown the DAC outputs. When either pin goes low, the corresponding DAC outputs are cleared. Shutdown pins disconnect the DAC output pins and cleared them to ground. However, the outputs registers’ values remain intact until they are changed by writing to the corresponding VOUT registers. When the DAC outputs are shutdown the device internally connects the DACs output pins to GND via a 3 kW internal resistor ALERT corresponding low temperature limit in the limit registers (0x56−0x59), one or more of these flags will be set in Status register 5. If the high limit of analog input signal is over the corresponding high limit in the limit registers (0x36−0x45) the corresponding flag in the status register 1−2 will be set. The ALERT output goes low whenever an out-of-limit measurement is detected or if the remote temperature sensor is open-circuit. It is an open drain pin and requires a 10 kW pull-up to VDD. Status registers 1−5 (0x10−0x14) contains flags indicating the result of the limit comparisons. If the local and/or remote temperature measurement is above the corresponding high temperature limit or below the http://onsemi.com 18 NCT7290 sensor is open-circuit, the corresponding flag bit cannot be reset. A flag bit can be reset only if the corresponding value register contains an in-limit measurement, or the sensor is good. The ALERT interrupt latch is not reset by reading the status register, but it resets when the ALERT output has been serviced by the master reading the device address, provided the error condition has gone away and the status register flag bits have been reset. If the low limit of analog input signal is below the corresponding low limit in the limit registers (0x46−0x55) the corresponding flag in the status register 3−4 will be set. These flags are NOR’d together, so that if any of them are high, the ALERT interrupt latch is set, and the ALERT output goes low. Reading the status register clears the flag bits provided the error conditions that caused the flags to be set have gone away. While a limit comparator is tripped due to a value register containing an out-of-limit measurement or the GPIOs HANDLING as an output, it has an open drain configuration and the status is determined by the corresponding GPIO-n-polarity bit in the GPIO Polarity Register (0x06). Note that a pull-up resistor of 10 kW is required when using any GPIO pin as an output. The NCT7290 has eight GPIO pins. The GPIO1−8 pins are dedicated general purpose bidirectional, digital I/O signals. These pins can receive an input or produce an output. GPIO Configuration register (0x05) can be used to configure a GPIO as input or output. When GPIO-n is used NCT7290 REGISTERS The NCT7290 16-bit registers that are used for the configuration, monitoring, setting limits and other application related functions. Important registers are described briefly below. In order to get detailed description of each individual register please see the Register Map section. ADC DATA Registers Configuration Register There are 12 DAC output data registers available to set the analog voltage level at the VOUT pins. These are 16 bit registers however, only the 12 LSB bits are available for the setting of corresponding VOUT value. The DAC output registers are available from address 0x2A to 0x35 and are called VOUT1_DATA to VOUT12_DATA respectively. The table below outlines what codes must be programmed to the DAC registers in order to obtain a certain output voltage. The digitized data of analog inputs VIN1−VIN16 is stored in the ADC data registers (0x1A−0x29). Similarly registers Local_Temp_Data (0xE) and Remote_Temp_data (0xF) store the measured values of local and remote temperatures. DAC Data Registers Configuration register (0x03) is critical to initialize the device for proper operation. Bit 0 is used to enable the monitoring of analog and temperature channels. Bit 1 is used to enable/disable the SMBUS timeout. Bit 5 is used to reset the device using the software control. Alert output can be enable/disable using the bit 6 of the configuration register. Remote Temperature Conversion Rate Register Limit Registers The conversion rate register (0x04) must be programmed with 0x06 on power-up to ensure correct operation. This setting corresponds to 4 conv/sec with averaging ON. For more detailed information please see the Register Map section. NCT7290 has 36 limit registers to store analog inputs, local and remote, high and low temperature limits. For more detailed information please see the Register Map section. These registers can be written to and read back over the SMBus. The high limit registers perform a > comparison, while the low limit registers perform a < comparison. For example, if the high limit register is programmed as a limit of 90_C, measuring 81_C results in an alert condition. Chanel Selector Registers There are three different sequencers, one for each ADC. Sequencer 1 starts with VIN1 and goes to VIN8 before starting again. Sequencer 2 starts at VIN9 and goes to VIN16 before starting again. The temperature channels have a separate sequencer. All three sequencers run in parallel. Individual VINs and temperature channels can be disabled to remove them from the round robin sequence of the respected ADCs CHANNEL_SELECTOR_REGISTERs (0x09−0x0B) See Register Map section for more information. GPIO Registers The writable GPIO registers are used to set the direction and polarity of the GPIO pins. There are also two read-only registers that gives the status of datain-out. The GPIO registers can be accessed from address 0x05−0x08 for this purpose. http://onsemi.com 19 NCT7290 COMMUNICATION slave device. If the R/W bit is a 1, the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a STOP condition. There are two communication interfaces on the NCT7290. On power-up you must select which interface you intend on using. This is done via the BUS_SEL pin. Grounding this pin selects the I2C interface while setting it to VDD will select the SPI interface. The table below show the pins related to each interface. Table 6. COMMUNICATION PIN CONFIGURATION BUS_SEL State GND VDD Pin No. I2C SPI 24 SCL SCLK 25 SDA SDI 26 ADD0 SDO 27 ADD1 CS Serial Bus Interface – I2C Control of the NCT7290 is carried out via the I2C bus. The NCT7290 is connected to this bus as a slave device, under the control of a master device. The NCT7290 has a 7-bit serial bus address. The upper 3 bits of the device address are fixed at ‘110’.The lower four bits are set by the state of pins 26 and 27 as shown in Table 7. The address pins are sampled continuously after power-up, so any changes made while power is on changes the I2C address. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the case of the NCT7290, write operations contain two bytes, and read operations contain two bytes and perform the following functions. To write data to one of the device data registers or read data from it, the Address Pointer Register must be set so that the correct data register is addressed, and then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the Address Pointer Register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. The device address is sent over the bus followed by R/W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second data byte is the data to be written to the internal data register. When reading data from a register there are two possibilities: 1. If the NCT7290’s Address Pointer Register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the NCT7290 as Table 7. ADDRESS SELECTION ADD1 ADD0 Device Address 0 0 110 0001 (0x61) 0 1 110 0010 (0x62) 1 0 110 0100 (0x64) 1 1 110 0101 (0x65) The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the http://onsemi.com 20 NCT7290 from the corresponding data register without first writing to the Address Pointer Register. before, but only the data byte containing the register address is sent, as data is not to be written to the register. A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data word read from the data register. This is shown in Figure 23. 2. If the Address Pointer Register is known to be already at the desired address, data can be read To read from a register it is necessary to first write the register address to the address pointer. The Byte Write protocol is used for this. 1 9 9 1 SCL SDA 1 1 0 START BY MASTER 0 D6 D7 W FRAME 1 SERIAL BUS ADDRESS BYTE D4 D5 ACK. BY NCT7290 D2 D3 D1 D0 ACK. BY NCT7290 FRAME 2 ADDRESS POINTER REGISTER BYTE STOP BY MASTER Figure 22. Writing to the Address Pointer 1 9 9 1 SCL SDA 1 1 0 0 D6 D7 R D5 D4 D3 D2 D1 D0 ACK. BY NCT7290 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK. BY MASTER FRAME 2 MSB DATA FROM VALUE REGISTER 1 9 D7 D4 D5 D6 D2 D3 D1 D0 FRAME 3 LSB DATA FROM VALUE REGISTERBYTE NACK. BY STOP BY MASTER MASTER Figure 23. Reading a Word from a Previously Selected Register 1 9 9 1 SCL SDA 1 1 0 0 D6 D7 W D4 D5 D2 D3 D1 D0 ACK. BY NCT7290 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 1 D7 9 D6 D5 D4 D3 FRAME 3 DATA BYTE D2 D1 1 D0 D7 9 D6 ACK. BY NCT7290 D5 D4 D3 http://onsemi.com D2 FRAME 4 DATA BYTE Figure 24. Writing a Word to a Specified Address 21 ACK. BY NCT7290 D1 D0 ACK. BY NCT7290 STOP BY MASTER NCT7290 Serial Peripheral Interface – SPI Data is sampled on the rising edge of SCLK. Data is clocked into the NCT7290 (on the SDI pin) on the falling edge of the clock and data is clocked out of the NCT7290 (on the SDO pin) on the rising edge of the clock When the SDO pin of the slave is not being used it goes into a high impedance state (Hi-Z). SPI data transmission begins when the CS line is asserted (active low). This selects the slave to be communicated with. The 8 register address bits are then sent with the MSB first. Once this is complete the control signal for the Write/Read operation is sent. This is by default set to read (low signal) and can be set to write by setting this bit high. The next 16 bits is then clocked in. The NCT7290 sees all this data on its SDI pin only. The SDO pin is used for read operations (i.e. sending data beck to the master). The data starts appearing on the NCT7290 SDO pin on the clock edge after the control signal has been sent. The SPI interface of the NCT7290 consists of 4 wires: CS, SCLK, SDI and SDO. The CS (chip select) pin is used to select the device when more than one device is connected to the serial clock and data lines. It is controlled by the SPI master and must go low at the start of a transmission and high at the end of a transmission. The part operates in a slave mode and requires an externally applied (from the SPI master) serial clock to the SCLK input to access data from the data registers. The master must configure the clock signal polarity with respect to the data. The NCT7290 operates using an active low (inverted) clock (shown in Figure 26). Data is simultaneously transmitted and received on the SDO and SDI pins. This is known as full-duplex communication. NCT7290 (Slave) Master SCLK SCLK SDO SDI SDI SDO CS CS Figure 25. SPI Interface between Master and NCT7290 (Slave) CS SCLK 1 8 SDO SDI 9 8 1 1 25 8 25 9 25 9 Figure 26. Bit Timing Diagram for SPI Communication http://onsemi.com 22 NCT7290 NCT7290 REGISTER MAP Table 8. REGISTER MAP Register Address Register Name R/W POR Default 0x00 COMPANYID RO 0x001A 0x01 DEVICEID RO 0x1C7A 0x02 REVISIONID RO 0x0000 0x03 CONFIGURATION1 RW 0x0001 0x04 REMOTE_TEMP_CONV_RATE RW 0x0005 0x05 GPIO_INOUT RW 0x0000 0x06 GPIO_POLARITY RW 0x00FF 0x07 GPIO_DATA_IN RO 0x0000 0x08 GPIO_DATA_OUT RW 0x0000 0x09 CHANNEL_SELECTOR1 RW 0x00FF 0x0A CHANNEL_SELECTOR2 RW 0x00FF 0x0B CHANNEL_SELECTOR3 RW 0x00C0 0x0C DAC_CHANNEL RW 0xFFFF 0x0D RESERVED WO 0x0000 0x0E LOCAL_TEMP_DATA RO 0x0000 0x0F REMOTE_TEMP_DATA RO 0x0000 0x10 STATUS1 RO 0x0000 0x11 STATUS2 RO 0x0000 0x12 STATUS3 RO 0x0000 0x13 STATUS4 RO 0x0000 0x14 STATUS5 RO 0x0000 0x15 MASK1 RW 0x00FF 0x16 MASK2 RW 0x00FF 0x17 MASK3 RW 0x00FF 0x18 MASK4 RW 0x00FF 0x19 MASK5 RW 0x001F 0x1A VIN1_DATA RO 0x0000 0x1B VIN2_DATA RO 0x0000 0x1C VIN3_DATA RO 0x0000 0x1D VIN4_DATA RO 0x0000 0x1E VIN5_DATA RO 0x0000 0x1F VIN6_DATA RO 0x0000 0x20 VIN7_DATA RO 0x0000 0x21 VIN8_DATA RO 0x0000 0x22 VIN9_DATA RO 0x0000 0x23 VIN10_DATA RO 0x0000 0x24 VIN11_DATA RO 0x0000 0x25 VIN12_DATA RO 0x0000 0x26 VIN13_DATA RO 0x0000 0x27 VIN14_DATA RO 0x0000 0x28 VIN15_DATA RO 0x0000 0x29 VIN16_DATA RO 0x0000 0x2A VOUT1_DATA RW 0x0000 0x2B VOUT2_DATA RW 0x0000 0x2C VOUT3_DATA RW 0x0000 http://onsemi.com 23 NCT7290 Table 8. REGISTER MAP (continued) Register Address Register Name R/W POR Default 0x2D VOUT4_DATA RW 0x0000 0x2E VOUT5_DATA RW 0x0000 0x2F VOUT6_DATA RW 0x0000 0x30 VOUT7_DATA RW 0x0000 0x31 VOUT8_DATA RW 0x0000 0x32 VOUT9_DATA RW 0x0000 0x33 VOUT10_DATA RW 0x0000 0x34 VOUT11_DATA RW 0x0000 0x35 VOUT12_DATA RW 0x0000 0x36 VIN1_HIGH_LIM RW 0x03FF 0x37 VIN2_HIGH_LIM RW 0x03FF 0x38 VIN3_HIGH_LIM RW 0x03FF 0x39 VIN4_HIGH_LIM RW 0x03FF 0x3A VIN5_HIGH_LIM RW 0x03FF 0x3B VIN6_HIGH_LIM RW 0x03FF 0x3C VIN7_HIGH_LIM RW 0x03FF 0x3D VIN8_HIGH_LIM RW 0x03FF 0x3E VIN9_HIGH_LIM RW 0x03FF 0x3F VIN10_HIGH_LIM RW 0x03FF 0x40 VIN11_HIGH_LIM RW 0x03FF 0x41 VIN12_HIGH_LIM RW 0x03FF 0x42 VIN13_HIGH_LIM RW 0x03FF 0x43 VIN14_HIGH_LIM RW 0x03FF 0x44 VIN15_HIGH_LIM RW 0x03FF 0x45 VIN16_HIGH_LIM RW 0x03FF 0x46 VIN1_LOW_LIM RW 0x0000 0x47 VIN2_LOW_LIM RW 0x0000 0x48 VIN3_LOW_LIM RW 0x0000 0x49 VIN4_LOW_LIM RW 0x0000 0x4A VIN5_LOW_LIM RW 0x0000 0x4B VIN6_LOW_LIM RW 0x0000 0x4C VIN7_LOW_LIM RW 0x0000 0x4D VIN8_LOW_LIM RW 0x0000 0x4E VIN9_LOW_LIM RW 0x0000 0x4F VIN10_LOW_LIM RW 0x0000 0x50 VIN11_LOW_LIM RW 0x0000 0x51 VIN12_LOW_LIM RW 0x0000 0x52 VIN13_LOW_LIM RW 0x0000 0x53 VIN14_LOW_LIM RW 0x0000 0x54 VIN15_LOW_LIM RW 0x0000 0x55 VIN16_LOW_LIM RW 0x0000 0x56 LOCAL_TEMP_HIGH_LIM RW 0x0154 0x57 LOCAL_TEMP_LOW_LIM RW 0x0000 0x58 REMOTE_TEMP_HIGH_LIM RW 0x01B8 0x59 REMOTE_TEMP_LOW_LIM RW 0x0000 0x5A LOCAL_TEMP_OFFSET RW 0x0000 0x5B REMOTE_TEMP_OFFSET RW 0x0000 http://onsemi.com 24 NCT7290 REGISTER DETAILS Table 9. 0x03 CONFIGURATION REGISTER 1 Bit Field Name 15:8 Reserved 7 DAC_12_op_sel 6 Mask_alert 5 Sw_reset 4:2 Reserved 1 Timeout_disable 0 Start Description Access Default RO Returns 0s 0x00 12 V DAC Setting to Output 5 V if set to 0 0: 5 V Output 1: 12 V Output RW 0 Turns Off ALERT Output 0: ALERT is Unmasked 1: ALERT is Masked RW 0 Resets All Configuration Registers and Limits to Default Values 0: Reset Disabled 1: Resets All Configuration Registers and Limits to Default Values RW 0 RO 0 Disables Timeout 0: Enable_timeout 1: Disable_timeout RW 0 Enables Monitoring 0: Disable Monitoring 1: Enable Monitoring RW 1 I2C Table 10. 0x04 REMOTE TEMP CONVERSION RATE Bit Field Name 15:5 Reserved 4 Averaging_off 3:0 Remote_temp_conv_rate Description Access Default RO Returns 0s 0x000 Average Configuration 0: Turns Averaging On for the Remote Channel 1: Turns Averaging Off for the Remote Channel RW 0 10 Different Timing Options 0x0: 1/16 (Conv/Sec). Averaging On 0x1: 1/8 (Conv/Sec). Averaging On 0x2: 1/4 (Conv/Sec). Averaging On 0x3: 1/2 (Conv/Sec). Averaging On 0x4: 1 (Conv/Sec). Averaging On 0x5: 2 (Conv/Sec). Averaging On 0x6: 4 (Conv/Sec). Averaging Off 0x7: 8 (Conv/Sec). Averaging Off 0x8: 16 (Conv/Sec). Averaging Off 0x9: 20 (Conv/Sec). Averaging Off 0xA: 20 (Conv/Sec). Averaging Off 0xB: 20 (Conv/Sec). Averaging Off 0xC: 20 (Conv/Sec). Averaging Off 0xD: 20 (Conv/Sec). Averaging Off 0xE: 20 (Conv/Sec). Averaging Off 0xF: 20 (Conv/Sec). Averaging Off RW 0x5 http://onsemi.com 25 NCT7290 Table 11. 0x05 GPIO CONFIG Bit Field Name 15:8 Reserved 7 gpio8_inout 6 gpio7_inout 5 gpio6_inout 4 gpio5_inout 3 gpio4_inout 2 gpio3_inout 1 gpio2_inout 0 gpio1_inout Description 0: Configures the Pin as an Input 1: Configures the Pin as an Output Access Default RO Returns 0s 0x000 RW 0 Access Default RO Returns 0s 0x00 RW 1 Access Default RO Returns 0s 0x00 RO 0 Table 12. 0x06 GPIO POLARITY Bit Field Name 15:8 Reserved 7 gpio8_polarity 6 gpio7_polarity 5 gpio6_polarity 4 gpio5_polarity 3 gpio4_polarity 2 gpio3_polarity 1 gpio2_polarity 0 gpio1_polarity Description Controls Polarity of GPIO Pin 0: Active Low 1: Active High Table 13. 0x07 GPIO DATA IN Bit Field Name 15:8 Reserved 7 gpio8_data 6 gpio7_data 5 gpio6_data 4 gpio5_data 3 gpio4_data 2 gpio3_data 1 gpio2_data 0 gpio1_data Description Incoming Data for GPIO Pin Read 0: Logic Low Data Read 1: Logic High Data http://onsemi.com 26 NCT7290 Table 14. 0x08 GPIO DATA OUT Bit Field Name 15:8 Reserved 7 gpio8_data 6 gpio7_data 5 gpio6_data 4 gpio5_data 3 gpio4_data 2 gpio3_data 1 gpio2_data 0 gpio1_data Description Outgoing Data for GPIO Pin 0: Logic Low Data 1: Logic High Data Access Default RO Returns 0s 0x00 RW 0 Access Default RO Returns 0s 0x00 RW 1 Access Default RO Returns 0s 0x00 RW 1 Table 15. 0x09 CHANNEL SELECTOR 1 Bit Field Name 15:8 Reserved 7 Vin8_en 6 Vin7_en 5 Vin6_en 4 Vin5_en 3 Vin4_en 2 Vin3_en 1 Vin2_en 0 Vin1_en Description Enables Vin in the Round Robin ADC Conversion Sequence 0: Disables Vin Channel from Round Robin Sequence 1: Enables Vin Channel in the Round Robin Sequence Table 16. 0x0A CHANNEL SELECTOR 2 Bit Field Name 15:8 Reserved 7 Vin16_en 6 Vin15_en 5 Vin14_en 4 Vin13_en 3 Vin12_en 2 Vin11_en 1 Vin10_en 0 Vin9_en Description Enables Vin in the Round Robin ADC Conversion Sequence 0: Disables Vin Channel from Round Robin Sequence 1: Enables Vin Channel in the Round Robin Sequence http://onsemi.com 27 NCT7290 Table 17. 0x0B CHANNEL SELECTOR 3 Bit Field Name 15:8 Reserved 7 Local_temp_en 6 Remote_temp_en 5:0 Reserved Description Access Default RO Returns 0s 0x00 Enables Local Temp in the Round Robin ADC Conversion Sequence 0: Disables Local Temp Channel from Round Robin Sequence 1: Enables Local Temp Channel in the Round Robin Sequence RW 1 Enables Remote Temp in the Round Robin ADC Conversion Sequence 0: Disables Remote Temp Channel from Round Robin Sequence 1: Enables Remote Temp Channel in the Round Robin Sequence RW 1 0x00 Table 18. 0x0C DACOUTPUT SHUTDOWN Bit Field Name 15 Reserved 14 Reserved 13 Description Access Default Reserved RW 1 Reserved RW 1 VOUT12 Shutdown VOUT12 by Writing 0 to this Bit RW 1 12 VOUT11 Shutdown VOUT11 by Writing 0 to this Bit RW 1 11 VOUT10 Shutdown VOUT10 by Writing 0 to this Bit RW 1 10 VOUT9 Shutdown VOUT9 by Writing 0 to this Bit RW 1 9 VOUT8 Shutdown VOUT8 by Writing 0 to this Bit RW 1 8 VOUT7 Shutdown VOUT7 by Writing 0 to this Bit RW 1 7 Reserved Reserved RW 1 6 Reserved Reserved RW 1 5 VOUT6 Shutdown VOUT6 by Writing 0 to this Bit RW 1 4 VOUT5 Shutdown VOUT5 by Writing 0 to this Bit RW 1 3 VOUT4 Shutdown VOUT4 by Writing 0 to this Bit RW 1 2 VOUT3 Shutdown VOUT3 by Writing 0 to this Bit RW 1 1 VOUT2 Shutdown VOUT2 by Writing 0 to this Bit RW 1 0 VOUT1 Shutdown VOUT1 by Writing 0 to this Bit RW 1 Access Default RO 0x000 Access Default RO Returns 0s 0x00 RO 0x000 Table 19. 0x0D RESERVED Bit Field Name 15:0 Reserved Description Table 20. 0x0E LOCAL TEMPERATURE DATA Bit Field Name 15:10 Reserved 9:0 Local_Temp_Data Description Stores the Local Temperature Data http://onsemi.com 28 NCT7290 Table 21. 0x0F REMOTE TEMPERATURE DATA Bit Field Name 15:10 Reserved 9:0 Remote_Temp_Data Description Remote Temperature Data Access Default RO Returns 0s 0x00 RO 0x000 Access Default RO Returns 0s 0x00 RO 0 Table 22. 0x10 STATUS 1 (Note 11) Bit Field Name 15:8 Reserved 7 Vin8_High 6 Vin7_High 5 Vin6_High 4 Vin5_High 3 Vin4_High 2 Vin3_High 1 Vin2_High 0 Vin1_High Description Vin_High Tripped 11. Status registers (0x10−0x013) take 1 read to deassert ALERT and update register, so registers are not seen as cleared until second read. Table 23. 0x11 STATUS 2 (Note 12) Bit Field Name 15:8 Reserved 7 Vin16_High 6 Vin15_High 5 Vin14_High 4 Vin13_High 3 Vin12_High 2 Vin11_High 1 Vin10_High 0 Vin9_High Description Vin_High Tripped Access Default RO Returns 0s 0x00 RO 0 12. Status registers (0x10−0x013) take 1 read to deassert ALERT and update register, so registers are not seen as cleared until second read. Table 24. 0x12 STATUS 3 (Note 13) Bit Field Name 15:8 Reserved 7 Vin8_Low 6 Vin7_Low 5 Vin6_Low 4 Vin5_Low 3 Vin4_Low 2 Vin3_Low 1 Vin2_Low 0 Vin1_Low Description Vin_Low Tripped Access Default RO Returns 0s 0x00 RO 0 13. Status registers (0x10−0x013) take 1 read to deassert ALERT and update register, so registers are not seen as cleared until second read. http://onsemi.com 29 NCT7290 Table 25. 0x13 STATUS 4 Bit Field Name 15:8 Reserved 7 Vin16_Low 6 Vin15_Low 5 Vin14_Low 4 Vin13_Low 3 Vin12_Low 2 Vin11_Low 1 Vin10_Low 0 Vin9_Low Description Vin_Low tripped Access Default RO Returns 0s 0x00 RO 0 Access Default RO Returns 0s 0x000 RO 0 Access Default RO Returns 0s 0x00 RW 1 Access Default RO Returns 0s 0x00 RW 1 Table 26. 0x14 STATUS 5 Bit Field Name 15:5 Reserved 4 Diode_open_short 3 Local_High 2 Remote_High 1 Local_Low 0 Remote_Low Description This Bit is Set if the Remote Diode Pins are Open Circuit or Short Circuit Local_High Temperature Tripped Remote_High Temperature Tripped Local_Low Temperature Tripped Remote_Low Temperature Tripped Table 27. 0x15 MASK 1 Bit Field Name 15:8 Reserved 7 Vin8_high_mask 6 Vin7_high_mask 5 Vin6_high_mask 4 Vin5_high_mask 3 Vin4_high_mask 2 Vin3_high_mask 1 Vin2_high_mask 0 Vin1_high_mask Description Masks Vin_high Alert 0: Alert Not Masked for this Status Bit 1: Alert Masked for this Status Bit Table 28. 0x16 MASK 2 Bit Field Name 15:8 Reserved 7 Vin16_high_mask 6 Vin15_high_mask 5 Vin14_high_mask 4 Vin13_high_mask 3 Vin12_high_mask 2 Vin11_high_mask 1 Vin10_high_mask 0 Vin9_high_mask Description Masks Vin_high Alert 0: Alert Not Masked for this Status Bit 1: Alert Masked for this Status Bit http://onsemi.com 30 NCT7290 Table 29. 0x17 MASK 3 Bit Field Name 15:8 Reserved 7 Vin8_low_mask 6 Vin7_low_mask 5 Vin6_low_mask 4 Vin5_low_mask 3 Vin4_low_mask 2 Vin3_low_mask 1 Vin2_low_mask 0 Vin1_low_mask Description Access Default RO Returns 0s 0x00 RW 1 Access Default RO Returns 0s 0x00 RW 1 Access Default RO Returns 0s 0x000 Masks Diode_open_short Bit. Masked by Default RW 1 Masks Local_Low Temperature Alert RW 1 Masks Remote_High Temperature Alert RW 1 Masks Local_Low Temperature Alert RW 1 Masks Remote_Low Temperature Alert RW 1 Access Default RO Returns 0s 0x00 RO 0x000 Access Default RO Returns 0s 0x0 RW 0x000 Masks Vin_low Alert 0: Alert Not Masked for this Status Bit 1: Alert Masked for this Status Bit Table 30. 0x18 MASK 4 Bit Field Name 15:8 Reserved 7 Vin16_low_mask 6 Vin15_low_mask 5 Vin14_low_mask 4 Vin13_low_mask 3 Vin12_low_mask 2 Vin11_low_mask 1 Vin10_low_mask 0 Vin9_low_mask Description Masks Vin_low Alert 0: Alert Not Masked for this Status Bit 1: Alert Masked for this Status Bit Table 31. 0x19 MASK 5 Bit Field Name 15:5 Reserved 4 Diode_open_short_mask 3 Local_High_mask 2 Remote_High_mask 1 Local_Low_mask 0 Remote_Low_mask Description Table 32. 0x1A−0x29 VIN1−VIN16 DATA REGISTERS Bit Field Name 15:10 Reserved 9:0 Vin_data Description Vin Data is Stored in this Register (10 bits) Table 33. 0x2A−0x35 VOUT1−VOUT12 DATA REGISTERS Bit Field Name 15:12 Reserved 11:0 Vout_data Description Data Register for the DAC Output http://onsemi.com 31 NCT7290 Table 34. 0x36−0x45 VIN1−VIN16 HIGH LIMIT REGISTERS Bit Field Name 15:10 Reserved 9:0 Vin_high_lim Description High Limit Register for Analog Input Access Default RO Returns 0s 0x00 RW 0x3FF Access Default RO Returns 0s 0x00 RW 0x000 Access Default Table 35. 0x46−0x55 VIN1−VIN16 LOW LIMIT REGISTERS Bit Field Name 15:10 Reserved 9:0 Vin_low_lim Description Low Limit Register for Analog Input Table 36. 0x56 LOCAL TEMPERATURE HIGH LIMIT Bit Field Name 15:10 Reserved 9:0 Local_temp_high_lim Description High Limit for the Local Temperature RO Returns 0s 0x00 RW 0x154 Access Default RO Returns 0s 0x00 RW 0x000 Access Default RO Returns 0s 0x00 RW 0x1B8 Access Default RO Returns 0s 0x00 RW 0x000 Access Default RO Returns 0s 0x00 RW 0x000 Access Default RO Returns 0s 0x00 RW 0x000 Table 37. 0x57 LOCAL TEMPERATURE LOW LIMIT Bit Field Name 15:10 Reserved 9:0 Local_temp_low_lim Description Low Limit for the Local Temperature Table 38. 0x58 REMOTE TEMPERATURE HIGH LIMIT Bit Field Name 15:10 Reserved 9:0 Remote_temp_high_lim Description High Limit for the Remote Temperature Table 39. 0x59 REMOTE TEMPERATURE LOW LIMIT Bit Field Name 15:10 Reserved 9:0 Remote_temp_low_lim Description Low Limit for the Remote Temperature Table 40. 0x5A LOCAL TEMPERATURE OFFSET Bit Field Name 15:8 Reserved 7:0 Local_offset Description Two’s complement offset register. Any value entered into this register is added to the local temperature result. Table 41. 0x5B REMOTE TEMPERATURE OFFSET Bit Field Name 15:8 Reserved 7:0 Offset_data Description Two’s complement offset register. Any value entered into this register is added to the remote temperature result. http://onsemi.com 32 NCT7290 PACKAGE DIMENSIONS QFN56 8x8, 0.5P CASE 485BK ISSUE O ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ A B D PIN ONE LOCATION L L1 DETAIL A E ALTERNATE CONSTRUCTIONS TOP VIEW ALTERNATE CONSTRUCTION A 0.08 C A1 SIDE VIEW NOTE 4 MOLD CMPD DETAIL B (A3) DETAIL B 0.10 C C DETAIL A 56X MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 8.00 BSC 6.30 6.50 8.00 BSC 6.30 6.50 0.50 BSC 0.20 −−− 0.30 0.50 0.05 0.15 SEATING PLANE RECOMMENDED MOUNTING FOOTPRINT 0.10 C A B D2 DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉÉ ÉÉÉ EXPOSED Cu 0.15 C 0.15 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L 8.30 0.10 C A B 56X 0.63 6.54 1 E2 6.54 8.30 1 K 56 e 56X e/2 b 0.10 C A B BOTTOM VIEW 0.05 C PKG OUTLINE NOTE 3 0.50 PITCH 56X 0.32 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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