Precision Analog Microcontroller, 14-Bit Analog I/O with MDIO Interface, ARM Cortex-M3 ADuCM320i Data Sheet FEATURES Analog input/output Multichannel, 14-bit, 1 MSPS analog-to-digital converter (ADC) Up to 16 ADC input channels 0 V to VREF analog input range Fully differential and single-ended modes AVDD and IOVDD monitors 12-bit voltage output digital-to-analog converters (VDACs) 8 VDACs with a range of 0 V to 2.5 V or AVDD outputs 12-bit current output DACs (IDACs) 4 IDACS with a range of 0 mA to 150 mA outputs Voltage comparator Microcontroller ARM Cortex-M3 processor, 32-bit RISC architecture Serial wire port supports code download and debug Clocking options 80 MHz PLL with programmable divider Trimmed on-chip oscillator (±3%) External 16 MHz crystal option External clock source up to 80 MHz Memory 2 × 128 kB independent Flash/EE memories 10,000 cycle Flash/EE endurance 20-year Flash/EE retention 32 kB SRAM In circuit reprogrammability via I2C Rev. 0 On-chip peripherals MDIO slave up to 4 MHz 2 × I2C, 2 × SPI, UART Multiple general-purpose input/output (GPIO) pins: 3.6 V compliant 7 × 1.2 V compatible when used for MDIO 32-element programmable logic array (PLA) 3 general-purpose timers Wake-up timer Watchdog timer 16-bit pulse width modulator (PWM) Power Supply range: 2.9 V to 3.6 V, and 1.8 V to 2.5 V for IDACs Flexible operating modes for low power applications Package and temperature range 6 mm × 6mm, 96-ball CSP_BGA package Fully specified for −40°C to +85°C ambient operation Tools Low cost QuickStart development system Full third party support APPLICATIONS Optical networking Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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Technical Support www.analog.com ADUCM320I* Product Page Quick Links Last Content Update: 08/30/2016 Comparable Parts Design Resources View a parametric search of comparable parts • • • • Documentation Application Notes • AN-1322: ADuCM320 Code Execution Speed • AN-806: Flash Programming via I2C—Protocol Type 5 Data Sheet • ADuCM320i: Precision Analog Microcontroller, 14-Bit Analog I/O with MDIO Interface, ARM Cortex-M3 Data Sheet User Guides • UG-868: ADuCM320i/ADuCM322/ADuCM322i Reference Manual Software and Systems Requirements ADuCM320i Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all ADuCM320i EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number • IAR EWARM • Keil MDKARM * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. 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ADuCM320i Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution................................................................................ 17 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions........................... 18 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 23 Functional Block Diagram .............................................................. 3 Applications Information .............................................................. 24 General Description ......................................................................... 4 Recommended Circuit and Component Values .................... 24 Specifications..................................................................................... 5 Packaging and Ordering Information ......................................... 26 Microcontroller Electrical Specifications .................................. 5 Outline Dimensions ................................................................... 26 Timing Specifications ................................................................ 11 Ordering Guide .......................................................................... 26 Absolute Maximum Ratings ..................................................... 17 REVISION HISTORY 8/15—Revision 0: Initial Version Rev. 0 | Page 2 of 26 Data Sheet ADuCM320i FUNCTIONAL BLOCK DIAGRAM BUF_VREF2V5 2.5V BAND GAP XTALO XTALI ECLKIN 1.8 V LDO CLOCK SYSTEM 32.768kHz 16MHz OSC 80MHz PLL AIN0 AIN5 AIN6 14-BIT SAR ADC MUX DGNDx AVDDx AGNDx IOVDDx IOGNDx AIN15 INTERNAL CHANNELS: TEMPERATURE, AVDD, IOV DD COMPARATOR VDAC0 VDAC VDAC7 VDAC IDAC0 IDAC IDAC3 IDAC ARM CORTEX-M3 PROCESSOR MEMORY 2 × 128kB FLASH 32kB SRAM DMA NVIC GPIO PORTS UART 2 × SPI 2 × I2C EXT IRQS MDIO PLA GENERALPURPOSE I/O PORTS 3 × GP TIMER WD TIMER WAKE-UP TIMER PWM PWM0 TO PWM6 ADuCM320i RESET SYSTEM SERIAL WIRE SWDIO PVDDx PGND RESET Figure 1. Rev. 0 | Page 3 of 26 13422-001 SWCLK ADuCM320i Data Sheet GENERAL DESCRIPTION The ADuCM320i is a fully integrated single package device that incorporates high performance analog peripherals together with digital peripherals controlled by an 80 MHz ARM® Cortex™-M3 processor and integral flash for code and data. The ADC on the ADuCM320i provides 14-bit, 1 MSPS data acquisition on up to 16 input pins that can be programmed for single-ended or differential operation. The voltage at the IDAC output pins can also be measured by the ADC, which is useful for controlling the power consumption of the current DACs. Additionally, chip temperature and supply voltages can be measured. The ADC input voltage is 0 V to VREF. A sequencer is provided, which allows a user to select a set of ADC channels to be measured in sequence without software involvement during the sequence. The sequence can optionally repeat automatically at a user selectable rate. Up to eight VDACs are provided with output ranges that are programmable to one of two voltage ranges. Four IDAC sources are provided. The output currents are programmable with a range of 0 mA to 150 mA. A low drift band gap reference and voltage comparator completes the analog input peripheral set. The ADuCM320i can be configured so that the digital and analog outputs retain their output voltages and currents through a watchdog or software reset sequence. Thus, a product can remain functional even while the ADuCM320i is resetting itself. The ADuCM320i has a low power ARM Cortex-M3 processor and a 32-bit RISC machine that offers up to 100 MIPS peak performance. Also integrated on chip are 2 × 128 kB Flash/EE memory and 32 kB of SRAM. The flash comprises two separate 128 kB blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block. The ADuCM320i operates from an on-chip oscillator or a 16 MHz external crystal and a PLL at 80 MHz. This clock can optionally be divided down to reduce current consumption. Additional low power modes can be set via software. In normal operating mode, the ADuCM320i digital core consumes about 300 µA per MHz. The device includes an MDIO interface capable of operating at up to 4 MHz. The capability to simultaneously execute from one flash block and write/erase the other flash block makes the ADuCM320i ideal for 10G, 40G, and 100G optical applications. User programming is eased by incorporating PHYADR and DEVADD hardware comparators. In addition, the nonerasable kernel code plus flags in user flash provide assistance by allowing user code to robustly switch between the two blocks of user flash code and data spaces. The ADuCM320i integrates a range of on-chip peripherals that can be configured under software control, as required in the application. These peripherals include 1 × UART, 2 × I2C, and 2 × SPI serial input/output (I/O) communication controllers, GPIO, 32-element programmable logic array, 3 general-purpose timers, plus a wake-up timer and system watchdog timer. A 16-bit PWM with seven output channels is also provided. GPIO pins on the device power up in high impedance input mode. In output mode, the software chooses between opendrain mode and push-pull mode. The pull-up resistors can be disabled and enabled in software. In GPIO output mode, the inputs can remain enabled to monitor the pins. The GPIO pins can also be programmed to handle digital or analog peripheral signals, in which case the pin characteristics are matched to the specific requirement. A large support ecosystem is available for the ARM Cortex-M3 processor to ease product development of the ADuCM320i. Access is via the ARM serial wire debug port (SW-DP). On-chip factory firmware supports in-circuit serial download via I2C. These features are incorporated into a low cost QuickStart™ development system supporting this precision analog microcontroller family. Note that throughout this data sheet, multifunction pins, such as VDAC0/P5.3, are referred to either by the entire pin name or by a single function of the pin, for example, VDAC0, when only that function is relevant. Rev. 0 | Page 4 of 26 Data Sheet ADuCM320i SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS AVDD (the voltage applied to the AVDD3 and AVDD4 pin) = IOVDDx (the voltage applied to the IOVDDx pins (IOVDD0, IOVDD1, IOVDD2)) = VDD1 (the voltage applied to the VDD1 pin) = 2.9 V to 3.6 V (see Figure 14) maximum difference between supplies = 0.3 V, VREF = 2.5 V internal reference, fCORE = 80 MHz, TA = −40°C to +85°C, unless otherwise noted. PVDDx (the voltage applied to the PVDDx pins (PVDD0, PVDD1, PVDD2, PVDD3)) for IDACs = 1.8 V to 2.5 V. Power-up sequence must be VDD1, IOVDDx, AVDDx, and then PVDDx, but no delays in the sequence are required. Table 1. Parameter ADC BASIC SPECIFICATIONS ADC Power-Up Time Data Rate DC Accuracy 1 Resolution1 Integral Nonlinearity Differential Nonlinearity Symbol Min INL DNL −0.99 ±1.75 ±1.75 LSB ±0.75 +1 LSB ±3 LSB ±200 +1.2 −250 −2.6 +2 ±1 ±400 −4 µV µV/°C µV µV/°C LSB +2 µV µV/°C +3 µV µV/°C −350 −4.5 Match ADC DYNAMIC PERFORMANCE LSB ±0.75 −2.25 Input Buffer On Gain Drift1 Unit µs MSPS Bits Bits LSB 1 14 16 ADC ENDPOINT ERRORS Offset Error Input Buffer Off Drift1 Input Buffer On Drift1 Match Full-Scale Error Input Buffer Off Gain Drift1 Input Buffer Disabled Enabled Total Harmonic Distortion Input Buffer Disabled Enabled Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk Max 5 fSAMPLE DC Code Distribution Signal-to-Noise Ratio Typ ±1 Test Conditions/Comments Single-ended mode, unless otherwise stated 1 LSB = 2.5 V/214 Number of data bits 2.5 V internal reference; 1 LSB = 2.5 V/214 2.5 V external reference; 1 LSB = 2.5 V/214 2.5 V internal reference; 1 LSB = 2.5 V/214 2.5 V external reference; 1 LSB = 2.5 V/214 ADC input 1.25 V; 1 LSB = 2.5 V/214 Using 2.5 V external reference Using 2.5 V external reference Matching compared to AIN8 Full-scale error drift minus offset error drift Full-scale error drift minus offset error drift LSB fIN = 665.25 Hz sine wave, fSAMPLE = 100 kSPS; input filter = 15 Ω, 2 nF Includes distortion and noise components SNR 80 74 dB dB −86 −83 −88 −90 dB dB dB dB THD Rev. 0 | Page 5 of 26 Measured on adjacent channels ADuCM320i Parameter ADC INPUT Input Voltage Ranges Single-Ended Mode1 Differential Mode1 Data Sheet Symbol Compliance1 Common Mode1 Leakage Current AIN0 to AIN4, AIN6 to AIN15 AIN5 Input Current Input Capacitance ADC INPUT BUFFER 2 Voltage Compliance1 Input Current Min Max Unit Test Conditions/Comments Input buffer not enabled AGND4 −VREF VREF +VREF V Voltage between differential pins AGND4 0.9 AVDD4 1.6 V Output Impedance Load Current1 VDAC CHANNEL SPECIFICATIONS DC Accuracy1 Resolution1 Relative Accuracy 4 Differential Nonlinearity4 ±1.5 ±20 ±9 ±6 ±4 nA nA µA/V µA/V µA/V 20 pF 0.15 ON-CHIP VOLTAGE REFERENCE Accuracy Reference Temperature Coefficient1 Power Supply Rejection Ratio Internal VREF Power-On Time EXTERNAL REFERENCE INPUT Range1 Input Current BUFFERED REFFERNCE OUTPUT Output Voltage Accuracy Reference Temperature Coefficient1 Typ −34 PSRR ±100 2.5 V nA 2.51 V ±5 +4 mV ppm/°C dB ms 2.5 200 V µA 2.504 ±8 −5 +40 V mV µV/°C 1.2 Ω mA −15 60 50 1.8 −55 10 12 12 INL DNL ±15 mV ±4 −0.99 Offset Error ±3 Drift Gain Error 5 ±13 ±0.3 ±0.4 6.5 0.1 Drift Mismatch +1 Bits Bits LSB LSB Rev. 0 | Page 6 of 26 ±0.85 ±1 µV/°C % % ppm/°C % Pin shared with comparator At 1 MSPS; buffer off ≤800 kSPS; buffer off 500 kSPS; buffer off; ADCCNVC[25:16] = 0x1E During ADC acquisition When enabled by software Reduced accuracy below 0.15 V VIN = 0.15 V to 2.5 V, ADC converting 0.47 µF from VREF_1V2 to AGND4; reference is measured with all ADCs, VDACs, and IDACs enabled TA = 25°C ADC TA = 25°C, load = 1.2 mA 100 nF from BUF_VREF2V5 to AGND4 TA = 25°C RL = 5 kΩ, CL = 100 pF 3 1 LSB = 2.5 V/212 Number of data bits 1 LSB = 2.5 V/212 Guaranteed monotonic, 1 LSB = 2.5 V/212 2.5 V internal reference, DAC Output Code 0 0 V to internal VREF range 0 V to AVDD range Excluding reference drift % of full scale on DAC0 Data Sheet Parameter Analog Outputs Output Voltage Range 11 Output Voltage Range 21 Output Impedance DAC AC Characteristics Output Settling Time Glitch Energy ADuCM320i Symbol Min Typ Max Unit 2.5 AVDDx − 0.15 2 V V Ω 10 ±20 µs nV-sec Settled to ±1 LSB 1 LSB change when the maximum number of bits changes simultaneously in the DACxDAT register Bits Combination of overlapping 11 bits and 5 bits 0.15 0.15 IDAC CHANNEL SPECIFICATIONS Resolution1 14 Full-Scale Output1 Supply Voltage Each Channel1 1.8 2.5 mA V 0.4 0.4 PVDDx – 0.4 PVDDx – 0.25 V V ±0.75 ±3.5 ±0.75 % % % ±6 +1.5 µA/°C µA/°C µA/°C LSB LSB 150 Output Compliance Range IDAC0, IDAC1 IDAC2, IDAC3 Full-Scale Error IDAC0, IDAC1 IDAC2, IDAC3 Full-Scale Error Drift IDAC0, IDAC1 −40°C to +85°C 25°C to 85°C IDAC2, IDAC3 Integral Nonlinearity Differential Nonlinearity Zero-Scale Error Zero-Scale Error Drift IDAC0, IDAC1 IDAC2, IDAC3 Noise Current Pull-Down Current Settling Time To 0.1% To 1% Full Scale to 0 mA Overheat Shutdown PVDD ACPSRR 100 Hz 1 kHz 10 kHz 100 kHz Test Conditions/Comments Separate PVDDx supply for each channel See Figure 11 See Figure 11 IDAC set to 85% of full scale 25°C to 105°C range −40°C to +105°C range −40°C to +105°C range Internal VREF INL DNL 25 5 2 ±3 −0.99 −220 ±50 µA ±300 ±800 2 −165 nA/°C nA/°C µA µA −100 100 50 20 135 µs µs µs °C 51 45 25 10 dB dB dB dB Rev. 0 | Page 7 of 26 Internal VREF 1 LSB = 150 mA/211 Guaranteed 11-bit monotonic, 1 LSB = 150 mA/211 IDACxCON[5:2] = 0 When enabled IDACxCON[5:2] = 0 ±4 mA change from midscale ±4 mA change from midscale Pull-down enabled Junction temperature IDACxCON[5:2] = 0 ADuCM320i Parameter COMPARATOR Input Offset Voltage Bias Current Voltage Range1 Capacitance Hysteresis1 Response Time TEMPERATURE SENSOR Data Sheet Symbol Min Typ ±10 1 7 0.5 °C AVDDx − 1.2 7 8.5 Accuracy1 15 1.34 POR Unit mV nA V pF mV µs AGNDx Resolution POWER-ON RESET PIN RESET Minimum Time To Reset Maximum Time Not To Reset WATCHDOG TIMER Timeout Period FLASH/EE MEMORY Endurance1 Data Retention1 DIGITAL INPUTS Input Leakage Current Logic 1 GPIO Max 2.85 1.43 V 2.9 V µs µs 32 sec Default at power-up Cycles Years TJ = 85°C WDT 10,000 20 nA Logic 0 GPIO 10 nA PRTADDRx, MCK 1 16 10 6.5 8.5 5 5 10 µA µA pF pF pF pF pF pF Low High When enabled in software AFECOMP[2:1] = 0 Indicates die temperature, see Figure 9 When precision calibrated by the user 6 ADC measured voltage for temperature sensor channel without calibration, TA = 25°C 1.2 0.5 1 Input Capacitance MCK, PRTADDRx MDIO XTALI XTALO All Other Pins LOGIC INPUTS GPIO Input Voltage Low High MDIO PRTADDRx Input Voltage Low High MCK, MDIO Input Voltage Test Conditions/Comments VINL VINH 0.58 × IOVDDx VINL VINH 0.84 0.25 × IOVDDx V V 0.36 V V VIH = IOVDD, pull-up resistor disabled VIL = 0 V, pull-up resistor disabled Pull-up disabled Pull-up to 1.8 V enabled Setup time ≥10 ns; hold time ≥10 ns; MCK/MDIO VINL VINH 0.36 0.84 Rev. 0 | Page 8 of 26 V V Data Sheet Parameter XTALI Input Voltage Low High Pull-Up Current Pull-Down Current LOGIC OUTPUTS GPIO Output Voltage 7 High Low GPIO Short-Circuit Current1 MDIO Output Voltage High Low Delay Time OSCILLATORS Internal System Oscillator Accuracy System PLL External Crystal Oscillator ADuCM320i Symbol VINL VINH Typ VOH VOL Max Unit 120 100 V V µA µA 1.1 1.7 30 30 IOVDDx − 0.4 0.4 11 VOH VOL 1.0 0.2 100 16 ±0.5 80 16 32 kHz Internal Oscillator Accuracy External Clock START-UP TIME At Power-On After Other Reset From All Power-Down Modes PROGRAMMABLE LOGIC ARRAY Propagation Delay Pin Element EXTERNAL INTERRUPTS Pulse Width1 Level Triggered Edge Triggered POWER REQUIREMENTS 8 Power Supply Voltage Range AVDDx to AGNDx and IOVDDx to DGNDx1 Analog Power Supply Currents AVDDx Current Digital Power Supply Current IOVDDx Current in Normal Mode Min 32.768 ±5 0.05 ±3 ±20 80 Test Conditions/Comments VIN = 0 V, see Figure 10 VIN = 3.3 V, see Figure 10 All digital outputs excluding XTALO V V mA ISOURCE = 2 mA ISINK = 2 mA See Figure 13 V V ns ISOURCE = 4 mA ISINK = 4 mA MCK to MDIO out MHz % MHz MHz kHz % MHz 40 1.5 ms ms 1.25 µs 17 1.5 ns ns Main system clock Can be selected in place of internal oscillator Use for watchdog Can be selected in place of PLL Processor clock = 80 MHz POR to first user code execution Reset to first user code execution PLA 7 1 2.9 From input pin to output pin Per PLA cell ns ns 3.3 3.6 V 6.3 mA Analog peripherals in idle mode 4 mA All GPIO pull-up resistors enabled Rev. 0 | Page 9 of 26 ADuCM320i Parameter VDDx Current Normal Mode Data Sheet Symbol Min CORE_SLEEP Mode SYS_SLEEP Mode Hibernate Mode Additional Power Supply Currents ADC ADC Input Buffer IDAC DAC Total Supply Current Thermal Performance Impedance, Junction to Ambient 35 Typ Unit Test Conditions/Comments 29 mA 20 10 16 8 6.6 mA mA mA mA mA CD = 0 (80 MHz clock) executing typical code CD = 1 executing typical code CD = 7 executing typical code 4.1 mA 4.0 16.5 340 mA mA µA 40 45 Max 45 mA °C/W Continuously converting at 100 kSPS Both buffers enabled Excluding load current Per powered up DAC, excluding load current VDD1, IOVDDx, AVDDx connected together; condition when entering user code: peripheral clocks on, peripherals idle, no load currents JEDEC 2S2P These numbers are not production tested but are guaranteed by design and/or characterization data at production release. Enabling the input buffer changes the ADC input characteristics as described in these specifications (the ADC Input Buffer specifications). 3 The data in the Microcontroller Electrical Specifications section also applies for a load of RL = 1 kΩ and CL = 100 pF to ground but only for 0 V to 2.5 V. However, this is not production tested. 4 DAC linearity is calculated using a reduced code range of 100 to 3900. 5 DAC gain error is calculated using a reduced code range of 100 to an internal 2.5 V VREF. 6 Due to self heating, internal temperature measurements cannot be used to predict external temperatures. This value is only relevant after user calibration and only for internal and external conditions identical to those at calibration. 7 The average current from all GPIO pins must not exceed 3 mA per pin. 8 Power specifcations exclude any load currents to external circuits. 1 2 Rev. 0 | Page 10 of 26 Data Sheet ADuCM320i TIMING SPECIFICATIONS I2C Timing Table 2. I2C Timing in Standard Mode (100 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tVD; DAT tVD;ACK Description SCL low pulse width SCL high pulse width Start condition hold time Data setup time Data hold time (SDA held internally for 300 ns after falling edge of SCL) Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCL and SDA Fall time for both SCL and SDA Data valid time Data valid acknowledge time Min 4.7 4.0 4.0 250 0 4.7 4.0 4.7 Slave Typ Max Unit µs ns µs ns µs µs µs µs µs ns µs µs 3.45 1 300 3.45 3.45 15 Table 3. I2C Timing in Fast Mode (400 kHz) Description SCL low pulse width SCL high pulse width Start condition hold time Data setup time Data hold time (SDA held internally for 300 ns after falling edge of SCL) Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCL and SDA Fall time for both SCL and SDA Data valid time Data valid acknowledge time Min 1.3 0.6 0.6 100 0 0.6 0.6 1.3 20 Max Unit µs ns µs ns µs µs µs µs ns ns µs µs 300 300 0.9 0.9 15 tBUF tR SDA (I/O) MSB LSB ACK tDSU tDSU tVD; DAT tR tVD; ACK 1 S tF tRSU tH tSHD SCL (I) MSB tDHD tDHD tPSU P Slave Typ 2–7 8 tL STOP START CONDITION CONDITION 9 1 S(R) REPEATED START Figure 2. I2C-Compatible Interface Timing Rev. 0 | Page 11 of 26 tF 13422-002 Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tVD; DAT tVD; ACK ADuCM320i Data Sheet SPI Timing Table 4. SPI Master Mode Timing (Phase Mode = 1) Description SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time SCLK (POLARITY = 0) Min Typ (SPIDIV + 1) × tHCLK/2 (SPIDIV + 1) × tHCLK/2 3 ½ SCLK SCLK SCLK 25 25 20 0 Max Unit ns ns ns ns ns ns ns ns ns tSH tSL tSR SCLK (POLARITY = 1) tDAV tDF MOSI MISO MSB MSB IN tSF tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 tDSU LSB LSB IN 13422-003 Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) Rev. 0 | Page 12 of 26 Data Sheet ADuCM320i Table 5. SPI Master Mode Timing (Phase Mode = 0) Description SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data output setup before SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time Min Typ (SPIDIV + 1) × tHCLK/2 (SPIDIV + 1) × tHCLK/2 3 ½ SCLK SCLK SCLK 25 25 20 20 0 Max Unit ns ns ns ns ns ns ns ns ns ns SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDOSU MOSI MISO tDF MSB MSB IN tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN tDSU 13422-004 Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF tDHD Figure 4. SPI Master Mode Timing (Phase Mode = 0) Rev. 0 | Page 13 of 26 ADuCM320i Data Sheet Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter tCS Description CS to SCLK edge Min 10 tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time CS high after SCLK edge Typ Max (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 20 ns ns ns ns ns ns ns ns ns ns 10 10 25 25 1 1 20 CS tSFS tCS SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV MISO tDF MSB MOSI MSB IN tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN 13422-005 tDSU tDHD Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev. 0 | Page 14 of 26 Unit ns Data Sheet ADuCM320i Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter tCS Description CS to SCLK edge Min 10 tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time Data output valid after CS edge CS high after SCLK edge Typ Max Unit ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 20 ns ns ns ns ns ns ns ns ns ns ns 10 10 25 25 1 1 20 10 CS tCS tSFS SCLK (POLARITY = 0) tSH tSL tSF tSR SCLK (POLARITY = 1) tDAV tDOCS tDF MOSI MSB MSB IN BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN 13422-006 MISO tDR tDSU tDHD Figure 6. SPI Slave Mode Timing (Phase Mode = 0) Rev. 0 | Page 15 of 26 ADuCM320i Data Sheet Table 8. MDIO vs MCK Timing Parameter tSETUP tHOLD tDELAY Description MDIO setup before MCK edge MDIO valid after MCK edge Data output after MCK edge Min 10 10 Typ Max Unit ns ns ns 100 MCK VIH VIL CFP INPUT MDIO VIH VIL CFP INPUT MDIO tSETUP tHOLD Figure 7. MDIO Timing Rev. 0 | Page 16 of 26 tDELAY 13422-007 VOH VOL CFP OUTPUT Data Sheet ADuCM320i ABSOLUTE MAXIMUM RATINGS All requirements applicable to each pin must be met. Where multiple limits apply to a pin each one must be met individually. The limits apply according to the functionality of the pins at the time. Pins that can be either analog or digital, that is, that have two types indicated in the pin descriptions, must meet the limits for both types. For pin types, see Table 10. When powered up, all ground pins and ADC_REFN must be connected together to a node referred to as GND in Table 9. The limits that are listed must be reduced by any difference between any GNDx pin. Also, AVDD3 must be connected to AVDD4 and IOVDD1 must be connected to IOVDD3. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Table 9. Parameter Any Pin to GND Any PVDDx Pin to GND MDIO 1, MCK, and PRTADDR0 to PRTADDR4 in MDIO Mode to GND Between Any of AVDDx, IOVDDx, and VDD1 Pins Any Type I Pin to GND 2 Any Type AI or AO Pin to GND 3 Any IDACx, CDAMPx, IDAC_TST, IREF to GND ADC_REFP to GND Total Positive GPIO Pin Currents Total Negative GPIO Pin Currents Maximum Power Dissipation Operating Ambient Temperature Range Storage Temperature Range Operating Junction Temperature Range ESD HBM ESD FICDM Rating −0.3 V to +3.9 V −0.3 V to +2.8 V −0.3 V to +2.1 V −0.3 V to +0.3 V −0.3 V to IOVDDx + 0.3 V −0.3 V to AVDDx + 0.3 V −0.3 V to PVDDx + 0.3 V −0.3 V to AVDDx + 0.3 V 0 mA to 30 mA −30 mA to 0 mA 1W −40°C to +85°C −65°C to +160°C −40°C to +120°C 4 kV 1 kV Note that this pin is always in MDIO mode. This limit does not apply if no current can be drawn by external circuits on IOVDDx because, in this case, IOVDD follows to a suitable level. 3 This limit does not apply if no current can be drawn by external circuits on AVDDx because, in this case, AVDD follows to a suitable level. 1 2 Rev. 0 | Page 17 of 26 ADuCM320i Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 A IDAC_ TST IDAC0 PVDD0 PV DD2 IDAC 2 PGND IDAC 3 P V DD3 B IOVDD1 RES ET P3.3/ PRTADDR3/ PLAI[15] CDA MP0 CDA MP2 PGND CDAMP3 CDAMP1 P1.0/SIN/ P1.1/SOUT/ ECLKIN/ PLACLK1/ PLAI[5] PLAI[4] C IOG ND1 P0.0/ SCLK0/ PLAI[0] P2.3/BM P1.3/ PWM1/ PLAI[7] P1.4/ PWM2/ SCLK1/ PLAO[10] P1.5/ PWM3/ MISO1/ PLAO[11] P1.6/ PWM4/ MOSI1/ PLAO[12] D P0.2/ MOSI0/ PLAI[2] P0.1/ MISO0/ PLAI[1] P3.2/ PRTADDR2/ PLAI[14] P2.4/IRQ5/ ADCCONV/ PWM6/ PLAO[18] DGND2 IOVDD2 E P0.5/ SDA0 / PLAO[3] P0.4/ SCL0/ PLAO[2] P0.3/ IRQ0/CS0/ PLACLK0/ PLAI[3] SWCLK SWDIO IOG ND2 F P2.6/ IRQ7/ PLAO[20] P0.7/ SDA1/ PLAO[5] P0.6/ SCL1/ PLAO[4] AVDD_ REG0 AVDD_ RE G1 VRE F_1V2 G P2.7/ IRQ8/ PLAO[21] P3.1/ PRTADDR1/ PLAI[13] P3.0/ PRTADDR0/ PLAI[12] AIN15/ P4.7 AIN13/ P4.5 AVDD4 H P3.5/ MCK/ PLAO[27] XTALO MDIO AIN14/ P4.6 AIN12/ P4.4 AGND4 J IOVDD3 XTALI VDAC7/ P5.2 VDAC4 AGND1 AIN0 AIN1 AIN2 AIN7 AIN10 AIN11/ BUF_ VREF2V5 K IOG ND3 DVDD_ 2V5 VDAC6/ P5.1 VDAC3/ P5.0 VDAC1 VDD1 AGND2 AIN3 AIN6 AIN9/ P4.3 ADC _ REFP L DGND1 DVD D_1V8 VDAC5 VDAC2 / P3.7/ PLAO[29] VDAC0/ P5.3 AVDD3 AGND3 AIN4 AIN5 AIN8/ P4.2 ADC _ REFN IDAC P2.2/ P2.0/IRQ2/ IRQ4/POR/ PWMTRIP/ CLKOUT/ PLACLK2/ PLAI[10] PLAI[8] 7 8 ADuCM320i TO P VIEW (Not to Scale) 9 P VDD1 10 11 IDAC1 IREF P1.2/ PWM0/ PLAI[6] P1.7/IRQ1/ P3.4/ PWM5/ PRTADDR4/ CS1/ PLAO[26] PLAO[13] ANALOG Figure 8. Pin Configuration Table 10. Pin Function Descriptions Pin No. B2 C2 Mnemonic RESET P0.0/SCLK0/PLAI[0] Type 1 I I/O D2 P0.1/MISO0/PLAI[1] I/O D1 P0.2/MOSI0/PLAI[2] I/O E3 P0.3/IRQ0/CS0/PLACLK0/PLAI[3] I/O E2 P0.4/SCL0/PLAO[2] I/O Description Reset Input (Active Low). An internal pull-up resistor is included. Digital I/O Port 0.0 (P0.0). SPI0 Clock (SCLK0). Input to PLA Element 0 (PLAI[0]). Digital I/O Port 0.1 (P0.1). SPI0 Master Input, Slave Output (MISO0). Input to PLA Element 1 (PLAI[1]). Digital I/O Port 0.2 (P0.2). SPI0 Master Output, Slave Input (MOSI0). Input to PLA Element 2 (PLAI[2]). Digital I/O Port 0.3 (P0.3). External Interrupt 0 (IRQ0). SPI0 Chip Select 0 (CS0). When using SPI0, configure this pin as CS0. PLA Clock 0 (PLACLK0). Input to PLA Element 3 (PLAI[3]). Digital I/O Port 0.4 (P0.4). I2C0 Serial Clock (SCL0). Output of PLA Element 2 (PLAO[2]). Rev. 0 | Page 18 of 26 13422-008 DIGITAL 6 Data Sheet ADuCM320i Pin No. E1 Mnemonic P0.5/SDA0/PLAO[3] Type 1 I/O F3 P0.6/SCL1/PLAO[4] I/O F2 P0.7/SDA1/PLAO[5] I/O B9 P1.0/SIN/ECLKIN/PLAI[4] I/O B10 P1.1/SOUT/PLACLK1/PLAI[5] I/O B11 P1.2/PWM0/PLAI[6] I/O C6 P1.3/PWM1/PLAI[7] I/O C7 P1.4/PWM2/SCLK1/PLAO[10] I/O C8 P1.5/PWM3/MISO1/PLAO[11] I/O C9 P1.6/PWM4/MOSI1/PLAO[12] I/O C10 P1.7/IRQ1/PWM5/CS1/PLAO[13] I/O C5 P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8] I/O C4 P2.2/IRQ4/POR/CLKOUT/PLAI[10] I/O Description Digital I/O Port 0.5 (P0.5). I2C0 Serial Data (SDA0). Output of PLA Element 3 (PLAO[3]). Digital I/O Port 0.6 (P0.6). I2C1 Serial Clock (SCL1). Output of PLA Element 4 (PLAO[4]). Digital I/O Port 0.7 (P0.7). I2C1 Serial Data (SDA1). Output of PLA Element 5 (PLAO[5]). Digital I/O Port 1.0 (P1.0). UART Input (SIN). External Input Clock (ECLKIN). Input to PLA Element 4 (PLAI[4]). Digital I/O Port 1.1 (P1.1). UART Output (SOUT) PLA Clock 1(PLACLK1). Input to PLA Element 5 (PLAI[5]). Digital I/O Port 1.2 (P1.2). PWM Output 0 (PWM0). Input to PLA Element 6 (PLAI[6]). Digital I/O Port 1.3 (P1.3). PWM Output 1 (PWM1). Input to PLA Element 7 (PLAI[7]). Digital I/O Port 1.4 (P1.4). PWM Output 2 (PWM2). SPI1 Clock (SCLK1). Output of PLA Element 10 (PLAO[10]). Digital I/O Port 1.5 (P1.5). PWM Output 3 (PWM3). SPI1 Master Input, Slave Output (MISO1). Output of PLA Element 11 (PLAO[11]). Digital I/O Port 1.6 (P1.6). PWM Output 4 (PWM4). SPI1 Master Output, Slave Input (MOSI1). Output of PLA Element 12 (PLAO[12]). Digital I/O Port 1.7 (P1.7). External Interrupt 1 (IRQ1). PWM Output 5 (PWM5). SPI1 Chip Select 1 (CS1). When using SPI1, configure this pin as CS1. Output of PLA Element 13 (PLAO[13]). Digital I/O Port 2.0 (P2.0). External Interrupt 2 (IRQ2). PWM Trip (PWMTRIP). PLA Input Clock 2 (PLACLK2). Input to PLA Element 8 (PLAI[8]). Digital I/O Port 2.2 (P2.2). External Interrupt 4 (IRQ4). Reset Output (POR). Clock Output (CLKOUT). Input to PLA Element 10 (PLAI[10]). Rev. 0 | Page 19 of 26 ADuCM320i Data Sheet Pin No. C3 Mnemonic P2.3/BM Type 1 I/O D9 P2.4/IRQ5/ADCCONV/PWM6/PLAO[18] I/O F1 P2.6/IRQ7/PLAO[20] I/O G1 P2.7/IRQ8/PLAO[21] I/O G3 P3.0/PRTADDR0/PLAI[12] I/O G2 P3.1/PRTADDR1/PLAI[13] I/O D3 P3.2/PRTADDR2/PLAI[14] I/O B3 P3.3/PRTADDR3/PLAI[15] I/O C11 P3.4/PRTADDR4/PLAO[26] I/O H1 P3.5/MCK/PLAO[27] I/O H3 E9 E10 F11 MDIO SWCLK SWDIO VREF_1V2 I/O I I/O S A11 IREF AI J6 J7 J8 K8 L8 L9 K9 J9 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AI AI AI AI AI AI AI AI Description Digital I/O Port 2.3 (P2.3). Boot Mode (BM). This pin determines the start-up sequence after every reset. Pull-up is enabled at power-up. Digital I/O Port 2.4 (P2.4). External Interrupt 5 (IRQ5). External Input to Start ADC Conversions (ADCCONV). PWM Output 6 (PWM6). Output of PLA Element 18 (PLAO[18]). Digital I/O Port 2.6 (P2.6). External Interrupt 7 (IRQ7). Output of PLA Element 20 (PLAO[20]). Digital I/O Port 2.7 (P2.7). External Interrupt 8 (IRQ8). Output of PLA Element 21 (PLAO[21]). Digital I/O Port 3.0 (P3.0). MDIO Port Address Bit 0 (PRTADDR0). See the digital inputs parameter in Table 1 for details. Input to PLA Element 12 (PLAI[12]). Digital I/O Port 3.1 (P3.1). MDIO Port Address Bit 1 (PRTADDR1). See the digital inputs parameter in Table 1 for details. Input to PLA Element 13 (PLAI[13]). Digital I/O Port 3.2 (P3.2). MDIO Port Address Bit 2 (PRTADDR2). See the digital inputs parameter in Table 1 for details. Input to PLA Element 14 (PLAI[14]). Digital I/O Port 3.3 (P3.3). MDIO Port Address Bit 3 (PRTADDR3). See the digital inputs parameter in Table 1 for details. Input of PLA Element 15 (PLAI[15]). Digital I/O Port 3.4 (P3.4). MDIO Port Address Bit 4 (PRTADDR4). See the digital inputs parameter in Table 1 for details. Output of PLA Element 26 (PLAO[26]). Digital I/O Port 3.5 (P3.5). MDIO Clock (MCK) See the digital inputs parameter in Table 1 for more details. Output of PLA Element 27 (PLAO[27]). MDIO Data. Serial Wire Debug Clock. Serial Wire Bidirectional Data. 1.2 V Reference. This pin cannot be used to source current externally. Connect VREF_1V2 to AGNDx via a 470 nF capacitor. IDAC Reference Current. This pin generates the reference current for the IDACs and is set by an external resistor, REXT. Connect REXT from IREF to AGND4. Analog Input 0. Analog Input 1. Analog Input 2. Analog Input 3. Analog Input 4. Analog Input 5. AIN5 can be the negative input for the comparator. Analog Input 6. AIN6 is also the positive input for the comparator. Analog Input 7. Rev. 0 | Page 20 of 26 Data Sheet ADuCM320i Pin No. L10 Mnemonic AIN8/P4.2 Type 1 AI/I/O K10 AIN9/P4.3 AI/I/O J10 J11 AIN10 AIN11/BUF_VREF2V5 AI AI/AO H10 AIN12/P4.4 AI/I/O G10 AIN13/P4.5 AI/I/O H9 AIN14/P4.6 AI/I/O G9 AIN15/P4.7 AI/I/O L5 VDAC0/P5.3 AO/I/O K5 L4 VDAC1 VDAC2/P3.7/PLAO[29] AO AO/I/O K4 VDAC3/P5.0 AO/I/O J4 L3 K3 VDAC4 VDAC5 VDAC6/P5.1 AO AO AO/I/O J3 VDAC7/P5.2 AO/I/O A2 A3 B4 A10 A9 B8 A5 A4 B5 A7 A8 B7 B6 A6 A1 L2 IDAC0 PVDD0 CDAMP0 IDAC1 PVDD1 CDAMP1 IDAC2 PVDD2 CDAMP2 IDAC3 PVDD3 CDAMP3 PGND PGND IDAC_TST DVDD_1V8 AO S AI AO S AI AO S AI AO S AI S S AI/AO AO K2 DVDD_2V5 AO Description Analog Input 8 (AIN8). Digital I/O Port 4.2 (P4.2). Analog Input 9 (AIN9). Digital I/O Port 4.3 (P4.3). Analog Input 10. Analog Input 11 (AIN11). Buffered 2.5 V Bias (BUF_VREF2V5). The maximum load is 1.2 mA. Connect BUF_VREF2V5 to AGNDx via a 100 nF capacitor. Analog Input 12 (AIN12). Digital I/O Port 4.4 (P4.4). Analog Input 13 (AIN13). Digital I/O Port 4.5 (P4.5). Analog Input 14 (AIN14). Digital I/O Port 4.6 (P4.6). Analog Input 15 (AIN15). Digital I/O Port 4.7 (P4.7). Voltage DAC0 Output (VDAC0). Digital I/O Port 5.3 (P5.3). Voltage DAC1 Output. Voltage DAC2 Output (VDAC2). Digital I/O Port 3.7 (P3.7). Output of PLA Element 29 (PLAO[29]). Voltage DAC3 Output (VDAC3). Digital I/O Port 5.0 (P5.0). Voltage DAC4 Output (VDAC4). Voltage DAC5 Output (VDAC5). Voltage DAC6 Output (VDAC6). Digital I/O Port 5.1 (P5.1). Voltage DAC7 Output (VDAC7). Digital I/O Port 5.2 (P5.2). IDAC0. 0 mA to 150 mA full-scale output. Power for IDAC0. Damping Capacitor 0. Connect a damping capacitor from this pin to PVDD0. IDAC1. 0 mA to 150 mA full-scale output. Power for IDAC1. Damping Capacitor 1. Connect a damping capacitor from this pin to PVDD1. IDAC2. 0 mA to 150 mA full-scale output. Power for IDAC2. Damping Capacitor 2. Connect a damping capacitor from this pin to PVDD2. IDAC3. 0 mA to 150 mA full-scale output. Power for IDAC3. Damping Capacitor 3. Connect a damping capacitor from this pin to PVDD3. Power Supply Ground for IDACs. Power Supply Ground for IDACs. Pin for IDAC Test Purposes. Leave IDAC_TST unconnected. 1.8 V Digital Supply. A 470 nF capacitor to DGND1 must be connected to this pin to stabilize the internal 1.8 V regulator that supplies flash memory and the ARM Cortex-M3 processor. 2.5 V Digital Supply. A 470 nF capacitor to IOGND3 must be connected to this pin to stabilize the internal 2.5 V regulator that supplies the analog digital control. Rev. 0 | Page 21 of 26 ADuCM320i Data Sheet Pin No. F9 Mnemonic AVDD_REG0 Type 1 AO F10 AVDD_REG1 AO L1 D10 B1 D11 J1 C1 E11 K1 J5 K7 L7 H11 K6 L6 G11 L11 DGND1 DGND2 IOVDD1 IOVDD2 IOVDD3 IOGND1 IOGND2 IOGND3 AGND1 AGND2 AGND3 AGND4 VDD1 AVDD3 AVDD4 ADC_REFN S S S S S S S S S S S S S S S AO/A K11 ADC_REFP AO/A H2 XTALO O J2 XTALI I 1 Description Analog Regulator 0 Supply. A 470 nF capacitor to AGND4 must be connected to this pin to stabilize the internal 2.5 V regulator that supplies the ADC. Analog Regulator 1 Supply. Output of 2.5 V on-chip LDO regulator. A 470 nF capacitor to AGND4 must be connected to this pin. This regulator supplies the IDACs. Digital Ground 1 for DVDD_1V8. Digital Ground 2. Connect to DGND1. 3.3 V GPIO Supply. 3.3 V GPIO Supply and Interdie Communications. 3.3 V GPIO Supply. Ground for IOVDD1. Ground for IOVDD2. Ground for IOVDD3 and Interdie Communications. Analog Ground for VDD1. ESD Ground for Pad Ring. Ground for AVDD3. Ground for AVDD4, AVDD_REG0, and AVDD_REG1. 3.3 V Supply for Digital Die. VDAC and IDAC Supply (3.3 V). ADC Supply (3.3 V). Negative Decoupling Capacitor Connection for ADC Reference Buffer. Connect this pin to AGND4. Positive Decoupling Capacitor Connection for ADC Reference Buffer. Connect this pin to a 4.7 µF capacitor to the ADC_REFN pin. ADC_REFP can be overdriven by an external reference. Output from the Crystal Oscillator Inverter. When not using an external crystal, leave XTALO unconnected. Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. When not using an external crystal, connect XTALI to DGNDx. I is digital input, O is digital output, S is supply, AI is analog input, and AO is analog output. Rev. 0 | Page 22 of 26 Data Sheet ADuCM320i TYPICAL PERFORMANCE CHARACTERISTICS 0 50000 IDAC0 IDAC1 IDAC2 IDAC3 –10 PVDD AC PSRR (dB) ADC CODE (LSB 16) 45000 DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 40000 35000 –20 –30 –40 –50 30000 –40 –20 0 20 40 60 80 100 –70 13422-009 25000 –60 120 TEMPERATURE (°C) 100 3.0 2.5 OUTPUT VOLTAGE (V) PIN CURRENT (µA) 70 100k Figure 12. Typical PVDD AC PSRR vs. Frequency MAX PULL-UP MIN PULL-UP MIN PULL-DOWN MAX PULL-DOWN 80 10k FREQUENCY (Hz) Figure 9. Typical Temperature Measurement (ADC Code) vs. Internal Temperature (VDD = 3.3 V, 50 kSPS) 90 1k 13422-012 –60 60 50 40 30 20 10 VOH MAX VOH MIN VOL MIN VOL MAX 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 PIN VOLTAGE (V) 0 13422-010 6 8 10 12 14 16 Figure 13. Typical Output Voltage vs. Load Current IDAC2 IDAC3 IDAC0 IDAC1 3.6 VDD1 (V) 250 200 150 AFTER 40ms VDD1 MUST STAY ABOVE 2.9V INCLUDING NOISE EXCURSIONS 3.0 2.9 100 40ms min 50 0 0 25 50 75 100 125 150 IDAC OUTPUT CURRENT (mA) 13422-011 IDAC HEADROOM (mV) 300 4 LOAD CURRENT (mA) Figure 10. Typical Pull-Up/Pull-Down Pin Current vs. Pin Voltage (VDD = 3.3 V, 25°C) 350 2 Figure 11. Typical IDAC Headroom vs. IDAC Output Current VDD1 MUST BE ABOVE 3V FOR AT LEAST 40ms TO COMPLETE POR TIME (Not to Scale) Figure 14. VDD1 Power-On Requirements Rev. 0 | Page 23 of 26 13422-014 –10 13422-013 0 ADuCM320i Data Sheet APPLICATIONS INFORMATION capacitor near to each ball and their associated GND balls (PGND). In addition, place at least one 10 μF capacitor at the source of the PVDDx supply. RECOMMENDED CIRCUIT AND COMPONENT VALUES Figure 15 shows a typical connection diagram for the ADuCM320i. Supplies and regulators must be adequately decoupled with capacitors connected between the AVDDx, PVDDx, DVDD_x, AVDD_REGx, IOVDDx, and VDD1 balls and their associated GND balls (AGNDx, PGND, IOGNDx, and DGNDx). Table 10 indicates which ground balls are paired with which supply balls. There are four digital supply balls, IOVDD1, IOVDD2, IOVDD3, and VDD1. Decouple these balls with a 100 nF capacitor placed as near as possible to each of the four balls and their associated GND balls (IOGNDx and AGND1, respectively). In addition, place a 10 μF capacitor conveniently near to these balls. Similarly, the analog supply pins, AVDD3 and AVDD4, each require a 100 nF capacitor placed as near as possible to each ball and its associated AGNDx ball, and place a 10 μF capacitor conveniently near to these balls. The IDACs source their output currents from the PVDDx supply balls. Each PVDDx supply ball must have a 100 nF The IDAC output filters depend on a 10 nF capacitor being placed between the CDAMPx and PVDDx pins. The ADC reference requires a 4.7 μF capacitor placed between ADC_REFP and ADC_REFN and located as near as possible to each ball. ADC_REFN must be connected directly to AGND4. The ADuCM320i contains four internal regulators. These regulators require external decoupling capacitors. The DVDD_1V8 and DVDD_2V5 balls each require a 470 nF capacitor to DGND1 and IOGND3, respectively. AVDD_REG0 and AVDD_REG1 each require a decoupling capacitor to AGND4. To generate an accurate and low drift reference current, connect the IREF ball to AGND4 via a low ppm 3.16 kΩ resistor. Take care in the layout to ensure that currents flowing from the ground end of each decoupling capacitor to its associated ground ball share as little track as possible with other ground currents on the printed circuit board. Rev. 0 | Page 24 of 26 Data Sheet ADuCM320i VDD1 DVDD 0.47µF 0.47µF D11 J1 K6 L2 K2 L1 D10 C1 E11 K1 IOVDD2 IOVDD3 VDD1 DVDD_1V8 DVDD_2V5 DGND1 DGND2 IOGND1 IOGND2 IOGND3 10kΩ B1 IOVDD1 VDD1 RESET B2 RESET 12pF DGND J2 XTALI H2 XTALO A3 PVDD0 A9 PVDD1 VDD1 PVDD B7 CDAMP3 PGND B6 PGND SWDIO E10 ADC_REFN A6 P1.1/SOUT B10 L6 G11 F11 A11 K11 L11 AGND4 CDAMP2 AGND3 CDAMP1 B5 AGND2 B8 SWCLK E9 AGND1 CDAMP0 AVDD_REG1 B4 P1.0/SIN/ECLKIN/PLAI[4] B9 F10 J5 K7 L7 H11 AVDD_REG0 PVDD3 ADC_REFP 10nF PVDD2 A8 IREF 10nF A4 VREF_1V2 10nF P2.3/BM C3 ADuCM320i AVDD4 10nF 10kΩ AVDD3 12pF F9 0.47µF 3.16kΩ 4.7µF RESET RESET GND SWDIO Tx 0.47µF 0.47µF AGND DGND SWCLK Rx NC VDD1 DVDD 1.6Ω 10µF VIN ADP7102ARDZ3.3 VIN 0.1µF 10µF 1.6Ω VOUT 10kΩ EN/UVLO 0.1µF 10µF PG GND DGND ADP1741ACPZ +2.5V DGND DGND1 DVDD SENSE/ADJ 0.1µF 10µF 0.1µF AGND1 AVDD 0.1µF AGND AGND PVDD VIN VOUT 30kΩ EN 10µF EP GND PGND 10µF ADJ SS 10kΩ PGND 10µF PGND Figure 15. Recommended Circuit and Component Values Rev. 0 | Page 25 of 26 13422-015 INTERFACE BOARD CONNECTOR AVDD ADuCM320i Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 6.10 6.00 SQ 5.90 A1 BALL CORNER A1 BALL CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L 5.00 REF SQ 0.50 BSC 1.200 1.083 1.000 BOTTOM VIEW DETAIL A DETAIL A 0.223 NOM 0.173 MIN SEATING PLANE 0.35 0.30 0.25 BALL DIAMETER 0.93 0.86 0.79 COPLANARITY 0.08 04-02-2013-A 0.50 REF TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-195-AC WITH THE EXCEPTION TO BALL COUNT. Figure 16. 96-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-96-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 Temperature Range Package Description ADUCM320BBCZI ADUCM320BBCZI-RL EVAL-ADUCM320IQSPZ −40°C to +85°C −40°C to +85°C 96-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 96-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board with QuickStart Development System 1 Package Option Ordering Quantity BC-96-2 BC-96-2 429 2,500 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13422-0-8/15(0) www.analog.com/ADuCM320i Rev. 0 | Page 26 of 26