TI1 M38510/34701B2A 8-bit identity comparator Datasheet

 SDFS091 − MARCH 1987 − REVISED OCTOBER 1993
SN54F521 . . . J PACKAGE
SN74F521 . . . DW OR N PACKAGE
(TOP VIEW)
Compares Two 8-Bit Words
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These identity comparators perform comparisons
on two 8-bit binary or BCD words. They provide
P = Q outputs.
The SN54F521 is characterized for operation over
the full military temperature range of − 55°C to
125°C. The SN74F521 is characterized for
operation from 0°C to 70°C.
OE
P0
Q0
P1
Q1
P2
Q2
P3
Q3
GND
INPUTS
P=Q
L
L
P≠Q
X
H
X
H
H
P1
Q1
P2
Q2
P3
logic symbol†
P0
P1
P2
P3
P4
P5
P6
P7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
P=Q
Q7
P7
Q6
P6
Q5
P5
Q4
P4
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
Q7
P7
Q6
P6
Q5
Q3
GND
P4
Q4
P5
COMP
1
OE
2
Q0
P0
OE
VCC
OUTPUT
P=Q
OE
20
SN54F521 . . . FK PACKAGE
(TOP VIEW)
FUNCTION TABLE
P, Q
1
P=Q
•
•
0
4
6
8
11
P
13
15
17
3
7
19
1P = Q
0
P=Q
5
7
9
12
Q
14
16
18
7
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Copyright  1993, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
• DALLAS, TEXAS 75265
• HOUSTON, TEXAS 77251−1443
POST OFFICE BOX 655303
POST OFFICE BOX 1443
2−1
SDFS091 − MARCH 1987 − REVISED OCTOBER 1993
logic diagram (positive logic)
P7
Q7
P6
Q6
P5
Q5
P4
Q4
17
18
15
16
13
14
11
12
19
P3
Q3
P2
Q2
P1
Q1
P0
Q0
OE
2−2
8
9
6
7
4
5
2
3
1
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
P=Q
SDFS091 − MARCH 1987 − REVISED OCTOBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range: SN54F521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
SN74F521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
SN54F521
SN74F521
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
0.8
0.8
V
Input clamp current
−18
−18
mA
IOH
IOL
High-level output current
−1
−1
mA
Low-level output current
20
20
mA
TA
Operating free-air temperature
70
°C
High-level input voltage
2
2
−55
125
V
V
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
IIL
IOS§
ICC
SN54F521
TYP‡
MAX
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = − 18 mA
IOH = − 1 mA
VCC = 4.75 V,
VCC = 4.5 V,
IOH = − 1 mA
IOL = 20 mA
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.5 V
VO = 0
MIN
SN74F521
TYP‡
MAX
MIN
−1.2
2.5
3.4
−1.2
2.5
0.5
V
0.5
V
100
0.3
100
µA
20
20
µA
− 0.6
−60
−150
−60
VCC = 5.5 V,
See Note 2
21
32
21
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with all inputs at 4.5 V.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
V
3.4
2.7
0.3
UNIT
− 0.6
mA
−150
mA
32
mA
2−3
SDFS091 − MARCH 1987 − REVISED OCTOBER 1993
switching characteristics (see Note 3)
PARAMETER
FROM
(INPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX†
′F521
tPLH
tPHL
P or Q
P=Q
tPLH
tPHL
OE
P=Q
SN74F521
MIN
TYP
MAX
MIN
MAX
MIN
MAX
2.7
6.6
10
2.7
14
2.7
11
3.7
6.6
10
3.2
12
3.2
11
2.2
4.6
6.5
2.2
8.5
2.2
7.5
2.7
6.1
9
2.7
13.5
2.7
10
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
2−4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
UNIT
SN54F521
ns
ns
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9759101Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629759101Q2Q
SNJ54F
521FK
5962-9759101QRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9759101QR
A
SNJ54F521J
JM38510/34701B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
34701B2A
JM38510/34701BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
34701BRA
JM38510/34701BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
34701BSA
M38510/34701B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
34701B2A
M38510/34701BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
34701BRA
M38510/34701BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
34701BSA
SN54F521J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54F521J
SN74F521DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
F521
SN74F521DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
F521
SN74F521DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
F521
SN74F521DWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
F521
SN74F521N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74F521N
SN74F521N3
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
0 to 70
SN74F521NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
Addendum-Page 1
74F521
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SNJ54F521FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629759101Q2Q
SNJ54F
521FK
SNJ54F521J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9759101QR
A
SNJ54F521J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54F521, SN74F521 :
• Catalog: SN74F521
• Military: SN54F521
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74F521DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74F521NSR
SO
NS
20
2000
330.0
24.4
9.0
13.0
2.4
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74F521DWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74F521NSR
SO
NS
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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