TI AFE8221 Dual if analog front-end for digital radio Datasheet

AFE8221
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SBAS394A – APRIL 2007 – REVISED MARCH 2008
Dual IF Analog Front-End for Digital Radio
FEATURES
1
• Two IF ADCs
• Two 12-Bit Auxiliary DACs
• 8-Bit Auxiliary ADCs with Four-Channel Input
MUX
• Integrated IF Digital Processing Core
• Integrated Circuitry for Third-Overtone Master
Clock Oscillator
• Wakeup Circuit/Real-Time Clock with Separate
Crystal Oscillator
• Flexible Data Interface Optimized for TMS
Family of Digital Baseband Processors
• Pin-Selectable SPI™ and I2C™ Control
Interfaces
• 3.3V/1.8V Supply (Integrated Regulator
Available to Optionally Generate 1.8V Supply)
• TQFP-144, PowerPAD™ Package
2345
APPLICATIONS
•
•
IF-Sampled AM/FM Radio
HD, DAB Digital Radio
DESCRIPTION
The AFE8221 implements the intermediate frequency
(IF) sampling and processing functions of a digital
radio receiver system. It is designed to be used with
TI's digital radio baseband processors and AM/FM
tuners. The AFE8221 can also be programmed by
the baseband processor for use in conventional
AM/FM and digital radio. This unit includes two IF
inputs with associated filtering and digital processing
circuitry.
The receive circuit oversamples the radio tuner IF
output to reduce noise and improve dynamic range.
The IF analog-to-digital converter (ADC) oversamples
the IF input at rates up to 75MHz. The AFE8221 then
digitally mixes, filters, and decimates the signal to
provide I and Q output signals to the baseband
processor. A clock oscillator circuit is provided that
can be used with an appropriate third-overtone crystal
and external tank circuit to generate the sampling
clock for the IF ADCs.
The AFE8221 also includes a real-time clock and
associated low-power oscillator circuit. Two auxiliary
digital-to-analog converters (DACs) are included for
system control functions. An 8-bit auxiliary ADC and
input multiplexer (MUX) can be used for system
diagnostic functions. Other features include 12
general-purpose
input/output
(GPIO)
lines,
programmable interrupt generators, and an I2C
master for communication between the AFE and the
tuner(s).
The AFE8221 is available in a TQFP-144 (20mm ×
20mm) package and uses a 3.3V and a 1.8V power
supply. An onboard voltage regulator is included to
optionally generate the 1.8V digital supply for the
AFE8221.
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
SPI is a trademark of Motorola, Inc.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
AFE8221
www.ti.com
SBAS394A – APRIL 2007 – REVISED MARCH 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
AFE8221
TQFP-144
RFP
OPERATING
TEMPERATURE
RANGE
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
–40°C to +85°C
AFE8221RFP
Tray, 60
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage range
Voltage between:
Digital inputs
AFE8221
UNIT
AVDD
–0.5 to +3.6
V
DVDD
–0.5 to +3.6
V
IOVDD
–0.5 to +3.6
V
AGND to DGND
–0.3 to +0.5
V
AVDD to DVDD
–3.3 to +3.3
V
–0.3 to DVDD + 0.3
V
(2)
Digital data output
–0.3 to DVDD + 0.3
V
Operating free-air temperature range, TA
–40 to +85
°C
Storage temperature range
–55 to +125
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to DGND.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
AFE8221
PARAMETER
MIN
TYP
MAX
UNIT
+85
°C
POWER SUPPLY
Operation free-air temperature
TA
–40
Analog supply voltage
AVDD
3.14
3.3
3.6
V
Digital supply voltage
DVDD
1.6
1.8
2.0
V
IOVDD
1.6
3.6
V
Output driver supply voltage
Input common-mode voltage
Differential input voltage range
VCM
V
2
VPP
DIGITAL INPUTS
High-level input voltage
VIH
Low-level input voltage
VIL
2
0.7 × IOVDD
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V
0.25 × IOVDD
V
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): AFE8221
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SBAS394A – APRIL 2007 – REVISED MARCH 2008
POWER SUPPLY SPECIFICATIONS
At +25°C, AVDD, IOVDD = 3.3V, and DVDD = 1.8V, unless otherwise noted.
AFE8221
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER CONSUMPTION
Analog supply current
Digital supply current
Digital I/O supply current
130
155
mA
REG_ENB disabled
65
85
mA
REG_ENB disabled
35
50
mA
125
REG_ENB enabled
105
REG_ENB disabled
660
mW
REG_ENB enabled
725
mW
Software power-down
Control register address 1 set to 0x0000
100
mW
Hardware power-down
PWD enabled
50
µW
Power dissipation
mA
REDUCED POWER MODES
IF ADC SPECIFICATIONS
At +25°C, AVDD, IOVDD = 3.3V, DVDD = 1.8V, and fS = 75MHz, unless otherwise noted.
AFE8221
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
Input impedance
Offset error
Gain error
Full-scale input level
2
kΩ
3.0
mV
1.0
%FS
Peak differential, 1x gain
2.0
VPP
Peak differential, 2x gain
1.0
VPP
AVDD = 3.15VDC to 3.6VDC
72
dB
POWER SUPPLY
Power-supply rejection ratio, PSRR
REFERENCES
Positive reference
REFP
1.9
2.0
2.1
V
Negative reference
REFN
0.9
1.0
1.1
V
VCM
1.4
1.5
1.6
V
Common-mode voltage
AC PERFORMANCE
Input sample rate
Signal-to-noise ratio within a limited
passband
75
SNR
Third-order intermodulation distortion
Spurious-free dynamic range
SFDR
Input 10.7MHz, –1dBFS, in 3kHz passband
Input 10.7MHz, –1dBFS, in 100kHz passband
MHz
90
85
88
–7dB signals at 10.656MHz and 10.729MHz
91
–10dB signals at 10.656MHz and 10.729MHz
94
–1dB input at 10.7MHz, 100kHz passband
88
96
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dBc
dB
dBc
3
AFE8221
www.ti.com
SBAS394A – APRIL 2007 – REVISED MARCH 2008
AUXILIARY DAC SPECIFICATIONS
At +25°C, AVDD, IOVDD = 3.3V, and DVDD = 1.8V, unless otherwise noted.
AFE8221
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
12
Bits
Input code 0x000
0
V
Input code 0x3FF
2.7
V
OUTPUT VOLTAGE RANGE
Output voltage range
SETTLING TIME
Settling time
0.1% of FSR
10
µs
DC PERFORMANCE
Offset
±1
% of FSR
Gain error
±5
% of FSR
Monotonic
±0.5
LSB
Offset and gain errors removed
±3.0
LSB
Input code 0x200, AVDD = 3.15VDC to
3.6VDC
30
dB
DNL
INL
PSRR
AUXILIARY ADC SPECIFICATIONS
At +25°C, AVDD, IOVDD = 3.3V, and DVDD = 1.8V, unless otherwise noted.
AFE8221
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
10
Bits
Input code 0x00
0
V
Input code 0xFF
3.0
V
30
kΩ
INPUT VOLTAGE RANGE
Input voltage range
INPUT IMPEDANCE
Input impedance
CONVERSION TIME
Conversion Time
8704
MCLK
cycles
DC PERFORMANCE
Offset
±1.0
% of FSR
Gain error
±1.5
% of FSR
DNL
Monotonic
–1.0
INL
Offset and gain errors removed
–1.5
PSRR
4
Midscale input, AVDD = 3.15VDC to 3.6VDC
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±0.5
30
1.5
LSB
1.5
LSB
dB
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): AFE8221
AFE8221
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SBAS394A – APRIL 2007 – REVISED MARCH 2008
DIGITAL I/O SPECIFICATIONS
At +25°C and IOVDD = 3.3V, unless otherwise noted.
AFE8221
PARAMETER
High-level input current
Low-level input current
TEST CONDITIONS
MIN
MAX
UNIT
IIH
VIH = 1.6V to 3.6V
–10
TYP
10
µA
IIL
10
µA
VIL = 0V to 0.4V
–10
High-level output voltage
VOH
IOH = –50µA
0.8 × IOVDD
Low-level output voltage
VOL
IOL = 50µA
V
0.2 × IOVDD
V
MAX
UNIT
75
MHz
CLOCK OSCILLATOR SPECIFICATIONS
At +25°C, IOVDD = 1.8V, and DVDD = 1.8V, unless otherwise noted.
AFE8221
PARAMETER
Crystal frequency
TEST CONDITIONS
MIN
See the Master Clock Oscillator
section
20
TYP
IF_INP0
IF_INM0
PGA
S/H
IF_REFP
IF_VCM
IF_REFM
IF_BIAS
IF_INP1
IF_INM1
12-Bit
Pipeline
ADC
Attenuator
and
Overflow
Sensor
12-Bit
Pipeline
ADC
CIC Filter
N
Quadrature
Mixer
FIR Filter 1
2
RTC_REF
FIR Filter 2A
2
FIR Filter 2B
2
NCO
Voltage
Reference
PGA
S/H
RTCI
RTCO
RTC_REF
Real-Time
Clock
NCO
Attenuator
and
Overflow
Sensor
SCL0
SDA0
SCL1
SDA1
Dual
2
I C Master
CIC Filter
N
Quadrature
Mixer
Master
Oscillator
FIR Filter 1
2
Timing
Generator
FIR Filter 2A
2
FIR Filter 2B
2
IF Data Interface
Control
DAC
RT Clock
Oscillator
IF_DOUT3
IF_DOUT2
IF_DOUT1
IF_DOUT0
IF_DFSO
IF_DCLK
BB_WS
BB_BCK
BB_IDAT0
BB_QDAT0
BB_IDAT1
BB_QDAT1
PWD
REFCLK
RST
GRST
CDAC0
Interrupt
Generator
MCLKO
Control
DAC
GPIO
Control
Interface
MCLKI
CDAC1
WAKEUP
IRQ0
IRQ1
IRQ2
Aux ADC
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
AUX_ADC0
AUX_ADC1
AUX_ADC2
AUX_ADC3
MUX
CTRL_MODE
CS/A1
MISO/SDA
MOSI/A0
SCK/SCL
FUNCTIONAL BLOCK DIAGRAM
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SBAS394A – APRIL 2007 – REVISED MARCH 2008
PIN CONFIGURATION
GPIO4
GPIO2
GPIO3
GPIO0
GPIO1
GPIO10
GPIO11
GPIO8
GPIO9
DVSS
DVSS
DVSS
IOVSS
DVDD
IOVDD
AVDD
AVSS
DVDD
VSS
RTCI
RTCO
DVSS
RTC_REF
AVSS
AVDD
RTC_REF
SCL0
VSS
NC
SDA0
NC
NC
AVDD
AVDD
AVDD
AVDD
TQFP-144
Top View
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
NC
1
108 NC
NC
2
107 GPIO5
NC
3
106 GPIO6
AUX_ADC0
4
105 GPIO7
AUX_ADC1
5
104 DVDD
AUX_ADC2
6
103 DVSS
AUX_ADC3
7
102 REG_ENB
AVDD1
8
101 CTRL_MODE
CDAC0
9
100 SCK/SCL
AVSS 10
99 MISO/SDA
CDAC1 11
98 MOSI/A0
AVDD1 12
97 CS/A1
AVDD1 13
96 IOVDD
AVSS 14
95 IOVSS
AVSS 15
94 IF_DOUT0
AVSS 16
93 IF_DOUT1
IF_INP0 17
92 IF_DOUT2
IF_INM0 18
91 DVDD
AFE8221
IF_VCM 19
90 DVSS
IF_REFP 20
89 IF_DOUT3
IF_REFM 21
88 IF_DCLK
AVSS 22
87 IF_DFSO
AVDD1 23
86 IOVDD
AVDD1 24
85 IOVSS
AVSS 25
84 DVDD
AVSS 26
83 DVSS
IF_BIAS 27
82 NC
AVSS 28
81 NC
IF_INM1 29
80 NC
IF_INP1 30
79 NC
AVSS 31
78 NC
AVSS 32
77 NC
AVSS 33
76 NC
AVDD1 34
75 NC
NC 35
74 NC
6
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65
66
67
68
69
70
71
72
RST
64
PWD
63
IRQ2
62
IRQ1
61
IRQ0
60
GRST
59
WAKEUP
58
BB_QDAT1
57
BB_IDAT1
56
BB_IDAT0
55
BB_QDAT0
DVSS2
54
BB_WS
AVSS
53
BB_BCK
REFCLK
52
DVSS
AVDD
REFCLK
51
IOVSS
VSS
50
DVDD
49
IOVDD
48
AVSS
47
AVDD
46
VSS
45
DVDD2
44
MCLKO
43
MCLKI
42
SCL1
AVDD
41
NC
40
SDA1
39
AVDD
38
AVDD
73 NC
37
AVDD
NC 36
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): AFE8221
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SBAS394A – APRIL 2007 – REVISED MARCH 2008
TERMINAL FUNCTIONS
NAME
PIN #
FUNCTION
N/C
1
Open
No connect
DESCRIPTION
N/C
2
Open
No connect
N/C
3
Open
No connect
AUX_ADC0
4
Analog input
Auxiliary ADC channel 0
AUX_ADC1
5
Analog input
Auxiliary ADC channel 1
AUX_ADC2
6
Analog input
Auxiliary ADC channel 2
AUX_ADC3
7
Analog input
Auxiliary ADC channel 3
AVDD1
8
Supply
3.3V analog supply (internally switched)
CDAC0
9
Output
Control DAC 0 output
AVSS
10
Ground
Analog ground
CDAC1
11
Output
Control DAC 1 output
AVDD1
12
Supply
3.3V analog supply (internally switched)
AVDD1
13
Supply
3.3V analog supply (internally switched)
AVSS
14
Ground
Analog ground
AVSS
15
Ground
Analog ground
AVSS
16
Ground
Analog ground
IF_INP0
17
Input
IF ADC channel 0 positive input
IF_INM0
18
Input
IF ADC channel 0 negative input
IF_VCM
19
Output
IF ADC common-mode voltage
IF_REFP
20
Output
IF ADC positive reference
IF_REFM
21
Output
IF ADC negative reference
AVSS
22
Ground
Analog ground
AVDD1
23
Supply
3.3V analog supply (internally switched)
AVDD1
24
Supply
3.3V analog supply (internally switched)
AVSS
25
Ground
Analog ground
AVSS
26
Ground
Analog ground
IF_BIAS
27
Input
AVSS
28
Ground
IF_INM1
29
Input
IF ADC channel 1 negative input
IF_INP1
30
Input
IF ADC channel 1 positive input
AVSS
31
Ground
Analog ground
AVSS
32
Ground
Analog ground
AVSS
33
Ground
Analog ground
AVDD1
34
Supply
3.3V analog supply (internally switched)
N/C
35
Open
No connect
N/C
36
Open
No connect
AVDD
37
Supply
3.3V analog supply
AVDD
38
Supply
3.3V analog supply
AVDD
39
Supply
3.3V analog supply
AVDD
40
Supply
3.3V analog supply
N/C
41
Open
No connect
SDA1
42
Bidirectional
Channel 1 tuner I2C data
SCL1
43
Output
Channel 1 tuner I2C clock
IF ADC bias input
Analog ground
AVSS
44
Ground
Analog ground
AVDD
45
Supply
3.3V analog supply
REFCLKN
46
Output
Inverted reference clock output
REFCLK
47
Output
Reference clock output
AVSS
48
Ground
Analog ground
DVSS2
49
Ground
Digital ground (for RTC oscillator)
MCLKI
50
Input
MCLKO
51
Output
MCLK oscillator input
MCLK oscillator output
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SBAS394A – APRIL 2007 – REVISED MARCH 2008
TERMINAL FUNCTIONS (continued)
8
NAME
PIN #
FUNCTION
DVDD2
52
Supply
1.8V digital supply (for MCLK oscillator)
DESCRIPTION
AVSS
53
Ground
Analog ground
AVDD
54
Supply
3.3V analog supply
AVSS
55
Ground
Analog ground
DVDD
56
Supply
1.8V digital supply
IOVDD
57
Supply
3.3V digital I/O supply
DVSS
58
Ground
Digital ground
IOVSS
59
Ground
Digital I/O ground
BB_WS
60
Output
Secondary baseband word select
BB_BCK
61
Output
Secondary baseband word bit clock
BB_IDAT0
62
Output
Secondary baseband channel 0 output (I)
BB_QDAT0
63
Output
Secondary baseband channel 0 output (Q)
BB_IDAT1
64
Output
Secondary baseband channel 1 output (I)
BB_QDAT1
65
Output
Secondary baseband channel 1 output (Q)
GRSTN
66
Input
Global reset (active low)
WAKEUP
67
Output
WAKEUP interrupt output
IRQ0
68
Output
Interrupt output 0
IRQ1
69
Output
Interrupt output 1
IRQ2
70
Output
Interrupt output 2
PWD
71
Input
Power-down pin (active high)
RSTN
72
Input
Reset pin (active low)
N/C
73
Open
No connect
N/C
74
Open
No connect
N/C
75
Open
No connect
N/C
76
Open
No connect
N/C
77
Open
No connect
N/C
78
Open
No connect
N/C
79
Open
No connect
N/C
80
Open
No connect
N/C
81
Open
No connect
N/C
82
Open
No connect
DVSS
83
Ground
Digital ground
DVDD
84
Supply
1.8V digital supply
IOVSS
85
Ground
Digital I/O ground
IOVDD
86
Supply
3.3V digital I/O supply
IF_DFSO
87
Output
IF interface frame sync
IF_DCLK
88
Output
IF interface bit clock
IF_DOUT3
89
Output
IF interface data out 3
DVSS
90
Ground
Digital ground
DVDD
91
Supply
1.8V digital supply
IF_DOUT2
92
Output
IF interface data out 2
IF_DOUT1
93
Output
IF interface data out 1
IF_DOUT0
94
Output
IF interface data out 0
IOVSS
95
Ground
Digital I/O ground
IOVDD
96
Supply
3.3V digital I/O supply
CSN/A1
97
Input
SPI chip select (active low) (I2C address bit 1)
MOSI/A0
98
Input
SPI data in (I2C address bit 0)
MISO/SDA
99
Bidirectional
SCK/SCL
100
Input
SPI clock (I2C SCL)
CTRL_MODE
101
Input
Control interface mode select (SPI = 0, I2C = 1)
REG_ENBN
102
Input
Enable onboard DVDD regulator (active low)
SPI data out (I2C SDA)
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TERMINAL FUNCTIONS (continued)
NAME
PIN #
FUNCTION
DVSS
103
Ground
Digital ground
DESCRIPTION
1.8V digital supply
DVDD
104
Supply
GPIO7
105
Bidirectional
GPIO 7
GPIO6
106
Bidirectional
GPIO 6
GPIO5
107
Bidirectional
GPIO 5
N/C
108
Open
GPIO4
109
Bidirectional
No connect
GPIO 4
GPIO3
110
Bidirectional
GPIO 3
GPIO2
111
Bidirectional
GPIO 2
GPIO1
112
Bidirectional
GPIO 1
GPIO0
113
Bidirectional
GPIO 0
GPIO11
114
Bidirectional
GPIO 11
GPIO10
115
Bidirectional
GPIO 10
GPIO9
116
Bidirectional
GPIO 9
GPIO8
117
Bidirectional
GPIO 8
DVSS
118
Ground/input
Digital ground/Test1
DVSS
119
Ground/input
Digital ground/Test0
IOVSS
120
Ground
Digital I/O ground
DVSS
121
Ground
Digital ground
IOVDD
122
Supply
3.3V digital I/O supply
DVDD
123
Supply
1.8V digital supply
AVSS
124
Ground
Analog ground
AVDD
125
Supply
3.3V analog supply
AVSS
126
Ground
Analog ground
DVDD
127
Supply
1.8V digital supply (for RTC oscillator)
RTCO
128
Output
RTC oscillator output
RTCI
129
Input
DVSS
130
Ground
Digital ground (for RTC oscillator)
AVSS
131
Ground
Analog ground
RTC_REF
132
Output
RTC output
RTC_REFN
133
Output
Inverted RTC output
AVDD
134
Supply
3.3V analog supply
AVSS
135
Ground
Analog ground
SCL0
136
Output
Channel 0 tuner I2C clock
SDA0
137
Bidirectional
Channel 0 tuner I2C data
N/C
138
Open
No connect
N/C
139
Open
No connect
N/C
140
Open
No connect
AVDD
141
Supply
3.3V analog supply
AVDD
142
Supply
3.3V analog supply
AVDD
143
Supply
3.3V analog supply
AVDD
144
Supply
3.3V analog supply
AVSS
—
Analog ground
RTC oscillator input
Center pad
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55TIMING DIAGRAMS
DCLK
DFSO
IA[15]
DOUTx
IA[14]
IA[13]
IA[12]
tD2
tD1
Figure 1. Output Data Interface Timing
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DCLK to DFSO delay
tD1
–2.9
3.7
ns
DCLK to DOUTx delay
tD2
–3.1
3.8
ns
PRIMARY DATA INTERFACE TIMING
BCLK
WS
IA[15]
DOUTx
tD1
IA[14]
IA[13]
IA[12]
tD2
Figure 2. Output Data Interface Timing
MAX
UNITS
BCLK to WS delay
PARAMETER
tD1
CONDITIONS
–2.9
MIN
TYP
3.7
ns
BCLK to DOUTx delay
tD2
–3.1
3.8
ns
SECONDARY DATA INTERFACE TIMING
SCK
CS
MOSI
MISO
tL
tSU3
tH3
tT
tD4
tI
Figure 3. SPI Control Interface Timing
PARAMETER
CONDITIONS
MIN
Maximum SCK frequency
TYP
MAX
UNITS
20
MHz
CS lead time
tL
Trailing CS to leading SCK
5.0
ns
CS trail time
tT
Trailing SCK to leading CS
5.0
ns
CS idle time
tI
Leading CS to trailing CS
5.0
ns
ns
MOSI to SCK setup time
tSU3
5.0
MOSI to SCK hold time
tH3
1.0
SCK to MISO delay
tD4
1.0
10
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ns
10.4
ns
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I2C BUS INTERFACE TIMING
SDA
VIH
VIL
SCK
tSTART
tLOW
tBUF
tHD_DAT
tSU_DAT
tHIGH
tSTOP
Figure 4. I2C Bus Interface Timing
PARAMETER
MIN
SCK clock frequency
0
Input voltage, low
VIL
Input voltage, high
VIH
Setup time for START or repeated START
condition
TYP
MAX
UNITS
400
kHz
0.3 × VDD
V
0.7 × VDD
V
tSTART
0.6
µs
tSTOP
0.6
µs
LOW period of SCK clock
tLOW
1.3
µs
HIGH period of SCK clock
tHIGH
0.6
µs
Setup time for STOP condition
Data hold time from SCK falling
tHD_DAT
Data setup time to SCK rising
tSU_DAT
Bus free time between a STOP and START
condition
(1)
tBUF
100
(1)
250
100 (1)
250
4.7
ns
ns
µs
Valid when MCLK > 20MHz; otherwise is 250ns.
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DETAILED DESCRIPTION
RESET PINS
External 1.8V Core Supply
The AFE8221 has two active-low reset pins, GRST
and RST. When GRST is brought low, all registers on
the chip are brought to default values (0, unless
otherwise specified). When RST is brought low, all
registers are brought to default values except for:
• Real-time clock registers (counters and alarms)
• Registers to configure the WAKEUP interrupt
• Registers controlling the GPIO pins
These registers are left in the previously programmed
states.
If an external 1.8V supply is used, all DVDD pins
should be connected to the +1.8V supply and
appropriately bypassed with 0.1µF and 0.01µF
capacitors. DVDD1 and DVDD2 pins may also be
connected directly to the +1.8V supply or may be
optionally connected through a small (1Ω–10Ω)
series resistor to reduce supply noise coupling into
the MCLK oscillator (powered through DVDD1) or the
RTC oscillator (powered through DVDD2).
ANALOG SUPPLY CONNECTIONS
A clean +3.3V analog supply should be connected to
all AVDD pins (37–40, 45, 54, 125, 134, and
141–144). Limited decoupling is required on the
AVDD pins; a 0.1µF capacitor near pins 45 and 54
and another capacitor near pins 125 and 134 should
suffice.
The AFE8221 contains an internal analog switch that
is used to disconnect power from the major analog
blocks when the PWD pin is high. When the PWD pin
is low, the AVDD1 pins (8, 12, 13, 23, 24, and 34) are
internally connected to the AVDD pins (37–40 and
141–144). Since the AVDD1 pins are actually the
active supply pins for the IF ADC and other analog
components, the AVDD1 pins should be heavily
bypassed with a minimum of parallel 0.1µF and
0.01µF ceramic capacitors at each pin (or pin pair).
DIGITAL SUPPLY CONNECTIONS
The digital supply connections depend on whether
the onboard regulators are used to generate the 1.8V
digital core voltage (REG_ENB low); or if the digital
core voltage comes from a system-level supply
(REG_ENB high). In either case, all IOVDD pins
should be connected to the +3.3V IO supply and
appropriately bypassed. If the internal regulators are
used, this supply also sources the current drawn by
the digital core.
12
When using an external supply, the PWD pin disables
the MCLK oscillator when high, shutting off the clock
to most of the digital core. As long as the external
+1.8V supply is maintained, all register settings in the
digital core are maintained when PWD is high.
Internal 1.8V Regulator
If the internal 1.8V regulator is used, then 0.1µF and
0.01µF decoupling capacitors should still be put at
the DVDD, DVDD1, and DVDD2 pins. DVDD1 should
still be connected to the DVDD either directly or
through a small series resistor. DVDD2 must be
isolated from DVDD and DVDD1.
While using the internal regulators, the MCLK
oscillator and the internal regulators are disabled
when the PWD pin is high. This condition causes
most of the register settings to be lost, except for the
registers associated with the real-time clock, GPIO,
and WAKEUP interrupt. For this reason, the RST pin
should be brought low prior to bringing the PWD pin
low (to come out of power-down). The RST pin
should be held low for at least 10ms after PWD goes
low to allow the internal regulators to stabilize.
Note that the internal regulators are linear regulators,
and therefore are relatively inefficient. Power
dissipation as a result of the digital core almost
doubles when the internal regulators are used (same
core current, but drawn from a 3.3V supply instead of
a 1.8V supply). Whenever possible, the use of a more
efficient external switching regulator is encouraged in
order to minimize overall system power as well as to
reduce the thermal stress on the AFE8221.
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CONTROL INTERFACE
Configuration and control data are written to the
AFE8221 via the control interface. The control
interface supports two protocols, SPI and I2C. If the
CTRL_MODE pin is tied low, then an SPI interface is
implemented. If CTRL_MODE is tied high, then an
I2C protocol-compatible interface is implemented.
SPI Interface
The SPI interface consists of four signals: a serial
clock (SCK), an active-low chip select (CS), a serial
data input (MOSI—master out, slave in), and a serial
data output (MISO—master in, slave out). Data are
transferred in groups of 32 bits. The first 16 bits are
the instruction, which indicates:
1. If data are to be written or to be read;
2. If the data target is a register or RAM; and
3. The address of the data target.
The second 16 bits are the data transfer, which is
input on MOSI for a write cycle or output on MISO for
a read cycle.
Figure 5 shows an SPI write cycle. The cycle is
initiated by the high-to-low transition of the CS line.
32 SCK pulses clock the instruction and the data into
the MOSI line. Data are clocked in MSB first. The first
16 bits are the instruction. There are two possible
write cycle instructions: register write and memory
write. The formats for these instructions are shown in
Figure 6 and Figure 7, respectively.
The only information required for a register write is
the seven-bit register address (REG_ADDR). For a
memory write, both the five-bit memory select (MEM)
plus the six-bit memory address (MEM_ADDR) are
required.
Following the 16-bit instruction, the 16-bit data word
is clocked in, again MSB first. At the end of the write
cycle, this data word is written to the appropriate
register or memory location in the AFE8221.
SCK
CS
MOSI
MISO
INSTRUCTION
DATA
NOTE: To terminate a Write/Read cycle, CS must be brought high.
Figure 5. SPI Control Interface Write Cycle
1
0
0
15
14
13
REG_ADDR
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
Figure 6. Register Write Instruction Format
1
0
1
15
14
13
MEM_ADDR
MEM
12
11
10
9
8
7
6
5
4
3
2
Figure 7. Memory Write Instruction Format
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Figure 8 shows the SPI interface read cycle. It is
similar to the write cycle, except that instead of the
data word being clocked into MOSI during the second
half of the cycle, the data word is clocked out of
MISO. Note that only register reads are permitted;
RAM reads cannot be read back.
For reading and writing, data block transfers are
supported. For a block transfer, multiple data words
are transmitted following the memory read or write
instruction. The data words are read from or written
sequentially starting at the address contained in the
instruction. The sequential access terminates when
the CS line goes high. Figure 9 shows a register
block read cycle. In the illustration, three succeeding
register locations are read starting at address N. The
block write cycle is similar except, of course, data are
clocked into MOSI.
In all cases, the control interface is reset when CS
goes high. If the final SCK is not received before CS
goes high, then the cycle ends prematurely. For a
read cycle, data transfer terminates; for a write cycle,
no data are written to either a register or to memory.
I2C Slave Interface
The AFE8221 control interface can be configured to
provide I2C slave operation. It has a 10-bit slave
address of 00010010AB and complies with the Philips
I2C specification. Note that address bits A and B are
determined by the state of the I2C address pins A1
and A0. The mapping of SPI pins to I2C pins is shown
in Table 1.
Table 1. SPI/I2C Pin Mapping
CTRL_MODE = 1 (I2C)
CTRL_MODE = 0 (SPI)
2
Chip select (CS)
I C address bit (A1)
Master out slave in (MOSI)
I2C address bit (A0)
Master in slave out (MISO)
Serial data line (SDA)
SPI clock (SCK)
Serial clock line (SCL)
The AFE8221 I2C interface supports both fast mode
(400K bits/sec) and standard mode (100K bits/sec)
operation. However, if the master crystal frequency is
less than 20MHz, then only standard mode is
supported.
SCK
CS
MOSI
MISO
INSTRUCTION
DATA
Figure 8. SPI Control Interface Read Cycle
SCK
CS
MOSI
MISO
INSTRUCTION
DATA[N]
DATA[N+1]
DATA[N+2]
Figure 9. SPI Control Interface Block Read Cycle
14
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As a reference, a typical data transfer on the I2C bus
is described in Figure 10. Each data byte is eight bits
long and must be followed by an Acknowledge bit.
Start and stop conditions are defined as a transition
of the SDA signal with SCL high. A pulse of the SCL
clock signal indicates the transfer of data or an
Acknowledge bit on the SDA pin. The transmitting
device drives SDA data during clock periods 1–8. The
receiving device acknowledges by driving SDA low
during clock 9. Master devices always generate the
SCL clock and initiate transactions. Refer to the
Philips I2C Bus Specification for further details.
required, further pairs of bytes may be used as part
of a block transfer. After the final pair of write data
bytes, an I2C stop condition must be provided to
terminate the transaction. Figure 12 illustrates a block
write transfer of N 16-bit data words. Gray areas
denote slave-driven SDA cycles; white areas are
master-driven.
I2C Read Operation
Read operations require a start condition followed by
two bytes describing both a 10-bit address format and
the AFE8221 10-bit slave address. The next two
bytes must contain the 16-bit instruction word format,
as illustrated in Figure 11. A repeated start followed
by the first byte of the slave address is then required
to create a combined transaction. Note that the R/W
bit is set to '1' (read), indicating that subsequent bytes
are to be read from the slave. The AFE8221 presents
addressed 16-bit data words in 8-bit pairs until a
NACK (N) is provided by the master. After the final
pair of read data bytes, an I2C stop condition must be
provided to terminate the transaction. Figure 13
illustrates a block read transfer of N 16-bit data
words. Gray areas denote slave-driven SDA cycles;
white areas are master-driven.
The AFE8221 has 16-bit internal registers and
operates on 16-bit instructions. Because the I2C
interface is inherently an 8-bit interface, special
formats are required to send instructions and data
between an I2C Master and the AFE8221. The I2C
Write Operation and I2C Read Operation sections
describe these formats in detail.
I2C Write Operation
Write operations require a start condition followed by
two bytes describing both a 10-bit address format and
the AFE8221 10-bit slave address. The next two
bytes must contain the 16-bit instruction word format
described previously in Figure 6 or Figure 7,
depending on the internal resource being addressed.
Finally, a pair of bytes containing the 16-bit write data
must be provided. If additional 16-bit writes are
SDA
SCL
MSB
1
S
LSB ACK
LSB R/W ACK MSB
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
START
CONDITION
P
STOP
CONDITION
Figure 10. Example Data Transfer on the I2C Bus
0
1
0
15
14
13
REG_ADDR
12
11
10
9
8
7
6
5
4
3
2
1
0
Figure 11. Register Read Instruction Format
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‘0’ Indicates Following Bytes
are Written to Slave
2
I C Reserved Combination
Indicating 10-Bit Addressing is
in Use
10-Bit Slave Address
Write
Start
S
1
1
1
1
0
0
0
Slave Address 1st 7 Bits
0
Slave
ACK
R/W
A
0
1
0
0
1
0
A
Slave Address 2nd Byte
Slave
ACK
Bits 15-8 of Instruction
A
A
Bits 7-0 of Instruction
A
A
A
Slave
ACK
Bits 7-0 of First 16-Bit Data Word
Slave
ACK
Bits 15-8 of Second 16-Bit Data Word
Slave
ACK
Slave
ACK
Slave
ACK
Bits 15-8 of First 16-Bit Data Word
B
A
Slave
ACK
Bits 7-0 of Second 16-Bit Data Word
A
¼
Slave
ACK
Bits 15-8 of Nth 16-Bit Data Word
A
Slave
ACK Stop
Bits 7-0 of Nth 16-Bit Data Word
A
P
Figure 12. Example I2C Write Operation
16
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‘0’ Indicates Following Bytes
are Written to Slave
2
I C Reserved Combination
Indicating 10-Bit Addressing is
in Use
10-Bit Slave Address
Write
Start
1
S
1
1
1
0
0
0
Slave Address 1st 7 Bits
0
Slave
ACK
R/W
A
0
1
0
0
1
0
A
Slave Address 2nd Byte
Slave
ACK
Bits 15-8 of Instruction
A
B
Slave
ACK
A
Slave
ACK
Bits 7-0 of Instruction
A
2
I C Reserved Combination
Bits 9 and 8 of the 10-Bit
Indicating 10-Bit Addressing is Slave Address
‘1’ Indicates Following Bytes
in Use
are Read from Slave
Read
Repeated
Slave
1
1
1
0
0
0
1 ACK
Start 1
Sr
Slave Address 1st 7 Bits
R/W
A
Master
ACK
Bits 15-8 of First 16-Bit Data Word
A
Master
ACK
Bits 7-0 of First 16-Bit Data Word
Master
ACK
Bits 15-8 of Second 16-Bit Data Word
A
A
Master
ACK
Bits 7-0 of Second 16-Bit Data Word
A
¼
Master
ACK
Bits 15-8 of Nth 16-Bit Data Word
A
Bits 7-0 of Nth 16-Bit Data Word
Master
NACK
Stop
N
P
Figure 13. Example I2C Read Operation
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IF ANALOG-TO-DIGITAL CONVERTERS
(IF_ADC0 AND IF_ADC1)
within the ADC core). In low-power mode, both
ifadc_en[0] and ifadc_en[1] are low. In this case, all
IF ADC circuits are in the minimum bias mode. Note
that to reach a true sleep mode, the analog supply to
the IF ADC block must be turned off.
IF_ADC0 and IF_ADC1 are 12-bit pipeline ADCs that
are used to sample the output of the tuner(s).
Figure 14 shows recommended connections for the
IF ADCs.
When ifadc_gain0 is low, IF_ADC0 is in its normal 1x
gain operating state. If ifadc_gain0 is high, then the
gain of IF_ADC0 is changed to 2x. In a similar
fashion, ifadc_gain1 controls the gain of IF_ADC1.
Table 2 shows the ifadc_en and ifadc_gain control
variable parameters.
The IF ADCs have three power modes controlled by
ifadc_en[0] and ifadc_en[1]. Full-power mode occurs
when both ifadc_en[0] and ifadc_en[1] are high. In
this case, both ADCs are biased to the highest levels
and are ready to operate. If only ifadc_en[0] or
ifadc_en[1] is high, then the converters are operating
in reduced-power mode, where the enabled ADC is
fully biased and ready to operate while the second
ADC is in a low (but not zero) bias state (a minimum
bias current is necessary to maintain safe voltages
13W
17
IFP
Table 2. IF_ADC Control Register Settings
ADDRESS
BITS
ifadc_en[0]
PARAMETER
1
0
ifadc_en[1]
1
1
ifadc_gain0
1
2
ifadc_gain1
1
3
IF_INP0
12pF
TUNER_0
13W
18
IFM
IF_INM0
VCM
AFE8221
13W
30
IFP
IF_INP1
12pF
TUNER_1
13W
IFM
29
19
VCM
IF_INM1
IF_VCM
IF_REFP
1mF
0.1mF
IF_REFM
20
IF_BIAS
21
27
0.1mF
56kW
0.01mF
0.01mF
0.1mF
0.1mF
1mF
0.1mF
Figure 14. IF ADC Connections
18
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Table 4. DDC Control Register Settings
IF ADC ALARM/ATTENUATOR
The output of each IF ADC is monitored to ensure
that the full-scale input range is not exceeded. If an
ADC over-range condition occurs, an overflow signal
is generated that may be used to generate an
interrupt on the IRQ line, depending on the settings in
the IRQ interrupt generator.
In addition, programmable limits may be set for each
IF ADC. If the absolute value of IF_ADC0 exceeds
if_adc_limit0 or the absolute value of IF_ADC1
exceeds ifadc_limit1, then an interrupt may be
generated on IRQ again depending on the settings in
the IRQ interrupt generator.
In the case of an IF ADC event, the IRQ status
register can be read back to determine the type of
event and on which ADC channel it occurred. The
IRQ status register can be polled to determine if an IF
ADC event has occurred in the case where IF ADC
events are masked from generating an interrupt.
The control variable ddc0_atten causes an
attenuation of the IF_ADC0 output prior to the DDC.
The attenuation ranges in 3dB steps from 0dB (for
ddc0_atten = 0) to –18dB (for ddc0_atten = 6).
ddc1_atten has the same effect on the output of
IF_ADC1.
In order to better synchronize the IF ADC attenuator
with the tuner automatic gain control (AGC), a delay
may be programmed between when a new value of
ddc_atten is written and when it takes effect. When a
new value of ddc0_atten is written, a counter (driven
by MCLK) is initialized to ddc0_delay. When the
counter reaches zero, the actual attenuation change
occurs. Likewise, ddc1_delay affects ddc1_atten.
Note that if a new ddc0_atten is written before the
delay counter has reached zero from the previous
write, the previous write is discarded. Table 3 shows
the attenuator, delay, and limit control variables.
Table 3. IF ADC Control Register Settings
PARAMETER
ADDRESS
BITS
ddc0_atten
3
2:0
ddc1_atten
15
2:0
ddc0_delay
4
15:0
ddc1_delay
16
15:0
ifadc_limit0
46
11:0
ifadc_limit1
47
11:0
PARAMETER
ADDRESS
BITS
ddc0_cic_dec_rate
9
8:0
ddc0_cic_scale
10
11:6
ddc0_cic_shift
10
5:0
ddc0_demod_freq[31:16]
5
15:0
ddc0_demod_freq[15:0]
6
15:0
ddc0_demod_phase[31:16]
7
15:0
ddc0_demod_phase[15:0]
8
15:0
ddc0_fir1_base_address
11
13:8
ddc0_fir1_mode
11
1:0
ddc0_fir1_ncoeffs
11
7:2
ddc0_fir1_nodec
14
9
ddc0_fir2_nodec
14
10
ddc0_fir2a_base_address
12
15:9
ddc0_fir2a_mode
12
1:0
ddc0_fir2a_ncoeffs
12
8:2
ddc0_fir2a_shift
14
3:0
ddc0_fir2b_base_address
13
15:9
ddc0_fir2b_mode
13
1:0
ddc0_fir2b_ncoeffs
13
8:2
ddc0_fir2b_shift
14
7:4
ddc0_interleave
14
8
ddc_en[0]
1
4
ddc_sync
1
6
QUADRATURE MIXER/NCO
The NCO frequency and initial phase are set by the
32-bit unsigned variables ddc0_demod_freq and
ddc0_demod_phase. The I and Q outputs of the
mixer can be calculated by Equation 1 and
Equation 2.
I = ADC ´ cos(2pft + f)
(1)
Q = ADC ´ sin(2pft + f)
(2)
where ADC is the output of the IF analog-to-digital
converter, f is the NCO phase offset (in radians)
given by Equation 3, and φ is the NCO phase offset
(in radians) given by Equation 4.
ddc0_demod_freq
f = fMCLK
32
2
(3)
ddc0_demod_phase
f = 2p
32
2
(4)
DIGITAL DOWNCONVERTER 0 (DDC0)
DDC0 operation is controlled by ddc_en[0]. When
ddc_en[0] is '1', operation of DDC0 is enabled. If
ddc_en[0] is '0', operation of DDC0 is disabled.
Table 4 shows the DDC0 operation control settings.
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The ddc_sync signal can be used to control the
phase of the mixer. While the ddc_sync signal is high,
the phase accumulator is held to a constant value
ddc0_demod_phase, essentially holding it to 0 in
Equation 1 and Equation 2. When the ddc_sync
signal is brought low, the phase accumulator is
incremented by the value ddc0_demod_freq once per
MCLK cycle.
CIC FILTER
The first stage of decimation filtering is provided by a
fifth-order CIC filter. The operation of the CIC filter is
controlled
by
the
unsigned
variables
ddc0_cic_dec_rate,
ddc0_cic_scale,
and
ddc0_cic_shift.
The
valid
range
for
ddc0_cic_dec_rate is from 4 to 256.
The inherent dc gain of the CIC filter is
ddc0_cic_dec_rate.
The
control
variables
ddc0_cic_shift and ddc0_cic_scale are used to
reduce this very high gain before the signal is output
to the next stage of the decimation filter. The
combined
effect
of
ddc0_cic_dec_rate,
ddc0_cic_shift, and ddc0_cic_scale produces an
overall dc gain for the CIC filter of Equation 5.
multiple filter responses may be stored in the memory
bank. The filter response may be changed simply by
updating the control register with new values for
ddc0_fir1_mode,
ddc0_fir1_ncoeff,
and
ddc0_fir1_base_addr.
ddc0_fir1_ncoeff defines the number of unique filter
coefficients that make up the filter response.
ddc0_fir1_base_addr defines the memory location
where the first filter coefficient is stored. The actual
filter length is a function of the ddc0_fir1_mode and
ddc0_fir1_ncoeff, as shown in Equation 6:
Filter Length = 2 ´ (ddc0_fir1_ncoeff - 1) + 1 for ODD
Filter Length = 2 ´ ddc0_fir1_ncoeff for EVEN
Filter Length = 4 ´ (ddc0_fir1_ncoeff - 1) + 1 for HALFBAND
Filter Length = ddc0_fir1_ncoeff for ARBITRARY
(6)
The maximum filter length that can be realized is
limited by two factors. First, the number of clock
cycles between successive filter outputs limits the
number of coefficients that can be processed, as
shown in Equation 7.
ddc0_fir1_ncoeff £ 2 ´ ddc0_cic_dec_rate
GAIN = ddc0_cic_dec_rate
5
ddc0_cic_scale/32
2ddc0_cic_shift
(5)
In general, ddc0_cic_shift and ddc0_cic_scale should
be chosen to make GAIN as close to 1 as possible.
For example, if ddc0_cic_dec_rate is 20, setting
ddc0_cic_shift to 22 and ddc0_cic_scale to 41 results
in a GAIN of 0.9775.
FIRST FIR FILTER
The block following the CIC filter is a decimate-by-two
finite impulse response (FIR) filter with programmable
coefficients. ddc0_fir1_mode sets the type of filter
response—ODD (MODE = 00: symmetric impulse
response, odd number of taps), EVEN (MODE = 01:
symmetric impulse response, even number of taps),
HALFBAND (MODE = 10), and ARBITRARY (MODE
= 11: non-symmetric impulse response).
(7)
where ddc0_cic_dec_rate is the decimation ration of
the CIC filter.
Second, the size of the data memory (which stores
incoming data samples) limits filter length to 62 taps.
Note that two data memory locations are required to
filter processing.
The dc gain of the FIR filter depends on the
coefficient values and the filter mode. For ODD mode
and HALFBAND mode, the dc gain is given by
Equation 8:
hNCOEFF +
GAIN =
NCOEFF - 1
å
n=1
15
2 -1
th
where hn is the n
stored in memory.
2hn
(8)
of NCOEFF filter coefficients
The 16-bit wide filter coefficients are stored in
memory bank 0. Up to 64 coefficients can be stored
in this memory. Depending on the types of filters
desired and the number of taps, coefficients for
20
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For EVEN mode the, dc gain is shown by Equation 9:
NCOEFF
GAIN =
å 2hn
n=1
15
2 -1
(9)
while for ARBITRARY mode the gain is shown by
Equation 10:
NCOEFF
å hn
GAIN =
n=1
15
2 -1
(10)
SECOND FIR FILTERS
The first FIR filter is followed by two parallel second
FIR filters, FIR2A and FIR2B. Duplicate filters allow
the output of two I and Q output streams with
different bandwidths. For example, the bandwidth of
FIR2A may be set wide to accommodate reception of
digital broadcasts, while FIR2B may be set narrower
to receive an analog broadcast sharing the same
band. Coefficients for FIR2A are stored in memory
bank 1 (MEM = 1) and coefficients for FIR2B are
stored in memory bank 2 (MEM = 2).
The operation of the second FIR filter is similar to the
first FIR filter with several notable exceptions. First,
the depths of the coefficient and data memories are
doubled to 128. This size increase allows for filters up
to 126 taps to be realized without running out of data
memory. It also allows longer sets of filter coefficients
to be stored in coefficient memory.
Second, because of the additional decimation by two
from the first FIR filter, twice as many MCLK cycles
are available to process coefficients, increasing the
maximum allowable value of NCOEFF, as shown in
Equation 11 and Equation 12.
ddc0_fir2a_ncoeff £ 4 ´ ddc0_cic_dec_rate
(11)
ddc0_fir2b_ncoeff £ 4 ´ ddc0_cic_dec_rate
(12)
weights must add up to (215 – 1) to achieve unity
gain through the filter. With longer filters (and
therefore, smaller coefficients), frequency response
errors may be introduced as a result of coefficient
truncation. A Shift parameter has been added to the
second FIR filter to alleviate this problem. The total of
all filter tap weights must add up to (215+ddc0_fir2a_shift
– 1) to achieve unity gain through FIR2A (similarly for
ddc0_fir2b_shift and FIR2B). Note that shift values for
FIR2A and FIR2B can be set separately.
Extended-Length Filter Mode
If FIR2A or FIR2B cannot provide enough filter taps
to achieve the desired frequency response, setting
control bit ddc0_interleave puts the two filters into an
interleaved mode that doubles the length of the filter
that can be realized. However, there are several
limitations:
1. Only odd symmetrical filters may be realized;
2. The filter length M must be such that (M + 1)/4 is
an integer; and
3. Only one filter can be realized (in ddc_interleave
mode the A and B outputs are identical: IB = IA
and QB = QA).
In addition to setting the ddc0_interleave bit, FIR2A
must be set to EVEN mode and FIR2A must be set to
ODD mode. ddc0_fir2a_ncoeff and ddc0_fir2b_ncoeff
are both set to (M + 1)/4. ddc0_fir2a_shift and
ddc0_fir2b_shift should be identical. There are no
restrictions
on
ddc0_fir2a_base_addr
or
ddc0_fir2b_base_addr.
The M-tap filter has (M + 1)/2 unique coefficients. The
first, third, fifth, etc. coefficients are loaded into the
FIR2A coefficient memory; the second, fourth, sixth,
etc. coefficients are loaded into the FIR2B memory.
The center coefficients of the filter end up as the last
coefficient loaded into FIR2B.
Third, in the first FIR filter the total of all the filter tap
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FIR Filter Transfer Functions
Equation 13 to Equation 21 show transfer functions and dc gain for the various filter modes. Generic names for
the control variables are used; just substitute the appropriate variable (that is, ddc0_fir2a_ncoeff for NCOEFF) as
necessary. Also, note that SHIFT has a value of 0 for FIR1.
Basic Filter Modes:
NCOEFF - 1
HEVEN(z) =
å
n=0
NCOEFF - 2
HODD(z) =
-n
-n
NCOEFF - 2
å
n=0
-2n
COEFFBASE_ADDR + n ´ (z
NCOEFF - 1
HARBITRARY(z) =
-(2 ´ NCOEFF - 2 - n)
COEFFBASE_ADDR + n ´ (z + z
å
n=0
HHALFBAND(z) =
-(2 ´ NCOEFF - 1 - n)
COEFFBASE_ADDR + n ´ (z + z
å
n=0
(13)
) + COEFFBASE_ADDR + NCOEFF - 1 ´ z
-(4 ´ NCOEFF - 6 - 2n)
+z
NCOEFF - 1
(14)
2 ´ NCOEFF - 3
) + COEFFBASE_ADDR + NCOEFF - 1 ´ z
COEFFBASE_ADDR + n ´ z
(15)
-n
2´
GAINEVEN(z) = 2
)
(16)
NCOEFF - 1
COEFFBASE_ADDR + n
å
n=0
-SHIFT
´
15
2 -1
2´
GAINODD = GAINHALFBAND = 2
å
n=0
-SHIFT
COEFFBASE_ADDR + n + COEFFBASE_ADDR + NCOEFF - 1
´
15
2 -1
NCOEFF - 1
å
GAINARBITRARY(z) = 2
(17)
NCOEFF - 2
n=0
-SHIFT
(18)
COEFFBASE_ADDR + n
´
15
2 -1
(19)
Extended-Length Filter Mode:
NCOEFF - 1
å
HEXTENDED(z) = 2
-2 ´ n
COEFF_ABASE_ADDR_A + n ´ (z
n=0
NCOEFF - 2
-SHIFT
+
´
COEFF_BBASE_ADDR_B + n ´ (z
å
n=0
+ COEFF_BBASE_ADDR_B + NCOEFF - 1 ´ z
-2 ´ (2 ´ NCOEFF - 1 - n)
+z
-2 ´ n + 1
)
-2 ´ (2 ´ NCOEFF - 2 - n) + 1
+z
)
2 ´ NCOEFF
(20)
NCOEFF - 1
2´
GAINEXTENDED =
2
-SHIFT
´
15
2 -1
å
COEFF_ABASE_ADDR_A + n
n=0
NCOEFF - 2
+2´
å
n=0
COEFF_BBASE_ADDR_B + n
+ COEFF_BBASE_ADDR_B + NCOEFF - 1
22
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DIGITAL DOWNCONVERTER 1 (DDC1)
The description of DDC1 is identical to the description
of DDC0, with the following exceptions:
1. DDC1 is enabled by ddc_en[1].
2. Control variables are prefixed with ddc1 instead
of ddc0.
3. FIR coefficients are stored in memory banks 3, 4,
and 5 instead of 0, 1, and 2.
Table 5. IF Control Register Settings
ADDRESS
BITS
ddc1_cic_dec_rate
21
8:0
ddc1_cic_scale
22
11:6
ddc1_cic_shift
22
5:0
ddc1_demod_freq[31:16]
17
15:0
Table 5 shows the DDC1 operation control settings.
ddc1_demod_freq[15:0]
18
15:0
ddc1_demod_phase[31:16]
19
15:0
PRIMARY IF DATA INTERFACE
ddc1_demod_phase[15:0]
20
15:0
ddc1_fir1_base_address
23
13:8
ddc1_fir1_mode
23
1:0
ddc1_fir1_ncoeffs
23
7:2
ddc1_fir1_nodec
26
9
ddc1_fir2_nodec
26
10
ddc1_fir2a_base_address
24
15:9
ddc1_fir2a_mode
24
1:0
ddc1_fir2a_ncoeffs
24
8:2
ddc1_fir2a_shift
26
3:0
ddc1_fir2b_base_address
25
15:9
ddc1_fir2b_mode
25
1:0
ddc1_fir2b_ncoeffs
25
8:2
ddc1_fir2b_shift
26
7:4
ddc1_interleave
26
8
ddc_en[1]
1
5
ddc_sync
1
6
The two DDCs produce a total of eight 16-bit output
values (I and Q from each of four final-stage FIR
filters). The IF data interface time-multiplexes these
eight values onto four serial lines. The IF data
interface also generates the necessary clock and
frame sync signals to complete the interface to the
DSP. The general timing of the IF data interface is
shown in Figure 15.
Note that each serial line (IF_DOUT0 through
IF_DOUT3) can carry up to four time-multiplexed
16-bit signals. The actual number of signals per line
is limited by:
a. the frequency of IF_DCLK, which can be
programmed to be the same as the IF sampling
clock (MCLK), one-half the IF sampling
frequency, or one-fourth the IF sampling
frequency; and
b. the overall decimation ratio of the DDC that
determines the frequency of IF_DFSO pulses and
therefore the number of IF_DCLK cycles
available to clock out data.
PARAMETER
IF_DCLK
IF_DFSO
IF_DOUT0
A0[15:0]
B0[15:0]
C0[15:0]
D0[15:0]
IF_DOUT1
A1[15:0]
B1[15:0]
C1[15:0]
D1[15:0]
IF_DOUT2
A2[15:0]
B2[15:0]
C2[15:0]
D2[15:0]
IF_DOUT3
A3[15:0]
B3[15:0]
C3[15:0]
D3[15:0]
Figure 15. IF Data General Timing
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Control register variables dout0_config, dout1_config,
dout2_config, and dout3_config, are used to assign
specific output data streams to particular time slots in
the IF interface output frame. Each register is broken
into four 4-bit values, each of which is used to assign
the source for a given time slot according to Table 6.
Table 6. Time Slot Sources
VALUE
SOURCE
0
No source assigned
1
DDC0, FIR2A, I
2
DDC0, FIR2A, Q
3
DDC0, FIR2B, I
4
DDC0, FIR2B, Q
5
DDC1, FIR2A, I
6
DDC1, FIR2A, Q
7
DDC1, FIR2B, I
8
DDC1, FIR2B, Q
dout0_config controls the four time slots of
IF_DOUT0, register 24 controls the four time slots of
IF_DOUT1, and so on. The mapping of register bits
to time slots is summarized in Table 7.
Table 7. Register Bit Mapping
PARAMETER
[15:12]
[11:8]
[7:4]
[3:0]
dout0_config
D0
C0
B0
A0
dout1_config
D1
C1
B1
A1
dout2_config
D2
C2
B2
A2
dout3_config
D3
C3
B3
A3
For example, bits [11:8] of dout2_config set the
source assignment for time slot C2 of IF_DOUT2.
The control variable if_dclk_div sets the frequency of
IF_DCLK, as shown in Equation 22 and Equation 23.
fMCLK
fIF_DCLK =
if_dclk_div > 1
if_dclk_div
(22)
fIF_DCLK = fMCLK
if_dclk_div £ 1
(23)
Normally the data and the frame sync change on the
rising edge of IF_DCLK. If if_dclk_edge is set to '1'
then IF_DCLK is inverted so that data and frame sync
change on the falling edge of IF_DCLK.
The control value if_dfso_select determines which
DDC is responsible for generating IF_DFSO. If
if_dfso_select is '0', then an IF_DFSO pulse is
generated each time a new output is ready from
DDC0. Similarly, if if_dfso_select is '1', then an
24
IF_DFSO pulse is generated each time a new output
is ready from DDC1. If the decimation rates of DDC0
and DDC1 are identical, then it does not matter which
DDC initiates the IF_DFSO pulse. If the decimation
rates are different, then the DDC with the smaller
decimation ratio (higher output rate) should be
chosen to generate the IF_DFSO pulse. Note that in
this case, outputs from the slower DDC are repeated
for multiple frames and it is the responsibility of the
DSP software to compensate. This compensation is
easiest to do if the higher decimation rate is an
integer multiple of the lower decimation rate.
Finally, if_dfso_mode is used to select alternate forms
of frame sync. In the default case (if_dfso_mode = 0),
the frame sync is a high pulse one clock period wide
that occurs the clock cycle before the first data bit of
the serial output. If if_dfso_mode is set to '1', then the
frame sync changes polarity once per frame; again,
one clock cycle before the first data bit of the frame. If
if_dfso_mode is set to 2, then the frame sync
behaves like the default frame sync except that the
sync pulse is 16 clock periods wide. The three frame
sync modes are illustrated in Figure 16 and
Figure 17. Table 8 shows the detailed timing
conditions for Figure 17.
It is recommended that the DSP interface be
configured to sample IF_DFSO and the four
IF_DOUT lines on the trailing edge of IF_DCLK.
Table 9 shows the dout, if_dclk, if_dfso, and if_dout
operation control settings.
Table 8. Detailed Timing Conditions
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNITS
tD1
IF_DCLK0 to
IF_DFS0 delay
TBD
0
TBD
ns
tD2
IF_DCLK0 to
IF_DOUTx delay
TBD
0
TBD
ns
Table 9. Primary IF Control Register Settings
PARAMETER
ADDRESS
BITS
dout_en
1
7
if_dclk_div
31
4:0
if_dclk_edge
31
5
if_dfso_mode
31
8:7
if_dfso_select
31
6
if_dout0_config
27
15:0
if_dout1_config
28
15:0
if_dout2_config
29
15:0
if_dout3_config
30
15:0
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IF_DCLK
IF_DFSO
Mode 0
IF_DFSO
Mode 1
IF_DFSO
Mode 2
IF_DOUT0
A0[15:0]
B0[15:0]
A0[15:0]
B0[15:0]
Figure 16. Frame Sync Modes
IF_DCLK
td1
IF_DFSO
td2
IF_DOUT0
A0[15]
A0[14]
IF_DOUT1
A1[15]
A1[14]
IF_DOUT2
A2[15]
A2[14]
IF_DOUT3
A3[15]
A3[14]
Figure 17. Detailed Timing
ALTERNATE IF DATA INTERFACE
AUXILIARY DACS
The operation and timing of the alternate IF data
interface are identical to the primary IF data interface.
Pin names are changed such that BB_BCK is
equivalent to IF_DCLK; BB_WS is equivalent to
IF_DFSO;` and BB_IOUT0, BB_IOUT1, BB_QOUT0,
and BB_QOUT1 are each equivalent to any
IF_DOUTx pins. The parameter names are also
changed to reflect the different interface pin names.
Table 10 shows the BB operation control settings.
CDAC0 is enabled by a high value set for cdac_en[0].
Similarly, CDAC1 is enabled by a high value set for
cdac_en[1]. A control DAC that is disabled is put into
a low-power state.
Table 10. Alternate IF Control Register Settings
PARAMETER
The control DAC outputs are set by the control
variable cdac0_out for CDAC0 and CDAC1_OUT for
CDAC1. A value of zero generates a '0' output from
the control DAC while a value of 4095 generates a
full-scale output from the control DAC. Table 11
shows the CDAC operation control settings.
Table 11. CDAC Control Register Settings
ADDRESS
BITS
bb_dclk_edge
36
5
bb_dclk_div
36
4:0
cdac_en[0]
1
9
bb_dout0_config
32
15:0
cdac_en[1]
1
10
bb_dout1_config
33
15:0
cdac0_out
37
11:0
bb_dout2_config
34
15:0
cdac1_out
38
11:0
bb_dout3_config
35
15:0
bb_en
1
8
bb_ws_mode
36
10:7
bb_ws_select
36
6
PARAMETER
ADDRESS
BITS
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AUXILIARY ADC
The auxiliary ADC is an 8-bit successive
approximation converter that is intended for
low-speed, low-accuracy tasks such as system
diagnostics. Any one of four input pins can be
connected to the auxiliary ADC. The parameter
aux_adc_sel is used to connect a particular input pin
to the converter. This input multiplexer operates
according to the following sequence:
• aux_adc_sel = 0:
– No aux ADC inputs are connected, all inputs
high impedance
• aux_adc_sel = 1:
– AUX_ADC0 pin connected to aux ADC
• aux_adc_sel = 2:
– AUX_ADC1 pin connected to aux ADC
• aux_adc_sel = 3:
– AUX_ADC2 pin connected to aux ADC
• aux_adc_sel = 4:
– AUX_ADC3 pin connected to aux ADC
A conversion in initiated by writing to register 39 with
bit 15 (aux_adc_trig) high. The conversion time is
8704 MCLK cycles. At the end of the conversion
auc_adc_done goes high and the result is returned in
aux_adc_out. As an alternative to polling
aux_adc_done, the AFE8221 can be configured to
generate an interrupt when an auxiliary ADC
conversion is completed. Table 12 shows the
aux_adc operation control settings.
Table 12. AUX_ADC Control Register Settings
PARAMETER
ADDRESS
BITS
aux_adc_done
39
15
aux_adc_out
39
7:0
aux_adc_sel
39
11:8
aux_adc_trig
39
15
MASTER CLOCK OSCILLATOR
The master clock oscillator supports third-overtone
designs from 55MHz to 75MHz. It can also support
fundamental operations in the 20MHz to 30MHz
range. The recommended third-overtone circuit for
third-overtone operation is shown in Figure 18 and
Table 13.
26
51
MCLKO
L1
Crystal
50
MCLKI
R1
AFE8221
1nF
C1
L2
C2
49
DVSS2
Figure 18. Third-Overtone Operation
Table 13. Third-Overtone Operation
Recommendations
FREQUENCY (MHz)
C1
(pF)
C2
(pF)
L1
(µH)
L2
(µH)
R1
(kΩ)
55
3
60
5
10
0.1
4.7
6.8
10
0.82
3.3
4.7
65
70
4
10
0.68
2.7
3.3
5
10
0.56
2.7
75
3.3
3
10
0.56
2.2
3.3
The master clock oscillator may be optionally divided
down to provide a reference clock on the REFCLK
pin. Control variable refclk_en enables the generation
of the reference clock when high. Two variables,
refclk_hi and refclk_lo, define the high and low
periods of REFCLK in terms of MCLK cycles.
REFCLK is high for refclk_hi cycles of MCLK, then
low for refclk_lo periods of MCLK. REFCLK frequency
is limited to integer submultiples of MCLK. Table 14
shows the refclk operation control settings.
Table 14. REFCLK Control Register Settings
PARAMETER
ADDRESS
BITS
refclk_en
1
13
refclk_hi
41
15:0
refclk_lo
40
15:0
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REAL-TIME CLOCK OSCILLATOR
The real-time clock oscillator supports crystals in the
frequency range of 32.768kHz through 150kHz. The
real-time clock module can be programmed to
operate accurately with crystals in this frequency
range.
The real-time clock oscillator output may be optionally
output on the RTC_OUT pin when rtc_oe is set high.
This option allows the real-time clock oscillator to be
used as an alternate reference clock in the event that
an acceptable frequency cannot be derived from
MCLK. Table 15 shows the rtc_oe control setting.
Although two pairs of SCL and SDA pins are
provided, the pins share a common master function.
Reprogramming of the i2cm_if_select variable should
only be performed when the i2cm_done status is '1',
indicating that all pending I2C transactions have
completed and that it is safe to change the selected
pair.
Table 16. I2C Control Register Settings
ADDRESS
BITS
i2cm_10b_addressing
124
12
i2cm_allow_slave_nack
124
10
i2cm_clear_slave_nack
124
11
Table 15. RTC Control Register Setting
i2cm_clk_cycles
124
7:0
PARAMETER
i2cm_done
124
15
i2cm_holding
124
14
i2cm_if_sel
121
14
i2cm_multimaster
124
8
The I C Master interface uses control variables (as
shown in Table 16) and two 16-byte buffers to create
I2C bus transactions compliant with the Philips
I2C-Bus Specification Version 2.1. Both 7- and 10-bit
addressing schemes are supported. Control variables
supply address, data transfer direction, data burst
length, and transaction control information to an I2C
master engine. This engine handles the details of the
I2C signaling and uses two 16-byte buffers to store
data transferred during the transaction. A block
diagram for this interface is illustrated in Figure 19.
i2cm_read_auto_inc
123
15
i2cm_read_byte
123
7:0
i2cm_read_byte_ptr
123
11:8
i2cm_restart_data_length
121
12:8
i2cm_restart_rw
121
13
i2cm_scl_sync_en
124
9
i2cm_slave_addr
120
14:0
i2cm_start_data_length
121
4:0
i2cm_start_rw
121
5
i2cm_use_sr
121
15
SCL clock rates are controlled
i2cm_clk_cycles
control
variable
Equation 24.
fMCLK
fSCL =
4 ´ i2cm_clk_cycles
i2cm_use_stop
124
13
i2cm_write_auto_inc
122
15
i2cm_write_byte
122
7:0
i2cm_write_byte_ptr
122
11:8
rtc_oe
ADDRESS
1
BITS
12
I2C MASTER
2
using
given
the
by
PARAMETER
(24)
The interface supports both standard and fast-mode
clock rates of 100kHz and 400kHz respectively.
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2
I CM_IF_SEL
Slave
Address
SLAVE_ADDR[14:0]
2
I CM_SLAVE_ADDR[14:0]
2
I CM_WRITE_BYTE_PTR[3:0]
Write Buffer
Control
2
I CM_WRITE_BYTE[7:0]
2
I CM_WRITE_AUTO_INC
SCL0
2
I C Master Engine
16-Byte
Write
Memory
SCL
SCL1
WRITE_DATA[7:0]
SDA0
SDA
SDA1
2
I CM_READ_BYTE_PTR[3:0]
Read Buffer
Control
2
I CM_READ_BYTE[7:0]
2
I CM_READ_BYTE_AUTO_INC
16-Byte
Read
Memory
2
I CM_START_DATA_LENGTH[4:0]
2
Slave Burst
Length
I CM_RESTART_DATA_LENGTH[4:0]
2
I CM_USE_SR
2
I CM_START_RW
2
I CM_RESTART_RW
2
I CM_CLK_CYCLES[7:0]
2
START_DATA_LENGTH[4:0]
RESTART_DATA_LENGTH[4:0]
RESTART_RW
USE_SR
START_RW
CLK_CYCLES[7:0]
I CM_MULTIMASTER
MULTIMASTER
2
SCL_SYNC_EN
I CM_SCL_SYNC_EN
2
Transaction
Control
READ_DATA[7:0]
I CM_ALLOW_SLAVE_NACK
2
I CM_CLEAR_SLAVE_NACK
2
ALLOW_SLAVE_NACK
CLEAR_SLAVE_NACK
I CM_10B_ADDR
TEN_BIT_ADDR
2
USE_STOP
I CM_USE_STOP
2
I CM_HOLDING
2
I CM_DONE
HOLDING
DONE
Figure 19. I2C Master Block Diagram
Start → Slave Addr → Write Data Burst → Stop
I2C Write Transactions
Write data must be stored in sequential locations in
the write buffer starting at location zero.
i2cm_write_byte_ptr[3:0] specifies one of the 16
memory locations where i2cm_write_byte[7:0] data
will be written. An auto-increment feature permits the
internal update of this pointer without specifying an
offset for each byte after the first byte.
I2C Read Transactions
i2cm_start_data_length[4:0] must specify the number
of bytes to read and i2cm_start_rw should be '1',
indicating that read data will follow the address.
i2cm_10b_addr specifies the addressing scheme.
Once the desired write data are loaded into this
memory, i2cm_start_data_length[4:0] must specify
the number of bytes to write and i2cm_start_rw
should be set to '0', indicating that write data will
follow the address. i2cm_10b_addr should be set to
select the desired 7- or 10-bit addressing scheme as
described in the Control Register Assignments
section of this document.
The read transaction is initiated by writing the slave
address to i2cm_slave_addr. The host controller
should poll the i2cm_done bit for a '1', indicating the
transaction has completed. Once completed, the read
data can be extracted from the read buffer using the
control
variables
i2cm_read_ptr[3:0]
and
i2cm_read_byte[7:0]. The sequence of actions
generated on the bus are:
The write transaction is initiated by writing the slave
address to i2cm_slave_addr. The host controller
should poll the i2cm_done bit for a '1', indicating that
the transaction has completed. The sequence of
actions generated on the I2C bus are:
Start → Slave Addr → Read Data Burst → Stop
28
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I2C Combined Format Transactions
REAL-TIME CLOCK
2
The I C specification describes combined write/read
formats where a master initially transmits data to a
slave and then reads data from the same slave. The
i2cm_use_sr parameter is used to create a repeated
START condition to support this format. By setting
the i2cm_use_sr parameter to '1', the master
interface can create the following sequence of
actions:
Start → Slave Addr → Data Burst 1 →
Start → Slave Addr → Data Burst 2 → Stop
i2cm_start_data_length[4:0]
and
i2cm_start_rw
control the data burst length and direction for DATA
BURST
1.
i2cm_restart_data_length[4:0]
and
i2cm_restart_rw control the data burst length and
direction for DATA BURST 2. If the data direction is
the same for both halves of the combined transaction,
data are stored sequentially in the 16-byte buffer.
Writing i2cm_slave_addr initiates the transaction.
I2C Data Bursts Greater than 16 Bytes
To create an I2C read or write burst greater than 16
bytes, the i2cm_use_stop parameter should be set to
'0', causing the interface to pause between each
burst of bytes transferred. This pause allows the host
to either reload or empty the buffers, depending on
the direction of data transfer.
After
starting
the
transaction
by
writing
i2cm_slave_addr, the i2cm_holding status bit should
be monitored for a logic '1', indicating that the
interface has completed the current set of byte
transfers and is waiting for the host to continue. After
reloading or emptying the buffers as needed, the host
should rewrite i2cm_slave_address to continue the
transfer for the next block of up to 16 bytes. For the
final transfer of the long data burst, i2cm_use_stop
must be set to '1' prior to re-writing the
i2cm_slave_address. This configuration creates a
normal STOP condition to properly terminate the
transfer.
Interrupt Operation
As an alternative to polling the values of i2cm_done
or i2cm_use_stop, the AFE8221 can be programmed
to generate an interrupt when either of these values
goes high.
The real-time clock (RTC) is enabled by setting
rtc_en to 1. While rtc_en is '0', the RTC oscillator
continues to run but the RTC registers do not
advance.
The RTC can operate with a range of oscillator
frequencies up to 100kHz. At the beginning of each
second, 2x the value of rtc_max_count is loaded into
the RTC crystal counter. This counter is decremented
at the rate of the RTC oscillator until it hits zero,
which generates a strobe that increments the
seconds counter as well as re-initializes the RTC
crystal counter. For a nominal 32.768kHz clock
crystal, rtc_max_count should be set to 16,384 (the
default value); for a nominal 100kHz crystal,
rtc_max_count should be set to 50,000. Table 18
illustrates the RTC control variable settings.
The RTC can be coarsely calibrated by adjusting the
rtc_max_count to an appropriate value other than half
the nominal crystal frequency. If finer calibration is
required, compensation mode can be enabled by
setting rtc_comp_en to 1. In compensation mode, the
two's-complement value stored in rtc_comp_val is
added to the one-second counter when it is
re-initialized at the beginning of each hour; thus, the
first second of each hour is lengthened or shortened
depending on the sign of rtc_comp_val. The
compensation can be applied to several seconds at
the beginning of each hour; rtc_comp_cnt holds the
number of seconds per hour to which the
compensation is applied. By spreading the
compensation out over a number of seconds, the
impact on the length of any given second is
minimized.
Setting and Reading the RTC
Because of the need to carefully synchronize any
update of the RTC time registers (rtc_seconds,
rtc_minutes, etc...), they must be written in a slightly
different manner than the other control registers.
Time registers must be written individually; after a
particular register address is written, at least two
clock cycles of the RTC oscillator must pass before
another register write occurs. The MSB of each time
register address can be polled to determine if it is
safe to make another write: if the MSB is 1, the
interface is still busy and a new write should not be
initiated. If the MSB is '0', then the interface is ready
to accept another write. There is no limitation on
reading the time registers.
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Note that all time register values are BCD-encoded.
Also note that the rtc_day_of_week is a read-only
value that is internally calculated from the rtc_day,
rtc_month, and rtc_year registers. Ranges on the
various time registers are shown in Table 17. When
the rtc_mode changes, the real-time clock alarm
settings should also be changed to reflect the new
time format. For instance, an alarm setting of 1300
hours never generates an interrupt in 12-hour mode.
This setting should be reset to 1:00 PM when the
mode is changed to 12-hour mode.
Real-Time Clock Alarm
The real-time clock alarm function can be used to
generate an interrupt (or a wakeup interrupt) at a
pre-programmed time. If the appropriate bit in an
interrupt enable register is set, an interrupt will be
generated when the values in the RTC time registers
become equal to the values in the RTC alarm
registers. The register settings are shown in
Table 18.
Table 18. RTC Alarm Control Register Settings
Table 17. Time Register Ranges
PARAMETER
rtc_seconds
rtc_minutes
PARAMETER
ADDRESS
BITS
RANGE
rtc_seconds_alarm[6:0]
67
6:0
0 to 59
rtc_minutes_alarm[6:0]
68
6:0
0 to 59
rtc_hours_alarm[5:0]
69
5:0
rtc_ampm_alarm
69
7
rtc_day_alarm[5:0]
70
5:0
rtc_month_arlarm[4:0]
71
4:0
rtc_year_alarm[7:0]
72
7:0
rtc_hours
1 to 12 (12-hour mode);
0 to 23 (24-hour mode)
rtc_ampm
0 (AM) or 1 (PM)
12-hour mode only
rtc_day
1 to 31, depending on month
rtc_month
1 to 12
rtc_year
0 to 99
(for years 2000 to 2099)
rtc_day_of_week
0 (Sunday) to 6 (Saturday)
GPIO
Invalid combinations of rtc_day and rtc_month (trying
to set February 30, for example) cause unpredictable
behavior and should be avoided. The February 28/29
rollover variation based on leap year is automatically
corrected for.
The RTC defaults to operate in 12-hour plus AM/PM
mode. To operate in 24-hour mode (where the
AM/PM bits are disabled) set rtc_mode to '1'. Care
must be taken when switching between AM/PM mode
and 24-hour mode to avoid setting the time to a
invalid value. See Figure 20 and Figure 21 for the
proper procedures.
12 general-purpose I/O pins are provided, labeled
GPIO0 through GPIO11. The direction of the 12
GPIO pins can be independently set through control
variable gpio_oe(11:0). A pin is an input if the
corresponding bit of gpio_oe is '0'; a pin is an output
if the corresponding bit of gpio_oe is '1'.
The control variable gpio(11:0) serves different
functions, depending on whether it is read from or
written to. A read operation from gpio returns the
logic state of the eight GPIO pins regardless of their
direction. A write to gpio sets the output state of the
GPIO pins if they are configured as outputs; there is
no effect if the pin is configured as an input. Note that
the write value of gpio is stored in a register, so that if
a GPIO pin is changed from an input to an output its
logic state is set by the stored value of gpio. Table 21
shows the gpio control variable settings.
The GPIO inputs can be optionally debounced if an
RTC oscillator is running. Debouncing is controlled by
gpio_delay, which is divided into 12 2-bit fields, each
controlling a particular GPIO input according to
Table 19.
Table 19. gpio_delay
[23:22]
[21:20]
[19:18]
[17:16]
[15:14]
[13:12]
[11:10]
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
30
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Begin
Begin
Set rtc_mode = 1
Read rtc_hours Register
(Midnight)
Read rtc_hours and
rtc_ampm Registers
Does
rtc_hours = 0?
12:00AM = 0000 Hours
(Midnight)
Does
rtc_hours = 12 and
rtc_ampm = 0?
Yes
Yes
Set rtc_hours = 12
and rtc_ampm = 0
No
(AM)
Set rtc_hours = 0
Is
rtc_hours < 12?
Yes
Set rtc_ampm = 0
No
No
Is
rtc_ampm = 0?
(AM)
(Noon)
Yes
Does
rtc_hours = 12?
Yes
Set rtc_ampm = 1
No
No
Set rtc_hours =
rtc_hours - 12
and rtc_ampm = 1
Does
Yes
rtc_hours = 12 and
rtc_ampm = 1?
12:00 PM = 1200 Hours
(Noon)
No
Set rtc_mode = 0
Set rtc_hours =
rtc_hours + 12
Recalculate
Alarm Registers
Recalculate
Alarm Registers
Done
Done
Figure 20. Procedure for Updating RTC Hour
When Going from 12-Hour Mode to 24-Hour Mode
Figure 21. Procedure for Updating RTC Hour
When Going from 24-Hour Mode to 12-Hour Mode
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The debounce circuitry uses a clock divided from the
RTC oscillator, with a debounce clock frequency
given by Equation 25.
fRTC
fDEBOUNCE =
2 ´ GPIO_DEBOUNCE_FREQ + 1
2
(25)
If debounce is enabled, then in order for a GPIO input
to change value (and possibly generate an interrupt if
so programmed) it must remain stable for the number
of debounce clock cycles (zero to three) given in the
appropriate field of gpio_delay.
Table 20. General RTC Control Register Settings
PARAMETER
ADDRESS
BITS
Table 22. Alternate GPIO and DDC Control
Register Settings
PARAMETER
ADDRESS
BITS
96
gpio
11:0
97
ddc0_atten
96
ddc1_atten
97
14:12
INTERRUPT GENERATORS
There are three programmable interrupt pins; IRQ0,
IRQ1, and IRQ2. Only the operation of IRQ0 is
described here; IRQ1 and IRQ2 are programmed in
the same way, using different control variables.
rtc_ampm
75
7
rtc_comp_cnt[5:0]
64
12:7
rtc_comp_en
64
2
rtc_comp_val
66
15:0
rtc_day[5:0]
76
5:0
rtc_day_of_week[2:0]
79
2:0
BIT POSITION
SOURCE
BIT POSITION
rtc_en
64
0
0
GPIO
8
RTC alarm
rtc_hours[5:0]
75
5:0
rtc_max_count[15:0]
65
15:0
rtc_minutes[6:0]
74
6:0
rtc_mode
64
1
rtc_month[4:0]
77
4:0
rtc_seconds[6:0]
73
6:0
rtc_year[7:0]
78
7:0
Interrupts can be generated from various sources.
Interrupt generation is enabled through irq0_en, as
Table 23 shows.
Table 23. Interrupt Generation
1
None
9
RTC seconds
rollover
2
I2C Master
done
10
RTC minutes
rollover
3
Aux ADC done
11
RTC hours
rollover
4
IFADC0
over-range
12
RTC months
rollover
5
IFADC1
over-range
13
RTC day
rollover
6
IFADC0 limit
14
RTC year
rollover
7
IFADC1 limit
15
—
Table 21. GPIO Control Register Settings
PARAMETER
ADDRESS
BITS
gpio
43
11:0
gpio_delay[15:0]
44
15:0
gpio_oe
42
11:0
ALTERNATE REGISTERS—GPIO AND INPUT
ATTENUATOR
If some of the GPIO pins on the AFE8221 are to be
used to control the gain of a tuner, it may be
desirable to change the GPIO values at the same
time as the input attenuation to the DDC. To make
this process more deterministic, the control
parameters gpio, ddc0_atten, and ddc1_atten can be
accessed through the alternate control register
addresses of 96 and 97. By writing to register 96,
gpio and ddc0_atten can be changed in a single
register write; by writing to register 97, gpio and
ddc1_atten can be changed in a single register write.
Table 22 shows the operation control settings for
these parameters.
32
SOURCE
Setting a bit of irq0_en allows the generation of an
interrupt for the corresponding event. All three IRQ
generators run on the master clock (MCLK). When an
interrupt event occurs on a given source signal, a
value of '1' is written to the corresponding bit of
irq0_status. This value is held in irq0_status until it is
explicitly cleared by writing a '0' to the appropriate bit
of irq0_status. A typical sequence upon receipt of an
interrupt would be to poll irq0_status to determine the
source of the interrupt, take whatever system action
is appropriate, and then clear irq0_status.
Changes to any of the GPIO pins can also be
programmed as interrupts. GPIO pin events are
defined as changes from low to high or from high to
low, depending on whether the corresponding bit in
irq0_gpio_edge is high or low. GPIO interrupts are
enabled by setting the corresponding bit in
irq0_gpio_en; they are identified and cleared by
reading and writing the corresponding bit in
irq0_gpio_status.
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The behavior of the IRQ0 pin is determined by
irq0_sense. When irq0_sense is '0', IRQ0 is normally
low and goes high on an unmasked interrupt event.
When irq0_sense is '1', IRQ0 is normally high and
goes low on an unmasked interrupt event. Table 24
shows the irq0, irq1, and irq2 operations control
settings.
Table 24. IRQ Control Register Settings
PARAMETER
irq0_en
irq1_en
ADDRESS
BITS
50
15:0
55
15:0
irq2_en
60
15:0
irq0_gpio_edge
48
11:0
irq1_gpio_edge
53
11:0
2. The WAKEUP generator operates when the AFE
is in low-power mode, whereas the IRQ
generators do not; and
3. The interrupt sources for the WAKEUP interrupt
generator are slightly different.
Table 25 shows the wakeup control
Table 26 shows the generator functions.
Table 25. Wakeup Control Register Settings
PARAMETER
ADDRESS
2
0
wakeup_gpio_edge
80
11:0
wakeup_gpio_en
81
11:0
wakeup_en
82
15:0
wakeup_status
83
15:0
wakeup_gpio_status
84
11:0
58
11:0
irq0_gpio_en
49
11:0
irq1_gpio_en
54
11:0
irq2_gpio_en
59
11:0
irq0_gpio_status
52
11:0
BIT POSITION
SOURCE
11:0
0
GPIO
None
57
Table 26. WAKEUP Interrupt Generator
irq2_gpio_status
62
11:0
1
irq0_sense
2
1
2
None
2
3
None
None
irq1_sense
2
irq2_sense
2
3
4
irq0_status
51
15:0
5
None
15:0
6
None
15:0
7
None
irq1_status
irq2_status
56
61
WAKEUP INTERRUPT GENERATOR
The WAKEUP interrupt generator functions in the
same way as the IRQ generators with the following
exceptions:
1. The WAKEUP generator runs on the RTC clock
instead of MCLK;
BITS
wakeup_sense
irq2_gpio_edge
irq1_gpio_status
settings.
8
RTC alarm
9
RTC seconds rollover
10
RTC minutes rollover
11
RTC hours rollover
12
RTC months rollover
13
RTC day rollover
14
RTC year rollover
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CONTROL REGISTER ASSIGNMENTS
Table 27. Control Registers
Address: 1
Description: Functional Block Enables
Bits
Range
Action
Parameter Name
1:0
0..3
Enable IFADC converters
ifadc_en(1:0)
2
0/1
Gain control for IF_ADC0
ifadc_gain0
3
0/1
Gain control for IF_ADC1
ifadc_gain1
5:4
0..3
Enable DDCs
ddc_en(1:0)
6
0/1
Synchronize DDC0 and DDC1
ddc_sync
7
0/1
Enable primary IF data interface
dout_en
8
0/1
Enable secondary IF data interface
bb_en
10:9
0..3
Enable auxiliary DACs
cdac_en(1:0)
11
0/1
Enable auxiliary ADC
aux_adc_en
12
0/1
Enable RTC output pins
rtc_oe
13
0/1
Enable reference clock output pins
refclk_en
Address: 2
Description: Interrupt Output Level Configuration
Bits
Range
0
0/1
1
0/1
2
0/1
3
0/1
Action
Parameter Name
0 = Active high WAKEUP interrupt
1 = Active low WAKEUP interrupt
0 = Active high IRQ0 interrupt
1 = Active low IRQ0 interrupt
0 = Active high IRQ1 interrupt
1 = Active low IRQ1 interrupt
0 = Active high IRQ2 interrupt
1 = Active low IRQ2 interrupt
wakeup_sense
irq0_sense
irq1_sense
irq2_sense
Address: 3
Description: DDC0 Input Attenuator
Bits
Range
2:0
0..6
Action
Parameter Name
Attenuation setting for DDC0
ddc_atten(2:0)
Address: 4
Description: DDC0 Input Attenuator
Bits
Range
15:0
0..65535
Action
Parameter Name
Delay setting for DDC0 attenuator
ddc0_delay(15:0)
Address: 5
Description: DDC0 NCO Frequency
Bits
Range
15:0
0..65535
Action
Parameter Name
Upper bytes of DDC0 NCO frequency
ddc0_demod_freq(31:16)
Address: 6
Description: DDC0 NCO Frequency
Bits
Range
15:0
0..65535
Action
Parameter Name
Lower bytes of DDC0 NCO frequency
ddc0_demod_freq(15:0)
Address: 7
Description: DDC0 NCO Phase
Bits
Range
15:0
0..65535
34
Action
Parameter Name
Upper bytes of DDC0 NCO phase
ddc0_demod_phase(31:16)
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Table 27. Control Registers (continued)
Address: 8
Description: DDC0 NCO Phase (continued)
Bits
Range
15:0
0..65535
Action
Parameter name
Lower bytes of DDC0 NCO phase
ddc0_demod_phase(15:0)
Address: 9
Description: DDC0 CIC Filter
Bits
Range
Action
Parameter Name
8:0
4..256
CIC filter decimation rate
ddc0_cic_dec_rate(8:0)
Address: 10
Description: DDC0 CIC Filter
Bits
Range
Action
Parameter Name
5:0
11:6
0..63
CIC filter post-filter shift
ddc0_cic_shift(5:0)
0..32
CIC filter post-filter scale
ddc0_cic_scale(5:0)
Address: 11
Description: DDC0 FIR Filter 1
Bits
Range
Action
Parameter Name
1:0
0..3
FIR filter mode
ddc0_fir1_mode(1:0)
7:2
0..63
Number of coefficients to process
ddc0_fir1_ncoeffs(5:0)
13:8
0..63
Coefficient base address
ddc0_fir1_base_addr(5:0)
Address: 12
Description: DDC0 FIR Filter 2A
Bits
Range
1:0
0..3
Action
Parameter Name
FIR filter mode
8:2
ddc0_fir2a_mode(1:0)
0..127
Number of coefficients to process
ddc0_fir2a_ncoeffs(6:0)
15:9
0..127
Coefficient base address
ddc0_fir2a_base_addr(6:0)
Address: 13
Description: DDC0 FIR Filter 2B
Bits
Range
1:0
0..3
Action
Parameter Name
FIR filter mode
8:2
ddc0_fir2b_mode(1:0)
0..127
Number of coefficients to process
15:9
ddc0_fir2b_ncoeffs(6:0)
0..127
Coefficient base address
ddc0_fir2b_base_addr(6:0)
Address: 14
Description: DDC0 FIR Filter Extended Features
Bits
Range
Action
Parameter Name
3:0
7:4
0..15
Post-filter shift for FIR filter 2A
ddc0_fir2a_shift(3:0)
0..15
Post-filter shift for FIR filter 2B
8
ddc0_fir2b_shift(3:0)
0/1
Enable interleave mode for FIR filter 2A and FIR filter 2B
ddc0_interleave
9
0/1
Disable decimation for FIR filter 1
ddc0_fir1_nodec
10
0/1
Disable decimation for FIR filter 2A and FIR filter 2B
ddc0_fir2_nodec
Address: 15
Description: DDC1 Input Attenuator
Bits
Range
2:0
0..6
Action
Parameter Name
Attenuation setting for DDC1
ddc1_atten(2:0)
Address: 16
Description: DDC1 Input Attenuator
Bits
Range
15:0
0..65535
Action
Parameter Name
Delay setting for DDC1 attenuator
ddc1_delay(15:0)
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Table 27. Control Registers (continued)
Address: 17
Description: DDC1 NCO Frequency
Bits
Range
15:0
0..65535
Action
Parameter Name
Upper bytes of DDC1 NCO frequency
ddc1_demod_freq(31:16)
Address: 18
Description: DDC1 NCO Frequency
Bits
Range
15:0
0..65535
Action
Parameter Name
Lower bytes of DDC1 NCO frequency
ddc1_demod_freq(15:0)
Address: 19
Description: DDC1 NCO Phase
Bits
Range
15:0
0..65535
Action
Parameter Name
Upper bytes of DDC1 NCO phase
ddc1_demod_phase(31:16)
Address: 20
Description: DDC1 NCO Phase
Bits
Range
15:0
0..65536
Action
Parameter Name
Lower bytes of DDC1 NCO phase
ddc1_demod_phase(15:0)
Address: 21
Description: DDC1 CIC Filter Decimation
Bits
Range
Action
Parameter Name
8:0
4..256
CIC filter decimation rate
ddc1_cic_dec_rate(8:0)
Address: 22
Description: DDC1 CIC Filter
Bits
Range
Action
Parameter Name
5:0
0..63
CIC filter post-filter shift
ddc1_cic_shift(5:0)
11:6
0..32
CIC filter post-filter scale
ddc1_cic_scale(5:0)
Address: 23
Description: DDC1 FIR Filter 1
Bits
Range
Action
Parameter Name
1:0
0..3
FIR filter mode
ddc1_fir1_mode(1:0)
7:2
0..63
Number of coefficients to process
ddc1_fir1_ncoeffs(5:0)
13:8
0..63
Coefficient base address
ddc1_fir1_base_addr(5:0)
Address: 24
Description: DDC1 FIR Filter 2A
Bits
Range
Action
Parameter Name
1:0
0..3
FIR filter mode
ddc1_fir2a_mode(1:0)
8:2
0..127
Number of coefficients to process
ddc1_fir2a_ncoeffs(6:0)
15:9
0..127
Coefficient base address
ddc1_fir2a_base_addr(6:0)
Address: 25
Description: DDC1 FIR Filter 2B
Bits
Range
1:0
0..3
8:2
15:9
36
Action
Parameter Name
FIR filter mode
ddc1_fir2b_mode(1:0)
0..127
Number of coefficients to process
ddc1_fir2b_ncoeffs(6:0)
0..127
Coefficient base address
ddc1_fir2b_base_addr(6:0)
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Table 27. Control Registers (continued)
Address: 26
Description: DDC1 FIR Filter Extended Features
Bits
Range
Action
Parameter Name
3:0
0..15
Post-filter shift for FIR filter 2A
ddc1_fir2a_shift(3:0)
7:4
0..15
Post-filter shift for FIR filter 2B
ddc1_fir2b_shift(3:0)
8
0/1
Enable interleave mode for FIR filter 2A and FIR filter 2B
ddc1_interleave
9
0/1
Disable decimation for FIR filter 1
ddc1_fir1_nodec
10
0/1
Disable decimation for FIR filter 2A and FIR filter 2B
ddc1_fir2_nodec
Address: 27
Description: Data Interface Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
Configuration for IF_DOUT0
if_dout0_config
Address: 28
Description: Data Interface Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
Configuration for IF_DOUT1
if_dout1_config
Address: 29
Description Data Interface Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
Configuration for IF_DOUT2
if_dout2_config
Address: 30
Description: Data Interface Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
Configuration for IF_DOUT3
if_dout3_config
Address: 31
Description: Data Interface Configuration
Bits
Range
4:0
0..16
5
0/1
6
0/1
8:7
0..2
Action
Parameter Name
Divide factor to derive IF_DCLK from MCLK
if_dclk_div(4:0)
0: IF_DFSO and IF_DOUTx change on rising edge of IF_DCLK
1: IF_DFSO and IF_DOUTx change on falling edge of IF_DCLK
0: IF_DFSO generated by DDC0
1: IF_DFSO generated by DDC1
if_dclk_edge
if_dfso_select
0: IF_DFSO one IF_DCLK cycle wide
1: IF_DFSO toggles once per frame
if_dfso_mode(1:0)
2: IF_DFSO 16 IF_DCLK cycles wide
Address: 32
Description: Data Interface Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
Configuration for BB_DOUT0
bb_dout0_config
Address: 33
Description: Data Interface Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
Configuration for BB_DOUT1
bb_dout1_config
Address: 34
Description: Data Interface Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
Configuration for BB_DOUT2
bb_dout2_config
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Table 27. Control Registers (continued)
Address: 35
Description: Data Interface Configuration (continued)
Bits
Range
15:0
0..65535
Action
Parameter Name
Configuration for BB_DOUT3
bb_dout3_config
Address: 36
Description: Data Interface Configuration
Bits
Range
4:0
0..16
5
0/1
6
0/1
8:7
0..2
Action
Parameter Name
Divide factor to derive BB_BCK from MCLK
bb_bck_div(4:0)
0: BB_WS and BB_DOUTx change on rising edge of BB_BCK
1: BB_WS and BB_DOUTx change on falling edge of BB_BCK
0: BB_WS generated by DDC0
bb_bck_edge
bb_ws_select
1: BB_WS generated by DDC1
0: BB_WS one BB_BCK cycle wide
1: BB_WS toggles once per frame
bb_ws_mode(1:0)
2: BB_WS 16 BB_BCK cycles wide
Address: 37
Description: CDAC0 Output
Bits
Range
Action
Parameter Name
11:0
0..4095
Output value for CDAC0
cdac0_out(11:0)
Address: 38
Description: CDAC1 Output
Bits
Range
Action
Parameter Name
11:0
0..4095
Output value for CDAC1
cdac1_out(11:0)
Address: 39
Description: Aux ADC
Bits
Range
Action
Parameter Name
7:0
0..255
Register read: Conversion result for auxiliary ADC (read only)
aux_adc_out(7:0)
0: No aux ADC inputs connected
1: AUX_ADC0 pin connected to aux ADC
11:8
0, 1, 2, 4, or 8
2: AUX_ADC1 pin connected to aux ADC
aux_adc_sel(3:0)
4: AUX_ADC2 pin connected to aux ADC
8: AUX_ADC3 pin connected to aux ADC
14:12
Not used
Register write: Starts a conversion when '1' is written
15
0/1
Register read: Returns '0' while conversion is in progress, '1' when
conversion is finished
aux_adc_done
Address: 40
Description: Reference Clock Configuration
Bits
Range
Action
Parameter Name
15:0
0..4095
Low period ( in units of MCLK cycles) for reference clock output
refclk_lo(15:0)
Address: 41
Description: Reference Clock Configuration
Bits
Range
Action
Parameter Name
15:0
0..4095
High period (in units of MCLK cycles) for reference clock output
refclk_hi(15:0)
38
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Table 27. Control Registers (continued)
Address: 42
Description: GPIO Configuration
Bits
Range
0
0/1
1
0/1
2
0/1
3
0/1
4
0/1
5
0/1
6
0/1
7
0/1
8
0/1
9
0/1
10
0/1
11
0/1
Action
Parameter Name
0 = GPIO0 set as input
1 = GPIO0 set as output
0 = GPIO1 set as input
1 = GPIO1 set as output
0 = GPIO2 set as input
1 = GPIO2 set as output
0 = GPIO3 set as input
1 = GPIO3 set as output
0 = GPIO4 set as input
1 = GPIO4 set as output
0 = GPIO5 set as input
1 = GPIO5 set as output
0 = GPIO6 set as input
1 = GPIO6 set as output
0 = GPIO7 set as input
1 = GPIO7 set as output
0 = GPIO8 set as input
1 = GPIO8 set as output
0 = GPIO9 set as input
1 = GPIO9 set as output
0 = GPIO10 set as input
1 = GPIO10 set as output
0 = GPIO11 set as input
1 = GPIO11 set as output
gpio_oe(0)
gpio_oe(1)
gpio_oe(2)
gpio_oe(3)
gpio_oe(4)
gpio_oe(5)
gpio_oe(6)
gpio_oe(7)
gpio_oe(8)
gpio_oe(9)
gpio_oe(10)
gpio_oe(11)
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Table 27. Control Registers (continued)
Address: 43
Description: GPIO Configuration (continued)
Bits
Range
0
0/1
1
0/1
2
0/1
3
0/1
4
0/1
5
0/1
6
0/1
7
0/1
8
0/1
9
0/1
10
0/1
11
0/1
Action
Parameter Name
Register write: drives value on GPIO0 pin if enabled as output
Register read: returns value on GPIO0 pin
Register write: drives value on GPIO1 pin if enabled as output
Register read: returns value on GPIO1 pin
Register write: drives value on GPIO2 pin if enabled as output
Register read: returns value on GPIO2 pin
Register write: drives value on GPIO3 pin if enabled as output
Register read: returns value on GPIO3 pin
Register write: drives value on GPIO4 pin if enabled as output
Register read: returns value on GPIO4 pin
Register write: drives value on GPIO5 pin if enabled as output
Register read: returns value on GPIO5 pin
Register write: drives value on GPIO6 pin if enabled as output
Register read: returns value on GPIO6 pin
Register write: drives value on GPIO7 pin if enabled as output
Register read: returns value on GPIO7 pin
Register write: drives value on GPIO8 pin if enabled as output
Register read: returns value on GPIO8 pin
Register write: drives value on GPIO9 pin if enabled as output
Register read: returns value on GPIO9 pin
Register write: drives value on GPIO10 pin if enabled as output
Register read: returns value on GPIO10 pin
Register write: drives value on GPIO11 pin if enabled as output
Register read: returns value on GPIO11 pin
gpio(0)
gpio(1)
gpio(2)
gpio(3)
gpio(4)
gpio(5)
gpio(6)
gpio(7)
gpio(8)
gpio(9)
gpio(10)
gpio(11)
Address: 44
Description: GPIO Configuration
Bits
Range
Action
Parameter Name
1:0
0..3
GPIO0 debounce setting
gpio_delay(1:0)
3:2
0..3
GPIO1 debounce setting
gpio_delay(3:2)
5:4
0..3
GPIO2 debounce setting
gpio_delay(5:4)
7:6
0..3
GPIO3 debounce setting
gpio_delay(7:6)
9:8
0..3
GPIO4 debounce setting
gpio_delay(9:8)
11:10
0..3
GPIO5 debounce setting
gpio_delay(11:10)
13:12
0..3
GPIO6 debounce setting
gpio_delay(13:12)
15:14
0..3
GPIO7 debounce setting
gpio_delay(15:14)
Address: 45
Description: GPIO Configuration
Bits
Range
1:0
3:2
40
Action
Parameter Name
0..3
GPIO8 debounce setting
gpio_delay(17:16)
0..3
GPIO9 debounce setting
gpio_delay(19:18)
5:4
0..3
GPIO10 debounce setting
gpio_delay(21:20)
7:6
0..3
GPIO11 debounce setting
gpio_delay(23:22)
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Table 27. Control Registers (continued)
Address: 46
Description: IF ADC Alarm
Bits
Range
Action
Parameter Name
11:0
0..2047
Alarm limit for IF_ADC0
ifadc0_limit(11:0)
Address: 47
Description: IF ADC Alarm
Bits
Range
Action
Parameter Name
11:0
0..2047
Alarm limit for IF_ADC1
ifadc1_limit(11:0)
Address: 48
Description: IRQ0 Configuration
Bits
Range
Action
Parameter Name
11:0
0..4095
GPIO input edge select for IRQ0
irq0_gpio_edge(11:0)
Address: 49
Description: IRQ0 Configuration
Bits
Range
Action
Parameter Name
11:0
0..4095
IRQ0 GPIO enable
irq0_gpio_en(11:0)
Address: 50
Description: IRQ0 Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
IRQ0 enable
irq0_en(15:0)
Address: 51
Description: IRQ0 Status
Bits
15:0
Range
0..65535
Action
Parameter Name
Register read: returns IRQ0 status
Register write: clears interrupt bit if '1' is written
irq0_status(15:0)
Address: 52
Description: IRQ0 GPIO Status
Bits
11:0
Range
0..4095
Action
Parameter Name
Register read: returns IRQ0 status
Register write: clears interrupt bit if '1' is written
irq0_gpio_status(11:0)
Address: 53
Description: IRQ1 Configuration
Bits
Range
Action
Parameter Name
11:0
0..4095
GPIO input edge select for IRQ1
irq1_gpio_edge(11:0)
Address: 54
Description: IRQ1 Configuration
Bits
Range
Action
Parameter Name
11:0
0..4095
IRQ1 GPIO enable
irq1_gpio_en(11:0)
Address: 55
Description: IRQ1 Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
IRQ1 enable
irq1_en(15:0)
Address: 56
Description: IRQ1 Status
Bits
15:0
Range
0..65535
Action
Parameter Name
Register read: returns IRQ1 status
Register write: clears interrupt bit if '1' is written
irq1_status(15:0)
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Table 27. Control Registers (continued)
Address: 57
Description: IRQ1 GPIO Status (continued)
Bits
11:0
Range
0..4095
Action
Parameter Name
Register read: returns IRQ1 status
irq1_gpio_status(11:0)
Register write: clears interrupt bit if '1' is written
Address: 58
Description: IRQ2 Configuration
Bits
Range
Action
Parameter Name
11:0
0..4095
GPIO input edge select for IRQ2
irq2_gpio_edge(11:0)
Address: 59
Description: IRQ2 Configuration
Bits
Range
Action
Parameter Name
11:0
0..4095
IRQ2 GPIO enable
irq2_gpio_en(11:0)
Address: 60
Description: IRQ2 Configuration
Bits
Range
15:0
0..65535
Action
Parameter Name
IRQ2 enable
irq2_en(15:0)
Address: 61
Description: IRQ2 Status
Bits
15:0
Range
0..65535
Action
Parameter Name
Register read: returns IRQ2 status
irq2_status(15:0)
Register write: clears interrupt bit if '1' is written
Address: 62
Description: IRQ2 GPIO Status
Bits
11:0
Range
0..4095
Action
Parameter Name
Register read: returns IRQ2 status
irq2_gpio_status(11:0)
Register write: clears interrupt bit if '1' is written
Address: 63
Description: Not Used
Bits
Range
—
—
Action
Parameter Name
—
—
Address: 64
Description: Real-Time Clock Configuration
Bits
Range
Action
Parameter Name
0
0/1
1
0/1
2
0/1
Enable clock compensation
rtc_comp_en
3
0/1
Enable clock test mode
rtc_test_en
6:4
0..4
Clock test mode selection
rtc_test_mode(2:0)
12:7
0..31
Compensation count
rtc_comp_cnt(5:0)
15:13
0..7
Frequency select for GPIO debounce
gpio_debounce_freq(2:0)
0 = Freeze real-time clock
rtc_en
1 = Enable real-time clock operation
0:12 hour mode
rtc_mode
1:24 hour mode
Address: 65
Description: Real-Time Clock Configuration
Bits
Range
15:0
0..32767
42
Action
Parameter Name
Real-time one second terminal count. Default = 16384 (for 32.768kHz
crystal)
rtc_max_count(15:0)
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Table 27. Control Registers (continued)
Address: 66
Description: Real-Time Clock Configuration (continued)
Bits
Range
15:0
–32768..32767
Action
Parameter Name
Real-time clock compensation value. Default = 16384
rtc_comp_val(15:0)
Address: 67
Description: Real-Time Clock Alarm
Bits
Range
6:0
0..59
Action
Parameter Name
Seconds alarm setting
rtc_seconds_alarm(6:0)
Address: 68
Description: Real-Time Clock Alarm
Bits
Range
6:0
0..59
Action
Parameter Name
Minutes alarm setting
rtc_minutes_alarm(6:0)
Address: 69
Description: Realtime Clock Alarm
Bits
5:0
6
7
Range
Action
Parameter Name
1..12
Hour alarm setting, 12-hour mode
0..23
Hour alarm setting, 24-hour mode
—
Not used
—
12-hour mode: 0 = AM, 1 = PM
0/1
rtc_hours_alarm(5:0)
24-hour mode: not used
rtc_ampm_alarm
Address: 70
Description: Real-Time Clock Alarm
Bits
Range
5:0
1..31
Action
Parameter Name
Day of the month alarm setting
rtc_day_alarm(5:0)
Address: 71
Description: Real-Time Clock Alarm
Bits
Range
4:0
1..12
Action
Parameter Name
Month alarm setting
rtc_months_alarm(4:0)
Address: 72
Description: Real-Time Clock Alarm
Bits
Range
7:0
0..99
Action
Parameter Name
Year alarm setting
rtc_year_alarm(7:0)
Address: 73
Description: Real-Time Clock Current Time
Bits
Range
6:0
0..59
14:7
—
15
0/1
Action
Parameter Name
Seconds register
rtc_seconds(6:0)
Not used
—
Real-time clock busy (read only)
rtc_busy
Address: 74
Description: Real-Time Clock Current Time
Bits
Range
Action
Parameter Name
6:0
0..59
Minutes register
rtc_minutes(6:0)
14:7
—
Not used
—
15
0/1
Real-time clock busy (read only)
rtc_busy
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Table 27. Control Registers (continued)
Address: 75
Description: Real-Time Clock Current Time (continued)
Bits
5:0
6
7
Range
Action
Parameter Name
1..12
Hour register, 12-hour mode
0..23
Hour register, 24-hour mode
—
Not used
—
12-hour mode: 0 = AM, 1 = PM
0/1
rtc_hours(5:0)
24-hour mode: not used
rtc_ampm
14:8
—
Not used
—
15
0/1
Real-time clock busy (read only)
rtc_busy
Address: 76
Description: Real-Time Clock Current Time
Bits
Range
5:0
1..31
Action
Parameter Name
Day of month register
rtc_day(5:0)
14:6
—
Not used
—
15
0/1
Real-time clock busy (read only)
rtc_busy
Address: 77
Description: Real-Time Clock Current Time
Bits
Range
4:0
1..12
14:5
—
15
0/1
Action
Parameter Name
Month register
rtc_month(4:0)
Not used
—
Real-time clock busy (read only)
rtc_busy
Address: 78
Description: Real-Time Clock Current Time
Bits
Range
7:0
0..99
14:8
—
15
0/1
Action
Parameter Name
Year register
rtc_year(7:0)
Not used
—
Real-time clock busy (read only)
rtc_busy
Address: 79
Description: Real-Time Clock Current Time
Bits
Range
Action
Parameter Name
2:0
0..6
Day of week
rtc_day_of_week(2:0)
14:3
—
Not used
—
15
0/1
Real-time clock busy (read only)
rtc_busy
Address: 80
Description: WAKEUP Configuration
Bits
Range
Action
Parameter Name
11:0
0..4095
GPIO input edge select for WAKEUP
wakeup_gpio_edge(11:0)
Address: 81
Description: WAKEUP Configuration
Bits
Range
Action
Parameter Name
11:0
0..4095
WAKEUP GPIO enable
wakeup_gpio_en(11:0)
Address: 82
Description: WAKEUP Configuration
Bits
Range
15:0
0..65535
44
Action
Parameter Name
WAKEUP enable
wakeup_en(15:0)
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Table 27. Control Registers (continued)
Address: 83
Description: WAKEUP Status
Bits
15:0
Range
0..65535
Action
Parameter Name
Register read: returns WAKEUP status
wakeup_status(15:0)
Register write: clears interrupt bit if '1' is written
Address: 84
Description: WAKEUP GPIO Status
Bits
11:0
Range
0..4095
Action
Parameter Name
Register read: returns WAKEUP status
wakeup_gpio_status(11:0)
Register write: clears interrupt bit if '1' is written
Address: 85–119
Description: Not Used
Bits
Range
—
—
Action
Parameter Name
—
—
Address: 120
Description: I2C Master—Slave Address
Bits
Range
Action
Parameter Name
Slave address used for master transactions. Also starts transaction.
14:0
0..32767
7-bit addressing: bits 6:0 are the slave address. Bits 14:7 are ignored.
i2cm_slave_addr(14:0)
10-bit addressing: bits 9:0 are the slave address. Bits 14:10 are the
upper five bits for the slave address first byte
15
—
Not used
—
Address: 121
Description: I2C Master—Slave Burst length
Bits
Range
4:0
1..16
Action
Parameter Name
Number of bytes to transfer for the first data burst
i2cm_start_data_length(4:0)
Selects the Read/Write bit value used with the slave address following
START.
5
0/1
7:6
—
12:8
1..16
i2cm_start_rw
'0' selects Write
'1' selects Read
Not used
—
Number of bytes to transfer for the second data burst in a combined
format transfer. This parameter is used only if i2cm_use_sr = 1.
i2cm_restart_data_length(4:0)
Selects the Read/Write bit value used with the slave address following
RESTART.
13
0/1
i2cm_restart_rw
'0' selects Write
'1' selects Read
14
0/1
15
0/1
0 = SDA0/SCL0 interface
1 = SDA1/SCL1 interface
'0' selects I2C transactions without a repeated start.
'1' selects combined transactions with a repeated start.
i2xm_if_sel
i2cm_use_sr
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Table 27. Control Registers (continued)
Address: 122
Description: I2C Master—Write Buffer Control
Bits
Range
Action
Parameter Name
7:0
0..255
Stores data in the write buffer at the location specified by
i2cm_write_byte_ptr(3:0)
i2cm_write_byte(7:0)
11:8
0..15
Buffer location where the i2cm_write_byte should be placed
i2cm_write_byte_ptr(3:0)
14:12
—
Not used
—
Auto increment
15
0 = i2cm_write_byte_ptr is used for storing the i2cm_write_byte value
in the write buffer memory
0/1
i2cm_write_auto_inc
1 = i2cm_write_byte_ptr is ignored from the host and it is
auto-incremented for writing the i2cm_write_byte to the buffer
Address: 123
Description: I2C Master—Read Buffer Control
Bits
Range
Action
Parameter Name
7:0
0..255
Read only - retrieves data read by the I2C master from the read buffer
i2cm_read_byte(7:0)
11:8
0..15
Buffer location where the i2cm_read_byte should be retrieved
i2cm_read_byte_ptr(3:0)
14:12
—
Not used
—
Auto increment
15
0 = i2cm_read_byte_ptr is used for retrieving the i2cm_write_byte
value in the read buffer memory
0/1
i2cm_read_auto_inc
1 = i2cm_read_byte_ptr is ignored from the host and it is
auto-incremented for retrieving the i2cm_read_byte from the buffer
Address: 124
Description: I2C Master—Read Buffer Control
Bits
Range
Action
Parameter Name
7:0
5..200
Controls the I2C SCL clock rate
i2cm_clk_cycles(7:0)
Multi-master
8
0/1
0 = single I2C master on SDA and SCL signals
i2cm_multimaster
1 = multiple I2C masters present on SDA and SCL signals
SCL sync enable
9
0/1
0 = prohibit SCL stretching by slave
i2cm_scl_sync_en
1 = permit SCL stretching by slave
Allow slave NACK
10
0/1
0 = require slave to ACK transfers
i2cm_allow_slave_nack
1 = permit slave to not-acknowledge (NACK)
11
0/1
12
0/1
Clear slave NACK. if i2cm_allow_slave_nack is zero and the slave fails
to acknowledge, this bit when read will be set. No further I2C
i2cm_clear_slave_nack
transactions are allowed until this bit is written as a '1' to clear the
slave NACK condition.
0 = Use 7 bit addressing
i2cm_10b_addressing
1 = Use 10 bit addressing
End transfer with stop
0 = do not issue a stop after last byte transferred and pause
transaction
13
0/1
i2cm_use_stop
14
0/1
Holding. Read-only. Used when i2cm_use_stop is set to zero.
i2cm_holding
0/1
Done. Read-only. When set, the I2C master has completed any
pending transactions.
i2cm_done
1 = issue a stop after the last byte transferred
15
46
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): AFE8221
AFE8221
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SBAS394A – APRIL 2007 – REVISED MARCH 2008
Revision History
Changes from Revision original (April 2007) to Revision A .......................................................................................... Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed typical PSRR specification in the Auxiliary ADC Specifications table.................................................................... 4
Reordered Terminal Functions table by pin number ............................................................................................................. 7
Changed Maximum SCK Frequency maximum timing specification ................................................................................... 10
Revised second paragraph of External 1.8V Core Supply section...................................................................................... 12
Changed fourth paragraph of SPI Interface section ............................................................................................................ 13
Added footnote to Figure 5 .................................................................................................................................................. 13
Changed Figure 11 ............................................................................................................................................................. 15
Changed seventh paragraph of First FIR Filter section....................................................................................................... 20
Changed second paragraph of Setting and Reading the RTC section ............................................................................... 29
Changed RANGE column of Table 17................................................................................................................................. 30
Changed Figure 20 ............................................................................................................................................................. 31
Changed Figure 21 ............................................................................................................................................................. 31
Changed Address 65 of Table 27 ........................................................................................................................................ 34
Changed Address 66 of Table 27 ........................................................................................................................................ 34
Changed range of Address 73 in Table 27.......................................................................................................................... 34
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