AD AD8451 Low cost, precision analog front end and controller for battery test/formation system Datasheet

Low Cost, Precision Analog Front End and
Controller for Battery Test/Formation Systems
AD8451
Data Sheet
FEATURES
GENERAL DESCRIPTION
Integrated constant current and voltage modes with
automatic switchover
Charge and discharge modes
Precision voltage and current measurement
Integrated precision control feedback blocks
Precision interface to PWM or linear power converters
Fixed gain settings
Current sense gain: 26 V/V (typ)
Voltage sense gain: 0.8 V/V (typ)
Excellent ac and dc performance
Maximum offset voltage drift: 0.9 µV/°C
Maximum gain drift: 3 ppm/°C
Low current sense amplifier input voltage noise: 9 nV/√Hz typ
Current sense CMRR: 108 dB min
TTL compliant logic
The AD8451 is a precision analog front end and controller for
testing and monitoring battery cells. A precision fixed gain
instrumentation amplifier (IA) measures the battery charge/
discharge current, and a fixed gain difference amplifier (DA)
measures the battery voltage (see Figure 1). Internal laser
trimmed resistor networks set the gains for the IA and the DA,
optimizing the performance of the AD8451 over the rated
temperature range. The IA gain is 26 V/V and the DA gain is
0.8 V/V.
Voltages at the ISET and VSET inputs set the desired constant
current (CC) and constant voltage (CV) values. CC to CV
switching is automatic and transparent to the system.
A TTL logic level input, MODE, selects the charge or discharge
mode (high for charge, and low for discharge). An analog output,
VCTRL, interfaces directly with the Analog Devices, Inc.,
ADP1972 pulse-width modulation (PWM) controller.
APPLICATIONS
The AD8451 simplifies designs by providing excellent accuracy,
performance over temperature, flexibility with functionality,
and overall reliability in a space-saving package. The AD8451 is
available in an 80-lead, 14 mm × 14 mm × 1.40 mm LQFP and
is rated for an operating temperature of −40°C to +85°C.
Battery cell formation and testing
Battery module testing
FUNCTIONAL BLOCK DIAGRAM
ISREFH/
ISREFL ISMEA
ISET IVE0/IVE1
VINT
AD8451
ISVP
MUX
CONSTANT
CURRENT LOOP
FILTER
26
ISVN
VCLP
×1
CURRENT
SENSE IA
VCTRL
VCLN
(CHARGE/
DISCHARGE)
SWITCHING
VOLTAGE
SENSE DA
BVP
0.8
CONSTANT
VOLTAGE LOOP
FILTER
BVN
BVREFH/
BVREFL
BVMEA
VSET VVE0/
VVE1
VVP0
VSETBF VINT
VOLTAGE
REFERENCE
VREF
12137-001
MODE
Figure 1.
Rev. 0
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AD8451* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
DISCUSSIONS
Application Notes
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• AN-1319: Compensator Design for a Battery Charge/
Discharge Unit Using the AD8450 or the AD8451
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Data Sheet
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AD8451
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
MODE Pin, Charge and Discharge Control ........................... 21
Applications ....................................................................................... 1
Applications Information .............................................................. 22
General Description ......................................................................... 1
Functional Description .............................................................. 22
Functional Block Diagram .............................................................. 1
Power Supply Connections ....................................................... 23
Revision History ............................................................................... 2
Current Sense IA Connections ................................................. 23
Specifications..................................................................................... 3
Voltage Sense DA Connections ................................................ 23
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
Battery Current and Voltage Control Inputs (ISET and VSET)
....................................................................................................... 23
ESD Caution .................................................................................. 6
Loop Filter Amplifiers ............................................................... 24
Pin Configuration and Function Descriptions ............................. 7
Connecting to a PWM Controller (VCTRL Pin) ...................... 24
Typical Performance Characteristics ............................................. 9
Step-by-Step Design Example................................................... 24
IA Characteristics ......................................................................... 9
Evaluation Board ............................................................................ 26
DA Characteristics ..................................................................... 11
Introduction ................................................................................ 26
CC and CV Loop Filter Amplifiers, and VSET Buffer .......... 13
Features and Tests....................................................................... 26
VINT Buffer ................................................................................ 15
Evaluating the AD8451.............................................................. 27
Reference Characteristics .......................................................... 16
Schematic and Artwork ............................................................. 28
Theory of Operation ...................................................................... 17
Outline Dimensions ....................................................................... 32
Overview...................................................................................... 17
Ordering Guide .......................................................................... 32
Instrumentation Amplifier (IA) ............................................... 18
Difference Amplifier (DA) ........................................................ 19
CC and CV Loop Filter Amplifiers .......................................... 19
REVISION HISTORY
3/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
AD8451
SPECIFICATIONS
AVCC = +15 V, AVEE = −15 V; DVCC = +5 V; TA = 25°C, unless otherwise noted.
Table 1.
Parameter
CURRENT SENSE INSTRUMENTATION AMPLIFIER
Internal Fixed Gain
Gain Error
Gain Drift
Gain Nonlinearity
Offset Voltage (RTI)
Offset Voltage Drift
Input Bias Current
Temperature Coefficient
Input Offset Current
Temperature Coefficient
Input Common-Mode Voltage Range
Over Temperature
Overvoltage Input Range
Differential Input Impedance
Input Common-Mode Impedance
Output Voltage Swing
Over Temperature
Capacitive Load Drive
Short-Circuit Current
Reference Input Voltage Range
Reference Input Bias Current
Output Voltage Level Shift
Maximum
Scale Factor
Common-Mode Rejection Ratio (CMRR)
Temperature Coefficient
Power Supply Rejection Ratio (PSRR)
Voltage Noise
Voltage Noise, Peak to Peak
Current Noise
Current Noise, Peak to Peak
Small Signal −3 dB Bandwidth
Slew Rate
VOLTAGE SENSE DIFFERENCE AMPLIFER
Internal Fixed Gains
Gain Error
Gain Drift
Gain Nonlinearity
Offset Voltage (RTO)
Offset Voltage Drift
Differential Input Voltage Range
Input Common-Mode Voltage Range
Differential Input Impedance
Input Common-Mode Impedance
Output Voltage Swing
Over Temperature
Capacitive Load Drive
Short-Circuit Current
Test Conditions/Comments
Min
Typ
Max
26
VISMEA = ±10 V
TA = TMIN to TMAX
VISMEA = ±10 V, RL = 2 kΩ
ISREFH and ISREFL pins grounded
TA = TMIN to TMAX
−110
15
TA = TMIN to TMAX
TA = TMIN to TMAX
VISVP − VISVN = 0 V
TA = TMIN to TMAX
AVEE + 2.3
AVEE + 2.6
AVCC − 55
±0.1
3
3
+110
0.9
30
150
2
10
AVCC − 2.4
AVCC − 2.6
AVEE + 55
150
150
TA = TMIN to TMAX
AVEE + 1.5
AVEE + 1.7
AVCC − 1.2
AVCC − 1.4
1000
40
ISREFH and ISREFL pins tied together
VISVP = VISVN = 0 V
ISREFL pin grounded
ISREFH pin connected to VREF pin
VISMEA/VISREFH
ΔVCM = 20 V
TA = TMIN to TMAX
ΔVS = 20 V
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
AVEE
AVCC
5
17
6.8
108
20
8
108
122
9
0.2
80
5
1.5
5
23
9.2
0.01
ΔVISMEA = 10 V
0.8
VIN = ±10 V
TA = TMIN to TMAX
VBVMEA = ±10 V, RL = 2 kΩ
BVREFH and BVREFL pins grounded
TA = TMIN to TMAX
VBVN = 0 V, VBVREFL = 0 V
VBVMEA = 0 V
±0.1
3
3
500
4
+16
+27
−16
−27
200
90
TA = TMIN to TMAX
AVEE + 1.5
AVEE + 1.7
AVCC − 1.5
AVCC − 1.7
1000
30
Rev. 0 | Page 3 of 32
Unit
V/V
%
ppm/°C
ppm
µV
µV/°C
nA
pA/°C
nA
pA/°C
V
V
V
GΩ
GΩ
V
V
pF
mA
V
µA
mV
mV/V
dB
µV/V/°C
dB
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
V/µs
V/V
%
ppm/°C
ppm
µV
µV/°C
V
V
kΩ
kΩ
V
V
pF
mA
AD8451
Parameter
Reference Input Voltage Range
Output Voltage Level Shift
Maximum
Scale Factor
CMRR
Temperature Coefficient
PSRR
Output Voltage Noise
Voltage Noise, Peak to Peak
Small Signal −3 dB Bandwidth
Slew Rate
CONSTANT CURRENT AND CONSTANT VOLTAGE
LOOP FILTER AMPLIFIERS
Offset Voltage
Offset Voltage Drift
Input Bias Current
Over Temperature
Input Common-Mode Voltage Range
Output Voltage Swing
Over Temperature
Closed-Loop Output Impedance
Capacitive Load Drive
Source Short-Circuit Current
Sink Short-Circuit Current
Open-Loop Gain
CMRR
PSRR
Voltage Noise
Voltage Noise, Peak to Peak
Current Noise
Current Noise, Peak to Peak
Small Signal Gain Bandwidth Product
Slew Rate
CC to CV Transition Time
VINT AND CONSTANT VOLTAGE BUFFER
Nominal Gain
Offset Voltage
Offset Voltage Drift
Input Bias Current
Over Temperature
Input Voltage Range
Output Voltage Swing
Current Sharing and Constant Voltage Buffers
Over Temperature
VINT Buffer
Over Temperature
Output Clamps Voltage Range
VCLP Pin
VCLN Pin
Closed-Loop Output Impedance
Capacitive Load Drive
Short-Circuit Current
PSRR
Data Sheet
Test Conditions/Comments
BVREFH and BVREFL pins tied together
BVREFL pin grounded
BVREFH pin connected to VREF pin
VBVMEA/VBVREFH
ΔVCM = 10 V, RTO
TA = TMIN to TMAX
ΔVS = 20 V, RTO
f = 1 kHz, RTI
f = 0.1 Hz to 10 Hz, RTI
Min
AVEE
Typ
Max
AVCC
Unit
V
4.5
1.8
80
5
2
5.5
2.2
mV
mV/V
dB
µV/V/°C
dB
nV/√Hz
µV p-p
MHz
V/µs
0.05
100
105
2
1
0.8
150
0.6
+5
+5
AVCC − 1.8
AVCC − 1
AVCC − 1
TA = TMIN to TMAX
TA = TMIN to TMAX
VVCLN = AVEE + 1 V, VVCLP = AVCC − 1 V
TA = TMIN to TMAX
−5
−5
AVEE + 1.5
AVEE + 1.5
AVEE + 1.7
0.01
1000
1
40
140
ΔVCM = 10 V
ΔVS = 20 V
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
100
100
10
0.3
80
5
3
1
1.5
ΔVVINT = 10 V
1
TA = TMIN to TMAX
CV buffer only
TA = TMIN to TMAX
TA = TMIN to TMAX
TA = TMIN to TMAX
VINT buffer only
−5
−5
AVEE + 1.5
150
0.6
+5
+5
AVCC − 1.8
V/V
µV
µV/°C
nA
nA
V
AVEE + 1.5
AVEE + 1.7
VVCLN − 0.6
VVCLN − 0.6
AVCC − 1.5
AVCC − 1.5
VVCLP + 0.6
VVCLP + 0.6
V
V
V
V
VVCLN
AVEE + 1
AVCC − 1
VVCLP
V
V
Ω
pF
mA
dB
1
1000
40
ΔVS = 20 V
Rev. 0 | Page 4 of 32
µV
µV/°C
nA
nA
V
V
V
Ω
pF
mA
mA
dB
dB
dB
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
V/µs
µs
100
Data Sheet
Parameter
Voltage Noise
Voltage Noise, Peak to Peak
Current Noise
Current Noise, Peak to Peak
Small Signal −3 dB Bandwidth
Slew Rate
VOLTAGE REFERENCE
Nominal Output Voltage
Output Voltage Error
Temperature Drift
Line Regulation
Load Regulation
Output Current, Sourcing
Voltage Noise
Voltage Noise, Peak to Peak
DIGITAL INTERFACE, MODE INPUT
Input Voltage High, VIH
Input Voltage Low, VIL
Mode Switching Time
POWER SUPPLY
Operating Voltage Range
AVCC
AVEE
Analog Supply Range
DVCC
Quiescent Current
AVCC
AVEE
DVCC
TEMPERATURE RANGE
For Specified Performance
Operational
AD8451
Test Conditions/Comments
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz, CV buffer only
f = 0.1 Hz to 10 Hz
Min
ΔVOUT = 10 V
Typ
10
0.3
80
5
3
1
With respect to AGND
2.5
±1
10
40
400
10
TA = TMIN to TMAX
ΔVS = 10 V
ΔIVREF = 1 mA (source only)
f = 1 kHz
f = 0.1 Hz to 10 Hz
MODE pin (Pin 39)
With respect to DGND
With respect to DGND
Max
100
5
2.0
DGND
AVCC − AVEE
7
6.5
40
−40
−55
Rev. 0 | Page 5 of 32
V
%
ppm/°C
ppm/V
ppm/mA
mA
nV/√Hz
µV p-p
DVCC
0.8
V
V
ns
36
0
36
5
V
V
V
V
10
10
70
mA
mA
µA
+85
+125
°C
°C
500
5
−31
5
3
Unit
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
V/µs
AD8451
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Analog Supply Voltage (AVCC − AVEE)
Digital Supply Voltage (DVCC − DGND)
Maximum Voltage at Any Input Pin
Minimum Voltage at Any Input Pin
Operating Temperature Range
Storage Temperature Range
The θJA value assumes a 4-layer JEDEC standard board with
zero airflow.
Rating
36 V
36 V
AVCC
AVEE
−40°C to +85°C
−65°C to +150°C
Table 3. Thermal Resistance
Package Type
80-Lead LQFP
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. 0 | Page 6 of 32
θJA
54.7
Unit
°C/W
Data Sheet
AD8451
ISVP 1
VINT
AVEE
69
NC
70
IVE1
71
IVE0
72
NC
73
ISREFB
NC
74
ISET
AVCC
75
ISMEA
76
AVEE
77
ISREFH
AGND
78
VREF
ISREFL
79
NC
80
ISREFLS
NC
NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
68
67
66
65
64
63
62
61
PIN 1
INDENTFIER
60 VCLP
59 VCTRL
RGP 2
NC 3
58 VCLN
NC 4
57 AVCC
NC 5
56 VINT
NC 6
55 NC
NC 7
54 VVE1
NC 8
53 VVE0
52 NC
NC 9
AD8451
NC 10
51 VVP0
50 VSETBF
NC 12
49 VSET
NC 13
48 NC
NC 14
47 DVCC
NC 15
46 NC
NC 16
45 DGND
NC 17
44 NC
NC 18
43 NC
29
30
31
32
33
34
35
36
37
38
39
40
NC
BVN
NC
NC
BVNS
AVEE
BVMEA
AVCC
MODE
NC
28
BVREFL
27
BVREFLS
26
AGND
25
BVREFH
24
NC
23
VREF
22
NC
21
BVP
41 NC
NC
42 VREF
ISVN 20
BVPS
RGN 19
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
12137-002
TOP VIEW
NC 11
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 20
Mnemonic
ISVP, ISVN
Input/Output 1
Input
2, 19
RGP, RGN
N/A
3 to 18, 21, 23, 25, 31, 33,
34, 40, 41, 43, 44, 46, 48,
52, 55, 63, 66, 69, 78 to 80
22, 35
24, 32
26, 42, 73
27
NC
N/A
BVPS, BVNS
BVP, BVN
VREF
BVREFH
Input
Input
Output
Input
28, 75
29
AGND
BVREFL
N/A
Input
30
BVREFLS
Input
Description
Current Sense Instrumentation Amplifier Positive (Noninverting) and Negative
(Inverting) Inputs. Connect these pins across the current sense shunt resistor.
Negative Input of the Preamplifiers of the Current Sense Instrumentation
Amplifier.
No Connect. Do not connect to this pin.
Kelvin Sense Pins for the BVP and BVN Voltage Sense Difference Amplifier Inputs.
Voltage Sense Difference Amplifier Inputs.
Voltage Reference Output Pins. VREF = 2.5 V.
Reference Input for the Voltage Sense Difference Amplifier. To level shift the
voltage sense difference amplifier output by approximately 5 mV, connect this
pin to the VREF pin. Otherwise, connect this pin to the BVREFL pin.
Analog Ground Pins.
Reference Input for the Voltage Sense Difference Amplifier. The default connection
is to ground.
Kelvin Sense Pin for the BVREFL Pin.
Rev. 0 | Page 7 of 32
AD8451
Data Sheet
Pin No.
36, 61, 72
37
38, 57, 70
39
Mnemonic
AVEE
BVMEA
AVCC
MODE
Input/Output 1
N/A
Output
N/A
Input
45
47
49
50
51
53
54
56, 62
58
59
DGND
DVCC
VSET
VSETBF
VVP0
VVE0
VVE1
VINT
VCLN
VCTRL
N/A
N/A
Input
Output
Input
Input
Input
Output
Input
Output
60
64
65
67
68
71
74
VCLP
IVE1
IVE0
ISET
ISREFB
ISMEA
ISREFH
Input
Input
Input
Input
Output
Output
Input
76
ISREFL
Input
77
ISREFLS
Input
1
Description
Analog Negative Supply Pins. The default voltage is −15 V.
Voltage Sense Difference Amplifier Output.
Analog Positive Supply Pins. The default voltage is 15 V.
TTL Compliant Logic Input Selects Charge or Discharge Mode. Low =
discharge, high = charge.
Digital Ground Pin.
Digital Supply. The default voltage is 5 V.
Target Voltage for the Voltage Sense Control Loop.
Buffered Voltage VSET.
Noninverting Input of the Voltage Sense Integrator for Discharge Mode.
Inverting Input Voltage for the Voltage Sense Integrator for Discharge Mode.
Inverting Input of the Voltage Sense Integrator for Charge Mode.
Minimum Output of the Voltage Sense and Current Sense Integrator Amplifiers.
Low Clamp Voltage for VCTRL.
Controller Output Voltage. Connect this pin to the input of the PWM controller
(for example, the COMP pin of the ADP1972).
High Clamp Voltage for VCTRL.
Inverting Input of the Current Sense Integrator for Charge Mode.
Inverting Input of the Current Sense Integrator for Discharge Mode.
Target Voltage for the Current Sense Control Loop.
Buffered Voltage ISREFL.
Current Sense Instrumentation Amplifier Output.
Reference Input for the Current Sense Amplifier. To level shift the current sense
instrumentation amplifier output by approximately 20 mV, connect this pin to
the VREF pin. Otherwise, connect this pin to the ISREFL pin.
Reference Input for the Current Sense Amplifier. The default connection is to
ground.
Kelvin Sense Pin for the ISREFL Pin.
N/A means not applicable.
Rev. 0 | Page 8 of 32
Data Sheet
AD8451
TYPICAL PERFORMANCE CHARACTERISTICS
AVCC = +15 V, AVEE = −15 V, TA = 25°C, and RL = ∞, unless otherwise noted.
30
20
25
15
20
15
10
5
0
−5
−10
−10
−5
0
15
10
5
OUTPUT VOLTAGE (V)
20
30
25
0
–5
–10
–15
0
–5
5
10
15
20
OUTPUT VOLTAGE (V)
Figure 3. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +25 V and AVEE = −5 V
Figure 6. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +15 V and AVEE = −15 V
15
15
10
AVCC = +15V
AVEE = –15V
10
INPUT CURRENT (mA)
INPUT CURRENT (mA)
5
AVCC = +15V
AVEE = –15V
–20
–20
–15
–10
12137-003
AVCC = +25V
AVEE = −5V
10
12137-006
INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
IA CHARACTERISTICS
5
0
–5
–10
5
0
–5
–10
0
5
10 15 20 25 30 35 40 45
INPUT VOLTAGE (V)
–15
–45 –40 –35 –30 –25 –20 –15 –10 –5 0
12137-004
–15
–35 –30 –25 –20 –15 –10 –5
5 10 15 20 25 30 35 40 45
INPUT VOLTAGE (V)
Figure 4. Input Overvoltage Performance
for AVCC = +25 V and AVEE = −5 V
12137-007
AVCC = +25V
AVEE = –5V
Figure 7. Input Overvoltage Performance
for AVCC = +15 V and AVEE = −15 V
17.0
20
16.8
19
INPUT BIAS CURRENT (nA)
16.4
AVCC = +15V
AVEE = –15V
16.2
16.0
AVCC = +25V
AVEE = –5V
15.8
15.6
18
17
+IB
16
–IB
15
14
15.4
15.0
–15
–10
–5
0
5
10
15
20
25
INPUT COMMON-MODE VOLTAGE (V)
12
–40 –30 –20 –10
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
Figure 5. Input Bias Current vs. Input Common-Mode Voltage
Figure 8. Input Bias Current vs. Temperature
Rev. 0 | Page 9 of 32
80
90
12137-008
13
15.2
12137-005
INPUT BIAS CURRENT (nA)
16.6
AD8451
Data Sheet
160
20
150
0
140
GAIN ERROR (µV/V)
130
CMRR (dB)
–20
–40
120
110
100
90
–60
80
70
–80
0
10
20
30
40
50
60
70
90
80
TEMPERATURE (°C)
50
0.1
12137-009
–100
–40 –30 –20 –10
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 9. Gain Error vs. Temperature
12137-012
60
Figure 12. CMRR vs. Frequency
0.3
160
AVCC = +25V
AVEE = –5V
140
0.2
120
AVCC
PSRR (dB)
CMRR (µV/V)
0.1
0
100
80
AVEE
60
–0.1
40
–0.2
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
0
12137-010
–0.3
–40 –30 –20 –10
1
10
10k
100k
1M
10k
100k
Figure 13. PSRR vs. Frequency
50
30
20
10
0
10k
100 k
FREQUENCY (Hz)
1M
10M
12137-011
−10
Figure 11. Gain vs. Frequency
RTI
10
1
0.1
1
10
100
1k
FREQUENCY (Hz)
Figure 14. Spectral Density Voltage Noise, RTI vs. Frequency
Rev. 0 | Page 10 of 32
12137-014
SPECTRAL DENSITY VOLTAGE NOISE (nV/√Hz)
100
40
GAIN (dB)
1k
FREQUENCY (Hz)
Figure 10. Normalized CMRR vs. Temperature
AVCC = +15V
AVEE = −15V
−20
1k
100
100
12137-013
20
Data Sheet
AD8451
50
50
40
40
30
20
10
0
–10
–20
–30
–40
–10
0
5
10
15
20
25
30
OUTPUT VOLTAGE (V)
10
0
–10
–20
–30
–50
–20
–15
–10
0
–5
5
15
10
20
Figure 15. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +25 V and AVEE = −5 V
Figure 18. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +15 V and AVEE = −15 V
0
50
–10
0
–20
–30
–50
–100
10k
100k
1M
FREQUENCY (Hz)
–200
–40 –30 –20 –10
12137-016
30
40
50
60
70
80
90
3
2
–40
1
CMRR (µV/V)
–20
–60
0
–1
–100
–2
10k
100k
FREQUENCY (Hz)
1M
12137-017
–80
1k
20
Figure 19. Gain Error vs. Temperature
VALID FOR ALL RATED
SUPPLY VOLTAGES
–120
100
10
TEMPERATURE (°C)
Figure 16. Gain vs. Frequency
0
0
Figure 17. CMRR vs. Frequency
–3
–40 –30 –20 –10
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
Figure 20. Normalized CMRR vs. Temperature
Rev. 0 | Page 11 of 32
80
90
12137-020
VALID FOR ALL RATED
SUPPLY VOLTAGES
–50
100
1k
12137-019
–150
–40
CMRR (dB)
AVCC = +15V
AVEE = −15V
OUTPUT VOLTAGE (V)
GAIN ERROR (ppm)
GAIN (dB)
20
–40
AVCC = +25V
AVEE = −5V
–5
30
12137-018
INPUT COMMON-MODE VOLTAGE (V)
60
12137-015
INPUT COMMON-MODE VOLTAGE (V)
DA CHARACTERISTICS
AD8451
Data Sheet
0
SPECTRAL DENSITY VOLTAGE NOISE (nV/√Hz)
1k
–20
AVEE
–60
RTI
100
–80
AVCC
–100
–120
10
100
1k
10k
FREQUENCY (Hz)
100k
12137-021
VALID FOR ALL RATED
SUPPLY VOLTAGES
–140
Figure 21. PSRR vs. Frequency
10
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 22. Spectral Density Voltage Noise, RTI vs. Frequency
Rev. 0 | Page 12 of 32
12137-022
PSRR (dB)
–40
Data Sheet
AD8451
500
2.0
400
1.8
OUTPUT SOURCE CURRENT (mA)
300
AVCC = +25V
AVEE = –5V
100
0
–100
–200
–300
1.6
1.4
1.0
AVCC = +15V
AVEE = –15V
0.8
0.6
0.4
–400
0.2
–10
–5
0
5
10
15
20
25
INPUT COMMON-MODE VOLTAGE (V)
0
–40 –30 –20 –10
12137-023
–500
–15
AVCC = +25V
AVEE = –5V
1.2
0
10
Figure 23. Input Offset Voltage vs. Input Common-Mode Voltage
for Two Supply Voltage Combinations
90
AVCC = +25V
AVEE = –5V
OPEN-LOOP GAIN (dB)
INPUT BIAS CURRENT (pA)
40
50
60
70
80
90
120
–45.0
100
–67.5
80
60
50
40
30
Figure 26. Output Source Current vs. Temperature
for Two Supply Voltage Combinations
100
70
20
TEMPERATURE (°C)
12137-026
200
AVCC = +15V
AVEE = –15V
CONSTANT CURRENT LOOP AND
CONSTANT VOLTAGE LOOP AMPLIFIERS
AVCC = +15V
AVEE = –15V
30
PHASE
80
–90.0
–112.5
60
–135.0
40
GAIN
20
–157.5
0
–180.0
–20
–202.5
PHASE (Degrees)
INPUT OFFSET VOLTAGE (µV)
CC AND CV LOOP FILTER AMPLIFIERS, AND VSET BUFFER
20
–5
0
5
10
15
20
25
INPUT COMMON-MODE VOLTAGE (V)
–40
10
100
10k
100k
1M
–225.0
10M
FREQUENCY (Hz)
Figure 24. Input Bias Current vs. Input Common-Mode Voltage
for Two Supply Voltage Combinations
Figure 27. Open-Loop Gain and Phase vs. Frequency
100
160
80
140
120
CMRR (dB)
60
40
20
0
100
80
60
40
–20
–40
–40 –30 –20 –10
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
80
CONSTANT CURRENT LOOP
AND
CONSTANT VOLTAGE
LOOP FILTER
AMPLIFIERS
20
–IB
+IB
90
12137-025
INPUT BIAS CURRENT (nA)
1k
12137-027
–10
Figure 25. Input Bias Current vs. Temperature
0
10
100
1k
10k
FREQUENCY (Hz)
Figure 28. CMRR vs. Frequency
Rev. 0 | Page 13 of 32
100k
1M
12137-028
0
–15
12137-024
10
AD8451
Data Sheet
1.5
140
120
1.0
OUTPUT VOLTAGE (V)
+PSRR
PSRR (dB)
100
80
60
–PSRR
40
AVCC = +15V
AVEE = –15V
0.5
TRANSITION
0
–0.5
–1.0
20
ISET
1k
10k
100k
1M
FREQUENCY (Hz)
12137-029
100
–1.5
–15
10
100
1k
10k
100k
FREQUENCY (Hz)
12137-030
SPECTRAL DENSITY VOLTAGE NOISE (nV/√Hz)
100
10
0
5
10
15
20
Figure 31. CC to CV Transition
1k
1
–5
TIME (µs)
Figure 29. PSRR vs. Frequency
1
0.1
–10
Figure 30. Range of Spectral Density Voltage Noise vs. Frequency
for the Op Amps and Buffers
Rev. 0 | Page 14 of 32
25
30
35
12137-031
VCTRL
0
10
Data Sheet
AD8451
VINT BUFFER
0.5
6
CL = 100pF
RL = 2kΩ
VCTRL OUTPUT WITH RESPECT TO VCLP
0.4
0.3
0.2
0.1
VCLP AND VCLN REFERENCE
0
VALID FOR ALL RATED
SUPPLY VOLTAGES
–0.1
4
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE SWING (V)
5
–0.2
3
2
1
–0.3
VCTRL OUTPUT WITH RESPECT TO VCLN
0
–0.4
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
–1
0
15
20
25
30
35
40
Figure 35. Large Signal Transient Response, RL = 2 kΩ, CL = 100 pF
15
0.20
CL = 10pF
CL = 100pF
CL = 510pF
CL = 680pF
CL = 1000pF
0.15
OUTPUT VOLTAGE (V)
VCLP
10
5
TEMP = –40°C
TEMP = +25°C
TEMP = +85°C
0
–5
0.10
0.05
0
–0.05
–0.10
VCLN
–15
100
1k
–0.15
10k
100k
1M
LOAD RESISTANCE (Ω)
–0.20
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
12137-036
–10
12137-033
Figure 36. Small Signal Transient Response vs. Capacitive Load
Figure 33. Output Voltage Swing vs. Load Resistance at Three Temperatures
100
6
5
OUTPUT IMPEDANCE (Ω)
VCLP
4
3
TEMP = –40°C
TEMP = 0°C
TEMP = +25°C
TEMP = +85°C
VIN = +6V/–1V
2
1
10
1
VCLN
0
15
20
25
30
35
OUTPUT CURRENT (mA)
40
0.1
10
12137-034
–1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 34. Clamped Output Voltage vs. Output Current
at Four Temperatures
Figure 37. Output Impedance vs. Frequency
Rev. 0 | Page 15 of 32
1M
12137-037
OUTPUT VOLTAGE SWING (V)
10
TIME (µs)
Figure 32. Output Voltage Swing with Respect to VCLP and VCLN
vs. Temperature
CLAMPED OUTPUT VOLTAGE (V)
5
12137-035
0
12137-032
–0.5
–40 –30 –20 –10
AD8451
Data Sheet
REFERENCE CHARACTERISTICS
2.51
AVCC = +25V
AVEE = –5V
1100
LOAD REGULATION (ppm/mA)
2.50
OUTPUT VOLTAGE (V)
1200
TA = +85°C
TA = +25°C
TA = 0°C
TA = –20°C
TA = –40°C
2.49
2.48
2.47
1000
900
800
700
1
2
3
4
5
6
7
8
9
10
OUTPUT CURRENT—SOURCING (mA)
600
–40 –30 –20 –10
2.7
2.6
2.5
2.4
–10
TA = +85°C
TA = +25°C
TA = 0°C
TA = –20°C
TA = –40°C
–9
–8
–7
–6
–5
–4
–3
–2
OUTPUT CURRENT—SINKING (mA)
–1
0
12137-039
OUTPUT VOLTAGE (V)
2.8
30
50
40
60
70
80
90
Figure 40. Source and Sink Load Regulation vs. Temperature
SPECTRAL DENSITY VOLTAGE NOISE (nV/√Hz)
AVCC = +25V
AVEE = –5V
20
TEMPERATURE (°C)
Figure 38. Output Voltage vs. Output Current (Sourcing) over Temperature
2.9
10
0
Figure 39. Output Voltage vs. Output Current (Sinking) over Temperature
Rev. 0 | Page 16 of 32
1k
100
10
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 41. Spectral Density Voltage Noise vs. Frequency
100k
12137-041
0
12137-038
2.46
12137-040
AVCC = +25V
AVEE = –5V
Data Sheet
AD8451
THEORY OF OPERATION
OVERVIEW
The AD8451 provides two control loops—CC loop and a CV
loop—that transition automatically after the battery reaches the
user defined target voltage. These loops are implemented via two
precision specialty amplifiers with external feedback networks
that set the transfer function of the CC and CV loops.
Moreover, in the AD8451, these loops reconfigure themselves to
charge or discharge the battery by toggling the MODE pin.
To form and test a battery, the battery must undergo charge and
discharge cycles. During these cycles, the battery terminal current
and voltage must be precisely controlled to prevent battery failure
or a reduction in the capacity of the battery. Therefore, battery
formation and test systems require a high precision analog front
end to monitor the battery current and terminal voltage. The
analog front end of the AD8451 includes a precision current
sense fixed gain instrumentation amplifier (IA) to measure the
battery current and a precision voltage sense fixed gain difference
amplifier (DA) to measure the battery voltage.
Figure 42 is a block diagram of the AD8451 that illustrates
the distinct sections of the AD8451, including the IA and DA
measurement blocks, and the loop filter amplifiers. Figure 43 is a
block diagram of a battery formation and test system.
80
69
AVEE
VINT
53
19.2kΩ
–
9
AVEE
BATTERY
CURRENT
SENSING IA
52
VSET
BUFFER
10kΩ
10
51
+
11
1667Ω
10kΩ
–
1×
CONSTANT
CURRENT AND
VOLTAGE LOOP
FILTER AMPLIFIERS
20kΩ
50
49
13
48
14
47
VCLP
VCTRL
VCLN
AVCC
VINT
NC
VVE1
VVE0
NC
VVP0
VSETBF
VSET
NC
AD8451
46
15
10kΩ
100kΩ
18
–
+/–
19
+
+
–
BATTERY
VOLTAGE
SENSING
DA
17
45
44
80kΩ
43
100kΩ
16
100Ω
31
32
33
34
35
Figure 42. Detailed Block Diagram
Rev. 0 | Page 17 of 32
36
37
38
39
DGND
NC
NC
NC
40
NC
30
MODE
29
AVCC
28
NC
27
BVN
26
NC
25
BVREFLS
24
BVREFL
23
41
AGND
22
BVREFH
21
NC
VREF
MODE
20
DVCC
42
50kΩ
ISVN
54
+
8
NC
RGN
NC
CV LOOP
FILTER
AMPLIFIER
BVP
NC
56
AVCC
NC
NC
57
55
BVPS
NC
59
AVEE
6
NC
NC
IVE1
+
1.1mA
NC
NC
60
58
CC LOOP
FILTER
AMPLIFIER
10kΩ
12
NC
IVE0
1×
4
79.9kΩ
NC
61
62
–
+
–
VREF
NC
63
64
1×
+/–
5
65
VINT
BUFFER
NC
NC
66
67
7
NC
NC
ISET
ISREFB
68
ISREFL
BUFFER
MODE
3
NC
AVCC
ISMEA
70
71
2.5V
VREF
12137-042
2
AVEE
ISREFH
AGND
ISREFL
ISREFLS
NC
VREF
72
73
BVMEA
NC
74
AVEE
NC
75
76
BVNS
NC
77
NC
NC
78
100kΩ
RGP
79
1
806Ω
ISVP
NC
NC
Battery formation and test systems charge and discharge batteries
using a constant current/constant voltage (CC/CV) algorithm. In
other words, the system first forces a set constant current into
or out of the battery until the battery voltage reaches a target
value. At this point, a set constant voltage is forced across the
battery terminals.
AD8451
SET
BATTERY
CURRENT
Data Sheet
CONSTANT
VOLTAGE LOOP
FILTER AMPLIFIER
ISET
V1
VINT
BUFFER
+
–
1×
CONSTANT
CURRENT LOOP
FILTER AMPLIFIER
MODE
SWITCHES
(3)
D
D C
IVE0
DC
VVE0
VSETBF
1×
CV
BUFFER
IVE1
C
VVE1
V2
POWER CONVERTER
SWITCHED OR LINEAR
+
–
VSET
VVP0
SET
BATTERY
VOLTAGE
VCTRL
AVEE
C = CHARGE
D = DISCHARGE
BATTERY
CURRENT
AD8451
CONTROLLER
VINT
ISVP
+
SENSE
RESISTOR
IA
ISVN
–
ISMEA
SYSTEM LOOP COMPENSATION
BVP
+
BVMEA
BATTERY
DA
–
BVN
12137-043
EXTERNAL
PASSIVE
COMPENSATION
NETWORK
Figure 43. Signal Path of an Li-Ion Battery Formation and Test System Using the AD8451
INSTRUMENTATION AMPLIFIER (IA)
Reversing Polarity When Charging and Discharging
Figure 43 shows that during the charge cycle, the power converter
feeds current into the battery, generating a positive voltage across
the current sense resistor. During the discharge cycle, the power
converter draws current from the battery, generating a negative
voltage across the sense resistor. In other words, the battery current
polarity reverses when the battery discharges.
In the CC control loop, this change in polarity can be problematic
if the polarity of the target current is not reversed. To solve this
problem, the AD8451 IA includes a multiplexer preceding its
inputs that inverts the polarity of the IA gain. This multiplexer
is controlled via the MODE pin. When the MODE pin is logic
high (charge mode), the IA gain is noninverting, and when the
MODE pin is logic low (discharge mode), the IA gain is
inverting.
+CURRENT
SHUNT
ISVP
±
RGP
100kΩ ISREFH
IA
10kΩ
+
19.2kΩ 806Ω ISREFL
–
10kΩ
G = 2 SUBTRACTOR
+
1667Ω
ISMEA
–
10kΩ
RGN
–CURRENT
SHUNT
–
ISVN
10kΩ
20kΩ
+
±
POLARITY
INVERTER
MODE
Figure 44. IA Simplified Block Diagram
IA Offset Option
As shown in Figure 44, the IA reference node is connected to
the ISREFL and ISREFH pins via an internal resistor divider.
This resistor divider can be used to introduce a temperature
insensitive offset to the output of the IA such that it always
reads a voltage higher than zero for a zero differential input.
Because the output voltage of the IA is always positive, a
unipolar analog-to-digital converter (ADC) can digitize it.
Rev. 0 | Page 18 of 32
12137-044
Figure 44 is a block diagram of the IA, which is used to monitor the
battery current. The architecture of the IA is the classic 3-op-amp
topology, similar to the Analog Devices industry-standard
AD8221 and AD620, with a fixed gain of 26. This architecture
provides the highest achievable CMRR at a given gain, enabling
high-side battery current sensing without the introduction of
significant errors in the measurement. For more information
about instrumentation amplifiers, see A Designer's Guide to
Instrumentation Amplifiers.
VREF
POLARITY
INVERTER
Data Sheet
AD8451
When the ISREFH pin is tied to the VREF pin with the ISREFL
pin grounded, the voltage at the ISMEA pin is increased by 20 mV,
guaranteeing that the output of the IA is always positive for zero
differential inputs. Other voltage shifts can be realized by tying
the ISREFH pin to an external voltage source. The gain from the
ISREFH pin to the ISMEA pin is 8 mV/V. For zero offset, tie
the ISREFL and ISREFH pins to ground.
The resistors that form the DA gain network are laser trimmed
to a matching level better than ±0.1%. This level of matching
minimizes the gain error and gain error drift of the DA while
maximizing the CMRR of the DA. This matching also allows
the controller to set a stable target voltage for the battery over
temperature while rejecting the ground bounce in the battery
negative terminal.
Battery Reversal and Overvoltage Protection
Like the IA, the DA can also level shift its output voltage via an
internal resistor divider that is tied to the DA reference node. This
resistor divider is connected to the BVREFH and BVREFL pins.
The AD8451 IA can be configured for high-side or low-side
current sensing. If the IA is configured for high-side current
sensing (see Figure 43) and the battery is connected backward,
the IA inputs may be held at a voltage that is below the negative
power rail (AVEE), depending on the battery voltage.
To prevent damage to the IA under these conditions, the IA
inputs include overvoltage protection circuitry that allows them
to be held at voltages of up to 55 V from the opposite power
rail. In other words, the safe voltage span for the IA inputs
extends from AVCC − 55 V to AVEE + 55 V.
DIFFERENCE AMPLIFIER (DA)
Figure 45 is a block diagram of the DA, which is used to monitor
the battery voltage. The architecture of the DA is a subtractor
amplifier with a fixed gain of 0.8. This gain value allows the DA to
funnel the voltage of a 5 V battery to a level that can be read by
a 5 V ADC with a 4.096 V reference.
BVP 100kΩ
DA
79.9kΩ
VREF
BVMEA
Figure 45. DA Simplified Block Diagram
12137-045
80kΩ
The CC and CV loop filter amplifiers are high precision, low
noise specialty amplifiers with very low offset voltage and very
low input bias current. These amplifiers serve two purposes:
•
•
–
BVN 100kΩ
CC AND CV LOOP FILTER AMPLIFIERS
100kΩ BVREFL
50kΩ BVREFH
+
When the BVREFH pin is tied to the VREF pin with the BVREFL
pin grounded, the voltage at the BVMEA pin is increased by 5 mV,
guaranteeing that the output of the DA is always positive for
zero differential inputs. Other voltage shifts can be realized by
tying the BVREFH pin to an external voltage source. The gain
from the BVREFH pin to the BVMEA pin is 2 mV/V. For zero
offset, tie the BVREFL and BVREFH pins to ground.
Using external components, the amplifiers implement active
loop filters that set the dynamics (transfer function) of the
CC and CV loops.
The amplifiers perform a seamless transition from CC to
CV mode after the battery reaches its target voltage.
Figure 46 is the functional block diagram of the AD8451 CC
and CV feedback loops for charge mode (MODE logic pin is high).
For illustration purposes, the external networks connected to
the loop amplifiers are simple RC networks configured to form
single-pole inverting integrators. The outputs of the CC and CV
loop filter amplifiers are coupled to the VINT pins via an analog
NOR circuit (minimum output selector circuit), such that they can
only pull the VINT node down. In other words, the loop amplifier
that requires the lowest voltage at the VINT pins is in control of
the node. Thus, only one loop amplifier, CC or CV, can be in
control of the system charging control loop at any given time.
Rev. 0 | Page 19 of 32
AD8451
Data Sheet
CURRENT
POWER
VCTRL BUS
IOUT
IBAT
ISVP
SENSE
RESISTOR
R1
V1
RS
ISVN
IA
+
GIA
ISMEAS
ISET
IVE1
C1
–
POWER
CONVERTER
CC LOOP
AMPLIFIER
VINT
VINT
BUFFER
VCLP
–
+
ANALOG
‘NOR’
+
MINIMUM
OUTPUT
SELECTOR
1×
BVP
BVN
DA
+
GDA
–
MODE
5V
–
BVMEA
VSET
VVE1
CV LOOP
AMPLIFIER
VCLN
V3
V4
VINT
V3 < VCTRL < V4
V2
12137-046
+
VBAT
–
VCTRL
C2
R2
Figure 46. Functional Block Diagram of the CC and CV Loops in Charge Mode (MODE Pin High)
1.00
where:
IBAT_SS = is the steady state charging current.
GIA is the IA gain.
RS is the value of the shunt resistor.
3
0.50
2
1
CC
CHARGE
ENDS
0
0
0
1
2
3
TIME (Hours)
4
5
Figure 47. Representative Constant Current to Constant Voltage Transition
near the End of a Battery Charging Cycle
VVSET
G DA
2.
where:
VBAT_SS = steady state battery voltage.
GDA is the DA gain.
Because the offset voltage of the loop amplifiers is in series with
the target voltage sources, VISET and VVSET, the high precision of
these amplifiers minimizes this source of error.
Figure 47 shows a typical CC/CV charging profile for a Li-Ion
battery. In the first stage of the charging process, the battery is
charged with a CC of 1 A. When the battery voltage reaches a
target voltage of 4.2 V, the charging process transitions such that
the battery is charged with a CV of 4.2 V.
The following steps describe how the AD8451 implements the
CC/CV charging profile (see Figure 46). In this scenario, the
battery begins in the fully discharged state, and the system has
just been turned on such that IBAT = 0 A at Time 0.
1.
0.75
0.25
The target voltage is set at
VBAT_SS =
4
VOLTAGE (V)
VISET
G IA × RS
5
TRANSITION FROM CC TO CV
CC
CHARGE
BEGINS
12137-047
IBAT_SS =
1.25
CURRENT (A)
The unity-gain amplifier (VINT buffer) buffers the VINT pins
and drives the VCTRL pin. The VCTRL pin is the control output
of the AD8451 and the control input of the power converter. The
VISET and VVSET voltage sources set the target constant current and
the target constant voltage, respectively. When the CC and CV
feedback loops are in a steady state, the charging current is set at
3.
4.
5.
Because the voltages at the ISMEA and BVMEA pins
are less than the target voltages (VISET and VVSET) at Time 0,
both integrators begin to ramp, increasing the voltage at
the VINT node.
Rev. 0 | Page 20 of 32
As the voltage at the VINT node increases, the voltage at
the VCRTL node rises, and the output current of the power
converter, IBAT, increases (assuming that an increasing voltage
at the VCRTL node increases the output current of the
power converter).
When the IBAT current reaches the CC steady state value,
IBAT_SS, the battery voltage is still less than the target steady
state value, VBAT_SS. Therefore, the CV loop tries to keep
pulling the VINT node up while the CC loop tries to keep
it at its current voltage. At this point, the voltage at the ISMEA
pin equals VISET; therefore, the CC loop stops integrating.
Because the loop amplifiers can only pull the VINT node
down due to the analog NOR circuit, the CC loop takes
control of the charging feedback loop, and the CV loop is
disabled.
As the charging process continues, the battery voltage
increases until it reaches the steady state value, VBAT_SS, and
the voltage at the BVMEA pin reaches the target voltage, VVSET.
Data Sheet
6.
7.
AD8451
the internal switches in the CC and CV amplifiers, the frequency
response of the loops in charge mode does not affect the
frequency response of the loops in discharge mode.
The CV loop tries to pull the VINT node down to reduce
the charging current (IBAT) and prevent the battery voltage
from rising any further. At the same time, the CC loop tries
to keep the VINT node at its current voltage to keep the
battery current at IBAT_SS.
Because the loop amplifiers can only pull the VINT node
down due to the analog NOR circuit, the CV loop takes
control of the charging feedback loop, and the CC loop is
disabled.
Unlike simpler controllers that use passive networks to ground
for frequency compensation, the AD8451 allows the use of
feedback networks for its CC and CV loop filter amplifiers.
These networks enable the implementation of both
proportional differentiator (PD) Type II and proportional
integrator differentiator (PID) Type III compensators. Note
that in charge mode, both the CC and CV loops implement
inverting compensators, whereas in discharge mode, the CC
loop implements an inverting compensator, and the CV loop
implements a noninverting compensator. As a result, the CV loop
in discharge mode includes an additional amplifier, VSET buffer, to
buffer the VSET node from the feedback network (see Figure 48).
The analog NOR (minimum output selector) circuit that couples
the outputs of the loop amplifiers is optimized to minimize the
transition time from CC to CV control. Any delay in the transition
causes the CC loop to remain in control of the charge feedback
loop after the battery voltage reaches its target value. Therefore,
the battery voltage continues to rise beyond VBAT_SS until the
control loop transitions; that is, the battery voltage overshoots
its target voltage. When the CV loop takes control of the charge
feedback loop, it reduces the battery voltage to the target voltage.
A large overshoot in the battery voltage due to transition delays
can damage the battery; thus, it is crucial to minimize delays by
implementing a fast CC to CV transition.
VINT Buffer
The unity-gain amplifier (VINT buffer) is a clamp amplifier
that drives the VCTRL pin. The VCTRL pin is the control
output of the AD8451 and the control input of the power
converter (see Figure 46 and Figure 48). The output voltage
range of this amplifier is bounded by the clamp voltages at the
VCLP and VCLN pins such that
Figure 48 is the functional block diagram of the AD8451 CC
and CV feedback loops for discharge mode (MODE logic pin is
low). In discharge mode, the feedback loops operate in a similar
manner as in charge mode. The only difference is in the CV
loop amplifier, which operates as a noninverting integrator in
discharge mode. For illustration purposes, the external networks
connected to the loop amplifiers are simple RC networks
configured to form single-pole integrators (see Figure 48).
The reduction in the output voltage range of the amplifier is a
safety feature that allows the AD8451 to drive devices such as
the ADP1972 PWM controller, whose input voltage range must
not exceed 5.5 V (that is, the voltage at the COMP pin of the
ADP1972 must be below 5.5 V).
Compensation
MODE PIN, CHARGE AND DISCHARGE CONTROL
In battery formation and test systems, the CC and CV feedback
loops have significantly different open-loop gain and crossover
frequencies; therefore, each loop requires its own frequency
compensation. The active filter architecture of the AD8451 CC
and CV loops allows the frequency response of each loop to be
set independently via external components. Moreover, due to
The MODE pin is a TTL logic input that configures the AD8451
for either charge or discharge mode. A logic low (VMODE < 0.8 V)
corresponds to discharge mode, and a logic high (VMODE > 2 V)
corresponds to charge mode. Internal to the AD8451, the MODE
pin toggles all single-pole, double throw (SPDT) switches in the
CC and CV loop amplifiers and inverts the gain polarity of the IA.
VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V
CURRENT
POWER
VCTRL BUS
IOUT
ISVP
+
VBAT
–
RS
ISVN
BVP
BVN
MODE
IA ISMEAS
+
GIA
ISET
IVE0
CC LOOP
AMPLIFIER
VINT
VINT
BUFFER
ANALOG
‘NOR’
+
MINIMUM
OUTPUT
SELECTOR
–
1×
VSET
+
1×
VSET
BUFFER
–
BVMEA
–
POWER
CONVERTER
VCLP
–
DA
+
GDA
C1
VSETBF
VVP0
VVE0
CV LOOP
AMPLIFIER
VCTRL
VCLN
V3
V4
VINT
V3 < VCTRL < V4
V2
R2
R2
C2
C2
Figure 48. Functional Block Diagram of the CC and CV Loops in Discharge Mode (MODE Pin Low)
Rev. 0 | Page 21 of 32
12137-048
SENSE
RESISTOR
R1
V1
IBAT
AD8451
Data Sheet
APPLICATIONS INFORMATION
This section describes how to use the AD8451 in the context of
a battery formation and test system. This section includes a
design example of a small scale model of an actual system.
•
FUNCTIONAL DESCRIPTION
•
The AD8451 is a precision analog front end and controller for
battery formation and test systems. These systems use precision
controllers and power stages to put batteries through charge and
discharge cycles. Figure 49 shows the signal path of a simplified
switching battery formation and test system using the AD8451
controller and the ADP1972 PWM controller. For more
information on the ADP1972, see the ADP1972 data sheet.
The AD8451 is suitable for systems that form and test NiCad,
NiMH, and Li-Ion batteries and is designed to operate in
conjunction with both linear and switching power stages.
A logic input pin (MODE) that changes the configuration of the
controller from charge to discharge mode. A logic high at the
MODE pin configures charge mode; a logic low configures
discharge mode.
A fixed gain IA that senses low-side or high-side battery
current.
A fixed gain DA that measures the terminal voltage of the
battery.
SET
BATTERY
CURRENT
ISET
CONSTANT
VOLTAGE LOOP
FILTER AMPLIFIER
1×
IVE0
IVE1
ADP1972
PWM
LEVEL
SHIFTER
OUTPUT
FILTER
OUTPUT
DRIVERS
DC-TO-DC POWER CONVERTER
MODE
SWITCHES
(3)
D
DC
VVE0
DC
VVE1
C
1×
CV
BUFFER
VCTRL
+
–
VSET
VVP0
AVEE
C = CHARGE
D = DISCHARGE
BATTERY
CURRENT
AD8451
CONTROLLER
VINT
ISVP
+
IA
–
ISVN
SENSE
RESISTOR
ISMEA
BVMEA
+
DA
EXTERNAL
PASSIVE
COMPENSATION
NETWORK
–
BVP
BATTERY
BVN
12137-049
SET
BATTERY
VOLTAGE
AVCC
VINT
BUFFER
+
–
CONSTANT
CURRENT LOOP
FILTER AMPLIFIER
VSETBF
•
•
•
The AD8451 includes the following blocks (see Figure 42 and
the Theory of Operation section for more information).
•
Two loop filter error amplifiers that receive the battery target
current and voltage and establish the dynamics of the CC and
CV feedback loops.
A minimum output selector circuit that combines the
outputs of the loop filter error amplifiers to perform
automatic CC to CV switching.
An output clamp amplifier that drives the VCTRL pin. The
voltage range of this amplifier is limited by the voltage at
the VCLP and VCLN pins such that it cannot overrange
the subsequent stage. The output clamp amplifier can drive
switching and linear power converters. Note that an
increasing voltage at the VCTRL pin must translate to a
larger output current in the power converter.
A 2.5 V reference whose output node is the VREF pin.
Figure 49. Complete Signal Path of a Battery Test or Formation System Suitable for Li-Ion Batteries
Rev. 0 | Page 22 of 32
Data Sheet
AD8451
POWER SUPPLY CONNECTIONS
Optional Low-Pass Filter
The AD8451 requires two analog power supplies (AVCC and
AVEE), one digital power supply (DVCC), one analog ground
(AGND), and one digital ground (DGND). AVCC and AVEE
power all the analog blocks, including the IA, DA, and op amps,
and DVCC powers the MODE input logic. AGND provides a
reference and return path for the 2.5 V reference, and DGND
provides a reference and return path for the digital circuitry.
The AD8451 is designed to control both linear regulators and
switching power converters. Linear regulators are generally
noise free, whereas switch mode power converters generate
switching noise. Connecting an external differential low-pass
filter between the current sensor and the IA inputs reduces the
injection of switching noise into the IA (see Figure 50).
ISVP
Connect decoupling capacitors to all the supply pins. A 1 µF
capacitor in parallel with a 0.1 µF capacitor is recommended.
CURRENT SENSE IA CONNECTIONS
For a description of the IA, see the Theory of Operation section,
Figure 42, and Figure 44. The IA fixed gain is 26.
Current Sensors
Two common options for current sensors are isolated current
sensing transducers and shunt resistors. Isolated current sensing
transducers are galvanically isolated from the power converter
and are affected less by the high frequency noise generated by
switch mode power supplies. Shunt resistors are less expensive
and easier to deploy.
If a shunt resistor sensor is used, a 4-terminal, low resistance shunt
resistor is recommended. Two of the four terminals conduct the
battery current, whereas the other two terminals conduct virtually
no current. The terminals that conduct no current are sense
terminals that are used to measure the voltage drop across the
resistor (and, therefore, the current flowing through it) using an
amplifier such as the IA of the AD8451. To interface the IA with
the current sensor, connect the sense terminals of the sensor to
the ISVP and ISVN pins of the AD8451 (see Figure 50).
RGP
IBAT
–
4 TERMINAL
SHUNT
DUT
10kΩ
20kΩ
+
1667Ω
LPF
10kΩ
RGN
–
ISVN
–
10kΩ
20kΩ
+
12137-050
A commonly used power supply combination is +15 V for
AVCC, −15 V for AVEE, and +5 V for DVCC. The +15 V rail
for AVCC provides enough headroom to the IA such that it can
be connected in a high-side current sensing configuration. The
−15 V rail for AVEE allows the DA to sense accidental reverse
battery conditions (see the Reverse Battery Conditions section).
10kΩ
+
The rated absolute maximum value for AVCC − AVEE is 36 V,
and the minimum operating AVCC and AVEE voltages are +5 V
and −5 V, respectively. Due to the high PSRR of the AD8451
analog blocks, AVCC can be connected directly to the high current
power bus (the input voltage of the power converter) without
risking the injection of supply noise to the controller outputs.
Figure 50. 4-Terminal Shunt Resistor Connected to the Current Sense IA
VOLTAGE SENSE DA CONNECTIONS
For a description of the DA, see the Theory of Operation
section, Figure 42, and Figure 45. The DA fixed gain is 0.8.
Reverse Battery Conditions
The output voltage of the AD8451 DA can be used to detect a
reverse battery connection. A −15 V rail for AVEE allows the
output of the DA to go below ground when the battery is
connected backward. Therefore, the condition can be detected
by monitoring the BVMEA pin for a negative voltage.
BATTERY CURRENT AND VOLTAGE CONTROL
INPUTS (ISET AND VSET)
The voltages at the ISET and VSET input pins set the target
battery current and voltage for the CC and CV loops. These
inputs must be driven by a precision voltage source (or a digitalto-analog converter [DAC] connected to a precision reference)
whose output voltage is referenced to the same voltage as the IA
and DA reference pins (ISREFH/ISREFL and BVREFH/BVREFL,
respectively). For example, if the IA reference pins are connected
to AGND, the voltage source connected to ISET must also be
referenced to AGND. In the same way, if the DA reference pins
are connected to AGND, the voltage source connected to VSET
must also be referenced to AGND.
In constant current mode, when the CC feedback loop is in a
steady state, the ISET input sets the battery current as follows:
IBAT_SS =
VISET
V
= ISET
G IA × RS
26 × RS
where:
GIA is the IA gain.
RS is the value of the shunt resistor.
Rev. 0 | Page 23 of 32
AD8451
Data Sheet
In constant voltage mode, when the CV feedback loop is in
steady state, the VSET input sets the battery voltage as follows:
VBAT_SS =
VVSET
V
= VSET
0. 8
G DA
where GDA is the DA gain.
Therefore, the accuracy and temperature stability of the formation
and test system are not only dependent on the precision of the
AD8451, but also on the accuracy of the ISET and VSET inputs.
LOOP FILTER AMPLIFIERS
The AD8451 has two loop filter amplifiers, also known as error
amplifiers (see Figure 49). One amplifier is for constant current
control (CC loop filter amplifier), and the other amplifier is for
constant voltage control (CV loop filter amplifier). The outputs
of these amplifiers are combined using a minimum output
selector circuit to perform automatic CC to CV switching.
Table 5 lists the inputs of the loop filter amplifiers for charge
mode and discharge mode.
Table 5. Integrator Input Connections
Feedback Loop Function
Control the Current While Discharging
a Battery
Control the Current While Charging
a Battery
Control the Voltage While Discharging
a Battery
Control the Voltage While Charging
a Battery
Reference
Input
ISET
Feedback
Terminal
IVE0
ISET
IVE1
VSET
VVE0
VSET
VVE1
The CC and CV amplifiers in charge mode and the CC amplifier
in discharge mode are inverting integrators, whereas the CV
amplifier in discharge mode is a noninverting integrator. Therefore,
the CV amplifier in discharge mode uses an extra amplifier, the
VSET buffer, to buffer the VSET input pin (see Figure 42). In
addition, the CV amplifier in discharge mode uses the VVP0
pin to couple the signal from the BVMEA pin to the integrator.
Given the architecture of the AD8451, the controller requires
that an increasing voltage at the VCTRL pin translates to a
larger output current in the power converter. If this is not the
case, a unity-gain inverting amplifier can be added in series
with the AD8451 output to add an extra inversion.
STEP-BY-STEP DESIGN EXAMPLE
This section describes the systematic design of a 1 A battery
charger/discharger using the AD8451 controller and the
ADP1972 PWM controller. The power converter used in this
design is a nonisolated buck boost dc-to-dc converter. The target
battery is a 4.2 V fully charged, 2.7 V fully discharged Li-Ion
battery.
Step 1: Design the Switching Power Converter
Select the switches and passive components of the buck boost
power converter to support the 1 A maximum battery current.
The design of the power converter is beyond the scope of this
data sheet; however, there are many application notes and other
helpful documents available from manufacturers of integrated
driver circuits and power MOSFET output devices that can be
used for reference.
Step 2: Identify the Control Voltage Range of the
ADP1972
The control voltage range of the ADP1972 (voltage range of the
COMP input pin) is 0.5 V to 4.5 V. An input voltage of 4.5 V
results in the highest duty cycle and output current, whereas an
input voltage of 0.5 V results in the lowest duty cycle and output
current. Because the COMP pin connects directly to the VCTRL
output pin of the AD8451, the battery current is proportional to
the voltage at the VCTRL pin.
For information about how to interface the ADP1972 to the
power converter switches, see the ADP1972 data sheet.
Step 3: Determine the Control Voltage for the CV Loop
The relationship between the control voltage for the CV loop
(the voltage at the VSET pin), the target battery voltage, and the
DA gain is as follows:
CONNECTING TO A PWM CONTROLLER (VCTRL PIN)
The VCTRL output pin of the AD8451 is designed to interface
with linear power converters and with PWM controllers such as
the ADP1972. The voltage range of the VCTRL output pin is
bound by the voltages at the VCLP and VCLN pins, as follows:
VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V
CV Battery Target Voltage =
VVSET VVSET
=
G DA
0. 8
In charge mode, for a CV battery target voltage of 4.2 V, select a
CV control voltage of 3.36 V. In discharge mode, for a CV
battery target voltage of 2.7 V, select a CV control voltage of
2.16 V.
Because the maximum rated input voltage at the COMP pin of
the ADP1972 is 5.5 V, connect the clamp voltages of the output
amplifier to 5 V (VCLP) and ground (VCLN) to prevent overranging of the COMP input. As an additional precaution, install
an external 5.1 V Zener diode from the COMP pin to ground
with a series 1 kΩ resistor connected between the VCTRL and
COMP pins. Consult the ADP1972 data sheet for additional
applications information.
Rev. 0 | Page 24 of 32
Data Sheet
AD8451
Step 4: Determine the Control Voltage for the CC Loop
and the Shunt Resistor
The relationship between the control voltage for the CC loop
(the voltage at the ISET pin), the target battery current, and the
IA gain is as follows:
CC Battery Target Current =
V
VISET
= ISET
G IA × RS 26 × RS
The voltage across the shunt resistor is as follows:
Step 5: Choose the Control Voltage Sources
The input control voltages (the voltages at the ISET and VSET
pins) can be generated by an analog voltage source such as a
voltage reference or by a DAC. In both cases, select a device that
provides a stable, low noise output voltage. If a DAC is preferred,
Analog Devices offers a wide range of precision converters. For
example, the AD5668 16-bit DAC provides up to eight 0 V to
4 V sources when connected to an external 2 V reference.
To maximize accuracy, the control voltage sources must be
referenced to the same potential as the outputs of the IA and
DA. For example, if the IA and DA reference pins are connected
to AGND, connect the reference pins of the control voltage
sources to AGND.
V
V
Shunt Resistor Voltage = ISET = ISET
G IA
26
For target current of 1 A, choosing a 20 mΩ shunt resistor
results in a control voltage of 4 V.
When selecting a shunt resistor, consider the resistor style and
construction. For low power dissipation applications, many
temperature stable SMD styles can be soldered to a heat sink
pad on a printed circuit board (PCB). For optimum accuracy,
choose a shunt resistor that provides force and sense terminals.
In these resistors, the battery current flows through the force
terminals and the voltage drop in the resistor is read at the sense
terminals.
Step 6: Select the Compensation Devices
Feedback controlled switching power converters require
frequency compensation to guarantee loop stability. There are
many references available about how to design the compensation
for such power converters. The AD8451 provides active loop
filter error amplifiers for the CC and CV control loops that
can implement proportional integrator (PI), PD, and PID
compensators using external passive components.
Rev. 0 | Page 25 of 32
AD8451
Data Sheet
EVALUATION BOARD
INTRODUCTION
FEATURES AND TESTS
The AD8451-EVALZ evaluation board is a convenient
standalone platform for evaluating the major elements of the
AD8451, either as a standalone component or connected to a
battery test/formation system.
SMA connectors provide access for input voltages to the
sensitive instrumentation (IA) and difference (DA) amplifiers.
ISVP and ISVN connectors are the IA inputs, and BVP and
BVN are the DA inputs. These inputs accept the dc voltages
from battery current and voltage measurement sources, or from
a precision dc voltage source. SMA connectors ISET and VSET
are available for precision dc control voltages for CC or CV
battery charging voltages. SMA ISREFLO is available for
applying a nonzero reference voltage to the IA. SMA VCTRL
connects to the input of a dc-to-dc power converter as seen in
Figure 52. Convenient test loops are provided connecting scope
probes or instruments for the remainder of the input/output.
In the latter configuration, the AD8451-EVALZ operates just as
it would within a system including the PWM and dc-to-dc
power converter. Simply connect the current and voltage sense
voltages from the system directly to the board terminus. This
feature is used when setting or evaluating loop compensation
using a field of passive compensation components. Figure 51 is
a photograph of the AD8451-EVALZ.
12137-051
The MODE switch selects between the charge and discharge
option. Figure 52 is a schematic of the AD8451-EVALZ. Table 6
lists and describes the various switches and functions.
Figure 51. Photograph of the AD8451-EVALZ
Rev. 0 | Page 26 of 32
Data Sheet
AD8451
Table 6. AD8451-EVALZ Test Switches and Functions
Switch
MODE
RUN_TEST1
RUN_TEST2
ISREF_HI
ISREF_LO
Function
Selects the charge or the discharge
mode.
Selects between the user inputs and
the 2.5 V AD8451 reference voltage.
Tests the CC or CV loop filter
amplifiers.
The ISREF_HI switch connects
Pin 74 (ISREFH) to the internal 2.5 V
reference (2.5 position) or to the
SMA connector EXT (the external
input for a user defined VREF input).
Connects Pin 76 (ISREFL) to ground
(NORM) or to the ISREFL SMA input
connector.
Operation
The MODE switch selects CHG (logic high) or DISCH (logic low).
The AD8451 operates normally when the RUN_TEST1 switch is in the RUN
position. When in the TEST position, 2.5 V is applied to the ISET and VSET inputs.
The voltage at the VCTRL output (TPVCTRL) for all positions is 0 V when
RUN_TEST1 is in RUN position and 2.5 V when RUN_TEST1 in TEST position.
When in the 2.5V position, the ISREF_HI switch connects Pin 74 (ISREFH, an
internal 100 kΩ resistor) to Pin 73 (VREF, the 2.5 V reference). When the
ISREF_LO switch is in the NORM position, the output at Pin 71 (ISMEA)
shifts positive by 20 mV.
When in the NORM position and the ISREF_HI switch is in the EXT position,
there is no offset applied to the ISMEA output. When in the EXT position,
the ISREFLO SMA is selected.
EVALUATING THE AD8451
Test the Instrumentation Amplifier
Connect the TPISVN jumper to ground, and then apply
100 mV dc to TPISVP. Measure 2.6 V at the TPISMEA output.
Subtract any offset voltages from the output reading before
calculating the gain.
20 mV Offset at IMEAS Output
Connect a jumper from TPISVP to TPISVN to ground by using
another jumper and any one of the convenient black test loops.
Measure 0 V ± 2.86 mV at the TPISMEA output (that is, the IA
residual offset voltage multiplied by gain). Move the ISREFLO
switch to the EXT position, and the ISREFHI switch to the
20 mV (EXT) position. The output will then increase by 20 mV.
Test the Difference Amplifier
Insert a shorting jumper at Header GND_BVN. With 1 V dc
applied to TPBVP, measure 0.8 V at TPBVMEA. For the most
accurate gain measurement, subtract the offset voltage from the
output voltage before calculating gain.
5 mV Offset at BVMEAS Output
Insert jumpers in the GND_BVP and GND_BVN headers.
Measure 0 V ± 0.4mV at the TPBVMEA output (that is, the DA
residual offset voltage multiplied by gain). Connect a jumper
between TPBREFH and TP2.5V. The output will then increase
by 5 mV.
Default
Position
CHG
RUN
RUN
EXT
NORM
Note the four compensation networks, CC-CHARGE, CCDISCHARGE, CV-CHARGE, and CV-DISCHARGE, located
on the right-hand side of the schematic shown in Figure 52. To
make it easier to locate these components, the configuration of
these networks on the AD8451-EVALZ PCB approximates that
shown in the schematic (see Figure 52). Each of the components
locations accommodates both standard, 1206 size, surface-mount
chip resistors and capacitors or leaded components inserted into
the pairs of TP thru holes spanning the SM footprints. The TP
holes accept the popular 0.025” test pins if leaded devices are
preferred for multiple loop tests.
As shipped, CC and CV loop amplifier filters are configured as
voltage followers by replacing feedback capacitors to the inverting
inputs with resistors, and removing the dc coupling resistors from
the IA and DA outputs. The feedback loops must be reconfigured
to close the loops to operate as precision feedback loops.
Loop compensation requires knowledge of the output dc-to-dc
power converter. It is assumed that the AD8451 is most often
used with a switching converter. The scope and breadth of this
switching converter design architecture is quite broad, and a
thorough discussion of all the types and variants of this type of
converter is well beyond the scope of this data.
CC and CV Integrator Tests
When the circuit and component details of the power converter
are known, proceed with a calculation of the loop parameters
and components, and the values necessary to achieve loop
compensation.
Switches RUN_TEST1 and RUN_TEST2 set up the required
circuit conditions to test the integrators. RUN_TEST1 disconnects
the external inputs ISET and VSET and applies 2.5 V dc from
the reference, simultaneously, to both of the CC and CV.
Because the loop is of the type proportional/integrating (PI), a
direct dc path is required from the IA and DA amplifiers to the
error inputs of the CC and CV loop amplifiers. Install these
resistors at the R1, R6, R7, R11, and R12 locations.
RUN_TEST2 has three positions: RUN, TEST_CC, and
TEST_CV.
Likewise, the CC and CV amplifiers must be reconfigured from
voltage followers to integrators by replacing the 0 Ω capacitors
at C6, C10, C11, C19, and C24 with appropriate capacitors.
Loop Compensation
The AD8451-EVALZ is suitable for use as a test platform for
system loop compensation experiments. However, before
installing the platform in a system, component changes are necessary.
Rev. 0 | Page 27 of 32
+
ISVN
5V
C4
10µF
35V
TPISVN
RGN
+5V
+ C8
10µF
35V
DVCC
25 V
C7
10µF
+ 35V
AVCC
−5V
RGP
TPISVP
AVEE
ISVP
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NC
22
79
78
23
TPBVP
GND_BVP
21
ISVN
RGN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RGP
ISVP
NC
80
NC
BVPS
77
24
76
TPISREFLS
NC
NC
GND6 GND7 GND8 GND9 GND10
ISREFLS
BVP
BVP
C18
10µF
10V
25
75
2.5
26
74
TPISREFH
27
1
72
29
71
2.5
70
69
30
31
X1
TPBVN
32
68
34
67
2
35
66
6
VSET
5
C21
1µF
50V
−5V
36
65
37
64
TPISET
1
RUN
GND_BVN
TP_BVP
33
3
R19
1kΩ
TEST
TPISREFB
CR3
5.1V
25 V
TPISMEA
AD8451
TPBVREFH
28
73
−5V
C5 C20
10µF 1µF
10V 50V
ISREFH
BREFH
TPISREFL
AGND
VREF
2.5V
VREF
AGND
GND1 GND2 GND3 GND4 GND5
ISREFL
NC
2
ISMEA
3
NC
1
AVCC
3 2
ISET
NC
EXT NORM EXT
IVE0
AVEE
ISREFL
NC
BVNS
63
4
VSET
IVE1
BVMEA
ISET
25V
38
NC
AVCC
RUN_
TEST1
62
39
61
C9
0.1µF
50V
40
VVP0 51
NC 52
VVE0 53
VVE1 54
NC 55
VINT 56
45
46
42
JP 1
VVE1
R17
0Ω
JP 1
5
7
DISCH
1
8
VVP0
TP8
TP5
TP25
TP3
TP6
R6
TBD1206
TP12
TP36
TP10
TP37
TP24
TP27
TP39
TP35
R13
10kΩ
1206
TP32
TP38
TP34
C22
TBD1206
TP17
R10
10kΩ
1206
TP31
C12
TBD1206
TP23
R14
10kΩ
1206
TP33
C23
TBD1206
TP30
TP16
R8
10kΩ 1%
1206
TP29
C1
TBD1206
TP15
VVP0
TP44
TPBVMEA
AVCCRET DVCCRET
AVEERET
TP62
TP63
TP59
C19*
0Ω
1206
TP52 TP60
R9
10kΩ
1206
TP47
C13
TBD1206
TP51 TP58
R5
10kΩ
1206
TP19
TP57
C11*
0Ω
1206
C15
TBD1206
TP46
TP1
TP61
TP18
C24*
0Ω
1206
TP50 TP56
R15
10kΩ
1206
TP42
TP43
VVE0
TVVE 1
C17
TBD1206
TP49 TP55
TP54
C10*
0Ω
1206
C14
TBD1206
TP45
VINT
TP13
C6*
TBD1206
1206
TP48 TP53
TP14
R4
10kΩ
1206
TP41
TVVE1
IVE 0
TP40
R3
10kΩ
1206
TIVE1
R2
10kΩ 1%
1206
C3
TBD1206
TP11
TP9
*0Ω 1206 RESISTORS ARE TEMPORARILY INSTALLED IN
LOCATIONS C6, C14, C17, C15, AND C19.
SEE TEXT FOR FURTHER EXPLANATION.
TP4
C2
TBD1206
TP28
CV -DISCHARGE
TP26
R12
TBD1206
CV -CHARGE
TP2
R1
TBD1206
CC -DISCHARGE
TP7
R7
TBD1206
CC -CHARGE
R11
BVMEA TBD1206
BVMEA
VSETBF
CR 1
5 .1 V
ISMEA
VCTRL
TPVCTRL
6
VVE1
MODE
CHG 3 5 V
2
C19
10µF
10V
5V
CR2
5.1V
R19
1kΩ VSET
TPVSETBF
TPMODE
NC 41
VREF
NC 43 NC
NC 44 NC
DGND
NC
DVCC 47
NC 48
VSET 49
VINT
25V
AVCC 57
VCLN 58
VCTRL 59
R18
1kΩ
R16
0Ω
5V
TVVE1
TPVCLN
TPVCLP
VCLP 60
−5V
VSETBF 50
−5V
T_CC
RUN_
3
T_CV
TEST2 1
RUN
4
2
VINT
VINT
MODE
ISREFHI
AVEE
BREFL
TPBREFL
BREFLS
TPBVREFLS
ISREFB
NC
NC
NC
NC
BVN
BVN
Rev. 0 | Page 28 of 32
NC
Figure 52. AD8451-EVALZ Schematic
TPBVNS
AVEE
NC
ISREFLO
AD8451
Data Sheet
SCHEMATIC AND ARTWORK
12137-052
AD8451
12137-053
Data Sheet
12137-054
Figure 53. AD8451-EVALZ Top Silkscreen
Figure 54. AD8451-EVALZ Primary Side Copper
Rev. 0 | Page 29 of 32
Data Sheet
12137-055
AD8451
12137-056
Figure 55. AD8451-EVALZ Secondary Side Copper
Figure 56. AD8451-EVALZ Power Plane
Rev. 0 | Page 30 of 32
AD8451
12137-057
Data Sheet
Figure 57. AD8451-EVALZ Ground Plane
Rev. 0 | Page 31 of 32
AD8451
Data Sheet
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.20
16.00 SQ
15.80
1.60
MAX
61
80
60
1
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.10
COPLANARITY
VIEW A
20
41
40
21
VIEW A
0.65
BSC
LEAD PITCH
ROTATED 90° CCW
0.38
0.32
0.22
051706-A
1.45
1.40
1.35
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 58. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD8451ASTZ
AD8451ASTZ-RL
AD8451-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
80-Lead LQFP
80-Lead LQFP
Evaluation Board
Z = RoHS Compliant Part.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12137-0-3/14(0)
Rev. 0 | Page 32 of 32
Package Option
ST-80-2
ST-80-2
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