TI1 OPA2625IDGST 18-bit analog-to-digital converter (adc) driver Datasheet

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OPA625, OPA2625
SBOS688A – APRIL 2015 – REVISED OCTOBER 2015
OPAx625 High-Bandwidth, High-Precision, Low THD+N,
16-Bit and 18-Bit Analog-to-Digital Converter (ADC) Drivers
1 Features
3 Description
•
The OPAx625 family of operational amplifiers are
excellent 16-bit and 18-bit, high-precision, SAR ADC
drivers with low THD and noise that allow for a
unique power-scalable solution. This family of devices
is fully characterized and specified with a 16-bit
settling time of 280 ns that enables a true 16-bit
effective number of bits (ENOB). With a high dc
precision of only 100 µV offset voltage, a wide gainbandwidth product of 120 MHz, and a low wideband
noise of 2.5 nV/√Hz, this family is optimized for
driving high-throughput, high-resolution SAR ADCs,
such as the ADS88xx family of SAR ADCs.
1
•
•
•
High-Drive Mode:
– GBW (G = 100): 120 MHz
– Slew Rate: 115 V/µs
– 16-Bit Settling at 4-V Step: 280 ns
– Low Voltage Noise: 2.5 nV/√Hz at 10 kHz
– Low Output Impedance: 1 Ω at 1 MHz
– Offset Voltage: ±100 µV (max)
– Offset Voltage Drift: ±3 µV/ºC (max)
– Low Quiescent Current: 2 mA (typ)
Low-Power Mode:
– GBW: 1 MHz
– Low Quiescent Current: 270 µA (typ)
Power-Scalable Features:
– Ultrafast Transition from Low-Power to HighDrive Mode: 170 ns
High AC and DC Precision:
– Low Distortion: –122 dBc for HD2 and –140
dBc for HD3 at 100 kHz
– Input Common-Mode Range Includes Negative
Rail
– Rail-to-Rail Output
– Wide Temperature Range: Fully Specified from
–40°C to +125°C
The OPAx625 features two operating modes: highdrive and low-power. In the innovative low-power
mode, the OPAx625 tracks the input signal allowing
the device to transition from low-power mode to highdrive mode at 16-bit ENOB within 170 ns.
The OPAx625 family is available in 6-pin SOT and
10-pin VSSOP packages and is specified for
operation from –40°C to +125°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
OPA625
SOT (6)
2.90 mm × 1.60 mm
OPA2625
VSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
2 Applications
•
•
•
•
•
Precision SAR ADC Drivers
Precision Voltage Reference Buffers
Programmable Logic Controllers
Test and Measurement Equipment
Power-Sensitive Data Acquisition Systems
16-Bit SAR ADC, fIN = 10-kHz, 1-MSPS FFT
0
THD = -110.8 dBc
SNR = 91.88 dB
SINAD = 91.86 dB
ENOB = 14.97
-25
Amplitude (dB)
-50
SAR ADC Driver
1k
1k
Mode
Control
Input
Voltage
5V
±
VREF / 4
10 nF
+
4.7
-115.91 dBc (Third Harmonic)
-100
VREF
3.3 V
-125
REF
AVDD
-150
4.7
OPA625
-75
ADS8860
GND
-175
0
50
100
150
200 250 300 350
Frequency (kHz)
400
450
500
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA625, OPA2625
SBOS688A – APRIL 2015 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics High-Drive Mode............... 5
Electrical Characteristics Low-Power Mode.............. 7
Electrical Characteristics High-Drive Mode............... 8
Electrical Characteristics Low-Power Mode............ 10
Switching Characteristics ........................................ 11
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 23
7.1
7.2
7.3
7.4
DC Parameter Measurements ................................
Transient Parameter Measurements ......................
AC Parameter Measurements ................................
Noise Parameter Measurements ............................
23
24
24
25
8
Detailed Description ............................................ 26
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
26
26
27
28
Application and Implementation ........................ 30
9.1 Application Information............................................ 30
9.2 Typical Applications ................................................ 30
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 35
12 Device and Documentation Support ................. 36
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
37
37
37
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
Changes from Original (April 2015) to Revision A
Page
•
Changed OPA2625 from product preview to production data; added OPA2625 specifications to data sheet ..................... 1
•
Changed MODE B pin description options for V+ and V– ..................................................................................................... 3
•
Added crosstalk parameter to Electrical Characteristics table .............................................................................................. 5
•
Added crosstalk parameter to Electrical Characteristics table .............................................................................................. 8
•
Changed short-circuit current value from 150 mA to 80 mA in Electrical Characteristics table............................................. 9
•
Changed short-circuit current value from 100 mA to 50 mA in Electrical Characteristics table........................................... 10
•
Added OPA2625 data to Figure 12 ..................................................................................................................................... 13
•
Added Figure 24 ................................................................................................................................................................... 15
•
Deleted "18" from several typical characteristic figure titles (typo) ..................................................................................... 19
2
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SBOS688A – APRIL 2015 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
OPA625: DBV Package
6-Pin SOT
Top View
6
±IN A 2
2
+IN
MODE
+IN A 3
-
+
5
4
±IN
MODE A
8 ±IN B
7 +IN B
V± 4
3
9 OUT B
+
V±
10 V+
OUT A 1
V+
-
1
+
OUT
OPA2625: DGS Package
10-Pin VSSOP
Top View
6 MODE B
5
Pin Functions: OPA625
PIN
NAME
NO
I/O
DESCRIPTION
+IN
3
I
Noninverting input
–IN
4
I
Inverting input
MODE
5
I
Controls OPA625 mode:
V+ = low-power mode
V– = high-drive mode
NOTE: Do not float this pin.
OUT
1
O
Output terminal
V+
6
—
Positive supply voltage
V–
2
—
Negative supply voltage
Pin Functions: OPA2625
PIN
NAME
NO.
I/O
DESCRIPTION
+IN A
3
I
Noninverting input for channel A
–IN A
2
I
Inverting input for channel A
+IN B
7
I
Noninverting input for channel B
–IN B
8
I
Inverting input for channel B
MODE A
5
I
Controls OPA2625 mode for channel A:
V+ = low-power mode
V– = high-drive mode
NOTE: Do not float this pin.
MODE B
6
I
Controls OPA2625 mode for channel B:
V+ = low-power mode
V– = high-drive mode
NOTE: Do not float this pin.
OUT A
1
O
Output terminal for channel A
OUT B
9
O
Output terminal for channel B
V+
10
—
Positive supply voltage
V–
4
—
Negative supply voltage
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3
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SBOS688A – APRIL 2015 – REVISED OCTOBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VS
Input voltage (2)
Output voltage
Sink current
Source current
(V+) – (V–)
(1)
(2)
UNIT
6
V
+IN
(V–) – 0.3
(V+) + 0.3
–IN
(V–) – 0.3
(V+) + 0.3
MODE
(V–) – 0.3
(V+) + 0.3
(V–)
(V+)
OUT
+IN
10
–IN
10
MODE
10
OUT
150
+IN
10
–IN
10
MODE
10
OUT (2)
Temperature
MAX
V
V
mA
mA
150
Operating junction
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For input voltages beyond the power-supply rails, voltage or current must be limited.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
VI
Supply input voltage, (V+) – (V–)
Input voltage
NOM
MAX
2.7
5.5
+IN
(V–)
(V+) – 1.15
–IN
(V–)
(V+) – 1.15
MODE
(V–)
(V+)
UNIT
V
V
VO
Output voltage
(V–)
(V+)
V
IO
Output current
–120
120
mA
TA
Operating free-air temperature
–40
125
°C
TJ
Operating junction temperature
–40
125
°C
4
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SBOS688A – APRIL 2015 – REVISED OCTOBER 2015
6.4 Thermal Information
THERMAL METRIC (1)
OPA625
OPA2625
DBV (SOT)
DGS (VSSOP)
6 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
184.9
171.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
123.6
68.4
°C/W
RθJB
Junction-to-board thermal resistance
30.7
91.9
°C/W
ψJT
Junction-to-top characterization parameter
22.1
9.4
°C/W
ψJB
Junction-to-board characterization parameter
30.2
90.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics High-Drive Mode
at TA = 25°C, V+ = 5 V, V– = 0 V, MODE pin connected to V– pin, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF,
CLOAD = 20 pF, and RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Unity gain frequency
φm
Phase margin
GBW
Gain-bandwidth product
SR
Slew rate
VO = 10 mVPP
G = 100, VO = 10 mVPP
HD2
HD3
Settling time
120
MHz
VO = 4-V step, G = 2
115
VO = 4-V step, G = 2
VO = 4-V step, G = 2
Undershoot
VO = 4-V step, G = 2
Third-order harmonic
Distortion
Degrees
45
Overshoot
Second-order harmonic
Distortion
MHz
50
VO = 1-V step, G = 1
Settling time to 0.1%
(10-bit accuracy)
tsettle
80
VO = 2 VPP, G = 2
VO = 2 VPP, G = 2
V/µs
80
to 0.005%
(14-bit accuracy)
110
to 0.00153%
(16-bit accuracy)
280
ns
2.5%
3%
f = 10 kHz
144
f = 100 kHz
122
f = 1 MHz
80
f = 10 kHz
155
f = 100 kHz
140
f = 1 MHz
dBc
dBc
80
Second-order
VO = 2 VPP, f = 1 MHz, 200-kHz tone spacing
intermodulation distortion
90
dBc
Third-order
VO = 2 VPP, f = 1 MHz, 200-kHz tone spacing
intermodulation distortion
100
dBc
f = 0.1 Hz to 10 Hz, peak-to-peak
0.8
µVPP
f = 0.1 Hz to 10 Hz, rms
120
nVRMS
Input voltage noise
density
f = 1 kHz
3.2
f = 10 kHz
2.5
In
Input current noise
density
f = 1 kHz
4.1
f = 10 kHz
2.8
tOR
Overload recovery time
G=5
50
ns
Zo
Open-loop output
impedance
f = 1 MHz
1
Ω
VN
Input noise voltage
Vn
Crosstalk
DC
150
f = 1 MHz
127
nV/√Hz
pA/√Hz
dB
DC PERFORMANCE
VOS
Input offset voltage
15
TA = –40°C to +125°C
±100
±300
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5
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Electrical Characteristics High-Drive Mode (continued)
at TA = 25°C, V+ = 5 V, V– = 0 V, MODE pin connected to V– pin, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF,
CLOAD = 20 pF, and RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TA = –40°C to +125°C
TYP
MAX
UNIT
0.5
±3
µV/°C
0.6
±4
dVOS/dT
Input offset voltage drift
PSRR
Power-supply rejection
ratio
2.7 V ≤ (V+) ≤ 5 V
IB
Input bias current
TA = –40°C to +125°C
5.7
OPA2625 only, TA = –40°C to +125°C
6.5
OPA2625 only, TA = –40°C to +125°C
100
TA = –40°C to +125°C
90
dB
120
2
dIB/dT
Input bias current drift
TA = –40°C to +125°C
4
15
nA/°C
20
IOS
Input offset current
dIOS/dT
Input offset current drift
120
TA = –40°C to +125°C
150
OPA2625 only, TA = –40°C to +125°C
200
TA = –40°C to +125°C
µA
nA
0.6
nA/°C
dB
OPEN LOOP GAIN
AOL
(V–) + 0.2 V < VO < (V+) – 0.2 V, RLOAD = 600 Ω
110
(V–) + 0.15 V < VO < (V+) – 0.15 V, RLOAD = 10 kΩ
114
Open-loop gain
TA = –40°C to +125°C
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
106
128
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
110
132
INPUT VOLTAGE
VCM
Common-mode voltage
range
TA = –40°C to +125°C
CMRR
Common-mode rejection
ratio
(V–) < VCOM < (V+) – 1.15 V
(V+) –
1.15
(V–)
TA = –40°C to +125°C
100
117
90
115
V
dB
INPUT IMPEDANCE
ZID
Differential input
impedance
27 || 1.2
KΩ || pF
ZIC
Common-mode input
impedance
47 || 1.5
MΩ || pF
OUTPUT
60
RLOAD = 600 Ω
Output voltage swing to
the rail
Short-circuit current
CLOAD
Capacitive load drive
100
20
RLOAD = 10 kΩ
Isc
80
TA = –40°C to +125°C
35
TA = –40°C to +125°C
mV
40
150
mA
See Typical Characteristics
MODE
VIL
High-drive (HD) mode
threshold
TA = –40°C to +125°C
(V–)
(V–) + 0.5
V
VIH
Low-power (LP) mode
threshold
TA = –40°C to +125°C
(V–) + 1.2
(V+)
V
IIL
Low-level input current
TA = –40°C to +125°C, VMODE ≤ (V–) + 0.5 V
0.01
1
µA
TA = –40°C to +125°C, VMODE ≥ (V–) + 1.2 V
20
30
IIH
High-level input current
OPA2625 only, TA = –40°C to +125°C, VMODE ≥ (V–) + 1.2 V
1
µA
POWER SUPPLY
IQ
6
Quiescent current per
amplifier
IO = 0 mA,
MODE connected to ground
2
TA = –40°C to +125°C
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2.2
3.1
mA
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SBOS688A – APRIL 2015 – REVISED OCTOBER 2015
6.6 Electrical Characteristics Low-Power Mode
at TA = 25°C, V+ = 5 V, V– = 0 V, VMODE = 5 V, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
GBW
Gain-bandwidth product
φm
Phase margin
SR
Slew rate
Zo
Open-loop output
impedance
G = 100, VO = 10 mVPP
1
MHz
72
Degrees
VO = 1-V step
4.3
VO = 4-V step, G = 2
4.1
f = 1 MHz
12
V/µs
Ω
DC PERFORMANCE
VOS
Input offset voltage
PSRR
Power-supply rejection
ratio
2.7 V ≤ (V+) ≤ 5 V
IB
Input bias current
TA = –40°C to +125°C
TA = –40°C to +125°C
0.6
3
0.7
3.7
74
TA = –40°C to +125°C
70
mV
dB
100
150
140
OPA2625 only, TA = –40°C to +125°C
IOS
Input offset current
200
nA
250
20
TA = –40°C to +125°C
25
nA
OPEN LOOP GAIN
AOL
Open-loop gain
TA = –40°C to +125°C
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
70
100
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
90
100
dB
INPUT VOLTAGE
VCM
Common-mode voltage
range
TA = –40°C to +125°C
CMRR
Common-mode rejection
ratio
(V–) < VCOM < (V+) – 1.15 V
Output voltage swing to
the rail
TA = –40°C to +125°C
(V+) –
1.15
(V–)
TA = –40°C to +125°C
66
114
60
114
V
dB
OUTPUT
Isc
RLOAD = 600 Ω
110
RLOAD = 10 kΩ
40
Short-circuit current
100
mV
mA
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 mA,
MODE connected to V+
270
TA = –40°C to +125°C
320
450
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6.7 Electrical Characteristics High-Drive Mode
at TA = +25°C, V+ = 2.7 V, V– = 0 V, VMODE = 0 V, VCOM = VO = 1.35 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF,
and RLOAD = 1 kΩ connected to 1.35 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Unity gain frequency
VO = 10 mVPP
φm
Phase margin
GBW
Gain-bandwidth product
G = 100, VO = 10 mVPP
SR
Slew rate
VO = 1-V step, G = 2
tsettle
HD2
HD3
Settling time
VO = 1-V step, G = 2
Overshoot
VO = 1-V step, G = 2
Undershoot
VO = 1-V step, G = 2
Second order harmonic
Distortion
Third order harmonic
Distortion
(V+) = 3.3 V, (V–) = 0 V,
VCOM = 1.1 V,
VO = 2 VPP
(V+) = 3.3 V, (V–) = 0 V,
VCOM = 1.1 V,
VO = 2 VPP
76
MHz
45
Degrees
120
MHz
45
V/µs
to 0.1%
80
to 0.01%
170
to 0.000763% (17-bit accuracy)
250
ns
6%
5%
f = 10 kHz
136
f = 100 kHz
118
f = 1 MHz
80
f = 10 kHz
143
OPA2625 only, f = 10 kHz
143
f = 100 kHz
130
OPA2625 only, f = 100 kHz
125
f = 1 MHz
85
OPA2625 only, f = 1 MHz
74
dBc
dBc
Second order intermodulation distortion
(V+) = 3.3 V, (V–) = 0 V, VCOM = 1.1 V, VO = 2 VPP,
f = 1 MHz, 200-kHz tone spacing
95
dBc
Third order intermodulation distortion
(V+) = 3.3 V, (V–) = 0 V, VCOM = 1.1V, VO = 1 VPP,
f = 1 MHz, 200-kHz tone spacing
104
dBc
f = 0.1 Hz to 10 Hz peak to peak
0.8
µVPP
f = 0.1 Hz to 10 Hz rms
120
nVRMS
Input voltage noise
density
f = 10 kHz
2.5
nV/√Hz
In
Input current noise
density
f = 10 kHz
2.8
pA/√Hz
tOR
Overload recovery time
G=5
35
ns
Zo
Open-loop output
impedance
f = 1 MHz
1.3
Ω
DC
150
f = 1 MHz
127
VN
Input noise voltage
Vn
Crosstalk
dB
DC PERFORMANCE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
IB
dIB/dT
Input bias current
Input bias current drift
15
TA = –40°C to +125°C
±300
TA = –40°C to +125°C
0.5
±3.1
OPA2625 only, TA = –40°C to +125°C
0.6
±4
2
4
TA = –40°C to +125°C
5.7
OPA2625 only, TA = –40°C to +125°
6.5
TA = –40°C to +125°C
15
20
IOS
dIOS/dT
Input offset current
Input offset current drift
±100
µA
nA/°C
150
OPA2625 only, TA = –40°C to +125°
200
80
µV/°C
120
TA = –40°C to +125°C
TA = –40°C to +125°C
µV
nA
pA/°C
OPEN-LOOP GAIN
8
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SBOS688A – APRIL 2015 – REVISED OCTOBER 2015
Electrical Characteristics High-Drive Mode (continued)
at TA = +25°C, V+ = 2.7 V, V– = 0 V, VMODE = 0 V, VCOM = VO = 1.35 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF,
and RLOAD = 1 kΩ connected to 1.35 V (unless otherwise noted)
PARAMETER
AOL
Open-loop gain
TEST CONDITIONS
MIN
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
110
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
114
TA = –40°C to +125°C
TYP
MAX
UNIT
dB
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
106
128
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
110
132
INPUT VOLTAGE
VCM
Common-mode voltage
range
TA = –40°C to +125°C
CMRR
Common-mode rejection
ratio
(V–) < VCOM < (V+) – 1.15 V
(V+) –
1.15
(V–)
TA = –40°C to +125°C
100
117
90
115
V
dB
INPUT IMPEDANCE
ZID
Differential input
impedance
27 || 0.8
KΩ || pF
ZIC
Common-mode input
impedance
47 || 1.2
MΩ || pF
OUTPUT
60
R LOAD = 600 Ω
TA = –40°C to +125°C
Output voltage swing to
the rail
Short-circuit current
CLOAD
Capacitive load drive
100
20
R LOAD = 10 kΩ
ISC
80
35
TA = –40°C to +125°C
mV
40
80
mA
See Typical Characteristics
MODE
VIL
High-drive (HD) mode
threshold
TA = –40°C to +125°C
(V–)
(V–) + 0.5
V
VIH
Low-power (LP) mode
threshold
TA = –40°C to +125°C
(V–) + 1.2
(V+)
V
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 mA
MODE connected to ground
2
TA = –40°C to +125°C
2.1
2.8
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6.8 Electrical Characteristics Low-Power Mode
at TA = +25°C, V+ = 2.7 V, V– = 0 V, VMODE = 2.7 V, VCOM = VO = 1.35V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF,
and RLOAD = 1 kΩ connected to 1.35 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
GBW
Gain-bandwidth product
φm
Phase margin
SR
Slew rate
Zo
Open-loop output
impedance
G = 100, VIN = 10 mVPP
0.8
MHz
72
Degrees
VO = 1 V-step, G = 2
3.7
V/µs
f = 1 MHz
13
Ω
DC PERFORMANCE
VOS
Input offset voltage
IB
Input bias current
0.6
3
TA = –40°C to +125°C
0.7
±3.6
TA = –40°C to +125°C
140
mV
150
OPA2625 only, TA = –40°C to +125°
IOS
Input offset current
220
nA
250
20
TA = –40°C to +125°C
25
nA
OPEN LOOP GAIN
AOL
Open-loop gain
TA = –40°C to +125°C
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
74
100
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
84
100
dB
INPUT VOLTAGE
VCM
Common-mode voltage
range
TA = –40°C to +125°C
CMRR
Common-mode rejection
ratio
(V–) < VCOM < (V+) – 1.15 V
Output voltage swing to
rail
TA = –40°C to +125°C
(V+) –
1.15
(V–)
TA = –40°C to +125°C
66
114
60
114
V
dB
OUTPUT
Isc
RLOAD = 600 Ω
110
RLOAD = 10 kΩ
40
Short-circuit current
50
mV
mA
POWER SUPPLY
IQ
10
Quiescent current per
amplifier
IO = 0 mA,
MODE connected to V+
250
TA = –40°C to +125°C
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270
400
µA
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SBOS688A – APRIL 2015 – REVISED OCTOBER 2015
6.9 Switching Characteristics
at TA = 25°C, V+ = 5 V, V– = 0 V, MODE pin connected to V– pin, gain (G) = 1 , VCOM = VO = 2.5 V, CLOAD = 20 pF, and RLOAD
= 1 kΩ connected to 2.5 V (unless otherwise noted)
PARAMETER
tLP-HD
tHD-LP
TEST CONDITIONS
Delay time, MODE pin falling
(low-power mode to high-drive mode)
Delay time, MODE pin rising
(high-drive mode to low-power mode)
MODE
MIN
TYP
MAX
UNIT
Settling time to within 50 µV of final value,
MODE pin = high to low (LP to HD), VO = 3.8 V
180
ns
tLP-HD is defined as the time taken for the
quiescent current to increase from 110% of its
value in LP mode to 90% of its value in HD
mode.
170
ns
tHD-LP is defined as the time taken for the
quiescent current to decrease from 90% of its
value in HD mode to 110% of its value in LP
mode.
300
ns
tHD-LP
tLP-HD
OPAx625
STATE
Low-Power mode
High-Drive mode
Figure 1. Switching Characteristics Timing Diagram
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6.10 Typical Characteristics
25
25
20
20
15
15
10
10
5
5
Gain (dB)
Gain (dB)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
0
Gain = 1
±5
Gain = -1
±10
Gain = 2
±15
Gain = 1
±10
Gain = -1
Gain = 2
±15
Gain = 5
±20
0
±5
Gain = 5
±20
Gain = 10
±25
Gain = 10
±25
10k
100k
1M
10M
Frequency (Hz)
10k
100M
100k
VO = 10 mVPP
C005
10
5.5 V
8
2.7 V
6
2.0
1.5
4
Gain (dB)
Gain (dB)
100M
Figure 3. Large-Signal Frequency Response for Various
Gains
2.5
1.0
0.5
0.0
2
0
±2
0 pF
±4
8.2 pF
22 pF
±6
-0.5
33 pF
±8
-1.0
100k
47 pF
±10
1M
10M
100M
Frequency (Hz)
1M
10M
100M
Frequency (Hz)
C006
VO = 10 mVPP, G = 1
1G
C007
VO = 10 mVPP , G = 1
Figure 4. Small-Signal Frequency Response for Various
Power Supply Voltages
Figure 5. Small-Signal Frequency Response for Various
Capacitive Loads
2.5
2
1
2k
2.0
0
±1
1k
1.5
Gain (dB)
Gain (dB)
10M
VO = 2 VPP
Figure 2. Small-Signal Frequency Response for Various
Gains
±2
±3
±4
0 pF
±5
8.2 pF
1.0
0.5
22 pF
±6
0.0
33 pF
±7
47 pF
-0.5
±8
10k
100k
1M
Frequency (Hz)
10M
100M
1M
C007
VO = 2 VPP, G = 1
10M
100M
Frequency (Hz)
C007
VO = 10 mVPP , G = 1
Figure 6. Large-Signal Frequency Response for Various
Capacitive Loads
12
1M
Frequency (Hz)
C004
Figure 7. Small-Signal Frequency Response for Various
Resistive Loads
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
180
80
135
40
90
1000
0
100
Impedance (:)
120
Gain (dB)
225
Phase (ƒ)
160
10
45
Gain
Phase
-40
±40
0.01
0.01 0.10
0.1
11
10
10 100
100
1k
1k
0
0
10k
10k 100k 1000k
1M 10000k
10M 100000k
100M
Frequency (Hz)
1
10
C024
100
1k
10k
100k
Frequency (Hz)
VO = 10 mVPP
Figure 8. High-Drive Mode Open-Loop Gain and Phase vs
Frequency
180
80
150
60
120
40
90
20
60
Gain
0
10M
100M
Figure 9. High-Drive Mode Open-Loop Output Impedance vs
Frequency
1000
100
Impedance (:)
100
Gain (dB)
210
Phase (ƒ)
120
1M
10
30
Phase
-20
±20
0.01 0.1
0.10
1
10
100
1k
10k
00
10M
1M
100k 1000k
1M 10000k
10M
Frequency (Hz)
1
10
100
1k
10k
100k
Frequency (Hz)
C024
1M
10M
100M
VO = 10 mVPP , VMODE = 5 V
Figure 10. Low-Power Mode Open-Loop Gain and Phase vs
Frequency
Figure 11. Low-Power Mode Open-Loop Output Impedance
vs Frequency
140
OPA625
OPA2625
120
100
80
60
40
20
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (db)
140
120
100
80
60
40
PSRR+
20
PSRR-
0
0
10
1
100
1k
10k
100k
Frequency (Hz)
1M
10M
10
100M
Figure 12. Common-Mode Rejection Ratio vs Frequency
100
1k
10k
100k
1M
10M
Frequency (Hz)
100M
C025
Figure 13. Power-Supply Rejection Ratio vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
5
60
Riso = 0
55
50
Overshoot (%)
Gain (dB)
0
±5
±15
100k
Riso = 0
45
Riso = 25
Riso = 25
20
Riso = 50
15
V
Riso = 10
2.7 V
Riso = 50
V
10
1M
10M
100M
10
100
1000
10000
Load Capacitance (pF)
C024
C027
G = 1, VO = 10 mVPP
Figure 14. Series Resistance for Capacitive Load Stability
Figure 15. Overshoot vs Capacitive Load, G = 1
0
50
V
Riso = 25
40
Riso = 0
35
V
V
Riso = 25
30
V
Riso = 10
V
Riso = 50
5.5 V
Riso = 10
V
Riso = 50
V
HD2, Gain = 1
±20
HD3, Gain = 1
±40
Distortion (dBc)
Riso = 0
45
Overshoot (%)
V
V
Riso = 50
30
G = 1, CLOAD = 1.2 nF
25
20
15
HD2, Gain = 2
±60
HD3, Gain = 2
±80
±100
±120
10
±140
5
±160
0
±180
10
100
1000
Load Capacitance (pF)
1k
10000
10k
100k
Input Frequency (Hz)
C027
1M
C010
VS = 5.5 V, VO = 2 VPP, RLOAD = 600 Ω
G = –1, VO = 10 mVPP
Figure 16. Overshoot vs Capacitive Load, G = –1
Figure 17. Distortion vs Frequency for Various Gains
0
0
HD2, Vs = 5.5 V
±20
HD3, Vs = 5.5 V
±40
HD2, Vs = 3.3 V
±60
HD3, Vs = 3.3 V
Distortion (dBc)
Distortion (dBc)
V
Riso = 10
35
25
Frequency (Hz)
±80
±100
±120
±20
HD2, Vs = 5.5 V
±40
HD3, Vs = 5.5 V
±60
HD2, Vs = 3.3 V
HD3, Vs = 3.3 V
±80
±100
±120
±140
±140
±160
±180
±160
1k
10k
100k
Input Frequency (Hz)
1M
1k
10k
Figure 18. Distortion vs Frequency for Various Power
Supplies
100k
Input Frequency (Hz)
C010
G = 1, VO = 2 VPP, RLOAD = 600 Ω
14
V
40
Riso = 10
±10
V
Riso = 25
1M
C010
G = 2, VO = 2 VPP, RLOAD = 600 Ω
Figure 19. Distortion vs Frequency for Various Power
Supplies
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
0
0
2k
±20
f = 10 kHz
±40
f = 100 kHz
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
f = 1 kHz
f = 1 MHz
±60
±80
±100
±120
±140
±20
1k
±40
±60
±80
±100
±120
±140
±160
±160
1
2
3
4
Output Voltage (VPP)
1k
100k
1M
Input Frequency (Hz)
G = 1, RLOAD = 600 Ω
C010
G = 1, VO = 2 VPP , RLOAD = 600 Ω
Figure 20. Total Harmonic Distortion vs Output Voltage for
Various Frequencies
Figure 21. Total Harmonic Distortion vs Frequency for
Various Loads
1000
Current Noise Density (pA/rtHz)
1000
Voltage Noise Density (nV/rtHz)
10k
C013
100
10
1
100
10
1
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
0.1
1
Figure 22. Voltage Noise Density vs Frequency
10
100
1k
10k
Frequency (Hz)
C015
100k
C015
Figure 23. Current Noise Density vs Frequency
Voltage Noise (200 nV/div)
-80
Crosstalk (db)
-100
-120
-140
-160
-180
10
Time (1 s/div)
100
1k
10k
100k
Frequency (Hz)
1M
10M
C020
Figure 24. Crosstalk vs Frequency
Figure 25. 0.1-Hz to 10-Hz Voltage Noise
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
180
6
140
Maximum Output Voltage (VPP)
Falling, Gain = 1
Slew Rate (V/s)
VS = 5 V
VS = 3.3 V
Rising, Gain = 1
160
Rising, Gain = 2
120
Falling, Gain = 2
100
80
60
40
20
5
4
3
2
1
0
0
1
2
3
Output Voltage Step (V)
4
C018
Figure 26. Slew Rate vs Output Step Size
0
1k
10k
100k
1M
10M
Frequency (Hz)
100M
Output Voltage (1 V/div)
Output Voltage (1 V/div)
Figure 27. Maximum Output Voltage vs Frequency
Time (200 ns/div)
Time (200 ns/div)
C020
C019
G = 1, VO = 4-V step
G = –1, VO = 4-V step
Output Voltage (2 mV/div)
Figure 29. Large-Signal Pulse Response
Output Voltage (2 mV/div)
Figure 28. Large-Signal Pulse Response
Time (200 ns/div)
Time (200 ns/div)
C029
C029
G = 1, VO = 10-mV step
G = –1, VO = 10-mV step
Figure 30. Small-Signal Pulse Response
16
1G
Figure 31. Small-Signal Pulse Response
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
200
150
Output Delta from Final Value (µV)
Output Delta from Final Value (µV)
200
16-bit settling
100
50
0
±50
±100
16-bit settling
±150
±200
150
16-bit settling
100
50
0
±50
±100
16-bit settling
±150
±200
0
200
400
600
800
Time (ns)
1000
0
200
400
600
800
1000
Time (ns)
C032
VO = 3.6-V step at t = 0 s
C032
VO = 3.6-V step at t = 0 s
Figure 32. 16-Bit Negative Settling Time
Figure 33. 16-Bit Positive Settling Time
4
0.8
4
0.6
3
0.4
2
0.2
1
3
Input Voltage (V)
1
0
±1
±2
±3
Input
0.0
Input
Output
±4
Output Voltage (V)
Voltage (1 V/div)
2
0
Output
-0.2
Time (200 µs/div)
-1
Time (100 ns/div)
C021
C031
VS = ±2.75 V, G = 1
VS = ±2.75 V, G = 5
Figure 34. No Phase Reversal
Figure 35. Positive Overload Recovery
20
1
0.2
Input
0
C021
Offset Voltage (µV)
VS = ±2.75 V, G = 5
100
75
0
50
-4
Time (100 ns/div)
25
-0.8
5
0
-3
-25
-0.6
-50
-2
10
-75
-0.4
Amplifiers (%)
-1
-0.2
15
-100
Output
Output Voltage (V)
Input Voltage (V)
0.0
C013
Distribution taken from 3139 amplifiers
Figure 36. Negative Overload Recovery
Figure 37. Input Offset Voltage Distribution
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Typical Characteristics (continued)
20
15
15
Offset Voltage (µV)
Offset Voltage (µV)
C013
Distribution taken from 80 amplifiers, TA = 125°C
300
250
200
150
50
100
0
-50
-100
-300
300
250
200
150
50
100
0
-50
-100
0
-150
0
-200
5
-250
5
-150
10
-200
10
-250
Amplifiers (%)
20
-300
Amplifiers (%)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
C013
Distribution taken from 80 amplifiers, TA = 85°C
Figure 38. Input Offset Voltage Distribution
Figure 39. Input Offset Voltage Distribution
400
20
300
200
VOS (V)
Amplifiers (%)
15
10
100
0
±100
±200
5
±300
300
250
200
150
50
100
0
-50
-100
-150
-200
-250
-300
0
±400
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
Offset Voltage (µV)
150
C001
7 typical units shown
C013
Distribution taken from 80 amplifiers, TA = –40°C
Figure 41. Input Offset Voltage vs Temperature
30
35
25
30
25
Amplifiers (%)
20
15
10
20
15
5
4
3
2
1
3
2
2.5
1.5
1
0.5
0
-0.5
-1
0
-1.5
0
-2
5
-2.5
5
0
10
-3
Amplifiers (%)
Figure 40. Input Offset Voltage Distribution
Input Bias Current (µA)
Offset Voltage Drift (µV/ƒC)
C013
Distribution taken from 83 amplifiers, TA = –40°C to +125°C
Figure 42. Input Offset Voltage Drift Distribution
18
C013
Distribution taken from 3139 amplifiers
Figure 43. Input Bias Current Distribution
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
5
30
25
4
Amplifiers (%)
3
2
1
20
15
10
5
0
75
100
125
Temperature (ƒC)
150
C001
300
50
200
25
100
0
0
±25
-100
±50
-300
0
±75
-200
Input Bias Current (µA)
IB IB+
Input Offset Current (nA)
C013
Distribution taken from 3139 amplifiers
Figure 45. Input Offset Current Distribution
Figure 44. Input Bias Current vs Temperature
Common-Mode Rejection Ratio (µV/V)
Input Offset Current (nA)
1000
100
10
20
VS = ±2.75 V, (V±) ”9CM ” 9 ± 1.15
10
0
VS = ±1.35 V, (V±) ”9CM ” 9 ± 1.15 V
±10
±20
±30
1
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
±75
150
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
Figure 46. Input Offset Current vs Temperature
150
C001
Figure 47. Common-Mode Rejection Ratio vs Temperature
30
3.0
20
2.0
10
1.0
AOL (µV/V)
Power-Supply Rejection Ratio (µV/V)
30
0
VS = ±1.35 V
0.0
VS = ±2.5 V
-10
±1.0
-20
±2.0
±3.0
-30
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
2.7 V ≤ VS ≤ 5.5 V
150
C001
RLOAD = 10 kΩ
Figure 48. Power-Supply Rejection Ratio vs Temperature
Figure 49. Open-Loop Gain vs Temperature with 10-kΩ Load
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
5.0
1
4.0
0
Input Bias Current (µA)
3.0
AOL (µV/V)
2.0
VS = ±1.35 V
1.0
0.0
±1.0
VS = ±2.5 V
±2.0
±3.0
±1
±2
±3
±4
±4.0
±5.0
±5
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±4
0
±2
2
4
VCM (V)
C001
RLOAD = 600 Ω
C001
High-drive mode, VS = ±2.5 V
Figure 50. Open-Loop Gain vs Temperature with 600-Ω Load
Figure 51. Input Bias Current vs Input Common-Mode
Voltage
50
50
40
30
25
10
VOS (V)
VOS (V)
20
0
±10
±20
±30
VCM = 1.35 V
±25
VS = ±2.75 V
VS = ±1.35 V
VCM = ±2.5 V
0
±40
±50
±50
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
VSUPPLY (V)
2.8
±3
0
±1
1
2
VCM (V)
6 typical units shown, VS = ±1.35 V to ±2.75 V
C001
6 typical units shown, VS = ±2.5 V
Figure 52. Input Offset Voltage vs Power-Supply Voltage
Figure 53. Input Offset Voltage vs Common-Mode Voltage
200
3
180
25°C
2
±40°C
1
ISC, Sink
160
125°C
ISC (mA)
VO (V)
±2
C001
0
-1
125°C
140
ISC, Source
120
100
-2
80
±40°C
25°C
60
-3
0
20
40
60
80
100
120
140
160
180
IO (mA)
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 54. Output Voltage vs Output Current
20
200
C001
Figure 55. Short-Circuit Current vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
3
3
2.5
2.5
VS = ±2.5 V
VS = ±1.35 V
2
IQ (mA)
IQ (mA)
2
1.5
1.5
1
1
0.5
0.5
0
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
±75
6
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C001
High-drive mode
Figure 56. High-Drive Mode Quiescent Current vs PowerSupply Voltage
Figure 57. High-Drive Mode Quiescent Current vs
Temperature
450
400
400
350
350
VS = ±2.5 V
300
IQ (µA)
IQ (µA)
300
VS = ±1.35 V
250
200
250
200
150
150
100
100
50
50
0
0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
1.5
150
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
C001
MODE pin connected to V+
6
C001
Low-drive mode, MODE pin connected to V+
Figure 58. Low-Power Mode Quiescent Current vs
Temperature
Figure 59. Low-Power Mode Quiescent Current vs PowerSupply Voltage
4
4
4
4
2
3
IQ
2
±2
1
±4
Time (200 ns/div)
0
MODE Pin Voltage
0
2
IQ
±2
±4
Time (200 ns/div)
C035
IQ (mA)
0
MODE Pin Voltage (V)
3
2
IQ (mA)
MODE Pin Voltage (V)
MODE Pin Voltage
1
0
C035
VS = ±2.75 V
VS = ±2.75 V
Figure 60. Quiescent Current When MODE transitions From
High To Low
Figure 61. Quiescent Current When MODE Transitions From
Low To High
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Typical Characteristics (continued)
At TA = 25°C, V+ = 5 V, V– = 0 V, MODE = V–, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and
RLOAD = 2 kΩ connected to 2.5 V (unless otherwise noted)
16-bit settling
3
100
2
50
1
0
0
-1
±50
±100
16-bit settling
-3
±150
±200
±200
-2
0
200
400
Time (ns)
600
800
-4
1000
Change in Input Offset Voltage (PV)
MODE Pin
MODE Pin Voltage (V)
Output Delta from Final Value (µV)
150
3
4
200
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
0
0.2
C032
VO = 3.8 VDC
0.6
Time (s)
0.8
1
1.2
D001
OPA625 powered on in high-drive mode at t = 0 s, PCB
dimensions: 4 in2, 2 layer, FR4
Figure 62. Output Voltage When MODE Transitions From
High To Low
22
0.4
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7 Parameter Measurement Information
7.1 DC Parameter Measurements
The circuit shown in Figure 64 is used to measure the dc input offset related parameters of the OPAx625. Input
offset voltage, power supply rejection ratio, common mode rejection ratio and open loop gain can be measured
with this circuit. The basic test procedure requires setting the inputs (the power-supply voltage, VS, and the
common-mode voltage, VCM), to the desired values. VO is set to the desired value by adjusting the loop-drive
voltage while measuring VO. After all inputs are configured, measure the input offset at the VX measurement
point. Calculate the input offset voltage by dividing the measured result by 101. Changing the voltages on the
various inputs changes the input offset voltage. The input parameters can be measured according to the
relationships illustrated in Equation 1 through Equation 5.
RCOMP = 1 k RB = 1.26 k Loop
Drive
V+
VOS
RA = 12.6
V-
VCM
30 V
OPA551
+
OPA625
+
RIN = 12.6
+
±
CCOMP = 0.1 PF
VO
VX
-30 V
RLOAD
+
±
Figure 64. DC-Parameters Measurement Circuit
VOS
VX
101
VOSDrift
PSRR
CMRR
AOL
(1)
'VOS
'Temperature
'VOS
'VSUPPLY
(2)
(3)
'VOS
'VCM
(4)
'VO
'VOS
(5)
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7.2 Transient Parameter Measurements
The circuit shown in Figure 65 is used to measure the transient response of the OPAx625. Configure V+, V–,
RISO, RLOAD, and CLOAD as desired. Monitor the input and output voltages on an oscilloscope or other signal
analyzer. Use this circuit to measure large-signal and small-signal transient response, slew rate, overshoot, and
capacitive-load stability.
V+
RISO
OPA625
+
V-
O-Scope
CLOAD
RLOAD
+
Input
±
Figure 65. Pulse-Response Measurement Circuit
7.3 AC Parameter Measurements
The circuit shown in Figure 66 is used to measure the ac parameters of the OPAx625. Configure V+, V–, and
CLOAD as desired. The THS4271 are used to buffer the input and output of the OPAx625 to prevent loading by
the gain phase analyzer. Monitor the input and output voltages on a gain phase analyzer. Use this circuit to
measure the gain bandwidth product, and open-loop gain versus frequency versus capacitive load.
249
249
50
+
THS4271
249
Gain/Phase
Analyzer
249
50
1k
1k
+
THS4271
OPA625
+
CLOAD
Figure 66. AC-Parameters Measurement Circuit
24
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7.4 Noise Parameter Measurements
The circuit shown in Figure 67 is used to measure the voltage noise of the OPAx625. Configure V+, V–, and
CLOAD as desired.
10
1k
Spectrum
Analyzer
OPA625
+
CLOAD
Figure 67. Voltage Noise Measurement Circuit
The circuit shown in Figure 68 is used to measure the current noise of the OPAx625. Configure V+, V– and
CLOAD as desired.
Spectrum
Analyzer
OPA625
+
CLOAD
100 k
Figure 68. Current Noise Measurement Circuit
The circuit shown in Figure 69 is used to measure the OPAx625 0.1-Hz to 10-Hz voltage noise. Configure V+,
V–, and CLOAD as desired.
10
0.1 Hz to 10 Hz
Active Bandpass Filter
1k
O-Scope
OPA625
+
40 db/dec
-80 db/dec
CLOAD
Figure 69. 0.1-Hz to 10-Hz Voltage-Noise Measurement Circuit
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8 Detailed Description
8.1 Overview
The OPAx625 is a fast-settling, high slew rate, high-bandwidth, voltage-feedback operational amplifier. Low
offset and low offset drift combine with the superior dynamic performance and very low output impedance,
resulting in an amplifier suited for driving 16-bit SAR ADCs, and buffering precision voltage references in
industrial applications. The OPAx625 is comprised of a low-noise input stage, a slew boost stage, and a rail-torail output stage. A mode bias select feature allows the OPAx625 to be configured in a high-drive mode and a
low-power mode. High-drive mode is used when driving SAR ADCs during the ADC signal acquisition period.
The OPAx625 is also configurable in low-power mode while the SAR ADC is converting the acquired signal, thus
saving overall system power. To facilitate a fast transition from low-power mode to high-drive mode, the
OPAx625 does not completely shut down while in low-power mode; rather, the device remains as an active
amplifier with a lower bandwidth (1 MHz) and relaxed dc specifications.
8.2 Functional Block Diagram
MODE
V+
Mode Select / Bias
+IN
Low Noise Input
Stage
Common
Mode
Feedback
Slew
Boost
Rail-to-Rail
Output Stage
OUT
-IN
Frequency
Compensation
Network
V-
26
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8.3 Feature Description
8.3.1 SAR ADC Driver
The OPAx625 is designed to drive precision (16-bit and 18-bit) SAR ADCs at sample rates up to 1 MSPS. The
combination of low output impedance, low THD, low noise, and fast settling time make the OPAx625 the ideal
choice for driving both the SAR ADC inputs, as well as the reference input to the ADC. Internal slew boost
circuitry increases the slew rate as a function of the input signal magnitude, resulting in settling from a 4-V step
input to 16-bit levels within 280 ns. Low output impedance (1 Ω at 1 MHz) ensures capacitive load stability with
minimal overshoot.
8.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD
circuitry and its relevance to an electrical overstress event is helpful. See Figure 70 for an illustration of the ESD
circuits contained in the OPAx625. The ESD protection circuitry involves several current-steering diodes
connected from the input and output pins and routed back to the internal power-supply lines, where the diodes
meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
V+
MODE
Power Supply
ESD Cell
30
+IN
+
30
± IN
±
OUT
V±
Figure 70. Simplified ESD Circuit
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8.4 Device Functional Modes
The OPAx625 has two functional modes: high-drive and low-power. In low-power mode, the quiescent current of
the OPAx625 is reduced to 270 µA (typ), and results in significantly lower bandwidth, higher noise, and lower
output current drive. The OPAx625 transitions from low-power mode to high-drive mode in 170 ns.
tCONV-MAX
tCONV-MAX
tCONV-MIN
ADC State
Conversion
tCONV-MIN
Acquisition
Conversion
tsettle + tLP-HD
tmargin
MODE
tHD-LP
tLP-HD
tHD-LP
OPAx625
State
Low-Power Mode
High-Drive Mode
Figure 71. Simplified Timing Diagram: Power-Scaling Precision Signal Chain
8.4.1 High-Drive Mode
Place the OPAx625 into high-drive mode by applying a logic level low to the MODE pin. The MODE pin can be
driven by a general-purpose input/output (GPIO) from the system controller, from discrete logic gates, or can be
connected directly to the V– pin. Do not leave the MODE pin floating. When driving the MODE pin from a
microcontroller GPIO, make sure that the GPIO is not placed into a high-impedance state. Placing the GPIO into
a high impedance state results in the MODE pin essentially floating, and is not recommended. Do not drive the
MODE pin voltage below the voltage at the V– pin; see the Absolute Maximum Ratings for the allowable voltage
to drive the MODE pin. Use the MODE pin to force the OPAx625 in either the high-drive mode or the low-power
mode. The OPAx625 has 120-MHz gain bandwidth, 2.5-nV/√Hz input-referred noise, and consumes just 2 mA of
quiescent current in high-drive mode. In addition, the OPAx625 also has an offset voltage of 100 µV (max) and
offset voltage drift of 1 µV/°C (typ). This combination of high precision, high speed, and low noise makes this
device suitable for use as an input driver for high-precision, high-throughput SAR ADCs such as ADS88xx family
of SAR ADC, as shown in Figure 73.
In high-drive mode, the OPAx625 is fully specified as a wideband, low-noise, low-distortion precision amplifier.
High-drive mode is the primary mode of operation of the OPAx625 when driving the inputs of a SAR ADC during
the signal acquisition period just before the start of the conversion period. Placing the OPAx625 into the highdrive mode before the acquisition period is complete, and before the start of the conversion period, allows the
OPAx625 to settle to the final value just prior to the conversion. When the ADC is converting the input signal,
and therefore no longer acquiring the signal, place the OPAx625 into the low-power mode to reduce system
power. Using low-power mode allows the OPAx625 power consumption to scale directly with the sample rate.
The OPAx625 is unique in that the switching between the modes occurs in 170 ns (typ). This fast switching is
achieved by the architecture of the OPAx625 during low-power mode; see the Low-Power Mode section for more
information.
28
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Device Functional Modes (continued)
8.4.2 Low-Power Mode
Place the OPAx625 low-power mode by applying a logic level high to the MODE pin. The MODE pin can be
driven by a GPIO from the system controller, from discrete logic gates, or can be connected to directly to the V+
pin. Do not leave the MODE pin floating. When driving the MODE pin from a microcontroller GPIO, make sure
that the GPIO is not placed into a high-impedance state. Placing the GPIO into a high-impedance state results in
the MODE pin essentially floating, and is not recommended. Do not allow the MODE pin voltage to exceed the
voltage at the V+ pin; see the Absolute Maximum Ratings for the allowable voltage to drive the MODE pin.
In low-power mode, the OPAx625 is fully specified as a general-purpose operational amplifier. The MODE signal
can be controlled so that the OPAx625 is placed in high-drive mode just before the ADC enters the acquisition
phase. This configuration makes sure that the voltage on the antialiasing filter capacitor settles to the required
precision before the acquisition period is complete. The power consumed by the OPAx625 scales with the
throughput of the system when operated in this manner. This feature is extremely useful in power-critical
applications and variable-throughput data acquisition systems.
The OPAx625 is unique in that the switching between the modes occurs in 170 ns (typ). This fast switching is
achieved by the architecture of the OPAx625 during low-power mode. Most amplifiers in power-down or shutdown mode consume very minimal power, but are also not operating in a linear fashion. For example, the output
of a typical amplifier, when disabled, can be placed into a high-impedance state, and thus unable to drive any
load whatsoever. Switching from a shut-down state to a linear state requires charging internal capacitances and
bias points to a level within the linear operating range. Typically, this switch can take several microseconds or
longer. This problem is solved with the OPAx625. The OPAx625 operates as a linear operational amplifier in lowpower mode, and the output tracks the input signal, but with a lower bandwidth and slightly higher offset and
noise. Switching from low-power mode to high-drive mode and settling to 16-bit levels occurs in 170 ns (typ) as a
result of maintaining operation in a linear fashion throughout the duration of each mode. This configuration allows
for dynamic power scaling, while still maintaining high throughput rates.
4
150
MODE Pin
16-bit settling
3
100
2
50
1
0
0
-1
±50
±100
16-bit settling
-3
±150
±200
±200
-2
MODE Pin Voltage (V)
Output Delta from Final Value (µV)
200
0
200
400
600
800
Time (ns)
-4
1000
C032
Figure 72. Output Voltage when Mode Pin Changes High to Low
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx625 is a precision, high-speed, voltage-feedback operational amplifier. Fast settling to 16-bit levels, low
THD, and low noise make the OPAx625 suitable for driving SAR ADC inputs and buffering precision voltage
references. With a wide power-supply voltage range from 2.7 V to 5.5 V, and operating from –40°C to +125°C,
the OPAx625 is suitable for a variety of high-speed, industrial applications. The following sections show
application information for the OPAx625. For simplicity, power-supply decoupling capacitors are not shown in
these diagrams.
9.2 Typical Applications
9.2.1 Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
1k
1k
Mode
Control
5V
Input
Voltage
RFLT
4.7
VREF
OPA625
+
VREF / 4
10 nF
CFLT
3.3 V
REF
AVDD
ADS8860
GND
4.7
RFLT
Figure 73. Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
9.2.1.1 Design Requirements
SAR ADCs, such as the ADS8860, use sampling capacitors on the data converter input. During the signal
acquisition phase, these sampling capacitors are connected to the ADC analog input terminals, AINP and AINN,
through a set of switches. After the acquisition period has elapsed, the internal sampling capacitors are
disconnected from the input terminals and connected to the input of the ADC through a second set of switches,
during this period the ADC is performing the analog-to-digital conversion. Figure 74 illustrates this architecture.
SAR ADC
RSW
AINP
CS/H
RSW
CS/H
AINN
Figure 74. Simplified SAR ADC Input
30
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Typical Applications (continued)
The SAR ADC inputs and sampling capacitors must be driven by the OPA625 to 16-bit levels within the
acquisition time of the ADC. For the example illustrated in Figure 73, the OPA625 is used to drive the ADS8860
at a sample rate of 1 MSPS.
9.2.1.2 Detailed Design Procedure
The circuit illustrated in Figure 73 consists of the SAR ADC driver, a low-pass filter and the SAR ADC. The SAR
ADC driver circuit consists of an OPA625 configured in an inverting gain of 1. The filter consists of RFLT and CFLT,
connected between the output of the OPA625 and input of the ADS8860. Selecting the proper values for each of
these passive components is critical to obtain the best performance from the ADC. Capacitor CFLT serves as a
charge reservoir, providing the necessary charge to the ADC sampling capacitors. The dynamic load presented
by the ADC creates a glitch on the filter capacitor, CFLT. To minimize the magnitude of this glitch, choose a value
for CFLT large enough to maintain a glitch amplitude of less than 100 mV. Maintaining such a low glitch amplitude
at the amplifier output makes sure that the amplifier remains in the linear operating region, and results in a
minimum settling time. Using Equation 6, a 10-nF capacitor is selected for CFLT.
CFLT t 15 u CSH
(6)
Connecting a 10-nF capacitor directly to the output of the OPA625 degrades the OPA625 phase margin and
results in stability and settling-time problems. To properly drive the 10-nF capacitor, use a series resistor (RFLT)
to isolate the capacitor, CFLT, from the OPA625. RFLT must be sized based upon several constraints. To
determination a suitable value for RFLT, consider the impact upon the THD due to the voltage divider effect from
RFLT reacting with the switch resistance (RSW) of the ADC input circuit, as well as the impact of the output
impedance upon amplifier stability. In this example, 4.7-Ω resistors are selected. In this design example,
Figure 16 can be used to estimate a suitable value for RISO. RISO represents the total resistance in series with
CFLT, and in this example is equivalent to 2 × RFLT.
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design, TIDU014, "Power-optimized 16-bit 1MSPS
Data Acquisition Block for Lowest Distortion and Noise Reference Design".
9.2.1.3 Application Curves
Figure 75 illustrates the performance of the circuit shown in Figure 73.
0
THD = -110.8 dBc
SNR = 91.88 dB
SINAD = 91.86 dB
ENOB = 14.97
-25
Amplitude (dB)
-50
-75
-115.91 dBc (Third Harmonic)
-100
-125
-150
-175
0
50
100
150
200 250 300 350
Frequency (kHz)
400
450
500
4096-point FFT at 1 MSPS, fIN = 10 kHz , VIN = 1.5 VRMS
Figure 75. ADC Output FFT for Figure 73
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9.2.2 Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
In order to operate a high-resolution, 16-bit ADC at its maximum throughput, the full-scale voltage step must
settle to better than 16-bit accuracy at the ADC inputs within the minimum specified acquisition time (tACQ). This
settling imposes very stringent requirements on the driver amplifier in terms of large-signal bandwidth, slew rate,
and settling time. Figure 76 illustrates a typical multiplexed ADC driver application using the OPA625.
1.5 pF
8k
2k
Mode
Control
5V
5V
Mux
10
OPA320
+
10
OPA625
+
1 nF
TS5A3159
100 pF
22 µF
Input
Voltage
VREF
4.5 V
RFLT
12.4
CFLT
3.3 V
REF
AVDD
ADS8860
GND
12.4
RFLT
Figure 76. Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
9.2.2.1 Design Requirements
To optimize this circuit for performance, this design does not allow any large signal input transients at the inputs
of the driver circuit for a small quiet-time period (tQT) towards the end of the previous conversion. The input step
voltage can appear anytime from the beginning of conversion (CONVST rising edge) until the elapse of a half
cycle time (0.5 × tCYC). This timing constraint on the input step allows a minimum settling time of (tQT + tACQ) for
the ADC input to settle within the required accuracy, in the worst-case scenario. This provides more time for the
amplifier's output to slew and settle within the required accuracy before the next conversion starts. Figure 77
illustrates this timing sequence.
No Transients Allowed
Transients Allowed
CONVST
0.5 x tCYC_MIN = 500 ns
tQT
Slewing
tACQ
Settling
VIN
tCYC_MIN = 1 µs
Conversion
Sampling
Figure 77. Timing Diagram for Input Signals
32
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9.2.2.2 Detailed Design Procedure
An ADC input driver circuit mainly consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier
is used for signal conditioning of the input voltage and its low output impedance provides a buffer between the
signal source and the ADC input. The RC filter helps attenuate the sampling charge-injection from the switchedcapacitor input stage of the ADC as well as acts as an anti-aliasing filter to band-limit the wideband noise
contributed by the front-end circuit. The design of the ADC input driver involves optimizing the bandwidth of the
circuit, driven primarily by the following requirements:
• The RFLTCFLT filter bandwidth should be low to band-limit the noise fed into the input of the ADC thereby
increasing the signal-to-noise ratio (SNR) of the system.
• The overall system bandwidth should be large enough to accommodate optimal settling of the input signal at
the ADC input before the start of conversion.
CFLT is chosen based upon Equation 7 . CFLT is chosen to be 1 nF.
CFLT t 15 u CSH
(7)
Connecting a 1-nF capacitor directly to the output of the OPA625 would degrade the OPA625 phase margin and
result in stability and settling time problems. To properly drive the 1-nF capacitor, a series resistor, RFLT, is used
to isolate the capacitor, CFLT, from the OPA625. RFLT must be sized based upon several constraints. To
determination a suitable value for RFLT, the system designer must consider the impact upon the THD due to the
voltage divider effect from RFLT reacting with the switch resistance, RSW, of the ADC input circuit as well as the
impact of the output impedance upon amplifier stability. In this example 12.4-Ω resistors are selected. In this
design example, Figure 15 can be used to estimate a suitable value for RISO. RISO represents the total resistance
in series with CFLT, which in this example is equivalent to 2 × RFLT.
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design, TIDU012, "Power-optimized 16-bit 1MSPS
Data Acquisition Block for Lowest Distortion and Noise Reference Design".
9.2.2.3 Application Curves
2
2
1.5
1.5
1
1
0.5
0.5
Error (LSB)
Error (LSB)
Figure 78 illustrates the performance of the circuit shown in Figure 76.
0
-0.5
0
-0.5
-1
-1
-1.5
-1.5
-2
-2
0
500
1000
Time (ns)
1500
2000
Figure 78. Positive Transient Response for Figure 76
0
500
1000
Time (ns)
1500
2000
Figure 79. Negative Transient Response for Figure 76
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10 Power Supply Recommendations
The OPAx625 is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.75 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics. Place bypass capacitors close to the power-supply pins
to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on
bypass capacitor placement, see the Layout section.
CAUTION
Supply voltages larger than 6 V can cause permanent damage to the device. See to
the Absolute Maximum Ratings section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Use bypass capacitors to reduce the noise coupled from the power supply. Connect low ESR, ceramic,
bypass capacitors between the power supply pins (V+ and V–) and the ground plane. Place the bypass
capacitors as close to the device as possible with the 100-nF capacitor closest to the device, as indicated in
Figure 80. For single-supply applications, bypass capacitors on the V– pin are not required.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
SLOA089, Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular
as opposed to in parallel with the noisy trace.
• Minimize parasitic coupling between +IN and OUT for best ac performance.
• Place the external components as close to the device as possible. As shown in Figure 80, keeping RF, CF,
and RG close to the inverting input will minimize parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
34
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11.2 Layout Example
Power Supply
100 nF
1 µF
RIN
+
Input
Output
RG
RF
CF
(Schematic Representation)
Positive Power Supply
1 µF
Ground
Use Low-ESR, ceramic bypass
capacitors.
Place 100 nF capacitor close to the
device
100 nF
Output
1
OUT
Ground
2
V-
3
+IN
Input
V+
6
MODE
5
-IN
4
Ground
MODE pin can be connected to a GPIO on the system
controller for applications requiring the lowest power or
it can be connected to ground for active mode only
Ground
RG
RIN
Place close to the device to
reduce parasitic capacitance
Place close to the device to
reduce parasitic capacitance
RF
CF
Figure 80. PCB Layout Example
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SBOS688A – APRIL 2015 – REVISED OCTOBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
12.1.1.2 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
12.2 Documentation Support
12.2.1 Related Documentation
16-Bit, 1MSPS Multiplexed Data Acquisition Reference Design Guide, TIDUAD9
12.3 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA625
Click here
Click here
Click here
Click here
Click here
OPA2625
Click here
Click here
Click here
Click here
Click here
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided AS IS by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
36
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12.5 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA is a trademark of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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37
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2625IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2625
OPA2625IDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2625
OPA625IDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
O625
OPA625IDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
O625
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA2625IDGSR
Package Package Pins
Type Drawing
VSSOP
DGS
10
OPA2625IDGST
VSSOP
DGS
OPA625IDBVR
SOT-23
DBV
OPA625IDBVT
SOT-23
DBV
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.4
1.4
8.0
12.0
Q1
2500
330.0
12.4
10
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
5.3
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Oct-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2625IDGSR
VSSOP
DGS
10
2500
366.0
364.0
50.0
OPA2625IDGST
VSSOP
DGS
10
250
366.0
364.0
50.0
OPA625IDBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
OPA625IDBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
Pack Materials-Page 2
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