Product Folder Order Now Support & Community Tools & Software Technical Documents LSF0102-Q1 SDLS969 – MAY 2018 LSF0102-Q1 Automotive 2-Channel Auto Bidirectional Multi-Voltage Level Translator 1 Features 2 Applications • • • • • • • • • • • • • • • • AEC-Q100 Qualified for Automotive Applications – Temperature Grade 1: –40°C ≤ TA ≤ 125°C – Device HBM ESD Classification Level 2 – CDM ESD Classification Level C6 Provides Bidirectional Voltage Translation With No Direction Pin Supports open drain and push-pull applications such as I2C, SPI, UART, MDIO, SDIO, and GPIO Supports Up to 100 MHz Up Translation and Greater Than 100 MHz Down Translation at ≤ 30pF Cap Load and Up To 40 MHz Up/Down Translation at 50 pF Cap Load Enables Bidirectional Voltage Level Translation Between – 0.95 V ↔ 1.8/2.5/3.3/5 V – 1.2 V ↔ 1.8/2.5/3.3/5 V – 1.8 V ↔ 2.5/3.3/5 V – 2.5 V ↔ 3.3/5 V – 3.3 V ↔ 5 V Low Standby Current 5 V Tolerant I/O Ports to Support TTL Voltage Levels Low ron Provides Less Signal Distortion High-Impedance I/O pins when EN = Low Flow-Through Pinout for Ease of PCB Trace Routing Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II 3 Description The LSF0102-Q1 device is an auto bidirectional voltage translator that translates among a wide range of supplies without the need for a directional pin. The LSF0102-Q1 supports up to 100 MHz up translation and greater than 100 MHz down translation with capacitive loads ≤ 30 pF. Additionally, the LSF0102Q1 supports up to 40 MHz up and down translation at 50 pF capacitance load, which enables the LSF0102Q1 device to support a wide variety of standard interfaces commonly found in automotive applications such as I2C, SPI, GPIO, SDIO, UART, and MDIO. The LSF0102-Q1 device has 5-V tolerant data inputs. This makes the device compatible with TTL voltage levels. Furthermore, the LSF0102-Q1 supports mixed-mode voltage translation, allowing the device to up translate and down translate to different supply levels on each channel. Device Information(1) PART NUMBER PACKAGE(PINS) LSF0102QDCURQ1 VSSOP (8) BODY SIZE (NOM) 2.30 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Vref_A 2 Infotainment Head Unit Graphical Cluster ADAS Fusion ADAS Front Camera HEV Battery Management System Vref_B LSF0102-Q1 7 8 EN A1 3 SW 6 B1 A2 4 SW 5 B2 1 GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice. PRODUCT PREVIEW 1 LSF0102-Q1 SDLS969 – MAY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 8 8.1 8.2 8.3 8.4 9 Overview ................................................................... 9 Functional Block Diagrams ....................................... 9 Feature Description................................................... 9 Device Functional Modes........................................ 10 Application and Implementation ........................ 10 9.1 Application Information............................................ 10 9.2 Typical Application .................................................. 10 6.1 6.2 6.3 6.4 6.5 6.6 PRODUCT PREVIEW Absolute Maximum Ratings ...................................... 4 ESD Ratings ............................................................ 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics........................................... 5 Switching Characteristics (Translating Down): VGATE = 3.3 V ....................................................................... 6 6.7 Switching Characteristics (Translating Down): VGATE = 2.5 V ....................................................................... 6 6.8 Switching Characteristics Translating Up): VGATE = 3.3 V........................................................................... 6 6.9 Switching Characteristics (Translating Up): VGATE = 2.5 V........................................................................... 6 6.10 Typical Characteristics ............................................ 7 7 Detailed Description .............................................. 9 10 Power Supply Recommendations ..................... 13 11 Layout................................................................... 13 11.1 Layout Guidelines ................................................. 13 11.2 Layout Example .................................................... 13 12 Device and Documentation Support ................. 14 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ....................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 14 14 14 14 14 14 13 Mechanical, Packaging, and Orderable Information ........................................................... 14 Parameter Measurement Information .................. 8 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES May 2018 * Initial release. 2 Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 LSF0102-Q1 www.ti.com SDLS969 – MAY 2018 5 Pin Configuration and Functions LSF0102-Q1 DCU Package 8-Pin VSSOP Top View EN Vref_B GND Vref_A A1 B1 A2 B2 Pin Functions DCU I/O DESCRIPTION A1 3 I/O Input/Output A port for Channel 1 A2 4 I/O Input/Output A port for Channel 2 B1 6 I/O Input/Output B port for Channel 1 B2 5 I/O Input/Output B port for Channel 2 EN 8 I GND 1 — Ground Vref_A 2 — A side reference supply voltage; see Application and Implementation for setup and supply voltage range. Vref_B 7 — B side reference supply voltage. Must be connected to supply through 200 kΩ; see Application and Implementation for setup and supply voltage range. I/O enable input; see Figure 7 for typical setup. Should be tied directly to Vref_B to be enabled or pulled LOW to disable all I/O pins. PRODUCT PREVIEW PIN NAME 3 Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 LSF0102-Q1 SDLS969 – MAY 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) (1) Input voltage (2), VI Input/output voltage (2) , VI/O MIN MAX UNIT –0.5 7 V –0.5 Continuous channel current Input clamp current, IIK VI < 0 Storage temperature range, Tstg –65 Operating junction temperature, TJ (1) (2) 7 V 128 mA –50 mA 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed. 6.2 ESD Ratings VALUE PRODUCT PREVIEW V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2000 Charged-device model (CDM), per AEC Q100-011 ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VI/O Input/output voltage 5 Vref_A/B/EN Reference voltage 5 V IPASS Pass transistor current 64 mA TA Operating free-air temperature 125 °C –40 V 6.4 Thermal Information LSF0102-Q1 THERMAL METRIC (1) DCU (US8) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 229.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 106.5 °C/W RθJB Junction-to-board thermal resistance 141.7 °C/W ψJT Junction-to-top characterization parameter 35.3 °C/W ψJB Junction-to-board characterization parameter 141.4 °C/W (1) 4 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 LSF0102-Q1 www.ti.com SDLS969 – MAY 2018 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VIK Input clamp voltage II = –18 mA, VEN = 0 IIH I/O input high leakage VI = 5 V, VEN = 0 ICCBA Vref_B to Vref_A leakage Vref_B = VEN = 5.5 V, Vref_A = 4.5 V, IO = 0, VI = VCC or GND CI(ref_A/B/EN) Input capacitance Cio(off) I/O pin off-state capacitance Cio(on) I/O Pin on-state capacitance VO = 3 V or 0, VEN = 3 V ron (1) (2) On-state resistance TYP (1) MAX UNIT –1.2 V 5.0 µA 1 µA VI = 3 V or 0 11 pF VO = 3 V or 0, VEN = 0 4.0 6.0 pF 10.5 12.5 pF Vref_A = 3.3 V; Vref_B = VEN = 5 V 8.0 Vref_A = 1.8 V; Vref_B = VEN = 5 V 9.0 Vref_A = 1.0 V; Vref_B = VEN = 5 V 10 Vref_A = 1.8 V; Vref_B = VEN = 5 V 10 Vref_A = 2.5 V; Vref_B = VEN = 5 V 15 VI = 1.8 V, IO = 15 mA Vref_A = 3.3 V; Vref_B = VEN = 5 V 9.0 Ω VI = 1.0 V, IO = 10 mA Vref_A = 1.8 V; Vref_B = VEN = 3.3 V 18 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 3.3 V 20 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 1.8 V 30 Ω VI = 0, IO = 64 mA (2) MIN VI = 0, IO = 32 mA Ω Ω PRODUCT PREVIEW PARAMETER All typical values are at TA = 25°C. Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) pins. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 5 LSF0102-Q1 SDLS969 – MAY 2018 www.ti.com 6.6 Switching Characteristics (Translating Down): VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless otherwise noted) (see Parameter Measurement Information table) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high output From (input) A or B to (output) B or A tPHL Propagation delay time, high-to-low output From (input) A or B to (output) B or A CL = 50 pF MIN TYP CL = 30 pF MAX MIN 1.1 TYP CL = 15 pF MAX MIN 0.7 TYP MAX UNIT 0.3 ns 1.2 0.8 0.4 6.7 Switching Characteristics (Translating Down): VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless otherwise noted) (see Parameter Measurement Information table) PARAMETER TEST CONDITIONS PRODUCT PREVIEW tPLH Propagation delay time, low-to-high output From (input) A or B to (output) B or A tPHL Propagation delay time, high-to-low output From (input) A or B to (output) B or A CL = 50 pF MIN TYP CL = 30 pF MAX MIN 1.2 TYP CL = 15 pF MAX MIN 0.8 TYP MAX UNIT 0.35 ns 1.3 1 0.5 6.8 Switching Characteristics Translating Up): VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL = 300 (unless otherwise noted) (see Parameter Measurement Information table) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high output From (input) A or B to (output) B or A tPHL Propagation delay time, high-to-low output From (input) A or B to (output) B or A CL = 50 pF MIN TYP CL = 30 pF MAX MIN 1 TYP CL = 15 pF MAX MIN 0.8 TYP MAX UNIT 0.4 ns 1 0.9 0.4 6.9 Switching Characteristics (Translating Up): VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL = 300 (unless otherwise noted) (see Parameter Measurement Information table) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high output From (input) A or B to (output) B or A tPHL Propagation delay time, high-to-low output From (input) A or B to (output) B or A 6 CL = 50 pF MIN TYP CL = 30 pF MAX MIN 1.1 TYP 0.9 CL = 15 pF MAX MIN TYP MAX UNIT 0.45 ns 1.3 Submit Documentation Feedback 1.1 0.6 Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 LSF0102-Q1 www.ti.com SDLS969 – MAY 2018 6.10 Typical Characteristics 4.0 Input Output 3.5 3.0 Voltage (V) 2.5 2.0 1.5 1.0 0.5 0.0 ±0.5 0 5 10 15 20 Time (ns) C005 PRODUCT PREVIEW Figure 1. Signal Integrity (1.8 to 3.3 V Translation Up at 50 MHz) Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 7 LSF0102-Q1 SDLS969 – MAY 2018 www.ti.com 7 Parameter Measurement Information The outputs are measured one at a time, with one transition per measurement. All input pulses are supplied by generators that have the following characteristics: • PRR ≤ 10 MHz • ZO = 50 Ω • tr ≤ 2 ns • tf ≤ 2 ns VT RL S1 From Output Under Test S2 CL (1) (1) CL includes probe and jig capactictance. PRODUCT PREVIEW Figure 2. Load Circuit USAGE SWITCH Translating Up Translating Down S1 S2 Figure 3. Translating Up and Down Table 3.3 V VM Input VM 5V VIL Input VM VM VIL 5V Output VM 2V VM VOL Output VM VOL Figure 4. Translating Up 8 VM Figure 5. Translating Down Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 LSF0102-Q1 www.ti.com SDLS969 – MAY 2018 8 Detailed Description 8.1 Overview The LSF0102-Q1 device can be used in level translation applications for interfacing devices or systems operating at different interface voltages. The LSF0102-Q1 device is ideal for use in applications where an open-drain driver is connected to the data I/Os. With appropriate pull-up resistors and layout, the LSF0102-Q1 device can achieve 100 MHz. The LSF0102-Q1 can also be used in applications where a push-pull driver is connected to the data I/Os. 8.2 Functional Block Diagrams Vref_A 2 Vref_B LSF0102-Q1 7 A1 3 SW 6 B1 A2 4 SW 5 B2 1 GND Figure 6. LSF0102-Q1 Functional Block Diagram 8.3 Feature Description 8.3.1 Auto Bidirectional Voltage Translation The LSF0102-Q1 device is an auto bidirectional voltage level translator that operates from 0.95 to 4.5 V on Vref_A and 1.8 to 5.5 V on Vref_B. This allows bidirectional voltage translation between 0.95 V and 5.5 V without the need for a direction pin in open-drain or push-pull applications. The LSF0102-Q1 device supports level translation applications with transmission speeds greater than 100 Mbps for open-drain systems using a 250-Ω pullup resistor with a 30-pF capacitive load. 8.3.2 Output Enable When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. To enable the I/O pins, the EN input should be tied directly to Vref_B. To ensure the highimpedance state during power-up or power-down, EN must be LOW. For additional details on how to use the enable pin, see the Using the Enable Pin with the LSF Family video. Table 1. Enable Function Table (1) INPUT EN (1) PIN FUNCTION Tied directly to Vref_B An = Bn L Hi-Z EN is controlled by Vref_B logic levels and should be at least 1 V higher than Vref_A for best translator. 8.3.3 Mixed-Mode Voltage Translation The supply voltage (Vpu#) for each channel can be individually set up with a pull-up resistor. For example, CH1 can be used in up-translation mode (1.2 V ↔ 3.3 V) and CH2 in down-translation mode (2.5 V ↔ 1.8 V). For additional details on how to use the LSF0102-Q1 for mixed-mode voltage translation, see the Multi-Voltage Translation with the LSF Family video. Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 9 PRODUCT PREVIEW 8 EN LSF0102-Q1 SDLS969 – MAY 2018 www.ti.com 8.4 Device Functional Modes When the An or Bn port is LOW, the switch is in the ON-state and a low resistance connection exists between the An and Bn ports. The low Ron of the switch allows connections to be made with minimal propagation delay and signal distortion. Assuming the higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is limited to the voltage set by Vref_A. When the An port is HIGH, the Bn port is pulled to the drain pullup supply voltage (Vpu#) by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for direction control. For additional details on the functional operation of the LSF0102-Q1, see the Down Translation with the LSF Family and Up Translation with the LSF Family videos. 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. PRODUCT PREVIEW 9.1 Application Information The LSF0102-Q1 device is able to perform voltage translation for open-drain or push-pull interfaces such as I2C, SPI, UART, MDIO, SDIO, and GPIO. 9.2 Typical Application 9.2.1 Bidirectional Translation VB_Pullup = 3.3 V 200 NŸ Vref_A = 1.2 V Vref_A 2 Vref_B LSF0102-Q1 7 Rpu Vpu3 = 2.5 V Rpu 8 VCC GPIO3 VCC A1 A2 3 Vpu1 = 3.3 V SW 6 SW 5 EN B1 B2 Rpu VCC GPIO1 GPIO2 4 GPIO3 GND 1 GND GND Figure 7. Bidirectional Translation to Multiple Voltage Levels 9.2.1.1 Design Requirements 9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines The LSF0102-Q1 device has an EN input that is used to disable the device by setting EN LOW, which places all I/Os in the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is very low. It is recommended to always enable LSF0102-Q1 device for bidirectional applications by connecting the EN pin to the Vref_B pin, as shown in Figure 7. For additional details on setting up the Vref_A, Vref_B, and EN pins, see the Understanding the Bias Circuit for the LSF Family video. 10 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 LSF0102-Q1 www.ti.com SDLS969 – MAY 2018 Typical Application (continued) Table 2. Application Operating Condition PARAMETER MIN TYP MAX UNIT Vref_A (1) reference voltage (A) 0.95 4.5 V Vref_B reference voltage (B) Vref_A + 0.8 5.5 V VI(EN) input voltage on EN pin Vref_A + 0.8 5.5 V Vpu pull-up supply voltage Vref_B V (1) Vref_B 0 Vref_A is required to be the lowest voltage level across all inputs and outputs. The 200 kΩ, pull-up resistor is required to allow Vref_B to regulate the EN input. A filter capacitor on Vref_B is recommended. Also Vref_B and VI(EN) are recommended to be 1.0 V higher than Vref_A for best signal integrity. 9.2.1.2 Detailed Design Procedure For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to Vref_B and both pins pulled to HIGH side Vpu through a pull-up resistor (typically 200 kΩ), as shown in Figure 7. This allows Vref_B to regulate the EN input. A filter capacitor on Vref_B is recommended. The master output driver can be push-pull or open-drain (pull-up resistors may be required) and the slave device output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu). If either output is push-pull, data must be unidirectional or the outputs must be tri-state and be controlled by some direction-control mechanism to prevent HIGH-to-LOW contention in either direction. If both outputs are open-drain, no direction control is needed. In Figure 7, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage. When Vref_B is connected through a 200 kΩ resistor to a 3.3 V Vpu power supply, and Vref_A is set 1.2 V. The output of A1 has a maximum output voltage equal to Vref_A, and the bidirectional interface on channel 2 has a maximum output voltage equal to Vpu. 9.2.1.2.2 Pull-up Resistor Sizing To maintain an appropriate output low voltage, the pull-up resistor value should limit the current through the pass transistor when it is in the ON state to less than 15 mA. This ensures a pass voltage of 260 mV to 350 mV. To set the current through each pass transistor at 15 mA, the pull-up resistor value can be calculated using the following equation: Rpu = (Vpu – 0.35 V) / 0.015 A (1) The appropriate pull up resistor will depend on the current requirements of the application. Table 3 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of the transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the LSF0102Q1 device at 0.175 V, although the 15 mA applies only to current flowing through the LSF0102-Q1. Table 3. Pull-up Resistor Values (1) (2) VDPU (1) (2) (3) 15 mA NOMINAL (Ω) 10 mA +10% (3) (Ω) NOMINAL (Ω) 3 mA +10% (3) (Ω) NOMINAL (Ω) +10% (3) (Ω) 5V 310 341 465 512 1550 1705 3.3 V 197 217 295 325 983 1082 2.5 V 143 158 215 237 717 788 1.8 V 97 106 145 160 483 532 1.5 V 77 85 115 127 383 422 1.2 V 57 63 85 94 283 312 Calculated for VOL = 0.35 V Assumes output driver VOL = 0.175 V at stated current +10% to compensate for VDD range and resistor tolerance Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 11 PRODUCT PREVIEW 9.2.1.2.1 Bidirectional Translation LSF0102-Q1 SDLS969 – MAY 2018 www.ti.com 9.2.1.3 Application Curve 4 Input Output 3 Voltage (V) 2 1 0 -1 0 50 100 150 200 250 300 350 400 450 500 PRODUCT PREVIEW Time (ns) 2 Figure 8. Captured Waveform From Above I C Set-Up (1.8 V to 3.3 V at 2.5 MHz) 12 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 LSF0102-Q1 www.ti.com SDLS969 – MAY 2018 10 Power Supply Recommendations There are no power sequence requirements for the LSF family. For recommended operating voltages for all supply and input pins, see Table 5. Table 4. Recommended Operating Voltages PARAMETER MIN TYP MAX UNIT Vref_A (1) reference voltage (A) 0.95 4.5 V Vref_B reference voltage (B) Vref_A + 0.8 5.5 V VI(EN) input voltage on EN pin Vref_A + 0.8 5.5 V Vpu pull-up supply voltage 0 Vref_B V (1) Vref_A is required to be the lowest voltage level across all inputs and outputs. 11 Layout Because the LSF0102-Q1 device is a switch-type level translator, the signal integrity is dependent upon the pullup resistor value and PCB board parasitics. Consider the following recommendations when designing with the LSF0102-Q1. • Minimize the signal trace length to reduce capacitance • Avoid using stubs in the signal path to reduce parasitics. • Place the LSF0102-Q1 device near the high voltage side. • Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter. 11.2 Layout Example LSF0102-Q1 GND Vref_A A1 A2 1 2 3 4 8 7 6 5 EN Short Signal Trace as possible Vref_B B1 B2 Minimize Stub as possible Figure 9. Short Trace Layout TP1 SD Controller (1.8V IO) LSF0102-Q1 SDIO level translator SDIO Connector (3.3V IO) Device PCB TP2 Figure 10. Device Placement Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 13 PRODUCT PREVIEW 11.1 Layout Guidelines LSF0102-Q1 SDLS969 – MAY 2018 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Texas Instruments, TI Logic Minute: Introduction – Voltage Level Translation with the LSF Family video • Texas Instruments, Voltage-Level Translation With the LSF Family application report 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 5. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LSF0102 Click here Click here Click here Click here Click here PRODUCT PREVIEW 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Product Folder Links: LSF0102-Q1 PACKAGE OPTION ADDENDUM www.ti.com 23-May-2018 PACKAGING INFORMATION Orderable Device Status (1) LSF0102QDCURQ1 ACTIVE Package Type Package Pins Package Drawing Qty VSSOP DCU 8 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR Op Temp (°C) Device Marking (4/5) -40 to 125 NG2SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF LSF0102-Q1 : Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-May-2018 • Catalog: LSF0102 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. 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