L5150CJ
L5150CS
5 V low dropout voltage regulator
Datasheet − production data
Features
Max DC supply voltage
VS
40 V
Max output voltage tolerance
ΔVo
+/-2%
Max dropout voltage
Vdp
500 mV
Io
150 mA
Iqn
µA(1)
Output current
Quiescent current
55
*$3*36
PowerSSO-12
*$3*36
SO-8
1. Typical value
Description
■
Operating DC supply voltage range
5.6 V to 40 V
■
Low dropout voltage
■
Low quiescent current consumption
■
Precision output voltage 5 V +/- 2%
■
Reset circuit sensing the output voltage
■
Programmable reset pulse delay with external
capacitor
■
Adjustable reset threshold
■
Early warning
■
Very wide stability range with low value output
capacitor
■
Thermal shutdown and short-circuit protection
■
Wide temperature range (Tj = -40 °C to 150 °C)
Table 1.
L5150CJ and L5150CS are low dropout linear
regulators with microprocessor control functions
such as power on reset, low voltage reset, early
warning.
Typical quiescent current is 55 µA at very low
output current.
On chip trimming results in high output voltage
accuracy (2%). Accuracy is kept over wide
temperature range, line and load variation. Early
warning circuit monitors the input voltage and
compares it with an internal voltage reference.
Output voltage reset threshold can be adjusted
down to 3.5 V by means of an external voltage
divider.
The maximum input voltage is 40 V. The max
output current is internally limited. Internal
temperature protection disables the voltage
regulator output. In addition, only low-value
ceramic capacitor on output is required for
stability.
Device summary
Order codes
Package
Tube
Tape & reel
PowerSSO-12
L5150CJ
L5150CJTR
SO-8
L5150CS
L5150CSTR
September 2013
This is information on a product in full production.
Doc ID 15542 Rev. 15
1/34
www.st.com
1
Contents
L5150CJ / L5150CS
Contents
1
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
5
6
2/34
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4
PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5
SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PowerSSO-12 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 15542 Rev. 15
3/34
List of figures
L5150CJ / L5150CS
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
4/34
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output voltage vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output voltage vs. VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Drop voltage vs. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. output current (at light load condition). . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. input voltage (Io = 0.1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption vs. input voltage (Io = 75 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current limitation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current limitation vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Short-circuit current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Short-circuit current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VRhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VRlth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VEWi_thh vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VEWi_thl vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Icr vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Idr vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Stability region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Early warning time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PowerSSO-12 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 19
PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 20
Thermal fitting model of Vreg in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SO-8 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 22
SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Thermal fitting model of Vreg in in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
1
Block diagram and pins description
Block diagram and pins description
Figure 1.
Block diagram
9R
9V
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5HVHW
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7KUHVKROG
3RZHU
92/7$*(
5HV$GM
'ULYHU
5()(5(1&(
7KHUPDO
&XUUHQW
6KXWGRZQ
OLPLWHU
5HV
/RZ9ROWDJH
5HVHW
9FU
(:R
(:L
*1'
*$3*&)7
Figure 2.
Configuration diagram (top view)
7$% 6XEVWUDWH
62
*$3*&)7
3RZHU662
*$3*&)7
Doc ID 15542 Rev. 15
5/34
Block diagram and pins description
Table 2.
Pin name
6/34
L5150CJ / L5150CS
Pins description
PowerSSO-12
pin #
SO-8
pin #
Function
Res_Adj
1
8
Reset adjustable threshold. Connected to an
appropriate external voltage divider, it allows to
properly set the reset threshold down to 3.5 V.
Connect to GND if not needed.
Res
2
1
Reset output. Internally connected to Vo through a
20 KΩ pull up resistor. This pin is pulled low when
Vo < Vo_th. Keep open if not needed.
Vcr
3
2
Reset delay. Connect an external capacitor between
Vcr pin and ground to adjust the reset delay time.
Keep open if not needed.
GND
4
3
Ground reference.
NC
5, 11, 8, 9
-
Not connected.
Vo
6
4
5 V regulated output. Block to GND with a ceramic
capacitor (Co ≥ 220 nF for regulator stability).
VS
7
5
Supply voltage, block directly to GND on the IC with a
capacitor.
EWi
10
6
Early warning input. This pin monitors the VS voltage
level through a resistor divider. Connect to VS if not
needed.
EWo
12
7
Early warning output. Internally connected to Vo
through 20 KΩ pull up resistor. This pin is pulled low
when EWi is below bandgap reference voltage. Keep
open if not needed.
TAB
-
-
TAB is connected to the substrate of the chip: connect
toGND or leave open (see Figure 2 for PowerSSO-12
only).
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the Table 3: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
-0.3 to 40
V
Vsdc
DC supply voltage
Isdc
Input current
Vodc
DC output voltage
-0.3 to 6
Iodc
DC output current
internally limited
Vod Res
Open drain output voltage Res
-0.3 to Vodc + 0.3
Iod Res
Open drain output current Res
internally limited
VRes_adj
VRes_adj voltage
-0.3 to Vodc + 0.3
V
Vod EWo
Open drain output voltage EWo
-0.3 to Vodc + 0.3
V
Iod EWo
Open drain output current EWo
internally limited
Vcr voltage
-0.3 to Vo + 0.3
V
Early warning input voltage
-0.3 to 40
V
Junction temperature
-40 to 150
°C
+/- 2
kV
+/- 750
V
Vcr
VEWi
Tj
internally limited
VESD HBM
ESD HBM voltage level (HBM-MIL STD 883C)
VESD CDM
ESD CDM voltage level (CDM- )
Doc ID 15542 Rev. 15
V
V
7/34
Electrical specifications
2.2
L5150CJ / L5150CS
Thermal data
Table 4.
Thermal data
Value
Symbol
Parameter
Unit
PowerSSO-12
Rthj-case
Thermal resistance junction to case:
Rthj-lead
Thermal resistance junction to lead:
Rthj-amb(1)
SO-8
8
Thermal resistance junction to ambient:
°K/W
52
40
°K/W
112
°K/W
1. PowerSSO-12: The values quoted are for PCB 77 mm x 86 mm x 1.6 mm, FR4, double copper layer with
single heatsink layer, copper thickness 70 µm, thermal vias, copper area 2 cm2.
SO-8: The values quoted are for PCB 48 mm x 48 mm x 2 mm, FR4, double copper layer with single
heatsink layer, copper thickness 35 µm, copper area 2 cm2.
2.3
Electrical characteristics
Values specified in this section are for VS = 5.6 V to 31 V, Tj = -40 °C to +150 °C unless
otherwise stated.
Table 5.
Pin
Symbol
Vo
Vo_ref
Output voltage
VS = 8 V to 18 V
Io = 8 mA to 150 mA
4.9
5.0
5.1
V
Vo
Vo_ref
Output voltage
VS = 5.6 V to 31 V
Io = 8 mA to 150 mA
4.85
5.0
5.15
V
Vo
Vo_ref
Output voltage
VS = 5.6 V to 31 V
Io = 0.1 mA to 8 mA
4.75
5.0
5.25
V
Vo
Ishort
Short-circuit current
VS = 13.5 V
0.65 0.95 1.25
A
VS = 13.5 V
280
Vo
Ilim
VS, Vo
Vline
Vo
8/34
General
Vload
Parameter
Output current capability
Test condition
(1)
Line regulation voltage
Load regulation voltage
470
Unit
660
mA
VS = 6 V to 28 V
Io = 30 mA
40
mV
VS = 8 V to 18 V,
Io = 8 mA to 150 mA
55
mV
VS = 13.5 V,
Tj = 25 °C
Io = 8 mA to 150 mA
40
500
VS, Vo
Vdp
Drop voltage (2)
Io = 150 mA
VS, Vo
SVR
Ripple rejection
fr = 100 Hz(3)
Vo
Ioth_H
Normal consumption mode
output current
VS = 8 V to 18 V
Vo
Ioth_L
Very low consumption mode
VS = 8 V to 18 V
output current
Vo
Ioth_Hyst
Output current switching
threshold hysteresis
Min. Typ. Max.
VS = 13.5 V
Tj = 25 °C
Doc ID 15542 Rev. 15
60
mV
dB
8
mA
1.1
0.8
mA
mA
L5150CJ / L5150CS
Table 5.
Pin
VS, Vo
VS, Vo
Electrical specifications
General (continued)
Symbol
Parameter
Current consumption
Iqn_1 = IVs – Io
Iqn_1
Iqn_150
Current consumption
Iqn_150 = IVs – Io
Test condition
Min. Typ. Max.
VS = 13.5 V,
Io = 0.1 mA to 1 mA,
Tj = 25 °C
55
VS = 13.5 V,
Io = 0.1 mA to 1 mA,
95
VS = 13.5 V
Io = 150 mA
3
150
Thermal protection
temperature hysteresis
Tw_hy
80
µA
Thermal protection
temperature
Tw
Unit
4.2
mA
190
°C
10
°C
1. Measured Output Current when the output voltage has dropped 100 mV from its nominal Value obtained at
13.5 V and Io =75 mA.
2. Vs - Vo Measured Dropout when the output voltage has dropped 100 mV from its nominal Value obtained
at 13.5 V and Io =75 mA.
3. Guaranteed by design.
Table 6.
Reset
Pin
Symbol
Parameter
Res
Vres_l
Reset output low
voltage
Res
IRes_lkg
Res
Test condition
Min.
Typ.
Max.
Unit
Rext = 5 kΩ
Vo > 1 V
0.4
V
Reset output high
leakage current
VRes = 5 V
1
µA
RRes
Pull up internal
resistance
Versus Vo
Res
Vo_th
Vo out of regulation Vres_adj < 0.2 V,
threshold
Vo decreasing
Res_adj
Vres_adj
Res_adj
10
20
40
kΩ
6
8
10
% Below
Vo_ref
Reset adjustable
switching threshold
2.35
2.5
2.65
V
VRes_adjl
Reset adjustable
low voltage
0.4
0.9
1.3
V
Res_adj
IRes_adj_lkg
Reset adjustable
leakage current
Vres_adj = 2.5 V
-1
1
µA
Vcr
VRlth
Reset timing low
threshold
VS = 13.5 V
15
18
22
% Vo_ref
Vcr
VRhth
Reset timing high
threshold
VS =13.5 V
47
50
53
% Vo_ref
Vcr
Icr
Charge current
VS = 13.5 V
10
20
30
µA
Vcr
Idr
Discharge current
VS = 13.5 V
10
20
30
µA
Doc ID 15542 Rev. 15
9/34
Electrical specifications
Table 6.
Reset (continued)
Pin
Symbol
Parameter
Res
Trr
Reset reaction time
Res
Trd
Reset delay time
Table 7.
10/34
L5150CJ / L5150CS
Test condition
VS = 13.5 V;
Ctr = 1000 pF
Min.
Max.
Unit
2
µs
4
11
ms
Min.
Typ.
Max.
Unit
2
Typ.
Early warning
Pin
Symbol
Parameter
Test condition
EWi
VEWi_thl
EW input low threshold
voltage
2.35
2.50
2.65
V
EWi
VEWi_thh
EW input high
threshold voltage
2.42
2.57
2.72
V
EWi
VEWi_thhyst
EWi
IEWi_lkg
EWo
REWo
EWo
EWo
EW input threshold
hysteresis
70
EW input leakage
current
VEWi = 2.5 V,
VS > 4 V
-1
Pull up internal
resistance
Versus Vo
10
VEWo_lv
EW output low voltage
(with external pull up)
VEWi < 2.35 V;
VS > 4 V;
Rext = 5 kΩ
IEWo_lkg
EW output leakage
current
VEWo = 5 V
Doc ID 15542 Rev. 15
20
mV
1
µA
40
kΩ
0.4
V
1
µA
L5150CJ / L5150CS
Electrical specifications
2.4
Electrical characteristics curves
Figure 3.
Output voltage vs. Tj
Figure 4.
Output voltage vs. VS
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Drop voltage vs. output current
Figure 6.
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current
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Figure 7.
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current (at light load condition)
Figure 8.
Current consumption vs. input
voltage (Io = 0.1 mA)
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Doc ID 15542 Rev. 15
11/34
Electrical specifications
Figure 9.
L5150CJ / L5150CS
Current consumption vs. input
voltage (Io = 75 mA)
Figure 10. Current limitation vs. Tj
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Figure 11.
Current limitation vs. input voltage Figure 12. Short-circuit current vs. Tj
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Figure 13. Short-circuit current vs. input
voltage
Figure 14. VRhth vs. Tj
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12/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Electrical specifications
Figure 15. VRlth vs. Tj
Figure 16. VEWi_thh vs. Tj
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Figure 17. VEWi_thl vs. Tj
Figure 18. Icr vs. Tj
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Figure 19. Idr vs. Tj
Figure 20. PSRR
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Doc ID 15542 Rev. 15
13/34
Application information
L5150CJ / L5150CS
3
Application information
3.1
Voltage regulator
The voltage regulator uses a p-channel mos transistor as a regulating element. With this
structure a very low dropout voltage at current up to 150 mA is obtained. The output voltage
is regulated up to input supply voltage of 40 V. The high-precision of the output voltage (2%)
is obtained with a pre-trimmed reference voltage. The voltage regulator automatically
adapts its own quiescent current to the output current level. In light load conditions the
quiescent current goes to 55 µA only (low consumption mode). This procedure features a
certain hysteresis on the output current (see Figure 7). Short-circuit protection to GND and a
thermal shutdown are provided.
Figure 21. Application schematic
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The input capacitor C 1 ≥ 100 µF is necessary as backup supply for negative pulses which
may occur on the line. The second input capacitor C2 ≥ 220 nF is needed when the C1 is too
distant from the VS pin and it compensates smooth line disturbances. The C0 ceramic
capacitor, connected to the output pin, is for bypassing to GND the high-frequency noise
and it guarantees stability even during sudden line and load variations. Suggested value is
C0 = 220 nF?with ESR ≥ 100 mΩ .
Stability region is reported in Figure 22.
14/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Application information
Figure 22. Stability region
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Note: The curve which describes the minimum ESR is derived from characterization data on the regulator
with connected ceramic capacitors which feature low ESR values (at 100 kHz). Any capacitor with
further lower ESR than the given plot value must be evaluated in each and every case.
Figure 23. Maximum load variation response
Vo = 50 mV/div
Io = 50 mA/div
VS = 13.5 V
Io = 8 to 300 mA
Tc = 25 °C
Co = 220 nF
GAPGCFT00128
Doc ID 15542 Rev. 15
15/34
Application information
3.2
L5150CJ / L5150CS
Reset
The reset circuit monitors the output voltage Vo. If the output voltage becomes lower than
Vo_th then Res goes low with a delay time (trr). When the output voltage becomes higher
than Vo_th then Res goes high with a delay time trd. This delay is obtained by 32 periods of
oscillator. The oscillator period is given by:
Equation 1
Tosc = [(VRhth - VRlth) x Ctr] / Icr + [(VRhth - VRlth) x Ctr] / Idr
where:
Icr = 20 µA is an internally generated charge current,
Idr = 20 µA is an internally generated discharge current,
VRhth = 2.5 V (typ) and VRlth = 0.9 V (typ) are two voltage thresholds,
Ctr is an external capacitor put between Vcr pin and GND.
16/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Application information
Reset pulse delay Trd is given by:
Equation 2
trd = 32 x Tosc
The Output Voltage Reset threshold can be adjusted via an external voltage divider R1 + R2
(R1 connected between Res_Adj and V0, R2 connected between Res_Adj and GND) according
to the following formula:
Equation 3
Vthre = [(R1 + R2) / R2] * VRes_adj
The Output Voltage Reset threshold can be decreased down to 3.5 V. If it is needed to
maintain it to its default value (8% below V0_ref typical), it is enough to connect the Res_Adj
pin directly to GND.
Figure 24. Reset time diagram
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Doc ID 15542 Rev. 15
17/34
Application information
3.3
L5150CJ / L5150CS
Early warning
This circuit compares the EWi input signal with the internal voltage reference (typically
2.5 V). The use of an external voltage divider makes the comparator very flexible in the
application. This function can be used to supervise the supply input voltage either before or
after the protection diode and to give additional information to the microprocessor such as
low voltage warnings.
Figure 25. Early warning time diagram
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18/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Package and PCB thermal data
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 26. PowerSSO-12 PC board(1)
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1. Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias,
FR4 area = 77 mm x 86 mm, PCB thickness = 1.6 mm, Cu thickness = 70 µm (front and back side),
thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 25 µm,
footprint dimension 4.1 mm x 6.5 mm ).
Figure 27. Rthj-amb vs PCB copper area in open box free air condition
57+MDPE
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Doc ID 15542 Rev. 15
19/34
Package and PCB thermal data
L5150CJ / L5150CS
Figure 28. PowerSSO-12 thermal impedance junction ambient single pulse
=7+ &:
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Equation 4: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
Figure 29. Thermal fitting model of Vreg in PowerSSO-12
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20/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Table 8.
Package and PCB thermal data
PowerSSO-12 thermal parameter
Area (cm2)
Footprint
R1 (°K/W)
1.53
R2 (°K/W)
3.21
R3 (°K/W)
5.2
R4 (°K/W)
2
8
7
7
8
R5 (°K/W)
22
15
10
R6 (°K/W)
26
20
15
C1 (W.s/°K)
0.00004
C2 (W.s/°K)
0.0016
C3 (W.s/°K)
0.08
C4 (W.s/°K)
0.2
0.1
0.1
C5 (W.s/°K)
0.27
0.8
1
C6 (W.s/°K)
3
6
9
Doc ID 15542 Rev. 15
21/34
Package and PCB thermal data
4.2
L5150CJ / L5150CS
SO-8 thermal data
Figure 30. SO-8 PC board(1)
*$3*&)7
1. Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias,
FR4 area = 48 mm x 48 mm, PCB thickness = 2 mm, Cu thickness = 35 µm (front and back side),
Cu thickness on vias 25 µm, Footprint dimension 4.1 mm x 6.5 mm ).
Figure 31. Rthj-amb vs. PCB copper area in open box free air condition
57+MDPE
57+MDPE
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22/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Package and PCB thermal data
Figure 32. SO-8 thermal impedance junction ambient single pulse
=7+ &:
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Equation 5: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
Figure 33. Thermal fitting model of Vreg in in SO-8
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Doc ID 15542 Rev. 15
23/34
Package and PCB thermal data
Table 9.
24/34
L5150CJ / L5150CS
SO-8 thermal parameter
Area (cm2)
Footprint
R1 (°K/W)
1.53
R2 (°K/W)
3.21
R3 (°K/W)
5.4
R4 (°K/W)
32
R5 (°K/W)
34
R6 (°K/W)
52
C1 (W.s/°K)
0.00004
C2 (W.s/°K)
0.0016
C3 (W.s/°K)
0.04
C4 (W.s/°K)
0.05
C5 (W.s/°K)
0.15
C6 (W.s/°K)
1
Doc ID 15542 Rev. 15
2
36
2.5
L5150CJ / L5150CS
Package and packing information
5
Package and packing information
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-12 mechanical data
Figure 34. PowerSSO-12 package dimensions
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Doc ID 15542 Rev. 15
25/34
Package and packing information
Table 10.
L5150CJ / L5150CS
PowerSSO-12 mechanical data
Millimeters
Symbol
Min.
Max.
A
1.250
1.620
A1
0.000
0.100
A2
1.100
1.650
B
0.230
0.410
C
0.190
0.250
D
4.800
5.000
E
3.800
4.000
e
0.800
H
5.800
6.200
h
0.250
0.500
L
0.400
1.270
k
0°
8°
X
1.900
2.500
Y
3.600
4.200
ddd
26/34
Typ.
0.100
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
5.3
Package and packing information
SO-8 package information
Figure 35. SO-8 package dimensions
Doc ID 15542 Rev. 15
27/34
Package and packing information
Table 11.
L5150CJ / L5150CS
SO-8 mechanical data
Millimeters
Symbol
Min.
Typ.
A
Max.
1.75
A1
0.10
A2
1.25
b
0.28
0.48
c
0.17
0.23
D(1)
4.80
4.90
5.00
E
5.80
6.00
6.20
E1(2)
3.80
3.90
4.00
e
0.25
1.27
h
0.25
0.50
L
0.40
1.27
L1
k
1.04
0°
ccc
8°
0.10
1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
28/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
5.4
Package and packing information
PowerSSO-12 packing information
Figure 36. PowerSSO-12 tube shipment (no suffix)
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Doc ID 15542 Rev. 15
29/34
Package and packing information
5.5
L5150CJ / L5150CS
SO-8 packing information
Figure 38. SO-8 tube shipment (no suffix)
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30/34
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
6
Revision history
Revision history
Table 12.
Document revision history
Date
Revision
09-Aug-2007
1
Initial release.
2
Updated Table 5.: General:
– changed Vo_ref, Vline, Vload test conditions
– added notes to Ilim and Vdp parameters
– added Ioth_H, Ioth_L, Ioth parameters.
Updated Table 6.: Reset:
– added Vres_adj parameter
– changed VRlth values (min./ typ./ max.) from 17/20/23 to 20/23/26
(% Vo_ref).
Modified Section 3.2: Reset.
3
Updated Table 5.: General :
– changed Ilim values (Min./Typ./Max.) from 0.7/1/1.30 A to
280/470/660 mA
– Vo_ref parameter : updated Io test condition
Old -> Io = 0.1 mA to I0 mA
New -> Io = 0.1 mA to 8 mA.
13-Oct-2008
4
Updated Table 5.: General :
– Vload parameter : updated Io test condition
Old -> Io = 5 mA to I50 mA
New -> Io = 8 mA to 150 mA.
23-Oct-2008
5
Added S0-8 package option.
06-Mar-2008
09-May-2008
Changes
Doc ID 15542 Rev. 15
31/34
Revision history
L5150CJ / L5150CS
Table 12.
Document revision history (continued)
Date
16-Apr-2009
32/34
Revision
Changes
6
Updated corporate template from V2 to V3
Updated Figure 2: Configuration diagram (top view)
Table 2: Pins description
– Added new row
Table 3: Absolute maximum ratings
– VEn: deleted row
Table 4: Thermal data
– Rthj-amb: changed value
– Added new row
– Updated TableFootnote
Table 5: General
– Vload: changed max value for Vs = 8 V to 18 V, added new row
– Iqn_1: changed Test conditions (added Tj = 25 °C), added new row
Table 6: Reset
– VRlth: changed min/typ/max value
– VRes_adjl: replaced with VRlth, changed Parameter
Table 7: Early warning
– Updated symbols
Added Figure 3: Output voltage vs. Tj
Added Figure 4: Output voltage vs. VS
Added Figure 5: Drop voltage vs. output current
Added Figure 6: Current consumption vs. output current
Added Figure 7: Current consumption vs. output current (at light load
condition)
Added Figure 8: Current consumption vs. input voltage (Io = 0.1 mA)
Added Figure 9: Current consumption vs. input voltage (Io = 75 mA)
Added Figure 10: Current limitation vs. Tj
Added Figure 11: Current limitation vs. input voltage
Added Figure 12: Short-circuit current vs. Tj
Added Figure 13: Short-circuit current vs. input voltage
Added Figure 14: VRhth vs. Tj
Added Figure 15: VRlth vs. Tj
Added Figure 16: VEWi_thh vs. Tj
Added Figure 17: VEWi_thl vs. Tj
Added Figure 18: Icr vs. Tj
Added Figure 19: Idr vs. Tj
Added Figure 20: PSRR
Section 3.1: Voltage regulator
– Updated text
– Added Figure 21: Application schematic
– Added Figure 23: Maximum load variation response
Section 3.2: Reset
– VRlth: changed value from 1.15 V to 0.9 V in Equation 1
Added Section 4: Package and PCB thermal data
Changed Section 5.1: ECOPACK®
Doc ID 15542 Rev. 15
L5150CJ / L5150CS
Table 12.
Revision history
Document revision history (continued)
Date
Revision
Changes
7
Changed document title
Table 5: General
– Ioth_H, Ioth_L: added test condition
Updated Figure 4: Output voltage vs. VS
Section 3.3: Early warning
– changed internal voltage reference typical value
from 1.23 V to 2.5 V
Updated Figure 28: PowerSSO-12 thermal impedance junction
ambient single pulse
Updated Figure 32: SO-8 thermal impedance junction ambient single
pulse
04-Dec-2009
8
Updated features list.
Updated Table 2: Pins description.
Updated Section 3.1: Voltage regulator.
Corrected Equation 3 on Section 3.2: Reset.
26-Mar-2010
9
Updated Table 5: General:
– Iqn_1, Iqn_150: removed test condition En = high.
12-Apr-2010
10
Table 4: Thermal data:
– Rthj-amb: updated PowerSSO-12 value
14-Mar-2011
11
Table 4: Thermal data:
– Rthj-amb: updated PowerSSO-12 value
– Rthj-lead: updated SO-8 value
30-Jan-2012
12
Updated Figure 22: Stability region on page 15.
07-Feb-2012
13
Modified Figure 22: Stability region on page 15.
17-Apr-2012
14
Table 6: Reset:
– Trd: updated maximum value
19-Sep-2013
15
Updated disclaimer.
09-Jun-2009
Doc ID 15542 Rev. 15
33/34
L5150CJ / L5150CS
Please Read Carefully:
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34/34
Doc ID 15542 Rev. 15