Keysight M3300A-K32 Pxie arbitrary waveform generator and digitizer combo with optional real-time sequencing and fpga programming Datasheet

Keysight M3300A
PXIe Arbitrary Waveform Generator and
Digitizer Combo with Optional Real-Time
Sequencing and FPGA Programming
500 MSa/s, 16 Bits, 2/4 Channel AWG + 100 MSa/s,
14 Bits, 4/8 Channel Digitizer
Data Sheet
02 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Fast, Flexible, High-Performance Control, Testing
and Prototyping
The M3300A combines high-performance with arbitrary waveform generator channels
and digitizer channels in the same module providing the ideal tool for testing and
prototyping in control or communications applications. Performance meets simplicity
thanks to easy-to-use programming libraries, real-time sequencing technology (Hard
Virtual Instrumentation or HVI), and graphical FPGA programming technology.
Features
Outputs (AWG)
–– 500 MSa/s, 16 Bits, 2/4 Channels
Inputs (digitizer)
–– 100 MSa/s, 14 Bits, 4/8 Channels
Output features
–– AWGs, function generators, AM/FM/PM modulators
–– Advanced triggering and marking functionalities
Input features
–– Powerful data acquisition system (DAQ)
–– Advanced triggering and marking functionalities
Less than 400 ns input to output latency
Optional HW programming for high-performance applications
–– Real-time sequencing (HVI technology)
–– FPGA programming
–– Xilinx Kintex-7 325T or 410T FPGA
Up to 2 GB of onboard RAM (~ 1 Gsamples)
Mechanical/interface
–– 2 slots 3U (PXIe)
–– Up to 1.6 GB/s transfer BW with P2P capabilities (PCIe Gen 2)
–– Independent DMA channels for fast and efficient data transfer
Applications
General purpose AWGs & digitizers
High-performance control
Communications: BB/IF SDR, channel emulation, transceiver testing
Aerospace & defense (A/D): RADAR, electronic warfare (EW)
Hardware-in-the-loop (HIL), automated test equipment (ATE)
Scientific research
Quantum computing
03 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Programming technology and software tools
Software programming
–– Easy-to-use native programming libraries for most common languages: C, C++, Visual
Studio, LabVIEW, MATLAB, Python, and more
Hardware programming (optional)
–– Real-time sequencing (Hard Virtual Instrumentation or HVI technology)
–– Graphical flowchart-style M3601A design environment (-HV1 option required on HW)
–– Ultra-fast, fully-parallelized, hard real-time execution
–– Ultra-fast, time-deterministic decision-making
–– Off-the-shelf inter-module synchronization & data exchange
–– FPGA programming
–– Graphical M3602A FPGA design environment (-FP1 option required on HW)
–– No FPGA know-how required
–– Include high-level to low-level design elements: off-the-shelf DSP blocks, MATLAB/
Simulink designs, Xilinx CORE Generator IP cores, Xilinx VIVADO/ISE projects, VHDL
or Verilog code
–– Ultra-fast, one-click compiling and on-the-fly programming
No programming
–– Ready-to-use SD1 SPF (software front panels)
M31XX/M32XX/M33XX family product table
Outputs (AWGs)
Inputs (Digitizers)
Product
Type
Speed
(MSa/s)
Bits
Ch
BW
(MHz)
M3202A
AWG
1000
14
2/4
DC-400
M3201A
AWG
500
16
2/4
DC-200
M3102A
Speed
(MSa/s)
Bits
Ch
BW
(MHz)
Digitizer
500
14
2/4
DC-200
M3100A
Digitizer
100
14
4/8
DC-100
M3302A
Combo
500
16
2
DC-200
500
14
2
DC-200
M3300A
Combo
500
16
2/4
DC-200
100
14
4/8
DC-100
04 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Functional block diagram
Channel 1
Channel x
Function
generator
(FGx)
Channel 1
output
Frequency Phase
Amplitude Offset
Angle
modulator
FM
Dual
arbitrary
waveform
generator
(AWGx)
Amplitude
modulator
AM
DAC
LPF
Channel x
output
Quadrature
modulator
IQ
Channel n
Odd channels only
Even channels only
Channel n
output
Dual modulation option only
Figure 1. M3300A output functional block diagram, all channels have identical output structure
Channel 1
Channel 1
output
Channel x
Input settings
Channel x
output
Full scale, Z,
coupling (as
available)
Prescaler
÷
Data
acquisition
(DAQx)
Analog
trigger
Channel n
Channel n
output
Figure 2. M3300A input functional block diagram, all channels have identical input structure
05 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Ordering information
Product
Description
M3300A
PXI combo AWG + digitizer: 500/100 MSa/s, 16/14 bits
Options
Description
M3300A-C24 / -C48
√ Two channels AWG + four channels DIG / four channels AWG + eight channels DIG
M3300A-CLF
√ Fixed sampling clock, low jitter
M3300A-DM1
Dual modulation capability for the AWG (amplitude and angle simultaneously)
M3300A-M01 / -M12 / -M20
√ Memory 16 MB, 8 MSamples / 128 MB, 60 MSamples / 2 GB, 1 GSamples
HW programming options
Description
M3300A-HVI
Enabled HVI programming, requires an HVI design environment license (M3601A)
M3300A-FP1
Enabled FPGA programming, requires -K32 or -K41 option and an FPGA design environment license (M3602A)
M3300A-K32 / -K41
FPGA, Xilinx 7K325T / 7K410T, required for -FP1 option only (needs memory option -M20)
All options must be selected at time of purchase and are not upgradable
√ These options represent the standard configuration
Related software
Description
M3601A
HVI design environment
M3602A
FPGA design environment
06 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Output specifications (AWG)
Specifications summary
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
Inputs and outputs
Channels (single-ended mode)
2
4
Out
Channels (differential mode)
1
2
Out
clock 1
1
1
Out
Reference clock 2
1
1
In
Triggers/markers 1, 3
1
1
In/out
Reconfigurable
Triggers/markers 2, 3
8
8
In/out
Reconfigurable
500
500
MSa/s
Fixed sampling clock
Reference
Differential uses 2 channels
Output channels overview
Sampling rate
Voltage resolution
Output frequency
16
DC
Real-time BW
Output voltage
16
200
DC
200
–1.5
1.5
–1.5
Bits
200
MHz
200
MHz
1.5
Volts
Built-in functionalities
Function generators
2
4
1 per channel
Dual AWGs
2
4
1 per channel
IQ modulators
2
4
1 per channel
Frequency modulators
2
4
1 per channel
Phase modulators
2
4
1 per channel
Amplitude modulators
2
4
1 per channel
DC offset modulators
2
4
1 per channel
Onboard memory
RAM memory
16
1. At front panel
2. At backplane
3. Markers available from firmware version v3.0 or later
Table 1. General specifications
2048
16
2048
MBytes
07 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
I/O specifications
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
MSa/s
Fixed sampling clock
Output channels
Sampling rate
500
500
Output frequency
DC
200
DC
200
MHz
Limited by a reconstruction filter
Output voltage
–1.5
1.5
–1.5
1.5
Volts
On a 50 Ω load
Source impedance
50
50
Ω
10 or 100
10 or 100
MHz
Generated from the internal clock, user selectable
800
800
mVpp
On a 50 Ω load
Reference clock output
Frequency
Voltage
Power
2
2
dBm
On a 50 Ω load
Source impedance
50
50
Ω
AC coupled
External I/O trigger/marker
VIH
2
5
2
5
V
VIL
0
0.8
0
0.8
V
VOH
2.4
3.3
2.4
3.3
V
On a high Z load
VOL
0
0.5
0
0.5
V
On a high Z load
Input impedance
10
Source impedance
TTL
Speed
Table 2. Input/output specifications
10
KΩ
TTL
500
–
500
Mbps
08 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Function generators (FGs) specifications
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
General specifications
Function generators
2
4
–
1 per channel
Waveform types
4
4
–
Sinusoidal, triangular, square and DC
Frequency range
0
200
0
200
MHz
Frequency resolution
45
45
Bits
Frequency resolution
5.7
5.7
µHz
Phase range
0
360
0
360
Deg
Phase resolution
24
24
Bits
Phase resolution
21.5
21.5
µdeg
Speed performance
Frequency change rate
100
100
MChanges/s
With HVI technology
Frequency modulation rate
500
500
MSamples/s
With AWGs and angle modulators
Phase change rate
100
100
MChanges/s
With HVI technology
Phase modulation rate
500
500
MSamples/s
With AWGs and angle modulators
Table 3. Function generators (FGs) specifications
Amplitude and offset specifications
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
1.5
–1.5
Typ
Max
Units
Comments
1.5
Volts
Amplitude + offset values
General specifications
Amplitude/offset range
–1.5
Amplitude/offset resolution
16
16
Bits
Amplitude/offset resolution
45.8
45.8
µV
Speed performance
Amplitude/offset change rate
500
500
MChanges/s
With HVI technology
Amplitude/offset modulation rate
500
500
MSamples/s
With AWGs and amplitude modulators
Table 4. Amplitude and offset specifications
09 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Arbitrary waveform generators (AWGs) specifications
M3300A-C24
Parameter
Min
Typ
Max
M3300A-C48
Min
Typ
Max
Units
Comments
General specifications
Dual AWGs
2
Aggregated speed (16 bits)
2000
Aggregated speed (32 bits)
1000
Waveform multiple
5
16-bit waveform length
15
32-bit waveform length
10
Waveform length efficiency
Trigger
4
1 Dual AWG per output channel
4000
MSa/s
For all onboard waveforms combined
2000
MSa/s
For all onboard waveforms combined
Samples
Waveform length must be a multiple of this value
957M
Samples
Maximum depends on onboard RAM
478M
Samples
Maximum depends on onboard RAM
%
Effic. = waveform size/waveform size in RAM
5
957M
15
478M
10
93.5
93.5
Selec.
Selec.
External Trigger (input connector, backplane
triggers), software trigger
AWG specifications (16-bit single waveform)
Speed
500
Resolution
AWG destination
500
16
16
Selec.
Selec.
MSa/s
Per AWG
Bits
Amplitude, offset, frequency or phase
AWG specifications (16-bit dual waveform)
Speed (waveform A)
500
500
MSa/s
Per AWG
Speed (waveform B)
500
500
MSa/s
Per AWG
Resolution (waveform A)
16
Resolution (waveform B)
16
Bits
Bits
16
16
AWG destination (waveform A)
Selec.
Selec.
Amplitude, offset or I
AWG destination (waveform B)
Selec.
Selec.
Frequency, phase or Q
AWG specifications (32-bit single waveform)
Speed
100
Resolution
AWG destination
100
32
32
Selec.
Selec.
MSa/s
Per AWG, minimum prescaler: 1
Bits
Amplitude, offset, frequency or phase
AWG specifications (32-bit dual waveform)
Speed (waveform A)
100
Speed (waveform B)
100
100
MSa/s
Per AWG, minimum prescaler: 1
100
MSa/s
Per AWG, minimum prescaler: 1
Resolution (waveform A)
32
32
Bits
Resolution (waveform B)
32
32
Bits
AWG destination (waveform A)
Selec.
Selec.
Amplitude or offset
AWG destination (waveform B)
Selec.
Selec.
Frequency or phase
Table 5. Arbitrary waveform generators (AWGs) specifications
10 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Angle modulators specifications
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
General specifications
Frequency modulators
2
4
1 per output channel
Phase modulators
2
4
1 per output channel
Carrier signal source
Modulating signal source
FGs
FGs
Table 3 on page 8
AWGs
AWGs
Table 5 on page 9
Frequency modulators (16-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
–Dev. gain
16
Modulating signal BW
0
Deviation gain
0
Deviation gain resolution
+Dev. gain
16
250
0
200
0
16
MHz
Bits
AWG waveform
250
MHz
AWG Nyquist limit
200
MHz
16
Bits
Frequency modulators (32-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
–Dev. gain
32
+Dev. gain
32
MHz
Bits
AWG waveform
AWG Nyquist limit
Modulating signal BW
0
50
0
50
MHz
Deviation gain
0
200
0
200
MHz
Deviation gain resolution
16
16
Bits
Phase modulators (16-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
–Dev. gain
16
+Dev. gain
16
Deg
Bits
AWG waveform
AWG Nyquist limit
Modulating signal BW
0
250
0
250
MHz
Deviation gain
0
180
0
180
Deg
Deviation gain resolution
16
16
Bits
~ 5.5 mdeg
Phase modulators (32-bit modulating waveform)
Deviation
–Dev. gin
Modulating signal resolution
+Dev. gain
–Dev. gain
16
+Dev. gain
16
Deg
Bits
AWG waveform is truncated
AWG Nyquist limit
Modulating signal BW
0
50
0
50
MHz
Deviation gain
0
180
0
180
Deg
Deviation gain resolution
Table 6. Angle modulators specifications
16
16
Bits
~ 5.5 mdeg
11 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Amplitude modulators specifications
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
General specifications
Amplitude modulators
2
4
1 per output channel
Offset modulators
2
4
1 per output channel
Carrier signal source
Modulating signal source
FGs
FGs
Table 3 on page 8
AWGs
AWGs
Table 5 on page 9
Amplitude & offset modulators (16-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
–Dev. gain
16
Modulating signal BW
0
Deviation gain
0
Deviation gain resolution
+Dev. gain
16
250
0
1.5
0
16
Vp
Bits
AWG waveform
250
MHz
AWG Nyquist limit
1.5
Vp
16
Bits
Limited by the output DAC
Amplitude & offset modulators (32-bit modulating waveform)
Deviation
–Dev. gain
Modulating signal resolution
+Dev. gain
–Dev. gain
16
+Dev. gain
16
Vp
Bits
AWG waveform is truncated
AWG Nyquist limit
Modulating signal BW
0
50
0
50
MHz
Deviation gain
0
1.5
0
1.5
Vp
Deviation gain resolution
Table 7. Amplitude modulators specifications
16
16
Bits
Limited by the output DAC
12 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
IQ Modulators Specifications
M3300A
Parameter
Min
Typ
Max
Units
Comments
General specifications
IQ modulators
2
Carrier signal source
Modulating signal source
1 per output channel
FGs
Table 3 on page 8
AWGs
Table 5 on page 9
External I/O trigger/marker
Amplitude deviation
−1.5
Phase deviation
−180
I modulating signal resolution
1.5
Vp
180
Deg
16
I modulating signal BW
0
250
Q modulating signal resolution
16
Q modulating signal BW
0
250
Bits
AWG waveform
MHz
AWG Nyquist limit
Bits
AWG waveform
MHz
AWG Nyquist limit
Table 8. IQ modulators specifications
Clock system specifications
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
MHz
Fixed sampling clock
General specifications
Clock frequency
Table 9. Clock system specifications
500
500
13 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AC performance
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
General specifications
Analog output jitter
<2
<2
ps
RMS (cycle-to-cycle)
AWG trigger to output jitter
<2
<2
ps
RMS (cycle-to-cycle) for any trigger
referenced to the chassis clock;
independent of input trigger jitter if input
jitter < 4nS peak-to-peak
Trigger resolution
10
Channel-to-channel skew
10
ns
<20
<20
ps
Between ch 0 & ch 1, and ch 2 & ch 3
<50
<50
ps
Between any channel
150
150
ps
Between modules, chassis dependant 2
Clock output jitter
<2
<2
ps
RMS (cycle-to-cycle)
Clock accuracy and stability
25
25
ppm
PXIe, cPCIe versions; chassis dependent 1.
AC specifications
Spurious-free dynamic range (SFDR)
Pout = 4 dBm, measured from DC to max
frequency
fout = 10 MHz
63
63
dBc
fout = 40 MHz
63
63
dBc
fout = 80 MHz
64
64
dBc
fout = 120 MHz
69
69
dBc
fout = 160 MHz
67
67
dBc
fout = 200 MHz
63
63
dBc
fout = 10 MHz
<–105
<–105
dB
fout = 40 MHz
–85
–85
dB
Crosstalk (adjacent channels)
fout = 80 MHz
–75
–75
dB
fout = 120 MHz
–88
–88
dB
fout = 160 MHz
–73
–73
dB
fout = 200 MHz
–85
–85
dB
fout = 10 MHz
<–105
<–105
dB
fout = 40 MHz
–86
–86
dB
fout = 80 MHz
–78
–78
dB
fout = 120 MHz
<–105
<–105
dB
Crosstalk (non-adjacent channels)
fout = 160 MHz
–92
–92
dB
fout = 200 MHz
–100
–100
dB
Phase noise (SSB)
offset = 1 KHz
<–127
<–127
dBc/Hz
offset = 10 KHz
<–133
<–133
dBc/Hz
offset = 100 KHz
<–138
<–138
dBc/Hz
<–142
<–142
dBm/Hz
Average noise power density
1. This value corresponds to a M9505A chassis. This value can be improved with an external chassis clock or a system timing module.
2. This value corresponds to a M9005A PXIe chassis.
Table 10. AC performance
14 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AC performance graphs
Figure 3. Single-tone spectrum @ fout = 10 MHz
Figure 6. Single-tone spectrum @ fout = 40 MHz
Figure 4. Single-tone spectrum @ fout = 80 MHz
Figure 7. Single-tone spectrum @ fout = 120 MHz
Figure 5. Single-tone spectrum @ fout = 160 MHz
Figure 8. Single-tone spectrum @ fout = 200 MHz
15 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Input specifications (digitizer)
Specifications summary
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
Inputs and outputs
Channels
4
8
Out
Reference clock 1
1
1
Out
clock 2
Reference
1
1
In
Triggers/markers1, 3
1
1
In/out
Reconfigurable
Triggers/markers 2, 3
8
8
In/out
Reconfigurable
Sampling rate
100
100
MSa/s
Voltage resolution
14
14
Bits
Input channels overview
Input
frequency 4
DC
Real-time BW
100
DC
100
MHz
50
50
MHz
Input conditioning blocks
4
8
1 per channel
Analog trigger processors
4
8
1 per channel
Data acquisition blocks
4
8
1 per channel
Built-in functionalities
Onboard memory
RAM memory
1.
2.
3.
4.
16
2048
16
2048
MBytes
At front panel
At backplane
Markers available from firmware version v3.0 or later
100 MHz refer to the Front End bandwidth. This digitizer can operate in 1st and 2nd Nyquist zones (using undersampling technique), but its real-time BW is
limited by Nyquist to some 50 MHz. As an example for a band-limited signal of 70 MHz with a 10 MHz signal bandwidth the aliased component will appear
between 25 to 35 MHz (30 ± 5 MHz).
Table 11. General specifications
16 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
I/O specifications
Analog input characteristics
Number of channels
C24 or C48
Sampling rate
100 MSa/s option CLF
Configurable inputs: impedance
50Ω or 1 MΩ (HiZ)
Configurable inputs: Coupling
AC or DC
Input voltage range (50Ω)
400 mVpp to 6Vpp (continue: variable attenuator at input)
Input voltage range (HiZ)
200 mVpp to 20Vpp (continue: variable attenuator at input)
Bandwidth limit filters
100 MHz
Effective number of bits (ENOB)1
10.8 bits @30MHz (typical)
Noise floor
-142 dBm/Hz @30 MHz (typical)
SINAD
67 dB @30 MHz (typical)
Spurious free dynamic range (SFDR) + Total Harmonic Distorsion
79 dBc (typical)
Table 12. Input/output specifications
M3300A M3300A
Parameter
Min
Typ
Max
Units
Comments
10 or 100
MHz
Generated from the internal clock. User selectable
Voltage
800
mVpp
On a 50 Ω load
Power
2
dBm
On a 50 Ω load
Source impedance
50
Ω
AC coupled
Reference clock output
Frequency
External I/O trigger/marker
VIH
2
5
V
VIL
0
0.8
V
VOH
2.4
3.3
V
On a high Z load
VOL
0
0.5
V
On a high Z load
Input impedance
10
Source impedance
TTL
Speed
Table 12b.
KΩ
500
Mbps
17 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Data acquisition blocks (DAQs) specifications
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
General specifications
DAQs
4
8
Aggregated speed
1 per channel
400
Acquisition burst multiple
800
5
Acquisition RAM capacity
5
15
957M
Acquisition RAM capacity effic.
Trigger
15
957M
93.5
93.5
Selec.
Selec.
MSa/s
For all onboard DAQs combined
Samples
Burst length must be a multiple of this value
Samples
Maximum depends on onboard RAM
%
Effic. = waveform size/waveform size in RAM
Hardware trigger (analog channels, input
trigger, backplane triggers), Software trigger
DAQ specifications
Speed
100
Resolution
100
14
14
MSa/s
Per DAQ
Bits
Table 13. Data acquisition blocks (DAQs) specifications
Clock system specifications
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
General specifications
Clock frequency
100
100
MHz
Table 14. Clock system specifications
System specifications
Environmental specifications (PXI Express)
M3300A-C24
Parameter
Min
Typ
M3300A-C48
Max
Min
Typ
Max
Units
Comments
Slots
PXI Express (CompactPCI Express compatible)
–
Automatic gen negotiation, chassis dependent
Lanes
Automatic lane negotiation, chassis dependent
System bus
Slots
2
2
PCI Express type
Gen 1
Gen 2
Gen 1
Gen 2
PCI Express link
1
4
1
4
PCI Express speed
400
1600
400
1600
MBytes/s
Depends on # of lanes, chassis, congestion, and more
Sustainable throughput
200
800
200
800
MPoints/s
Depends on # of lanes, chassis, congestion, and more
Power dissipation
3.3 V PXIe power supply
3
3
A
~ 10 W
12 V PXIe power supply
3.5
3.5
A
~ 40 W
Table 15. Environmental specifications (PXI Express)
18 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Environmental
Temperature range
Operating
Non-operating
0 to +55°C (10,000 feet)
-40 to +70 °C (up to 15,000 feet)
Max operative altitude
2000 m (10,000 feet)
Operating Humidity range (%RH)
10 to 95% at 40 °C
Non-operating Humidity range (%RH): 5 to 95
5 to 95%
Calibration interval
1 year
EMC
Complies with European EMC Directive
– IEC/EN 61326-1
– CISPR Pub 11 Group 1, class A
This ISM device Compliace with Canadian ICES-001
Cet appareil ISM est conforme à la norme NMB-001 du Canada.
This ISM device Compliace with Australian and New Zealand RCM
This ISM device Compliace with South Korea EMC KCC
Table 16. Environmental
Samples of this product have been type tested in accordance with the Keysight Environmental Test Manual and verified to be robust
against the environmental stresses of Storage, Transportation and End-use; those stresses include but are not limited to temperature,
humidity, shock, vibration, altitude and power line conditions. Test Methods are aligned with IEC 60068-2 and levels are similar to
MIL-PRF-28800F Class 3.
19 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
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This information is subject to change without notice.
© Keysight Technologies, 2017
Published in USA, February 16, 2017
5992-1809EN
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