14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B, Dual Analog-to-Digital Converter AD9689 Data Sheet FEATURES 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation Programmable FIR filters for analog channel loss equalization 2 integrated, wideband digital processors per channel 48-bit NCO Programmable decimation rates Phase coherent NCO switching Up to 4 channels available Serial port control Supports 100 MHz SPI writes and 50 MHz SPI reads Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane Noise density −152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p −154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p −154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p −155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p 1.55 W total power per channel at 2.56 GSPS (default settings) SFDR at 2.56 GSPS encode 73 dBFS at 1.8 GHz AIN at −2.0 dBFS 59 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SNR at 2.56 GSPS encode 59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS 53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SFDR at 2.0 GSPS encode 78 dBFS at 900 MHz AIN at −2.0 dBFS 62 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SNR at 2.0 GSPS encode 62.7 dBFS at 900 MHz AIN at −2.0 dBFS 53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p APPLICATIONS Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers FUNCTIONAL BLOCK DIAGRAM ADC CORE FAST DETECT VIN+B VIN–B ADC CORE DRVDD2 (1.9V) SPIVDD (1.9V) 14 SIGNAL MONITOR BUFFER DRVDD1 (0.975V) 14 DIGITAL DOWNCONVERTER DIGITAL DOWNCONVERTER CROSSBAR MUX BUFFER DVDD (0.975V) CROSSBAR MUX VIN+A VIN–A AVDD3 AVDD1_SR (0.975V) (2.5V) AVDD2 (1.9V) PROGRAMMABLE FIR FILTER AVDD1 (0.975V) JESD204B LINK AND Tx OUTPUTS VREF 8 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SERDOUT4± SERDOUT5± SERDOUT6± SERDOUT7± SYNCINB± PDWN/STBY JESD204B SUBCLASS 1 CONTROL CLOCK DISTRIBUTION FD_A/GPIO_A0 GPIO MUX CLK+ CLK– SPI AND CONTROL REGISTERS ÷2 AD9689 ÷4 AGND GPIO_A1 FD_B/GPIO_B0 GPIO_B1 SDIO SCLK CSB DRGND DGND 15550-001 SYSREF± Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9689 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Frequency Translation ..................................................... 47 Applications ....................................................................................... 1 DDC Decimation Filters ........................................................... 55 Functional Block Diagram .............................................................. 1 DDC Gain Stage ......................................................................... 61 Revision History ............................................................................... 3 DDC Complex to Real Conversion ......................................... 61 General Description ......................................................................... 4 DDC Mixed Decimation Settings ............................................ 62 Product Highlights ........................................................................... 4 DDC Example Configurations ................................................. 64 Specifications..................................................................................... 5 DDC Power Consumption ........................................................ 67 DC Specifications ......................................................................... 5 Signal Monitor ................................................................................ 68 AC Specifications.......................................................................... 6 SPORT over JESD204B .............................................................. 69 Digital Specifications ................................................................... 8 Digital Outputs ............................................................................... 71 Switching Specifications .............................................................. 9 Introduction to the JESD204B Interface ................................. 71 Timing Specifications ................................................................ 10 JESD204B Overview .................................................................. 71 Absolute Maximum Ratings.......................................................... 12 Functional Overview ................................................................. 72 Thermal Resistance .................................................................... 12 JESD204B Link Establishment ................................................. 72 ESD Caution ................................................................................ 12 Physical Layer (Driver) Outputs .............................................. 74 Pin Configuration and Function Descriptions ........................... 13 fS × 4 Mode .................................................................................. 75 Typical Performance Characteristics ........................................... 16 Setting Up the AD9689 Digital Interface................................. 76 2.0 GSPS ....................................................................................... 16 Deterministic Latency.................................................................... 83 2.6 GSPS ....................................................................................... 21 Subclass 0 Operation.................................................................. 83 Equivalent Circuits ......................................................................... 26 Subclass 1 Operation.................................................................. 83 Theory of Operation ...................................................................... 28 Multichip Synchronization............................................................ 85 ADC Architecture ...................................................................... 28 Normal Mode.............................................................................. 85 Analog Input Considerations.................................................... 28 Timestamp Mode ....................................................................... 85 Voltage Reference ....................................................................... 31 SYSREF Input .............................................................................. 87 DC Offset Calibration ................................................................ 32 SYSREF± Setup/Hold Window Monitor ................................. 89 Clock Input Considerations ...................................................... 32 Latency ............................................................................................. 91 Power-Down and Standby Mode ............................................. 35 End to End Total Latency .......................................................... 91 Temperature Diode .................................................................... 35 Example Latency Calculations.................................................. 91 ADC Overrange and Fast Detect .................................................. 37 LMFC Referenced Latency........................................................ 91 ADC Overrange .......................................................................... 37 Test Modes ....................................................................................... 93 Fast Threshold Detection (FD_A and FD_B) ........................ 37 ADC Test Modes ........................................................................ 93 ADC Application Modes and JESD204B Tx Converter Mapping ........................................................................................................... 38 JESD204B Block Test Modes .................................................... 94 Serial Port Interface ........................................................................ 96 Programmable FIR Filters ............................................................. 40 Configuration Using the SPI ..................................................... 96 Supported Modes........................................................................ 40 Hardware Interface..................................................................... 96 Programming Instructions ........................................................ 42 SPI Accessible Features .............................................................. 96 Digital Downconverter (DDC) ..................................................... 44 Memory Map .................................................................................. 97 DDC I/Q Input Selection .......................................................... 44 Reading the Memory Map Register Table............................... 97 DDC I/Q Output Selection ....................................................... 44 Memory Map Register Details .................................................. 98 DDC General Description ........................................................ 44 Applications Information ............................................................ 132 Rev. A | Page 2 of 134 Data Sheet AD9689 Power Supply Recommendations .......................................... 132 Outline Dimensions ......................................................................134 Layout Guidelines .................................................................... 133 Ordering Guide .........................................................................134 AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8)........... 133 REVISION HISTORY 10/2017—Rev. 0 to Rev. A Added 2.0 GSPS ............................................................. Throughout Changes to Features Section ............................................................ 1 Changes to Product Highlights Section ......................................... 4 Changes to Table 1 ............................................................................ 5 Changes to Table 2 ............................................................................ 6 Changes to Table 4 ............................................................................ 9 Added 2.0 GSPS Section and Figure 6 to Figure 11; Renumbered Sequentially ......................................................................................16 Added Figure 12 to Figure 17 ........................................................17 Added Figure 18 to Figure 23 ........................................................18 Added Figure 24 through Figure 29..............................................19 Added Figure 30 through Figure 35..............................................20 Added 2.6 GSPS Section .................................................................21 Change to Figure 41 ........................................................................21 Change to Figure 45 ........................................................................22 Changes to Figure 52 and Figure 53 .............................................23 Changes to Figure 54, Figure 55, Figure 56, Figure 58, and Figure 59 ...........................................................................................24 Changes to Figure 60 and Figure 61 .............................................25 Changes to Figure 67 Caption ....................................................... 26 Changes to Table 10 ........................................................................ 30 Changes to Figure 87 ...................................................................... 32 Changes to Figure 96 Caption ....................................................... 35 Changes to Programming Instructions Section .......................... 42 Added Table 28; Renumbered Sequentially ................................. 67 Changes to Table 29 Title ............................................................... 67 Changes to De-Emphasis Section ................................................. 74 Changes to Figure 142 .................................................................... 82 Changes to Reading the Memory Map Register Table Section....... 97 Changes to Address 0x0006, Table 46 .......................................... 98 Changes to Address 0x010A, Table 47 ......................................... 99 Changes to Table 50 ...................................................................... 105 Changes to Table 51 ...................................................................... 117 Changes to Power Supply Recommendations Section, Figure 157, and Figure 158 ............................................................................... 132 Changes to Ordering Guide ......................................................... 134 9/2017—Revision 0: Initial Version Rev. A | Page 3 of 134 AD9689 Data Sheet GENERAL DESCRIPTION The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles. In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9689 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC. The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, fourlane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins. The AD9689 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI). The AD9689 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. This product is protected by a U.S. patent. Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. 8. Rev. A | Page 4 of 134 Wide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filters and NCO blocks supporting multiband receivers. Fast NCO switching enabled through the GPIO pins. SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature diode for system thermal management. 12 mm × 12 mm, 196-ball BGA. Pin, package, feature, and memory map compatible with the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC. Data Sheet AD9689 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, sampling rate = 2.0 GHz/2.56 GHz, clock divider = 2, 1.7 V p-p full-scale differential input, input amplitude (AIN) = −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ TJ ≤ +120°C, 1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE INPUT REFERRED NOISE ANALOG INPUTS Differential Input Voltage Range Common-Mode Voltage (VCM) Differential Input Capacitance −3 dB Bandwidth POWER SUPPLY AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD1 DRVDD2 SPIVDD IAVDD1 IAVDD2 IAVDD3 IAVDD1_SR IDVDD IDRVDD1 2 IDRVDD2 ISPIVDD Min 14 2.0 GSPS Typ Max Min 14 Guaranteed −2.9 −0.62 −9.9 0 ±1 ±0.2 ±0.4 ±2 +1.8 −4.9 +0.79 +8.1 −0.65 −16 2.6 GSPS Typ Max Guaranteed 0 0 ±1 +5.6 ±0.2 ±0.4 +0.75 ±6 +13 ±7.7 15 ±3.7 58 0.5 3.8 0.5 4.6 Unit Bits %FSR %FSR %FSR %FSR LSB LSB ppm/°C ppm/°C V LSB rms 1.1 1.7 1.4 0.35 9 2.0 1.1 1.7 1.4 0.35 9 2.0 V p-p V pF GHz 0.95 1.85 2.44 0.95 0.95 0.95 1.85 1.85 0.975 1.9 2.5 0.975 0.975 0.975 1.9 1.9 455 585 65 25 340 320 25 1 1.0 1.95 2.56 1.0 1.0 1.0 1.95 1.95 605 670 72 41 800 432 30 5 0.95 1.85 2.44 0.95 0.95 0.95 1.85 1.85 0.975 1.9 2.5 0.975 0.975 0.975 1.9 1.9 590 810 65 25 405 390 25 1 1.0 1.95 2.56 1.0 1.0 1.0 1.95 1.95 693 882 73 43 833 500 30 5 V V V V V V V V mA mA mA mA mA mA mA mA Rev. A | Page 5 of 134 AD9689 POWER CONSUMPTION Total Power Dissipation (Including Output Drivers) 3 Power-Down Dissipation Standby 4 Data Sheet 2.45 3.1 W 265 1.3 300 1.5 mW W The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C. All lanes running. Power dissipation on DRVDDx changes with lane rate and number of lanes used. 3 Default mode. No DDCs used. 4 Can be controlled by the SPI. 1 2 AC SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, sampling rate = 2.0 GHz/2.56 GHz, clock divider = 2, 1.7 V p-p full-scale differential input, input amplitude (AIN) = −2.0 dBFS, default SPI settings, −10°C ≤ TJ ≤ +120°C, 1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 2. Parameter 2 NOISE DENSITY 3 Full Scale = 1.7 V p-p Full Scale = 2.0 V p-p CODE ERROR RATE (CER) AVDD1 = 0.975 V AVDD1 = 1.0 V SIGNAL-TO-NOISE RATIO (SNR) fIN = 155 MHz fIN = 155 MHz (Full Scale = 2.0 V p-p) fIN = 750 MHz fIN = 900 MHz fIN = 1800 MHz fIN = 2100 MHz fIN = 3300 MHz fIN = 4350 MHz (Full Scale = 1.1 V p-p) fIN = 5530 MHz (Full Scale = 1.1 V p-p) SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 155 MHz fIN = 155 MHz (Full Scale = 2.0 V p-p) fIN = 750 MHz fIN = 900 MHz fIN = 1800 MHz fIN = 2100 MHz fIN = 3300 MHz fIN = 4350 MHz (Full Scale = 1.1 V p-p) fIN = 5530 MHz (Full Scale = 1.1 V p-p) EFFECTIVE NUMBER OF BITS (ENOB) fIN = 155 MHz fIN = 155 MHz (Full Scale = 2.0 V p-p) fIN = 750 MHz fIN = 900 MHz fIN = 1800 MHz fIN = 2100 MHz fIN = 3300 MHz fIN = 4350 MHz (Full Scale = 1.1 V p-p) fIN = 5530 MHz (Full Scale = 1.1 V p-p) Min 60.2 59.6 9.6 Rev. A | Page 6 of 134 2.0 GSPS Typ Max Min 2.6 GSPS Typ Max Unit −154.2 −155.3 −152 −154 dBFS/Hz dBFS/Hz 7 × 10−15 3 × 10−15 9 × 10−9 4.5 × 10−10 Errors Errors 63.7 65.0 63.1 62.7 60.9 59.9 58.3 54.4 53.1 56.0 61.3 62.5 61.0 60.9 59.7 59.3 58.0 54.0 53.0 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 52.4 61.2 62.4 60.7 60.5 59.4 59.1 56.6 51.0 49.5 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 8.4 9.9 10.1 9.8 9.8 9.6 9.5 9.1 8.2 7.9 Bits Bits Bits Bits Bits Bits Bits Bits Bits 63.5 64.7 62.8 62.5 60.8 59.7 55.3 53.2 52.3 10.3 10.5 10.1 10.1 9.8 9.6 8.9 8.6 8.4 Data Sheet Parameter 2 SPURIOUS FREE DYNAMIC RANGE (SFDR), SECOND OR THIRD HARMONIC 4, 5 fIN = 155 MHz fIN = 155 MHz (Full Scale = 2.0 V p-p) fIN = 750 MHz fIN = 900 MHz fIN = 1800 MHz fIN = 2100 MHz fIN = 3300 MHz fIN = 4350 MHz (Full Scale = 1.1 V p-p) fIN = 5530 MHz (Full Scale = 1.1 V p-p) WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC fIN = 155 MHz fIN = 155 MHz (Full Scale = 2.0 V p-p) fIN = 750 MHz fIN = 900 MHz fIN = 1800 MHz fIN = 2100 MHz fIN = 3300 MHz fIN = 4350 MHz (Full Scale = 1.1 V p-p) fIN = 5530 MHz (Full Scale = 1.1 V p-p) TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −8.0 dBFS fIN1 = 1841 MHz, fIN2 = 1846 MHz fIN1 = 2137 MHz, fIN2 = 2142 MHz CROSSTALK 6 ANALOG INPUT BANDWIDTH, FULL POWER 7 AD9689 Min 66 2.0 GSPS Typ Max 77 77 77 78 76 76 60 61 62 −99 −95 −100 −94 −91 −86 −85 −83 −82 −72 −74 >90 5 Min 58 −80 2.6 GSPS Typ 2 Rev. A | Page 7 of 134 Unit 78 78 73 74 73 73 64 60 59 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS −96 −98 −97 −96 −88 −94 −85 −84 −82 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS −72 −76 >90 5 The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C. See AN-835 for definitions and for details on how these tests were completed. 3 Noise density is measured at a low analog input frequency (30 MHz). 4 The input configuration component values are found in Table 9. Refer to Table 10 for the recommended buffer settings. 5 Figure 79 shows the differential transformer coupled configuration. Figure 80 is the input network configuration for frequencies > 5 GHz. 6 Crosstalk is measured at 950 MHz with a −2.0 dBFS analog input on one channel, and no input on the adjacent channel. 7 Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved. 1 Max −74 dBFS dBFS dB GHz AD9689 Data Sheet DIGITAL SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, −10°C ≤ TJ ≤ +120°C, 1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 3. Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance Differential Input Return Loss at 2.6 GHz 2 SYSTEM REFERENCE (SYSREF) INPUTS (SYSREF+, SYSREF−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0, FD_B/GPIO_B0, GPIO_A1, GPIO_B1) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUTS (SDIO, FD_A, FD_B) Logic Compliance Logic 1 Voltage (IOH = 4 mA) Logic 0 Voltage (IOL = 4 mA) SYNCHRONIZATION INPUT (SYNCINB+/SYNCINB−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance SYNCINB+ INPUT Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7) Logic Compliance Differential Output Voltage Differential Termination Impedance 1 2 Min 300 400 Typ LVDS/LVPECL 800 0.675 106 0.9 9.4 LVDS/LVPECL 800 0.675 18 1 Max Unit 1800 mV p-p V Ω pF dB 1800 2.0 mV p-p V kΩ pF CMOS 0.65 × SPIVDD 0 0.35 × SPIVDD 30 V V kΩ CMOS SPIVDD − 0.45V 0 400 0.45 LVDS/LVPECL 800 0.675 18 1 1800 2.0 V V mV p-p V kΩ pF CMOS 0.9 × DRVDD1 2 × DRVDD1 0.1 × DRVDD1 2.6 V V kΩ SST 360 80 560 100 The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C. Reference impedance = 100 Ω. Rev. A | Page 8 of 134 770 120 mV p-p Ω Data Sheet AD9689 SWITCHING SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, default SPI settings, −10°C ≤ TJ ≤ +120°C, 1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 4. Parameter CLOCK Clock Rate at CLK+/CLK− Pins Sample Rate 2 Clock Pulse Width High Clock Pulse Width Low OUTPUT PARAMETERS Unit Interval (UI) 3 Rise Time (tR) (20% to 80% into 100 Ω Load) Fall Time (tF) (20% to 80% into 100 Ω Load) Phase-Locked Loop (PLL) Lock Time Data Rate per Channel (Nonreturn to Zero) 4 LATENCY 5 Pipeline Latency 6 Fast Detect Latency NCO Channel Selection to Output WAKE-UP TIME Standby Power-Down APERTURE Delay (tA) Uncertainty (Jitter, tJ) Out of Range Recovery Time Min 2.0 GSPS Typ Max 1200 238.096 238.096 2000 62.5 66.67 26 26 5 13 1.6875 6 2100 Min 2.6 GSPS Typ Max 1900 185.185 185.185 2600 592.6 62.5 16 1.6875 66.67 26 26 5 13 75 26 6 2700 GHz MSPS ps ps 592.6 16 ps ps ps ms Gbps 8 Clock cycles Clock cycles Clock cycles 75 26 8 Unit 400 15 400 15 µs ms 250 55 1 250 55 1 ps fs rms Clock cycles The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C. The maximum sample rate is the clock rate after the divider. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 Default L = 8. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 8, M = 2, and F = 1. 6 Refer to the Latency section for more details. 1 2 Rev. A | Page 9 of 134 AD9689 Data Sheet TIMING SPECIFICATIONS Table 5. Parameter CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK for SPI Reads tCLK for SPI Writes tS tH tHIGH for SPI Reads tHIGH for SPI Writes tLOW for SPI Reads tLOW for SPI Writes tACCESS Description Min Device clock to SYSREF+ setup time Device clock to SYSREF+ hold time Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Minimum period that SCLK must be in a logic low state Maximum time delay between the falling edge of SCLK and output data valid for a read operation Time required for the SDIO pin to switch from an output to an input, relative to the SCLK rising edge (not shown in Figure 4) tDIS_SDIO 2 N – 75 N+1 N – 73 SAMPLE N N – 72 N–1 CLK– CLK+ CLK– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ SERDOUT4– SERDOUT4+ SERDOUT5– SERDOUT5+ SERDOUT6– SERDOUT6+ SERDOUT7– SERDOUT7+ A B C D E F G H I J CONVERTER0 SAMPLE N – 75 MSB A B C D E F G H I J CONVERTER0 SAMPLE N – 75 LSB A B C D E F G H I J CONVERTER0 SAMPLE N – 74 MSB A B C D E F G H I J CONVERTER0 SAMPLE N – 74 LSB A B C D E F G H I J CONVERTER1 SAMPLE N – 75 MSB A B C D E F G H I J CONVERTER1 SAMPLE N – 75 LSB A B C D E F G H I J CONVERTER1 SAMPLE N – 74 MSB A B C D E F G H I J CONVERTER1 SAMPLE N – 74 LSB SAMPLE N – 75 AND N – 74 ENCODED INTO ONE 8-BIT/10-BIT SYMBOL Figure 2. Data Output Timing Diagram Rev. A | Page 10 of 134 15550-002 CLK+ SERDOUT0– Unit −65 95 ps ps 5 ns ns ns ns ns ns ns ns ns ns ns 8 ns APERTURE DELAY N – 74 Max 2 2 20 10 2 2 8 4 8 4 Timing Diagrams ANALOG INPUT SIGNAL Typ Data Sheet AD9689 CLK– CLK+ tSU_SR tH_SR 15550-003 SYSREF– SYSREF+ Figure 3. CLK+ to SYSREF+ Setup and Hold Timing Diagram tDS tS tDH tACCESS tCLK tHIGH tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 Figure 4. SPI Interface Timing Diagram Rev. A | Page 11 of 134 D4 D3 D2 D1 D0 DON’T CARE 15550-004 SCLK DON’T CARE AD9689 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Electrical AVDD1 to AGND AVDD1_SR to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD1 to DRGND DRVDD2 to DRGND SPIVDD to DGND AGND to DRGND AGND to DGND DGND to DRGND VIN±x to AGND CLK± to AGND SCLK, SDIO, CSB to DGND PDWN/STBY to DGND SYSREF± to AGND SYNCINB± to DRGND Junction Temperature Range (TJ) Storage Temperature Range, Ambient (TA) Rating 1.05 V 1.05 V 2.0 V 2.70 V 1.05 V 1.05 V 2.0 V 2.0 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V AGND − 0.3 V to AVDD3 + 0.3 V AGND − 0.3 V to AVDD1 + 0.3 V DGND − 0.3 V to SPIVDD + 0.3 V DGND − 0.3 V to SPIVDD + 0.3 V 2.5 V 2.5 V −40°C to +125°C −65°C to +150°C Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. θJA is the natural convection junction-to-ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 7. Thermal Resistance Package Type BP-196-41 1 θJA 16.26 θJC_TOP 1.4 ΨJB 5.44 Unit °C/W Test Condition 1: Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with 190 thermal vias. See JEDEC JESD51. ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 12 of 134 Data Sheet AD9689 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A AVDD2 AVDD2 AVDD1 AVDD1 1 AVDD11 AGND1 CLK+ CLK– AGND1 AVDD1 1 AVDD1 1 AVDD1 AVDD2 AVDD2 B AVDD2 AVDD2 AVDD1 AVDD1 1 AGND AGND1 AGND1 AGND1 AGND1 AGND AVDD1 1 AVDD1 AVDD2 AVDD2 C AVDD2 AVDD2 AVDD1 AGND AGND AGND1 AGND1 AGND1 AGND1 AGND AGND AVDD1 AVDD2 AVDD2 D AVDD3 AGND AGND AGND AGND AGND AGND1 AGND1 AGND AGND AGND AGND AGND AVDD3 E VIN–B AGND AGND AGND AGND AGND2 AVDD1_SR AGND2 AGND AGND AGND AGND AGND VIN–A F VIN+B AGND AGND AGND AGND AGND SYSREF+ SYSREF– AGND AGND AGND AGND AGND VIN+A G AVDD3 AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AVDD3 H AGND AGND AGND AGND AGND AGND AGND AGND AGND VREF AGND AGND AGND AGND J AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND K AGND 3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 L DGND GPIO_B1 SPIVDD FD_B/ GPIO_B0 CSB SCLK SDIO PDWN/ STBY FD_A/ GPIO_A0 SPIVDD GPIO_A1 DGND DGND DGND M DGND DGND DRGND DRGND DRVDD1 DRVDD1 DRVDD1 DRVDD1 DRGND DRGND DRVDD1 DRGND DRVDD2 DVDD N DVDD DVDD DRGND SERDOUT7+ SERDOUT6+ SERDOUT5+ SERDOUT4+ SERDOUT3+ SERDOUT2+ SERDOUT1+ SERDOUT0+ DRGND SYNCINB+ DVDD P DVDD DVDD DRGND SERDOUT7– SERDOUT6– SERDOUT5– SERDOUT4– SERDOUT3– SERDOUT2– SERDOUT1– SERDOUT0– DRGND SYNCINB– DVDD 15550-005 1 DENOTES CLOCK DOMAIN. 2 DENOTES SYSREF± DOMAIN. 3 DENOTES ISOLATION DOMAIN. Figure 5. Pin Configuration (Top View) Rev. A | Page 13 of 134 AD9689 Data Sheet Table 8. Pin Function Descriptions 1 19F Pin No. Power Supplies A3, A12, B3, B12, C3, C12 A4, A5, A10, A11, B4, B11 A1, A2, A13, A14, B1, B2, B13, B14, C1, C2, C13, C14 D1, D14, G1, G14 E7 L3, L10 M14, N1, N2, N14, P1, P2, P14 M5 to M8, M11 M13 B5, B10, C4, C5, C10, C11, D2 to D6, D9 to D13, E2 to E5, E9 to E13, F2 to F6, F9 to F13, G2 to G13, H1 to H9, H11 to H14, J1 to J14 A6, A9, B6 to B9, C6 to C9, D7, D8 E6, E8 K1 to K14 L1, L12 to L14, M1, M2 M3, M4, M9, M10, M12, N3, N12, P3, P12 Analog E1, F1 E14, F14 A7, A8 H10 CMOS Inputs/Outputs L2 L4 L9 L11 Digital Inputs F7, F8 N13 P13 Data Outputs N4, P4 N5, P5 N6, P6 N7, P7 N8, P8 N9, P9 N10, P10 N11, P11 Mnemonic Type Description AVDD1 AVDD1 2 Power Power AVDD2 Power Analog Power Supply (0.975 V Nominal). Analog Power Supply for the Clock Domain (0.975 V Nominal). Analog Power Supply (1.9 V Nominal). AVDD3 AVDD1_SR SPIVDD DVDD DRVDD1 DRVDD2 AGND Power Power Power Power Power Power Ground Analog Power Supply (2.5 V Nominal). Analog Power Supply for SYSREF± (0.975 V Nominal). Digital Power Supply for SPI (1.9 V Nominal). Digital Power Supply (0.975 V Nominal). Digital Driver Power Supply (0.975 V Nominal). Digital Driver Power Supply (1.9 V Nominal). Analog Ground. These pins connect to the analog ground plane. AGND2 Ground Ground Reference for the Clock Domain. AGND 3 AGND 4 DGND Ground Ground Ground DRGND Ground Ground Reference for SYSREF±. Isolation Ground. Digital Control Ground Supply. These pins connect to the digital ground plane. Digital Driver Ground Supply. These pins connect to the digital driver ground plane. VIN−B, VIN+B VIN−A, VIN+A CLK+, CLK− VREF Input Input Input Input/output/ do not connect (DNC) ADC B Analog Input Complement/True. ADC A Analog Input Complement/True. Clock Input True/Complement. 0.50 V Reference Voltage Input/Do Not Connect. This pin is configurable through the SPI as a no connect or an input. Do not connect this pin if using the internal reference. This pin requires a 0.50 V reference voltage input if using an external voltage reference source. GPIO_B1 FD_B/GPIO_B0 FD_A/GPIO_A0 GPIO_A1 Input/output Input/output Input/output Input/output GPIO B1. Fast Detect Outputs for Channel B/GPIO B0. Fast Detect Outputs for Channel A/GPIO A0. GPIO A1. SYSREF+, SYSREF− Input SYNCINB+ SYNCINB− Input Input Active High JESD204B LVDS System Reference Input True/Complement. Active Low JESD204B LVDS/CMOS Sync Input True. Active Low JESD204B LVDS Sync Input Complement. SERDOUT7+, SERDOUT7− SERDOUT6+, SERDOUT6− SERDOUT5+, SERDOUT5− SERDOUT4+, SERDOUT4− SERDOUT3+, SERDOUT3− SERDOUT2+, SERDOUT2− SERDOUT1+, SERDOUT1− SERDOUT0+, SERDOUT0− Output Output Output Output Output Output Output Output Lane 7 Output Data True/Complement. Lane 6 Output Data True/Complement. Lane 5 Output Data True/Complement. Lane 4 Output Data True/Complement. Lane 3 Output Data True/Complement. Lane 2 Output Data True/Complement. Lane 1 Output Data True/Complement. Lane 0 Output Data True/Complement. 20F 21F 2F Rev. A | Page 14 of 134 Data Sheet Pin No. Digital Controls L5 L6 L7 L8 AD9689 Mnemonic Type Description CSB SCLK SDIO PDWN/STBY Input Input Input/output Input SPI Chip Select (Active Low). SPI Serial Clock. SPI Serial Data Input/Output. Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby. 1 See the Theory of Operation section and the Applications Information section for more information on isolating the planes for optimal performance. Denotes clock domain. Denotes SYSREF± domain. 4 Denotes isolation domain. 2 3 Rev. A | Page 15 of 134 AD9689 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 GSPS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, sampling rate = 2.0 GHz, clock divider = 2, 1.7 V p-p full-scale differential input, input amplitude (AIN) = −2.0 dBFS, TJ = 70°C (TA = 25°C), 128k fast Fourier transform (FFT) sample, unless otherwise noted. See Table 10 for the recommended settings. –15 –30 –30 AMPLITUDE (dB) –45 –60 –75 –90 –45 –60 –75 –90 –105 –105 –120 –120 –135 0 95 190 285 380 475 570 665 AIN = –2dBFS SNRFS = 62.7dB SFDR = 78dBFS ENOB = 10.1 BITS NSD = –152.7dBFS/Hz BUFFER CURRENT = 300µA –15 15550-406 AMPLITUDE (dB) 0 AIN = –2dBFS SNRFS = 63.7dB SFDR = 77dBFS ENOB = 10.3 BITS NSD = –153.7dBFS/Hz BUFFER CURRENT = 300µA 760 855 –135 950 15550-409 0 0 95 190 285 380 fIN (MHz) Figure 6. Single-Tone FFT at fIN = 155 MHz 0 –30 AMPLITUDE (dB) –45 –60 –75 –90 –45 –90 –120 –120 95 190 285 380 475 570 665 760 855 –135 950 0 95 190 285 380 fIN (MHz) 0 –30 –60 –75 –90 –45 –90 –120 –120 95 190 285 380 475 570 950 –75 –105 0 855 –60 –105 –135 760 665 760 855 950 fIN (MHz) –135 15550-411 AMPLITUDE (dB) –45 665 AIN = –2dBFS SNRFS = 59.9dB SFDR = 76dBFS ENOB = 9.6 BITS NSD = –149.9dBFS/Hz BUFFER CURRENT = 700µA –15 15550-408 AMPLITUDE (dB) –30 570 Figure 10. Single-Tone FFT at fIN = 1807 MHz AIN = –2dBFS SNRFS = 63.1dB SFDR = 77dBFS ENOB = 10.1 BITS NSD = –153.1dBFS/Hz BUFFER CURRENT = 300µA –15 475 fIN (MHz) Figure 7. Single-Tone FFT at fIN = 155 MHz, Full-Scale Voltage = 2.04 V p-p 0 950 –75 –105 0 855 –60 –105 –135 760 AIN = –2dBFS SNRFS = 60.9dB SFDR = 76dBFS ENOB = 9.8 BITS NSD = –150.9dBFS/Hz BUFFER CURRENT = 500µA –15 15550-407 AMPLITUDE (dB) –30 665 Figure 9. Single-Tone FFT at fIN = 905 MHz AIN = –2dBFS SNRFS = 65.0dB SFDR = 77dBFS ENOB = 10.5 BITS NSD = –155.0dBFS/Hz BUFFER CURRENT = 300µA –15 570 15550-410 0 475 fIN (MHz) 0 95 190 285 380 475 570 665 760 855 fIN (MHz) Figure 8. Single-Tone FFT at fIN = 750 MHz Figure 11. Single-Tone FFT at fIN = 2100 MHz Rev. A | Page 16 of 134 950 Data Sheet 300µA, 300µA, 500µA, 500µA, 700µA, 700µA, 40 –105 15550-415 3755 fIN (MHz) 3955 20 950 3555 855 3355 760 2955 665 3155 570 2555 475 2755 380 955 285 755 190 355 95 555 0 155 –135 30 15550-412 –120 SFDR SNR SFDR SNR SFDR SNR 2355 –90 50 2155 –75 1955 –60 60 1755 SNR/SFDR (dBFS) –45 70 1555 –30 1355 –15 AMPLITUDE (dB) 80 AIN = –2dBFS SNRFS = 58.3dB SFDR = 60dBFS ENOB = 8.9 BITS NSD = –148.3dBFS/Hz BUFFER CURRENT = 700µA 1155 0 AD9689 INPUT FREQUENCY (MHz) Figure 15. SNR/SFDR vs. Input Frequency (fIN) for Various Buffer Currents Figure 12. Single-Tone FFT at fIN = 3300 MHz 0 –15 –30 –45 –45 –50 –60 –75 –90 –60 –65 –70 –75 –105 –80 15550-416 3755 3555 3355 2955 3155 2755 2555 2355 fIN (MHz) 2155 –90 950 1955 855 1755 760 1355 665 1555 570 1155 475 755 380 955 285 555 190 355 95 155 0 –85 3955 15550-413 –120 –135 300µA 500µA 700µA –55 HD2 (dBFS) AMPLITUDE (dB) –40 AIN = –2dBFS SNRFS = 54.4dB SFDR = 61dBFS ENOB = 8.6 BITS NSD = –144.4dBFS/Hz BUFFER CURRENT = 900µA INPUT FREQUENCY (MHz) Figure 13. Single-Tone FFT at fIN = 4350 MHz; Full-Scale Voltage = 1.1 V p-p 0 –30 AIN = –2dBFS SNRFS = 53.1dB SFDR = 62dBFS ENOB = 8.4 BITS NSD = –143.1dBFS/Hz BUFFER CURRENT = 900µA –15 –30 –45 –40 300µA 500µA 700µA –50 HD3 (dBFS) AMPLITUDE (dB) Figure 16. HD2 vs. Input Frequency (fIN) for Various Buffer Currents –60 –75 –90 –60 –70 –105 15550-417 3955 3755 3555 3355 2955 3155 2755 2555 fIN (MHz) –90 2355 950 2155 855 1955 760 1755 665 1555 570 1355 475 1155 380 955 285 755 190 555 95 355 0 –80 155 –135 15550-414 –120 INPUT FREQUENCY (MHz) Figure 14. Single-Tone FFT at fIN = 5400 MHz; Full-Scale Voltage = 1.1 V p-p Rev. A | Page 17 of 134 Figure 17. HD3 vs. Input Frequency (fIN) for Various Buffer Currents AD9689 Data Sheet 0 0 AIN1 AND AIN2 = –8dBFS SFDR = 72dBFS IMD2 = 82dBFS IMD3 = 72dBFS BUFFER CURRENT = 500µA –45 –60 –75 –90 –45 –60 –75 –90 –105 –105 –120 –120 –135 750 875 –135 1000 –60 –45 –30 Figure 21. Two-Tone FFT; fIN1 = 947.5 MHz, fIN2 = 1855.5 MHz fCLK = 1.96608 GHz; Decimation Ratio = 16, NCO Frequency = 1842.5 MHz 0 0 AIN1 AND AIN2 = –8dBFS SFDR = 74dBFS IMD2 = 77dBFS IMD3 = 74dBFS BUFFER CURRENT = 700µA –20 500 625 750 875 15550-422 –130 1000 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 19. Two-Tone FFT; fIN1 = 2137 MHz, fIN2 = 2142 MHz; AIN1 and AIN2 = −8 dBFS Figure 22. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 1841.5 MHz, fIN2 = 1846.5 MHz 0 0 AIN1 AND AIN2 = –8dBFS NCO FREQUENCY = 942.5MHz SFDR = 91dBFS BUFFER CURRENT = 700µA 15 30 45 60 FREQUENCY (MHz) 15550-423 –140 –30 0 –36 –15 –42 –30 –48 –45 –54 –135 –120 –60 15550-420 –120 –100 –66 –105 –72 –90 –80 –78 –75 –60 –84 –60 –40 –90 –45 –60 SFDR (dBc) SFDR (dBFS) IMD3 (dBc) IMD3 (dBFS) –20 SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) –30 –30 375 –36 250 –42 125 –120 –48 0 –90 –100 –54 –135 –80 –110 15550-419 –120 –70 –60 –105 –60 –66 –90 –50 –72 –75 –40 –78 –60 –30 –84 –45 –90 AMPLITUDE (dBFS) –30 SFDR (dBc) SFDR (dBFS) IMD3 (dBc) IMD3 (dBFS) –10 SFDR/IMD3 (dBc AND dBFS) –15 60 45 30 FREQUENCY (MHz) Figure 18. Two-Tone FFT; fIN1 = 1841 MHz, fIN2 = 1846 MHz; AIN1 and AIN2 = −8 dBFS –15 15 0 –15 FREQUENCY (MHz) –12 625 –18 500 –12 375 –24 250 –18 125 0 15550-421 AMPLITUDE (dBFS) –30 15550-418 AMPLITUDE (dBFS) –30 AIN1 AND AIN2 = –8dBFS NCO FREQUENCY = 1.842GHz SFDR = 99dBFS BUFFER CURRENT = 700µA –15 –24 –15 INPUT AMPLITUDE (dBFS) Figure 20. Two-Tone FFT; fIN1 = 947.5 MHz, fIN2 = 1855.5 MHz fCLK = 1.96608 GHz; Decimation Ratio = 16, NCO Frequency = 942.5 MHz Rev. A | Page 18 of 134 Figure 23. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 2137.5 MHz, fIN2 = 2142.5 MHz AD9689 120 3.5 100 3.0 80 2.5 40 20 SNR (dBFS) SFDR (dBFS) SFDR (dBc) SNR (dBc) 0 AVDD1 + AVDD2 + AVDD3 POWER DRVDD1 + DRVDD2 POWER DVDD + SPIVDD POWER AVERAGE OF TOTAL POWER (W) 0.5 0 –10 –85 –81 –77 –73 –69 –65 –61 –57 –53 –49 –45 –41 –37 –33 –29 –25 –21 –17 –13 –9 –5 –40 1.5 1.0 15550-424 –20 2.0 15550-427 60 POWER (W) 0 10 20 INPUT AMPLITUDE (dBFS) 40 50 60 70 80 90 100 110 120 Figure 27. Power vs. Junction Temperature (TJ), fIN = 900 MHz 120 65 100 63 61 80 59 53 SNR (dBFS) SFDR (dBFS) SFDR (dBc) SNR (dBc) 90 80 80 70 70 SFDR SNR 40 30 15550-426 40 50 60 70 80 3895.3 30 10 30 3582.8 40 20 20 3270.3 50 10 10 2957.8 60 20 0 0 90 100 110 120 JUNCTION TEMPERATURE (°C) SFDR SNR 15550-429 SNR/SFDR (dBFS) 60 0 2645.3 Figure 28. SNR vs. Analog Input Frequency (fIN) for Various Clock Amplitude in Differential Peak-to-Peak Voltages 90 –10 2332.8 ANALOG INPUT FREQUENCY (MHz) Figure 25. SNR/SFDR vs. Input Amplitude (AIN), fIN = 1800 MHz 50 2020.3 INPUT AMPLITUDE (dBFS) 1717.8 47 –85 –81 –77 –73 –69 –65 –61 –57 –53 –49 –45 –41 –37 –33 –29 –25 –21 –17 –13 –9 –5 –40 15550-428 49 15550-425 –20 51 467.8 0 0.2V 0.3V 0.5V 0.8V 1.2V 1.8V 2.0V 55 155.3 20 57 1092.8 40 780.3 60 SNR (dBFS) SNR/SFDR (dBc AND dBFS) Figure 24. SNR/SFDR vs. Input Amplitude (AIN), fIN = 900 MHz SNR/SFDR (dBFS) 30 JUNCTION TEMPERATURE (°C) 1405.3 SNR/SFDR (dBc AND dBFS) Data Sheet 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 SAMPLE FREQUENCY (GHz) Figure 26. SNR/SFDR vs. Junction Temperature (TJ), fIN = 900 MHz Figure 29. SNR/SFDR vs. Sample Frequency (fS), fIN = 900 MHz Rev. A | Page 19 of 134 2.1 Data Sheet 80 400,000 70 350,000 60 300,000 NUMBER OF HITS SFDR SNR 50 40 30 250,000 200,000 150,000 100,000 20 50,000 15550-430 10 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0 2.1 N – 25 N – 23 N – 21 N – 19 N – 17 N – 15 N – 13 N – 10 N–8 N–6 N–4 N–2 N N+2 N+4 N+6 N+8 N + 10 N + 12 N + 14 N + 16 N + 18 N + 20 N + 22 N + 24 0 3.8 LSB RMS 15550-433 SNR/SFDR (dBFS) AD9689 SAMPLE FREQUENCY (GHz) OUTPUT CODE Figure 33. Input Referred Noise Histogram 3.0 6 2.5 4 2.0 2 INL (LSB) 1.5 AVDD1 + AVDD2 + AVDD3 POWER DRVDD1 + DRVDD2 POWER DVDD + SPIVDD POWER AVERAGE OF TOTAL POWER 1.0 –2 –4 15550-431 0.5 0 0 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 –6 2.1 15550-434 POWER DISSIPATION (W) Figure 30. SNR/SFDR vs. Sample Frequency (fS), fIN = 1.8 GHz 0 2000 4000 Figure 31. Power Dissipation vs. Sample Frequency (fS), fIN = 1.8 GHz 8000 10000 12000 14000 16000 Figure 34. INL, fIN = 155 MHz –3 0.8 –4 0.6 –5 –6 0.4 –7 –8 DNL (LSB) AMPLITUDE (dB) 6000 OUTPUT CODE SAMPLE FREQUENCY (GHz) –9 –10 0.2 0 –0.2 –11 –12 –0.4 –13 2100 4100 6100 8100 FREQUENCY (MHz) 10100 12100 15550-232 –15 100 Figure 32. Input Bandwidth (See Figure 80 for the Input Configuration) Rev. A | Page 20 of 134 –0.8 15550-435 –0.6 –14 0 2000 4000 6000 8000 10000 OUTPUT CODE Figure 35. DNL, fIN = 155 MHz 12000 14000 16000 Data Sheet AD9689 2.6 GSPS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, sampling rate = 2.56 GHz, clock divider = 2, 1.7 V p-p full-scale differential input, input amplitude (AIN) = −2.0 dBFS, TJ = 70°C (TA = 25°C), 128 k FFT sample, unless otherwise noted. See Table 10 for the recommended settings. –15 –30 –45 –60 –75 –45 –60 –75 –90 –90 –105 –105 0 150M 300M 450M 600M 750M 900M 1.05G 1.20G –120 15550-106 –120 AIN = –2dBFS SNRFS = 60.9dB SFDR = 74dBFS ENOB = 10.1 BITS NSD = –152.0dBFS/Hz BUFFER CURRENT = 300µA –15 AMPLITUDE (dB) –30 AMPLITUDE (dB) 0 AIN = –2dBFS SNRFS = 61.3dB SFDR = 78dBc ENOB = 10.2 BITS NSD = –152.4dBFS/Hz BUFFER CURRENT = 300µA 0 0 900M 1.05G 1.20G AIN = –2dBFS SNRFS = 59.7dB SFDR = 73dBFS ENOB = 9.6 BITS NSD = –150.8dBFS/Hz BUFFER CURRENT = 500µA –15 –30 AMPLITUDE (dB) AMPLITUDE (dB) –40 750M Figure 39. Single-Tone FFT at fIN = 905 MHz AIN = –2dBFS SNR = 62.5dBFS SFDR = 78dBFS ENOB = 10.4 BITS NSD = –153.6dBFS/Hz BUFFER CURRENT = 300µA –20 450M 600M fIN (Hz) Figure 36. Single-Tone FFT at fIN = 155 MHz 0 150M 300M 15550-109 0 –60 –80 –45 –60 –75 –90 0 150M 300M 450M 600M 750M 900M 1.05G 1.20G fIN (Hz) –120 15550-107 –120 0 0 AMPLITUDE (dB) –30 –45 –60 –75 –90 900M 1.05G 1.20G –45 –60 –75 –90 –105 –105 –120 0 150M 300M 450M 600M 750M 900M fIN (Hz) 1.20G Figure 38. Single-Tone FFT at fIN = 750 MHz –135 15550-111 –120 750M AIN = –2dBFS SNRFS = 59.3dB SFDR = 73dBFS ENOB = 9.5 BITS NSD = –150.4dBFS/Hz BUFFER CURRENT = 500µA –15 15550-108 AMPLITUDE (dB) –30 450M 600M Figure 40. Single-Tone FFT at fIN = 1807 MHz AIN = –2dBFS SNRFS = 61.0dB SFDR = 73dBFS ENOB = 10.1 BITS NSD = –152.1dBFS/Hz BUFFER CURRENT = 300µA –15 300M fIN (Hz) Figure 37. Single-Tone FFT at fIN = 155 MHz, Full-Scale Voltage = 2.04 V p-p 0 150M 15550-110 –105 0 150M 300M 450M 600M 750M 900M 1.05G 1.20G fIN (Hz) Figure 41. Single-Tone FFT at fIN = 2100 MHz Rev. A | Page 21 of 134 AD9689 0 80 AIN = –2dBFS SNRFS = 58.0dB SFDR = 64dBFS ENOB = 9.1 BITS NSD = –149.0dBFS/Hz BUFFER CURRENT = 700µA –15 75 70 65 SNR/SFDR (dBFS) –30 –45 –60 –75 –90 60 55 300µA, 300µA, 500µA, 500µA, 700µA, 700µA, 50 45 40 –105 SFDR SNR SFDR SNR SFDR SNR INPUT FREQUENCY (MHz) Figure 45. SNR/SFDR vs. Input Frequency (fIN) for Various Buffer Currents Figure 42. Single-Tone FFT at fIN = 3300 MHz 0 –30 –50 –45 –60 –75 –60 –65 –70 –90 INPUT FREQUENCY (MHz) Figure 43. Single-Tone FFT at fIN = 4350 MHz; Full-Scale Voltage = 1.1 V p-p 0 –30 –40 –45 –50 300µA 500µA 700µA –55 –45 HD3 (dBFS) AMPLITUDE (dB) Figure 46. Second Harmonics (HD2) vs. Input Frequency (fIN) for Various Buffer Currents AIN = –2dBFS SNRFS = 53.0dB SFDR = 59dBFS ENOB = 7.9 BITS NSD = –144.1dBFS/Hz BUFFER CURRENT = 700µA –15 15550-116 3955 3755 3555 3355 2955 3155 2755 2555 2355 2155 1955 1755 1555 1355 –80 1155 900M 1.05G 1.20G 955 750M fIN (Hz) 755 600M 555 450M 355 150M 300M 15550-113 0 155 –75 –105 –120 300µA 500µA 700µA –55 HD2 (dBFS) AMPLITUDE (dB) –45 AIN = –2dBFS SNRFS = 54.0dB SFDR = 60dBFS ENOB = 8.2 BITS NSD = –145.1dBFS/Hz BUFFER CURRENT = 700µA –15 15550-115 3755 3955 3555 3355 2955 3155 2555 2755 2355 2155 1955 1755 fIN (Hz) 30 1555 1.05G 1.20G 1355 900M 955 750M 755 450M 600M 355 150M 300M 555 0 155 35 15550-112 –120 1155 AMPLITUDE (dB) Data Sheet –60 –75 –60 –65 –70 –75 –90 –80 –105 3955 3755 3555 3355 2955 15550-117 INPUT FREQUENCY (MHz) Figure 44. Single-Tone FFT at fIN = 5400 MHz; Full-Scale Voltage = 1.1 V p-p 3155 2755 2555 2355 2155 1955 1755 1555 –90 1355 900M 1.05G 1.20G 1155 600M 750M fIN (Hz) 955 450M 755 300M 555 150M 355 0 155 –85 15550-114 –120 Figure 47. Third Harmonics (HD3) vs. Input Frequency (fIN) for Various Buffer Currents Rev. A | Page 22 of 134 Data Sheet 0 0 AIN1 AND AIN2 = –8dBFS SFDR = 72dBFS IMD2 = 72dBFS IMD3 = 78dBFS BUFFER CURRENT = 500µA –20 AIN1 AND AIN2 = –8dBFS NCO FREQUENCY = 2.14GHz SFDR = 84dBFS BUFFER CURRENT = 700µA –10 –20 –30 –40 –40 AMPLITUDE (dB) AMPLITUDE (dBFS) AD9689 –60 –80 –50 –60 –70 –80 –90 –100 –100 –110 160 320 480 640 800 960 1120 1280 FREQUENCY (MHz) Figure 48. Two-Tone FFT; fIN1 = 1841 MHz, fIN2 = 1846 MHz; AIN1 and AIN2 = −8 dBFS 0 0 92.16 122.88 IMD3 (dBc) IMD3 (dBFS) SFDR (dBc) SFDR (dBFS) –10 –20 SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) 61.44 Figure 51. Two-Tone FFT; fIN1 = 1846.5 MHz, fIN2 = 2142.5 MHz fCLK = 2.4576 GHz; Decimation Ratio = 10, NCO Frequency = 2140 MHz AIN1 AND AIN2 = –8dBFS SFDR = 76dBFS IMD2 = 78dBFS IMD3 = 76dBFS BUFFER CURRENT = 700µA –20 –130 30.72 0 –122.88 –92.16 –61.44 –30.72 FREQUENCY (MHz) 15550-118 0 15550-121 –120 –120 –40 –60 –80 –100 –30 –40 –50 –60 –70 –80 –90 –100 –110 320 480 640 800 960 1120 1280 FREQUENCY (MHz) –130 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 INPUT AMPLITUDE (dBFS) Figure 49. Two-Tone FFT; fIN1 = 2137 MHz, fIN2 = 2142 MHz; AIN1 and AIN2 = −8 dBFS –20 AMPLITUDE (dB) –30 0 AIN1 AND AIN2 = –8dBFS NCO FREQUENCY = 1.84GHz SFDR = 77dBFS BUFFER CURRENT = 700µA –20 –40 –50 –60 –70 –80 –90 –100 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –120 61.44 92.16 122.88 15550-120 –110 –130 –122.88 –92.16 –61.44 –30.72 0 30.72 FREQUENCY (MHz) IMD3 (dBc) IMD3 (dBFS) SFDR (dBc) SFDR (dBFS) –10 SFDR/IMD3 (dBc AND dBFS) 0 –10 Figure 52. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 1841.5 MHz, fIN2 = 1846.5 MHz Figure 50. Two-Tone FFT; fIN1 = 1846.5 MHz, fIN2 = 2142.5 MHz fCLK = 2.4576 GHz; Decimation Ratio = 10, NCO Frequency = 1840 MHz Rev. A | Page 23 of 134 –130 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 INPUT AMPLITUDE (dBFS) Figure 53. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 2137.5 MHz, fIN2 = 2142.5 MHz 15550-123 160 15550-119 0 15550-122 –120 –120 AD9689 Data Sheet 110 4.0 100 3.0 70 60 POWER (W) 50 40 30 20 10 0 2.5 2.0 1.5 1.0 SNR (dBc) SNR (dBFS) SFDR (dBc) SFDR (dBFS) –20 –30 –82 –74 –66 –58 –50 –42 –34 –26 –18 –10 –2 INPUT AMPLITUDE (dBFS) 0.5 0 –10 0 10 20 Figure 54. SNR/SFDR vs. Input Amplitude (AIN), fIN = 900 MHz 63 60 70 80 90 100 110 120 1.2V 1.8V 2.0V 1155.3 1655.3 2155.3 2655.3 3155.3 3655.3 61 90 80 59 70 60 SNR (dBFS) 50 40 30 20 10 0 57 55 53 51 SNR (dBc) SNR (dBFS) SFDR (dBc) SFDR (dBFS) –20 –30 –40 –90 –82 –74 –66 –58 –50 –42 –34 –26 –18 –10 –2 INPUT AMPLITUDE (dBFS) 49 Figure 55. SNR/SFDR vs. Input Amplitude (AIN), fIN = 1800 MHz 75 47 155.3 655.3 ANALOG INPUT FREQUENCY (MHz) 15550-128 –10 15550-125 Figure 58. SNR vs. Analog Input Frequency (fIN) for Various Clock Amplitude in Differential Peak-to-Peak Voltages 90 SNR SFDR 80 70 SNR/SFDR (dBFS) 70 65 60 60 50 40 30 20 55 0 10 20 30 40 50 60 70 80 90 100 110 120 JUNCTION TEMPERATURE (°C) 15550-126 10 Figure 56. SNR/SFDR vs. Junction Temperature (TJ), fIN = 900 MHz 0 1800 SNR SFDR 1900 2000 2100 2200 2300 2400 2500 SAMPLE FREQUENCY (MHz) 2600 2700 Figure 59. SNR/SFDR vs. Sample Frequency (fS), fIN = 900 MHz Rev. A | Page 24 of 134 15550-129 SNR/SFDR (dBc AND dBFS) 50 0.2V 0.3V 0.5V 0.8V 100 SNR/SFDR (dBFS) 40 Figure 57. Power vs. Junction Temperature (TJ), fIN = 900 MHz 110 50 –10 30 JUNCTION TEMPERATURE (°C) 15550-127 –10 15550-124 SNR/SFDR (dBc AND dBFS) 80 –40 –90 AVDD1 POWER/AVDD2 POWER/AVDD3 POWER (W) DRVDD1 POWER/DRVDD2 POWER (W) DVDD POWER/SPIVDD POWER (W) TOTAL POWER (W) 3.5 90 Data Sheet AD9689 80 400000 70 350000 60 300000 NUMBER OF HITS 50 40 30 20 150000 100000 50000 SNR SFDR 1900 2000 2100 2200 2300 2400 2500 2600 2700 SAMPLE FREQUENCY (MHz) 0 OUTPUT CODE Figure 63. Input Referred Noise Histogram Figure 60. SNR/SFDR vs. Sample Frequency (fS), fIN = 1.8 GHz 6 3.5 5 4 2.5 3 INL (LSB) POWER DISSIPATION (W) 3.0 2.0 1.5 15550-133 0 1800 200000 15550-130 10 250000 N – 25 N – 23 N – 21 N – 19 N – 17 N – 15 N – 13 N – 10 N–8 N–6 N–4 N–2 N N+2 N+4 N+6 N+8 N + 10 N + 12 N + 14 N + 16 N + 18 N + 20 N + 22 N + 24 SNR/SFDR (dBFS) 4.6 LSB RMS AVDD1 POWER/AVDD2 POWER/AVDD3 POWER DRVDD1 POWER/DRVDD2 POWER DVDD POWER/SPIVDD POWER TOTAL POWER 2 1 0 –1 1.0 –2 0.5 2000 2100 2200 2300 2400 2500 2600 2700 SAMPLE FREQUENCY (MHz) –4 0 2000 4000 6000 8000 10000 12000 14000 16000 14000 16000 OUTPUT CODE Figure 61. Power Dissipation vs. Sample Frequency (fS), fIN = 1.8 GHz 15550-135 1900 15550-131 0 1800 –3 Figure 64. INL, fIN = 155 MHz 0.8 –3 –4 0.6 –5 DNL (LSB) –7 –8 –9 0.2 0 –10 –11 –0.2 –12 –13 –0.4 2100 4100 6100 8100 FREQUENCY (MHz) 10100 12100 15550-232 –14 –15 100 0.4 –0.6 Figure 62. Input Bandwidth (See Figure 80 for the Input Configuration) Rev. A | Page 25 of 134 0 2000 4000 6000 8000 10000 OUTPUT CODE 12000 Figure 65. DNL, fIN = 155 MHz 15550-134 AMPLITUDE (dB) –6 AD9689 Data Sheet EQUIVALENT CIRCUITS AVDD1_SR AVDD3 AVDD3 100Ω SYSREF+ VIN+x 10kΩ 1.9pF 130kΩ 0.3pF 100Ω AVDD3 LEVEL TRANSLATOR VCM = 0.65V 100Ω AVDD3 130kΩ VIN–x AIN CONTROL (SPI) 100Ω SYSREF– 15550-037 0.3pF AVDD1_SR 10kΩ 15550-039 AVDD3 VCM BUFFER 1.9pF Figure 69. SYSREF± Inputs Figure 66. Analog Inputs AVDD1 EMPHASIS/SWING CONTROL (SPI) CLK+ DRVDD1 SERDOUTx+ DATA+ x = 0, 1, 2, 3, 4, 5, 6, 7 OUTPUT DRIVER AVDD1 VCM = 0.65V SERDOUTx– DATA– 15550-038 16kΩ 16kΩ CLK– DRGND DRVDD1 x = 0, 1, 2, 3, 4, 5, 6, 7 DRGND Figure 70. Digital Outputs Figure 67. Clock Inputs SPIVDD DRVDD1 ESD PROTECTED SYNCINB+ 100Ω CMOS PATH SPIVDD DRVDD1 SCLK 10kΩ 56kΩ ESD PROTECTED 1.9pF 130kΩ DRGND DGND DRGND Figure 71. SCLK Input LEVEL TRANSLATOR VCM = 0.65V 130kΩ 100Ω DRVDD1 10kΩ 1.9pF DRGND DRGND 15550-041 SYNCINB– DGND Figure 68. SYNCINB± Inputs Rev. A | Page 26 of 134 DGND 15550-042 2.6kΩ SYNCINB± PIN CONTROL (SPI) DRGND 15550-040 106Ω Data Sheet AD9689 SPIVDD SPIVDD ESD PROTECTED ESD PROTECTED 56kΩ PDWN/STBY 56kΩ DGND ESD PROTECTED 15550-043 ESD PROTECTED DGND DGND Figure 72. CSB Input SPIVDD PDWN CONTROL (SPI) DGND DGND 15550-046 CSB Figure 74. PDWN/STBY Input SPIVDD ESD PROTECTED SDI DGND VCM OUTPUT SPIVDD 56kΩ TEMPERATURE DIODE VOLTAGE OUTPUT AVDD2 SDO ESD PROTECTED EXTERNAL REFERENCE VOLTAGE INPUT DGND VREF PIN CONTROL (SPI) AGND Figure 73. SDIO Input Figure 75. VREF Input/Output SPIVDD SPIVDD ESD PROTECTED NCO BAND SELECT DGND FD_A/GPIO_A0, FD_B/GPIO_B0 SPIVDD FD JESD204B LMFC 56kΩ ESD PROTECTED JESD204B SYNC~ DGND DGND DGND FD PIN CONTROL (SPI) 15550-045 DGND Figure 76. FD_A/GPIO_A0, FD_B/GPIO_B0 SPIVDD ESD PROTECTED SPIVDD NCO BAND SELECT SDI GPIO_A1/GPIO_B1 ESD PROTECTED 56kΩ DGND DGND CHIP TRANSFER DGND GPIO_A1/GPIO_B1 PIN CONTROL (SPI) Figure 77. GPIO_A1/GPIO_B1 Rev. A | Page 27 of 134 15550-247 DGND 15550-044 VREF 15550-047 SDIO AD9689 Data Sheet THEORY OF OPERATION The AD9689 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. The Subclass 1 JESD204B-based high speed serialized output data lanes can be configured in one-lane (L = 1), two-lane (L = 2), four-lane (L = 4), and eight-lane (L = 8) configurations, depending on the sample rate and the decimation ratio. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins. The SYSREF± pin in the AD9689 can also be used as a timestamp of data as it passes through the ADC and out of the JESD204B interface. Figure 78 shows the differential input return loss curve for the analog inputs across a frequency range of 100 MHz to 10 GHz. The reference impedance is 100 Ω. 1.0 m5 The analog input to the AD9689 is a differential buffer. The internal common-mode voltage of the buffer is 1.4 V. The clock signal alternately switches the input circuit between sample mode and hold mode. 5.0 m1 m3 0 0 m2 –5.0 –0.2 –0.5 –2.0 –1.0 FREQUENCY (100MHz TO 10GHz) The architecture of the AD9689 consists of an input buffered pipelined ADC. The input buffer provides a termination impedance to the analog input signal. This termination impedance is set to 200 Ω. The equivalent circuit diagram of the analog input termination is shown in Figure 66. The input buffer is optimized for high linearity, low noise, and low power across a wide bandwidth. ANALOG INPUT CONSIDERATIONS m4 0.2 ADC ARCHITECTURE The input buffer provides a linear high input impedance (for ease of drive) and reduces kickback from the ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample; at the same time, the remaining stages operate with the preceding samples. Sampling occurs on the rising edge of the clock. 2.0 0.5 m1 FREQUENCY = 100MHz SDD11 = 0.301/–8.069 IMPEDANCE = Z 0 × (1.838 – j0.171) m4 FREQUENCY = 4GHz SDD11 = 0.500/136.667 IMPEDANCE = Z 0 × (0.379 + j0.347) m2 FREQUENCY = 1GHz SDD11 = 0.352/–73.534 IMPEDANCE = Z 0 × (0.947 – j0.731) m5 FREQUENCY = 5GHz SDD11 = 0.475/79.360 IMPEDANCE = Z 0 × (0.737 + j0.889) m3 FREQUENCY = 3GHz SDD11 = 0.496/175.045 IMPEDANCE = Z 0 × (0.337 – j0.038) 15550-248 The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Either a differential capacitor or two single-ended capacitors (or a combination of both) can be placed on the inputs to provide a matching passive network. These capacitors ultimately create a low-pass filter that limits unwanted broadband noise. For more information, refer to the Analog Dialogue article, “TransformerCoupled Front-End for Wideband A/D Converters” (Volume 39, April 2005). In general, the precise front-end network component values depend on the application. SDD11 The AD9689 has two analog input channels and up to eight JESD204B output lane pairs. The ADC samples wide bandwidth analog signals of up to 5 GHz. The actual −3 dB roll-off of the analog inputs is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. Figure 78. Differential Input Return Loss For best dynamic performance, the source impedances driving VIN+x and VIN−x must be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. For the AD9689, the available span is programmable through the SPI port from 1.13 V p-p to 2.04 V p-p differential, with 1.7 V p-p differential being the default. Rev. A | Page 28 of 134 Data Sheet AD9689 Differential Input Configurations For higher frequencies in the second or third Nyquist zones, it is recommended to remove some of the front-end passive components to ensure wideband operation (see Figure 80 and Table 9). There are several ways to drive the AD9689, either actively or passively. Optimum performance is achieved by driving the analog input differentially. C2 R1 MARKI BAL-0006 C3 R2 R1 For low to midrange frequencies, a double balun or double transformer network (see Figure 79 and Table 9) is recommended for optimum performance of the AD9689. C4 C1 R2 C2 C3 NOTES: 1. SEE TABLE 9 FOR COMPONENT VALUES 0.1µF 10Ω 25Ω MARKI BAL-0009 25Ω 200Ω 0.1µF 10Ω ADC 15550-250 25Ω 0.1µF Figure 80. Input Network Configuration for Frequencies > 5 GHz Table 9. Differential Transformer Coupled Input Configuration Component Values Transformer BAL-0006 BAL-0009 R1 25 Ω 25 Ω R2 25 Ω 25 Ω R3 10 Ω 10 Ω 200Ω ADC R3 Figure 79. Differential Transformer Coupled Configuration for the AD9689 25Ω Frequency Range <5000 MHz >5000 MHz R3 15550-249 For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 79 and Table 9) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9689. C1 0.1 μF 0.1 μF C2 0.1 μF 0.1 μF Rev. A | Page 29 of 134 C3 0.4 pF Open C4 0.4 pF or open Open AD9689 Data Sheet Input Common Mode The analog inputs of the AD9689 are internally biased to the common-mode voltage, as shown in Figure 82. The commonmode buffer has a limited range in that the performance suffers greatly if the common-mode voltage drops by more than 50 mV on either side of the nominal value. For dc-coupled applications, the recommended operation procedure is to export the common-mode voltage to the VREF pin using the SPI writes listed in this section. The common-mode voltage must be set by the exported value to ensure proper ADC operation. Disconnect the internal common-mode buffer from the analog input using Register 0x1908. When performing SPI writes for dc coupling operation, use the following register settings in order: Using Register 0x1A4C and Register 0x1A4D, the buffer behavior on each channel can be adjusted to optimize the SFDR over various input frequencies and bandwidths of interest. Use Register 0x1910 to change the internal reference voltage. Changing the internal reference voltage results in a change in the input full-scale voltage. When the input buffer current in Register 0x1A4C and Register 0x1A4D is set, the amount of current required by the AVDD3 supply changes. This relationship is shown in Figure 83. For a complete list of buffer current settings, see Table 46 and Table 53. 0.26 0.25 Set Register 0x1908, Bit 2 to disconnect the internal common-mode buffer from the analog input. Note that this is a local register. Set Register 0x18A6 to 0x00 to turn off the voltage reference. Set Register 0x18E6 to 0x00 to turn off the temperature diode export. Set Register 0x18E3, Bit 6 to 1 to turn on the VCM export. Set Register 0x18E3, Bits[5:0] to the buffer current setting (Register 0x1A4C and Register 0x1A4D) to improve the accuracy of the common-mode export. 4. 5. 0.21 0.2 0.18 0.17 400 500 ADC Table 10 shows the recommended values for the buffer current for various Nyquist zones. ADC VCM EXPORT SELECT SPI REGISTERS 0x1908, 0x18A6, 0x18E3, 0x18E6) 15550-251 VOCM AMP B Table 10. SFDR Optimization for Input Frequencies Figure 81. DC-Coupled Application Using the AD9689 Analog Input Buffer Controls and SFDR Optimization VIN+x AVDD3 Product AD9689-2600 Frequency DC to 1.3 GHz AD9689-2000 1.3 GHz to 2.6 GHz >2.6 GHz DC to 1000 MHz 0.3pF 100Ω AVDD3 1 GHz to 2 GHz >2 GHz VIN–x REG (0x0008, 0x1908) 1 N/A means not applicable. AVDD3 0.3pF REG (0x0008, 0x1A4C, 0x1A4D, 0x1910) 15550-252 100Ω AVDD3 700 Figure 83. AVDD3 Current (IAVDD3) vs. Buffer Current Setting (Buffer Control 1 Setting in Register 0x1A4C and Buffer Control 2 Setting in Register 0x1A4D) VREF AVDD3 600 BUFFER CURRENT SETTING (µA) ADC VOCM 0.22 0.19 Figure 81 shows the block diagram of a dc-coupled application. AMP A 0.23 15550-253 2. 3. 0.24 AVDD3 CURRENT (A) 1. The AD9689 input buffer offers flexible controls for the analog inputs, such as buffer current, dc coupling, and input full-scale adjustment. All the available controls are shown in Figure 82. Figure 82. Analog Input Controls Rev. A | Page 30 of 134 Register 0x1A4C and Register 0x1A4D Default (300 µA) 500 µA 700 µA Default (300 µA) 500 µA 700 µA High Frequency Setting Register 0x1A48 Default (0x14) Default (0x14) 0x54 N/A1 N/A N/A Data Sheet AD9689 The dither is on by default. It is not recommended to turn it off. Absolute Maximum Input Swing The absolute maximum input swing allowed at the inputs of the AD9689 is 5.8 V p-p differential. Signals operating near or at this level can cause permanent damage to the ADC. See Table 6 for more information. VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9689. This internal 0.5 V reference sets the full-scale input range of the ADC. The full-scale input range can be adjusted via the ADC input full-scale control register (Register 0x1910). For more information on adjusting the input swing, see Table 46 and Table 53. Figure 85 shows the block diagram of the internal 0.5 V reference controls. The SPI Register 0x18A6 enables the user to either use this internal 0.5 V reference, or to provide an external 0.5 V reference. When using an external voltage reference, provide a 0.5 V reference. The full-scale adjustment is made using the SPI, irrespective of the reference voltage. For more information on adjusting the full-scale level of the AD9689, refer to the Memory Map section. 1. 2. 3. Set Register 0x18E3 to 0x00 to turn off the VCM export. Set Register 0x18E6 to 0x00 to turn off the temperature diode export. Set Register 0x18A6 to 0x01 to turn on the external voltage reference. The use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 84 shows the typical drift characteristics of the internal 0.5 V reference. 0.5060 0.5055 0.5050 0.5045 0.5040 0.5035 0.5030 –10 10 30 50 90 110 130 Figure 84. Typical Reference Voltage (VREF) Drift The external reference must be a stable 0.5 V reference. The ADR130 is a sufficient option for providing the 0.5 V reference. Figure 86 shows how the ADR130 can be used to provide the external 0.5 V reference to the AD9689. The dashed lines show unused blocks within the AD9689 while using the ADR130 to provide the external reference. VIN+A/VIN+B VIN–A/VIN–B INTERNAL 0.5V REFERENCE GENERATOR 70 JUNCTION TEMPERATURE (°C) 15550-256 The AD9689 has internal on-chip dither circuitry that improves the ADC linearity and SFDR, particularly at smaller signal levels. A known but random amount of white noise is injected into the input of the AD9689. This dither improves the small signal linearity within the ADC transfer function and is precisely subtracted out digitally. The dither is turned on by default and does not reduce the ADC input dynamic range. The data sheet specifications and limits are obtained with the dither turned on. The SPI writes required to use the external voltage reference, in order, are as follows: BAND GAP VOLTAGE (V) Dither ADC CORE INPUT FULL-SCALE ADJUST VREF PIN CONTROL SPI REGISTER (0x18A6) Figure 85. Internal Reference Configuration and Controls Rev. A | Page 31 of 134 15550-254 INPUT FULL-SCALE RANGE ADJUST SPI REGISTER (0x1910) VREF AD9689 Data Sheet INTERNAL 0.5V REFERENCE GENERATOR ADR130 NC NC ADC GND SET INPUT VIN VOUT 0.1µF INPUT FULL-SCALE ADJUST VREF 0.1µF 15550-255 VREF PIN AND VFS CONTROL Figure 86. External Reference Using the ADR130 1.0 DC OFFSET CALIBRATION 2.0 0.5 m5 0.2 CLOCK INPUT CONSIDERATIONS 5.0 m4 m3 m2 m1 0 0 –5.0 –0.2 For optimum performance, drive the AD9689 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is ac-coupled to the CLK+ and CLK− pins via a transformer or clock drivers. These pins are biased internally and require no additional biasing. Figure 87 shows the differential input return loss curve for the clock inputs across a frequency range of 100 MHz to 6 GHz. The reference impedance is 100 Ω. –0.5 –2.0 –1.0 FREQUENCY (100MHz TO 10GHz) m1 FREQUENCY = 2.001GHz SDD11 = 0.274/–156.496 IMPEDANCE = Z 0 × (0.586 – j0.139) m4 FREQUENCY = 4.001GHz SDD11 = 0.360/139.617 IMPEDANCE = Z 0 × (0.518 + j0.278) m2 FREQUENCY = 2.602GHz SDD11 = 0.319/–176.549 IMPEDANCE = Z 0 × (0.516 – j0.022) m5 FREQUENCY = 5.202GHz SDD11 = 0.364/139.617 IMPEDANCE = Z 0 × (0.761 + j0.639) m3 FREQUENCY = 2.996GHz SDD11 = 0.337/169.383 IMPEDANCE = Z 0 × (0.499 – j0.070) Figure 87. Differential Input Return Loss for the CLK± Inputs Rev. A | Page 32 of 134 15550-257 SDD11 The AD9689 contains a digital filter to remove the dc offset from the output of the ADC. For ac-coupled applications, this filter can be enabled by writing 0x86 to Register 0x0701. The filter computes the average dc signal and it is digitally subtracted from the ADC output. As a result, the dc offset is improved to better than 70 dBFS at the output. Because the filter does not distinguish between the source of dc signals, this feature can be used when the signal content at dc is not of interest. The filter corrects dc up to ±512 codes and saturates beyond this value. Data Sheet AD9689 In some instances, the RF DAC series such as the AD9172 has a synthesizer that can output a clock output to clock the AD9689. Figure 91 shows the arrangement where the AD9172 clock outputs clock the AD9689. CLK+ CLOCK INPUT AD9172 ADC CLK– 15550-258 1:2Z CLKOUT+ Figure 88. Transformer-Coupled Differential Clock Another option is to ac couple a differential LVPECL or CML signal to the sample clock input pins, as shown in Figure 89 and Figure 90, respectively. CLK+ 100Ω DIFFERENTIAL TRACE 150Ω ADC CLOCK INPUT CLK– 150Ω 15550-259 LVDS DRIVER Figure 89. Differential LVPECL Sample Clock ADC CLOCK INPUT CLK– DIFFERENTIAL TRACE 15550-260 CLK+ CML DRIVER Figure 90. Differential CML Sample Clock Rev. A | Page 33 of 134 ADC DAC CLOCK INPUT CLK+ ADC CLOCK INPUT CLKOUT– CLK– 15550-261 Figure 88 shows a preferred method for clocking the AD9689. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. Figure 91. DAC Clock Output Clocking the AD9689 AD9689 Data Sheet Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. The AD9689 contains an internal clock divider and a duty cycle stabilizer comprised of DCS1 and DCS2, which is enabled by default. In applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock along with the usage of the clock divider is recommended. When it is not possible to provide a higher frequency clock, it is recommended to turn on the DCS using Register 0x011C and Register 0x011E. Figure 92 shows the different controls to the AD9689 clock inputs. The output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal ADC. See the Memory Map section for more details on using this feature. Input Clock Divider Register 0x0112, Bits[7:0] offer the user the option to delay the clock in 192 delay steps. Register 0x0111, Bits[7:0] offer the user the option to delay the clock in 128 superfine steps. These values can be programmed individually for each channel. To use the superfine delay option, set the clock delay control in Register 0x0110, Bits[2:0] to 0x2 or 0x6. Figure 93 shows the controls available to the clock dividers within AD9689. It is recommended to apply the same delay settings to the digital delay circuits as are applied to the analog delay circuits to maintain sample accuracy through the pipe. CHANNEL A PHASE CH. A CLK INPUT CLK_DIV The AD9689 contains an input clock divider with the ability to divide the input clock by 1, 2, or 4. Select the divider ratios using Register 0x0108 (see Figure 92). The maximum frequency at the CLK± inputs is 6 GHz, which is the limit of the divider. In applications where the clock input is a multiple of the sample clock, take care to program the appropriate divider ratio into the clock divider before applying the clock signal; this ensures that the current transients during device startup are controlled. REG 0x011C, 0x011E CLK+ ÷2 0x0109 FINE DELAY 0x0110, 0x0111, 0x0112 CHANNEL B Figure 93. Clock Divider Phase and Delay Controls The clock delay adjustment takes effect immediately when it is enabled via SPI writes. Enabling the clock fine delay adjust in Register 0x0110 causes a datapath reset. However, the contents of Register 0x0111 and Register 0x0112 can be changed without affecting the stability of the JESD204B link. Figure 92. Clock Divider Circuit The AD9689 clock divider can be synchronized using the external SYSREF± input. A valid SYSREF± signal causes the clock divider to reset to a programmable state. This synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. See the Memory Map Register Details section for more information. The AD9689 has many different domains within the analog supply that control various aspects of the data conversion. The clock domain is supplied by Pin A4, Pin A5, Pin A10, Pin A11, Pin B4, and Pin B11 on the analog supply, AVDD1 (0.975 V) and Pin A6, Pin A9, Pin B6, Pin B7, Pin B8, Pin B9, Pin C6, Pin C7, Pin C8, Pin C9, Pin D7, and Pin D8 on the ground (AGND) side. To minimize coupling between the clock supply domain and the other analog domains, it is recommended to add a supply Q factor reduction circuitry for Pin A4 and Pin A11, as well as Pin B4 and Pin B11, as shown in Figure 94. Input Clock Divider ½ Period Delay Adjust FERRITE BEAD 220Ω AT 100MHz DCR ≤ 0.5Ω The input clock divider in the AD9689 provides phase delay in increments of ½ the input clock cycle. Program Register 0x0109 to enable this delay independently for each channel. Changing this register does not affect the stability of the JESD204B link. A4 B4 A11 B11 100nF 10Ω AVDD1 PLANE Clock Fine Delay and Superfine Delay Adjust Adjust the AD9689 sampling edge instant by writing to Register 0x0110, Register 0x0111, and Register 0x0112. Bits[2:0] of Register 0x0110 enable the selection of the fine delay, or the fine delay with superfine delay. The fine delay allows the user to delay the clock edges with 16-step or 192-step delay options. The superfine delay is an unsigned control to adjust the clock delay in superfine steps of 0.25 ps each. FERRITE BEAD 220Ω AT 100MHz DCR ≤ 0.5Ω 100nF 10Ω 15550-264 REG 0x0108 0x0108 Clock Coupling Considerations ÷4 15550-262 CLK– PHASE CH. B 15550-263 Clock Duty Cycle Considerations Figure 94. Q Factor Reduction Network Recommendation for the Clock Domain Supply Rev. A | Page 34 of 134 AD9689 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. Calculate the degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) by SNR (dBFS) SNRJITTER = −20 × log10 (2 × π × fA × tJ) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. Intermediate frequency (IF) undersampling applications are particularly sensitive to jitter (see Figure 95). 130 12.5fS 25fS 50fS 100fS 200fS 400fS 800fS 120 110 90 100M 1G INPUT FREQUENCY (Hz) 10G Figure 96. Estimated SNR Degradation vs. Input Frequency and RMS Jitter for the 2.6 GSPS POWER-DOWN AND STANDBY MODE The AD9689 has a PDWN/STBY pin that can be used to configure the device in power-down or standby mode. The default operation is PDWN. The PDWN/STBY pin is a logic high pin. When in power-down mode, the JESD204B link is disrupted. The power-down option can also be set via Register 0x003F and Register 0x0040. 80 70 60 50 100 1000 10000 ANALOG INPUT FREQUENCY (MHz) 15550-265 40 30 10 25fS 50fS 75fS 100 fS 125 fS 150 fS 175 fS 200 fS Figure 95. Ideal SNR vs. Analog Input Frequency and Jitter Treat the clock input as an analog signal when aperture jitter may affect the dynamic range of the AD9689. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. If the clock is generated from another type of source (by gating, dividing, or other methods), retime the clock by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more information about jitter performance as it relates to ADCs. Figure 96 shows the estimated SNR of the AD9689 across input frequency for different clock induced jitter values. Estimate the SNR by using the following equation: − SNR JITTER −SNR ADC 10 10 SNR (dBFS) = −10log10 10 + 10 In standby mode, the JESD204B link is not disrupted and transmits zeros for all converter samples. Change this transmission using Register 0x0571, Bit 7 to select /K/ characters. TEMPERATURE DIODE The AD9689 contains diode-based temperature sensors. The diodes output voltages commensurate to the temperature of the silicon. There are multiple diodes on the die, but the results established using the temperature diode at the central location of the die can be regarded as representative of the entire die. However, in applications where only one channel is used (the other channel being in a power-down state), it is recommended to read the temperature diode corresponding to the channel that is on. Figure 97 shows the locations of the diodes in the AD9689 with voltages that can be output to the VREF pin. In each location, there is a pair of diodes, one of which is 20× the size of the other. It is recommended to use both diodes in a location to obtain an accurate estimate of the die temperature. For more information, see the AN-1432 Application Note. ADC ADC A ADC B VREF DIGITAL JESD204B DRIVER TEMPERATURE DIODE LOCATIONS CHANNEL A, CENTRAL, CHANNEL B Figure 97. Temperature Diode Locations in the Die Rev. A | Page 35 of 134 15550-267 IDEAL SNR (dB) 100 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 10M 15550-166 Data Sheet AD9689 Data Sheet 0.55 –20 0 40 20 60 80 100 JUNCTION TEMPERATURE (°C) Figure 99. Typical Voltage Response of the 1× Temperature Diode The relationship between the measured delta voltage (ΔV) and the junction temperature in °C is shown in Figure 100. Figure 98. Register Controls to Output Temperature Diode Voltage on the VREF Pin Set Register 0x0008 to 0x03 to select both channels. Set Register 0x18E3 to 0x00 to turn off VCM export. Set Register 0x18A6 to 0x00 to turn off voltage reference export. Set Register 0x18E6 to 0x01 to turn on voltage export of the central 1× temperature diode. The typical voltage response of the temperature diode is shown in Figure 99. Although this voltage represents the die temperature, it is recommended to take measurements from a pair of diodes for improved accuracy. Step 5 explains how to enable the 20× diode. Set Register 0x18E6 to 0x02 to turn on the second central temperature diode of the pair, which is 20× the size of the first. For the method using two diodes simultaneously to achieve a more accurate result, see the AN-1432 Application Note. 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 –10 –20 –30 –40 60 TJ (°C) The SPI writes required to export the central temperature diode are as follows (see Table 46 and Table 53 for more information): 5. 0.60 0.50 –40 15550-268 TEMPERATURE DIODE LOCATION SELECT SPI REGISTER (0x18E6) 4. 0.65 CHANNEL A CENTRAL CHANNEL B 1. 2. 3. 0.70 Rev. A | Page 36 of 134 65 70 75 80 85 90 95 100 105 DELTA VOLTAGE (mV) Figure 100. Junction Temperature vs. ΔV (mV) 110 15550-270 VREF 0.75 15550-269 VREF PIN CONTROL SPI REGISTER (0x18A6) 0.80 TEMPERATURE DIODE VOLTAGE (V) The temperature diode voltages can be exported to the VREF pin using the SPI. Use Register 0x18E6 to enable or disable diodes. It is important to note that other voltages may be exported to the VREF pin at the same time, which may result in undefined behavior. To ensure a proper readout, switch off all other voltage exporting circuits as described in this section. Figure 98 shows the block diagram of the controls that are required to enable the diode voltage readout. Data Sheet AD9689 ADC OVERRANGE AND FAST DETECT The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 101. In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overrange bit in the JESD204B outputs provides information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, the latency of this function is of major concern. Highly pipelined converters can have significant latency. The AD9689 contains fast detect circuitry for individual channels to monitor the threshold and assert the FD_A and FD_B pins. The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located at Register 0x0247 and Register 0x0248. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 28 clock cycles (maximum). The approximate upper threshold magnitude is defined by Upper Threshold Magnitude (dBFS) = 20log(Threshold Magnitude/213) The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, located at Register 0x0249 and Register 0x024A. The fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency, but is accurate in terms of converter resolution. The lower threshold magnitude is defined by ADC OVERRANGE The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange indicator can be embedded within the JESD204B link as a control bit (when CSB > 0). The latency of this overrange indicator matches the sample latency. The AD9689 also records any overrange condition in any of the eight virtual converters. For more information on the virtual converters, refer to Figure 109. The overrange status of each virtual converter is registered as a sticky bit in Register 0x0563. The contents of Register 0x0563 can be cleared using Register 0x0562, by toggling the bits corresponding to the virtual converter to set and reset position. Lower Threshold Magnitude (dBFS) = 20log(Threshold Magnitude/213) For example, to set an upper threshold of −6 dBFS, write 0xFFF to Register 0x0247 and Register 0x0248. To set a lower threshold of −10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A. FAST THRESHOLD DETECTION (FD_A AND FD_B) The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located at Register 0x024B and Register 0x024C. See Register 0x0040 and Register 0x0245 to Register 0x024C in the Memory Map section (see Table 46, Table 47, and Table 49) for more details. The FD_A or FD_B pin is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit is only cleared when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. This feature provides hysteresis and prevents the FD bit from excessively toggling. UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD DWELL TIME FD_A OR FD_B Figure 101. Threshold Settings for the FD_A and FD_B Signals Rev. A | Page 37 of 134 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 15550-048 MIDSCALE LOWER THRESHOLD AD9689 Data Sheet ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING Table 11 shows the number of virtual converters required and the transport layer mapping when channel swapping is disabled. Figure 102 shows the virtual converters and their relationship to the DDC outputs when complex outputs are used. The AD9689 contains a configurable signal path that allows different features to be enabled for different applications. These features are controlled using the chip mode register, Register 0x0200. The chip operating mode is controlled by Bits[3:0] in this register, and the chip Q ignore is controlled by Bit 5. Each DDC channel outputs either two sample streams (I/Q) for the complex data components (real + imaginary), or one sample stream for real (I) data. The AD9689 can be configured to use up to eight virtual converters, depending on the DDC configuration. The AD9689 contains the following modes: • • Full bandwidth mode: two 14-bit ADC cores running at full sample rate. DDC mode: up to four DDC channels. The I/Q samples are always mapped in pairs with the I samples mapped to the first virtual converter and the Q samples mapped to the second virtual converter. With this transport layer mapping, the number of virtual converters are the same whether a single real converter is used along with a digital downconverter block producing I/Q outputs, or whether an analog downconversion is used with two real converters producing I/Q outputs. After the chip application mode is selected, the output decimation ratio is set using the chip decimation ratio in Register 0x0201, Bits[3:0]. The output sample rate = ADC sample rate/the chip decimation ratio. To support the different application layer modes, the AD9689 treats each sample stream (real, I, or Q) as originating from separate virtual converters. Figure 103 shows a block diagram of the two scenarios described for I/Q transport layer mapping. Table 11. Virtual Converter Mapping Number of Virtual Converters Supported 1 to 2 1 2 2 4 4 8 Chip Application Mode (Reg. 0x0200, Bits[3:0]) Full bandwidth mode (0x0) One DDC mode (0x1) One DDC mode (0x1) Two DDC mode (0x2) Two DDC mode (0x2) Four DDC mode (0x3) Four DDC mode (0x3) Virtual Converter Mapping Chip Q Ignore (Reg. 0x0200, Bit 5) Real or complex (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) 0 ADC A samples DDC0 I samples DDC0 I samples DDC0 I samples DDC0 I samples DDC0 I samples DDC0 I samples 1 ADC B samples Unused 2 Unused 3 Unused 4 Unused 5 Unused 6 Unused 7 Unused Unused Unused Unused Unused Unused Unused DDC0 Q samples DDC1 I samples DDC0 Q samples DDC1 I samples DDC0 Q samples Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused DDC1 I samples DDC2 I samples DDC1 I samples DDC1 Q samples DDC3 I samples DDC1 Q samples Unused Unused Unused Unused Unused Unused Unused Unused DDC2 I samples DDC2 Q samples DDC3 I samples DDC3 Q samples Rev. A | Page 38 of 134 Data Sheet AD9689 REAL/I REAL/Q REAL/I I/Q CROSSBAR MUX REAL/Q REAL/I REAL/Q REAL/Q ADC B SAMPLING AT fS REAL/I REAL/Q I DDC 0 Q I I OUTPUT INTERFACE REAL/I CONVERTER 4 Q CONVERTER 5 I Q DDC 3 Q REAL/I CONVERTER 2 Q CONVERTER 3 I Q DDC 2 Q I Q DDC 1 Q REAL/I CONVERTER 0 Q CONVERTER 1 I REAL/I CONVERTER 6 Q CONVERTER 7 I Q 15550-066 ADC A SAMPLING AT fS Figure 102. DDCs and Virtual Converter Mapping DIGITAL DOWNCONVERSION M=2 I CONVERTER 0 REAL ADC REAL DIGITAL DOWN CONVERSION JESD204B Tx L LANES JESD204B Tx L LANES Q CONVERTER 1 I/Q ANALOG MIXING M=2 I REAL Σ ADC I CONVERTER 0 90° PHASE Q ADC Q CONVERTER 1 Figure 103. I/Q Transport Layer Mapping Rev. A | Page 39 of 134 15550-065 REAL/I AD9689 Data Sheet PROGRAMMABLE FIR FILTERS SUPPORTED MODES • The AD9689 supports the following modes of operation (the asterisk symbol (*) denotes convolution): • • PROGRAMMABLE FILTER (PFILT) I (REAL) ADC A CORE DINI [n] 48-TAP FIR FILTER xyI [n] DOUTI [n] I′ (REAL) SIGNAL PROCESSING BLOCKS Q (IMAG) ADC B CORE DINQ [n] 48-TAP FIR FILTER xyQ [n] DOUTQ [n] JESD204B INTERFACE Q′ (IMAG) 15550-274 • Real 48-tap filter for each I/Q channel (see Figure 104) • DOUT_I[n] = DIN_I[n] * XY_I[n] • DOUT_Q[n] = DIN_Q[n] * XY_Q[n] Real 96-tap filter for on either I or Q channel (see Figure 105) • DOUT_I[n] = DIN_I[n] * XY_I_XY_Q[n] • DOUT_Q[n] = DIN_Q[n] Real set of two cascaded 24-tap filters for each I/Q channel (see Figure 106) • DOUT_I[n] = DIN_I[n] * X_I[n] * Y_I[n] • DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n] Figure 104. Real 48-Tap Filter Configuration PROGRAMMABLE FILTER (PFILT) I (REAL) ADC A CORE DINI [n] 96-TAP FIR FILTER xIyIxQyQ [n] DOUTI [n] I′ (REAL) SIGNAL PROCESSING BLOCKS Q (IMAG) ADC B CORE DINQ [n] DOUTQ [n] Q′ (IMAG) Figure 105. Real 96-Tap Filter Configuration Rev. A | Page 40 of 134 JESD204B INTERFACE 15550-275 • Half complex filter using two real 48-tap filters for the I/Q channels (see Figure 107) • DOUT_I[n] = DIN_I[n] • DOUT_Q[n] = DIN_Q[n] * XY_Q[n] + DIN_I[n] * XY_I[n] Full complex filter using four real 24-tap filters for the I/Q channels (see Figure 108) • DOUT_I[n] = DIN_I[n] * X_I[n] + DIN_Q[n] * Y_Q[n] • DOUT_Q[n] = DIN_Q[n] * X_Q[n] + DIN_I[n] * Y_I[n] Data Sheet AD9689 PROGRAMMABLE FILTER (PFILT) ADC A CORE DINI [n] 24-TAP FIR FILTER xI [n] DOUTI [n] 24-TAP FIR FILTER yI [n] SIGNAL PROCESSING BLOCKS 24-TAP FIR FILTER yQ [n] Q (IMAG) ADC B CORE DINQ [n] I′ (REAL) 24-TAP FIR FILTER xQ [n] DOUTQ [n] JESD204B INTERFACE Q′ (IMAG) 15550-276 I (REAL) Figure 106. Real, Two Cascaded, 24-Tap Filter Configuration PROGRAMMABLE FILTER (PFILT) ADC A CORE DINI [n] DOUTI [n] 0 TO 47 DELAY TAPS 48-TAP FIR FILTER xyI [n] Q (IMAG) ADC B CORE DINQ [n] I′ (REAL) SIGNAL PROCESSING BLOCKS JESD204B INTERFACE + 48-TAP FIR FILTER xyQ [n] DOUTQ [n] + Q′ (IMAG) 15550-277 I (REAL) Figure 107. 48-Tap Half Complex Filter Configuration PROGRAMMABLE FILTER (PFILT) ADC A CORE DINI [n] 24-TAP FIR FILTER xI [n] DOUTI [n] + 24-TAP FIR FILTER yI [n] SIGNAL PROCESSING BLOCKS 24-TAP FIR FILTER yQ [n] Q (IMAG) ADC B CORE DINQ [n] 24-TAP FIR FILTER xQ [n] I′ (REAL) + JESD204B INTERFACE + + DOUTQ [n] Q′ (IMAG) Figure 108. 24-Tap Full Complex Filter Configuration. Rev. A | Page 41 of 134 15550-278 I (REAL) AD9689 Data Sheet PROGRAMMING INSTRUCTIONS Table 12. Register 0x0DF8 Definition Use the following procedure to set up the programmable FIR filter: Bit(s) [7:3] [2:0] 1. 2. 3. 4. 5. 6. 7. Enable the sample clock to the device. Configure the mode registers as follows: a. Set the device index to Channel A (I path) (Register 0x0008 = 0x01). b. Set the I path mode (I mode) and gain in Register 0x0DF8 and Register 0x0DF9 (see Table 12 and Table 13). c. Set the device index to Channel B (Q path) (Register 0x0008 = 0x02). d. Set the Q path mode (Q mode) and gain in Register 0x0DF8 and Register 0x0DF9. Wait at least 5 μs to allow the programmable filter to power up. Program the I path coefficients to the internal shadow registers as follows: a. Set the device index to Channel A (I path) (Register 0x0008 = 0x01). b. Program the XI coefficients in Register 0x0E00 to Register 0x0E7F (see Table 14 and Table 15). c. Program the YI coefficients in Register 0x0F00 to Register 0x0E7F (see Table 14 and Table 15). d. Program the tapped delay in Register 0x0F30 (note that this step is optional). Program the Q path coefficients to the internal shadow registers as follows: a. Set the device index to Channel B (Q path) (Register 0x0008 = 0x02). b. Set the Q path mode and gain in Register 0x0DF8 and Register 0x0DF9 (see Table 12 and Table 13). c. Program the XQ coefficients in Register 0x0E00 to Register 0x0E7F (see Table 14 and Table 15). d. Program the YQ coefficients in Register 0x0F00 to Register 0x0E7F (see Table 14 and Table 15). e. Program the tapped delay in Register 0x0F30 (note that this step is optional). Set the chip transfer bit using either of the following methods (note that setting the chip transfer bit applies the programmed shadow coefficients to the filter): a. Via the register map by setting the chip transfer bit (Register 0x000F = 0x01). b. Via a GPIO pin, as follows: i. Configure one of the GPIO pins as the chip transfer bit in Register 0x0040 to Register 0x0042. ii. Toggle the GPIO pin to initiate the chip transfer (the rising edge is triggered). When the I or Q path mode register changes in Register 0x0DF8, all coefficients must be reprogrammed. Description Reserved Filter mode (I mode or Q mode) 000: filters bypassed 001: real 24-tap filter (X only) 010: real 48-tap filter (X and Y together) 100: real set of two cascaded 24-tap filters (X then Y cascaded) 101: full complex filter using four real 24-tap filters for Channel A or Channel B (opposite channel must also be set to 101) 110: half complex filter using two real 48-tap filters + 48-tap delay line (X and Y together) (opposite channel must also be set to 010) 111: real 96-tap filter (XI, YI, XQ, and YQ together) (opposite channel must be set to 000) Table 13. Register 0x0DF9 Definition Bit(s) 7 [6:4] 3 [2:0] Description Reserved Y filter gain 110: −12 dB loss 111: −6 dB loss 000: 0 dB gain 001: 6 dB gain 010: 12 dB gain Reserved X filter gain 110: −12 dB loss 111: −6 dB loss 000: 0 dB gain 001: 6 dB gain 010: 12 dB gain Table 14 and Table 15 show the coefficient tables in Register 0x0E00 to Register 0x0F30. Note that all coefficients are in Q1.15 format (sign bit plus 15 fractional bits). Rev. A | Page 42 of 134 Data Sheet AD9689 Table 14. I Coefficient Table (Device Selection = 0x1) 1 Addr. 0x0E00 0x0E01 0x0E02 0x0E03 … 0x0E2E 0x0E2F 0x0F00 0x0F01 0x0F02 0x0F03 … 0x0F2E 0x0F2F 0x0F30 Single 24-Tap Filter (I Mode [2:0] = 0x1) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] Unused Unused Unused Unused … Unused Unused Unused Single 48-Tap Filter (I Mode [2:0] = 0x2) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C24 [7:0] YI C24 [15:8] YI C25 [7:0] YI C25 [15:8] … YI C47 [7:0] YI C47 [15:0] Unused Full Complex 24-Tap Filters (I Mode [2:0] = 0x5 and Q Mode [2:0] = 0x5) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C0 [7:0] YI C0 [15:8] YI C1 [7:0] YI C1 [15:8] … YI C23 [7:0] YI C23 [15:0] Unused Two Cascaded 24-Tap Filters (I Mode [2:0] = 0x4) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C0 [7:0] YI C0 [15:8] YI C1 [7:0] YI C1 [15:8] … YI C23 [7:0] YI C23 [15:0] Unused Half Complex 48-Tap Filters (I Mode [2:0] = 0x6 and Q Mode [2:0] = 0x2) 2 XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C24 [7:0] YI C24 [15:8] YI C25 [7:0] YI C25 [15:8] … YI C47 [7:0] YI C47 [15:0] I path tapped delay 0: 0 tapped delay (matches C0 in the filter) 1: 1 tapped delays … 47: 47 tapped delays I Path 96-Tap Filter (I Mode[2:0] = 0x7 and Q Mode [2:0] = 0x0) 3 XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C24 [7:0] YI C24 [15:8] YI C25 [7:0] YI C25 [15:8] … YI C47 [7:0] YI C47 [15:0] Unused Q Path 96-Tap Filter (I Mode [2:0] = 0x0 and Q Mode [2:0] = 0x7)3 XQ C48 [7:0] XQ C48 [15:8] XQ C49 [7:0] XQ C49 [15:8] … XQ C71 [7:0] XQ C71 [15:0] YQ C72 [7:0] YQ C72 [15:8] YQ C73 [7:0] YQ C73 [15:8] … YQ C95 [7:0] YQ C95 [15:0] Unused I Path 96-Tap Filter (Q Mode [2:0] = 0x0 and I Mode [2:0] = 0x7) 3 XI C48 [7:0] XI C48 [15:8] XI C49 [7:0] XI C49 [15:8] … XI C71 [7:0] XI C71 [15:0] YI C72 [7:0] YI C72 [15:8] YI C73 [7:0] YI C73 [15:8] … YI C95 [7:0] YI C95 [15:0] Unused Q Path 96-Tap Filter (Q Mode [2:0] = 0x7 and I Mode [2:0] = 0x0)3 XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C24 [7:0] YQ C24 [15:8] YQ C25 [7:0] YQ C25 [15:8] … YQ C47 [7:0] YQ C47 [15:0] Unused XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n. When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode. 3 When using the I path in 96-tap filter mode, the Q path must be in bypass mode. 1 2 Table 15. Q Coefficient Table (Device Selection = 0x2) 1 Addr. 0x0E00 0x0E01 0x0E02 0x0E03 … 0x0E2E 0x0E2F 0x0F00 0x0F01 0x0F02 0x0F03 … 0x0F2E 0x0F2F 0x0F30 1 2 3 Single 24-Tap Filter (Q Mode [2:0] = 0x1) XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] Unused Unused Unused Unused … Unused Unused Unused Single 48-Tap Filter (Q Mode [2:0] = 0x2) XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C24 [7:0] YQ C24 [15:8] YQ C25 [7:0] YQ C25 [15:8] … YQ C47 [7:0] YQ C47 [15:0] Unused Two Cascaded 24-Tap Filters (Q Mode [2:0] = 0x4) XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C0 [7:0] YQ C0 [15:8] YQ C1 [7:0] YQ C1 [15:8] … YQ C23 [7:0] YQ C23 [15:0] Unused Full Complex 24-Tap Filters (Q Mode [2:0] = 0x5 and I Mode [2:0] = 0x5) XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C0 [7:0] YQ C0 [15:8] YQ C1 [7:0] YQ C1 [15:8] … YQ C23 [7:0] YQ C23 [15:0] Unused Half Complex 48-Tap Filters (Q Mode [2:0] = 0x6 and I Mode [2:0] = 0x2) 2 XQ C0 [7:0] XQ C0 [15:8] XQ C1 [7:0] XQ C1 [15:8] … XQ C23 [7:0] XQ C23 [15:0] YQ C24 [7:0] YQ C24 [15:8] YQ C25 [7:0] YQ C25 [15:8] … YQ C47 [7:0] YQ C47 [15:0] Q path tapped delay 0: 0 tapped delay (matches C0 in the filter) 1: 1 tapped delays … 47: 47 tapped delays XQ Cn means Q Path X Coefficient n. YQ Cn means Q Path Y Coefficient n. When using the I path in half complex, 48-tap filter mode, the Q path must be in single 48-tap filter mode. When using the I path in 96-tap filter mode, the Q path must be in bypass mode. Rev. A | Page 43 of 134 AD9689 Data Sheet DIGITAL DOWNCONVERTER (DDC) The AD9689 includes four digital downconverters (DDC0 to DDC3) that provide filtering and reduce the output data rate. This digital processing section includes an NCO, multiple decimating FIR filters, a gain stage, and a complex to real conversion stage. Each of these processing blocks has control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverter can be configured to output either real data or complex output data. DDC GENERAL DESCRIPTION The DDCs output a 16-bit stream. To enable this operation, the converter number of bits, N, is set to a default value of 16, even though the analog core only outputs 14 bits. In full bandwidth operation, the ADC outputs are the 14-bit word followed by two zeros, unless the tail bits are enabled. • • • • DDC I/Q INPUT SELECTION The AD9689 has two ADC channels and four DDC channels. Each DDC channel has two input ports that can be paired to support both real and complex inputs through the I/Q crossbar mux. For real signals, both DDC input ports must select the same ADC channel (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel A). For complex signals, each DDC input port must select different ADC channels (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel B). The inputs to each DDC are controlled by the DDC input selection registers (Register 0x0311, Register 0x0331, Register 0x0351, and Register 0x0371). See Table 48 and Table 50 for information on how to configure the DDCs. DDC I/Q OUTPUT SELECTION Each DDC channel has two output ports that can be paired to support both real and complex outputs. For real output signals, only the DDC Output Port I is used (the DDC Output Port Q is invalid). For complex I/Q output signals, both DDC Output Port I and DDC Output Port Q are used. The I/Q outputs to each DDC channel are controlled by the DDCx complex to real enable bit, Bit 3, in the DDCx control registers (Register 0x0310, Register 0x0330, Register 0x0350, and Register 0x0370). The chip Q ignore bit in the chip mode register (Register 0x0200, Bit 5) controls the chip output muxing of all the DDC channels. When all DDC channels use real outputs, set this bit high to ignore all DDC Q output ports. When any of the DDC channels are set to use complex I/Q outputs, the user must clear this bit to use both DDC Output Port I and DDC Output Port Q. For more information, see Figure 126. The four DDC blocks extract a portion of the full digital spectrum captured by the ADC(s). They are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. Each DDC block contains the following signal processing stages: Frequency translation stage (optional) Filtering stage Gain stage (optional) Complex to real conversion stage (optional) DDC Frequency Translation Stage (Optional) This stage consists of a phase coherent NCO and quadrature mixers that can be used for frequency translation of both real or complex input signals. The phase coherent NCO allows an infinite number of frequency hops that are all referenced back to a single synchronization event. It also includes 16 shadow registers for fast switching applications. This stage shifts a portion of the available digital spectrum down to baseband. DDC Filtering Stage After shifting down to baseband, this stage decimates the frequency spectrum using multiple low-pass finite impulse response (FIR) filters for rate conversion. The decimation process lowers the output data rate, which in turn reduces the output interface rate. DDC Gain Stage (Optional) Because of losses associated with mixing a real input signal down to baseband, this stage compensates by adding an additional 0 dB or 6 dB of gain. DDC Complex to Real Conversion Stage (Optional) When real outputs are necessary, this stage converts the complex outputs back to real by performing an fS/4 mixing operation plus a filter to remove the complex component of the signal. Figure 109 shows the detailed block diagram of the DDCs implemented in the AD9689. Figure 110 shows an example usage of one of the four DDC channels with a real input signal and four half-band filters (HB4 + HB3 + HB2 + HB1) used. It shows both complex (decimate by 16) and real (decimate by 8) output options. Rev. A | Page 44 of 134 Data Sheet AD9689 REAL/I I REAL/I Q REAL/I I DECIMATION FILTERS REAL/I CONVERTER 4 L JESD204B LANES AT UP TO 16Gbps Q CONVERTER 5 DECIMATION FILTERS Q SYSREF REAL/I CONVERTER 6 Q CONVERTER 7 SYSREF DCM = DECIMATION NCO CHANNEL SELECTION 15550-053 NCO CHANNEL SELECTION CIRCUITS Q CONVERTER 3 DDC 3 REAL/I GPIO PINS DECIMATION FILTERS REAL/I CONVERTER 2 DDC 2 NCO + MIXER (OPTIONAL) REGISTER MAP CONTROLS Q CONVERTER 1 JESD204B TRANSMIT INTERFACE Q ADC B SAMPLING AT fS SYNCHRONIZATION CONTROL CIRCUITS COMPLEX TO REAL CONVERSION (OPTIONAL) I/Q CROSSBAR MUX REAL/I NCO + MIXER (OPTIONAL) SYSREF± PIN REAL/I CONVERTER 0 DDC 1 NCO + MIXER (OPTIONAL) REAL/Q COMPLEX TO REAL CONVERSION (OPTIONAL) I COMPLEX TO REAL CONVERSION (OPTIONAL) REAL/I ADC A SAMPLING AT fS REAL/I COMPLEX TO REAL CONVERSION (OPTIONAL) Q GAIN = 0 OR +6dB REAL/I DECIMATION FILTERS GAIN = 0 OR +6dB NCO + MIXER (OPTIONAL) GAIN = 0 OR +6dB I GAIN = 0 OR +6dB DDC 0 REAL/I Figure 109. DDC Detailed Block Diagram Rev. A | Page 45 of 134 AD9689 Data Sheet ADC –fS/2 –fS/3 ADC SAMPLING AT fS REAL REAL INPUT—SAMPLED AT fS BANDWIDTH OF INTEREST IMAGE –fS/4 REAL BANDWIDTH OF INTEREST –fS/32 fS/32 DC –fS/16 fS/16 –fS/8 fS/8 fS/2 fS/3 fS/4 FREQUENCY TRANSLATION STAGE (OPTIONAL) I DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND ((fS/3)/fS × 248 ) = +9.382513 (0x5555_5555_5555) REAL 48-BIT NCO NCO TUNES CENTER OF BANDWIDTH OF INTEREST TO BASEBAND cos(ωt) 90° 0° –sin(ωt) Q DIGITAL FILTER RESPONSE –fS/3 –fS/4 –fS/32 fS/32 DC fS/16 –fS/16 –fS/8 FILTERING STAGE HB4 FIR 4 DIGITAL HALF-BAND FILTERS (HB4 + HB3 + HB2 + HB1) I HALFBAND FILTER Q HALFBAND FILTER HB3 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER 2 2 HALFBAND FILTER fS/4 fS/3 HALFBAND FILTER 2 HB2 FIR I HB1 FIR HALFBAND FILTER 2 Q 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS 0dB OR +6dB GAIN I GAIN STAGE (OPTIONAL) Q 0dB OR 6dB GAIN –fS/32 fS/32 DC –fS/16 fS/16 –fS/8 COMPLEX (I/Q) OUTPUTS DECIMATE BY 16 GAIN STAGE (OPTIONAL) DIGITAL FILTER RESPONSE COMPLEX TO REAL CONVERSION STAGE (OPTIONAL) fS/2 HB1 FIR HB2 FIR HALFBAND FILTER HB3 FIR HB4 FIR fS/8 fS/8 fS/4 MIXING + COMPLEX FILTER TO REMOVE Q 2 +6dB 2 +6dB I Q –fS/32 fS/32 DC –fS/16 fS/16 DOWNSAMPLE BY 2 I REAL (I) OUTPUTS +6dB I DECIMATE BY 8 Q +6dB Q COMPLEX REAL/I TO REAL +6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS –fS/8 –fS/32 fS/32 DC –fS/16 fS/16 fS/8 Figure 110. DDC Theory of Operation Example (Real Input) Rev. A | Page 46 of 134 15550-054 –fS/2 BANDWIDTH OF INTEREST IMAGE (–6dB LOSS DUE TO NCO + MIXER) BANDWIDTH OF INTEREST (–6dB LOSS DUE TO NCO + MIXER) Data Sheet AD9689 DDC FREQUENCY TRANSLATION Variable IF Mode DDC Frequency Translation General Description In variable IF mode, the NCO and mixers are enabled. NCO output frequency can be used to digitally tune the IF frequency. Frequency translation is accomplished by using a 48-bit complex NCO with a digital quadrature mixer. This stage translates either a real or complex input signal from an IF to a baseband complex digital output (carrier frequency = 0 Hz). 0 Hz IF (ZIF) Mode In ZIF mode, the mixers are bypassed, and the NCO is disabled. fS/4 Hz IF Mode The frequency translation stage of each DDC can be controlled individually and supports four different IF modes using Bits[5:4] of the DDCx control registers (Register 0x0310, Register 0x0330, Register 0x0350, and Register 0x0370). These IF modes are Test Mode In test mode, input samples are forced to 0.999 to positive full scale. The NCO is enabled. This test mode allows the NCOs to directly drive the decimation filters. Variable IF mode 0 Hz IF or zero IF (ZIF) mode fS/4 Hz IF mode Test mode Figure 111 and Figure 112 show examples of the frequency translation stage for both real and complex inputs, respectively. NCO FREQUENCY TUNING WORD (FTW) SELECTION 48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 248 I ADC + DIGITAL MIXER + NCO REAL INPUT—SAMPLED AT fS REAL ADC SAMPLING AT fS REAL 48-BIT NCO cos(ωt) 90° 0° COMPLEX –sin(ωt) Q BANDWIDTH OF INTEREST BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 –fS/8 –fS/32 fS/32 DC fS/16 –fS/16 fS/8 fS/4 fS/3 fS/2 –6dB LOSS DUE TO NCO + MIXER 48-BIT NCO FTW = ROUND (( fS/3)/fS × 248) = +9.382513 (0x5555_5555_5555) POSITIVE FTW VALUES –fS/32 DC fS/32 48-BIT NCO FTW = ROUND (( fS/3)/fS × 248 ) = –9.382513 (0xAAAA_AAAA_AAAA) NEGATIVE FTW VALUES –fS/32 DC fS/32 Figure 111. DDC NCO Frequency Tuning Word Selection—Real Inputs Rev. A | Page 47 of 134 15550-055 • • • • In fS/4 Hz IF mode, the mixers and the NCO are enabled in downmixing by fS/4 mode to save power. AD9689 Data Sheet NCO FREQUENCY TUNING WORD (FTW) SELECTION 48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 248 QUADRATURE ANALOG MIXER + 2 ADCs + QUADRATURE DIGITAL MIXER + NCO REAL COMPLEX INPUT—SAMPLED AT fS QUADRATURE MIXER ADC SAMPLING AT fS + I I I 90° PHASE Q Q 48-BIT NCO 90° 0° Q Q ADC SAMPLING AT fS Q Q I I – –sin(ωt) I I + + COMPLEX Q BANDWIDTH OF INTEREST IMAGE DUE TO ANALOG I/Q MISMATCH –fS/3 –fS/4 –fS/8 fS/32 –fS/32 –fS/16 fS/16 DC fS/8 fS/4 fS/3 fS/2 48-BIT NCO FTW = ROUND ((fS/3)/fS × 248) = +9.382513 (0x5555_5555_5555) POSITIVE FTW VALUES –fS/32 fS/32 DC Figure 112. DDC NCO Frequency Tuning Word Selection—Complex Inputs Rev. A | Page 48 of 134 15550-056 –fS/2 Data Sheet AD9689 DDC NCO Description DDC NCO Coherent Mode Each DDC contains one NCO. Each NCO enables the frequency translation process by creating a complex exponential frequency (e-jωct), which can be mixed with the input spectrum to translate the desired frequency band of interest to dc, where it can be filtered by the subsequent low-pass filter blocks to prevent aliasing. DDC NCO coherent mode allows an infinite number of frequency hops where the phase is referenced to a single synchronization event at Time 0. This mode is useful when phase coherency must be maintained when switching between different frequency bands. In this mode, the user can switch to any tuning frequency without the need to reset the NCO. Although only one FTW is required, the NCO contains 16 shadow registers for fast switching applications. Selection of the shadow registers is controlled by the CMOS GPIO pins or through the register map of the SPI. In this mode, the NCO can be set up by providing the following: When placed in variable IF mode, the NCO supports two additional modes. DDC NCO Programmable Modulus Mode DDC NCO programmable modulus mode supports >48-bit frequency tuning accuracy for applications that require exact rational (M/N) frequency synthesis at a single carrier frequency. In this mode, the NCO is set up by providing the following: 48-bit frequency tuning word (FTW) 48-bit Modulus A word (MAW) 48-bit Modulus B word (MBW) 48-bit phase offset word (POW) Figure 113 shows a block diagram of one NCO and its connection to the rest of the design. The coherent phase accumulator block contains the logic that allows an infinite number of frequency hops. The gray lines in Figure 113 represent SPI control lines. NCO NCO CHANNEL SELECTION 0 48-BIT FTW/POW 0 FTW/POW 1 48-BIT FTW/POW 1 FTW/POW WRITE INDEX 15 48-BIT FTW/POW 15 REGISTER MAP SYNCHRONIZATION CONTROL CIRCUITS I/O CROSSBAR MUX MODULUS ERROR 48-BIT MAW/MBW COHERENT PHASE ACCUMULATOR BLOCK COS/SIN GENERATOR SYSREF I I Q Q DIGITAL QUADRATURE MIXER FTW = FREQUENCY TUNING WORD POW = PHASE OFFSET WORD MAW = MODULUS A WORD (NUMERATOR) MBW = MODULUS B WORD (DENOMINATOR) Figure 113. NCO + Mixer Block Diagram Rev. A | Page 49 of 134 DECIMATION FILTERS 15550-283 MAW/MBW cos(x) NCO CHANNEL SELECTION CIRCUITS Up to sixteen 48-bit FTWs. Up to sixteen 48-bit POWs. The 48-bit MAW must be set to zero in coherent mode. –sin(x) • • • • • • • AD9689 Data Sheet NCO FTW/POW/MAW/MAB Description The NCO frequency value is determined by the following settings: floor(x) is defined as the largest integer less than or equal to x. For example, floor(3.6) = 3. • • • Note that Equation 1 to Equation 4 apply to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). 48-bit twos complement number entered in the FTW. 48-bit unsigned number entered in the MAW. 48-bit unsigned number entered in the MBW. M and N are integers reduced to their lowest terms. MAW and MBW are integers reduced to their lowest terms. When MAW is set to zero, the programmable modulus logic is automatically disabled. Frequencies between −fS/2 and +fS/2 (fS/2 excluded) are represented using the following values: • • • FTW = 0x8000 0000 0000 and MAW = 0x0000 0000 0000 represents a frequency of −fS/2. FTW = 0x0000 0000 0000 and MAW = 0x0000 0000 0000 represents dc (frequency is 0 Hz). FTW = 0x7FFF FFFF FFFF and MAW = 0x0000 0000 0000 represents a frequency of +fS/2. For example, if the ADC sampling frequency (fS) is 2600 MSPS and the carrier frequency (fC) is 1001.5 MHz, then mod(1001.5, 2600) 2600 In programmable modulus mode, the FTW, MAW, and MBW must satisfy the following four equations (for a detailed description of the programmable modulus feature, see the DDS architecture described in the AN-953 Application Note): mod( f c , f s ) M = = fs N FTW = floor(248 FTW + mod( f c , f s ) fs MAW MBW 2 48 ) MAW = mod(248 × 2003, 5200) = 0x0000 0000 0300 MBW = 0x0000 0000 1450 The actual carrier frequency (fC_ACTUAL) can be calculated based on the following equation: f C _ ACTUAL = MBW = N (4) where: fC is the desired carrier frequency. fS is the ADC sampling frequency. M is the integer representing the rational numerator of the frequency ratio. N is the integer representing the rational denominator of the frequency ratio. FTW is the 48-bit twos complement number representing the NCO FTW. MAW is the 48-bit unsigned number representing the NCO MAW (must be <247). MBW is the 48-bit unsigned number representing the NCO MBW. mod(x) is a remainder function. For example, mod(110,100) = 10 and for negative numbers, mod(−32,10)= −2. MAW × fS MBW 2 48 f C _ ACTUAL 0x629B F68C 3590 × = = 1001.5MHz (2) (3) FTW + For the previous example, the actual carrier frequency (fC_ACTUAL) is (1) MAW = mod(248 × M,N) M 2003 = N 5200 mod(1001.5, 2600) FTW = floor 248 2600 = 0x629B F68C 3590 NCO FTW/POW/MAW/MAB Programmable Modulus Mode For programmable modulus mode, the MAW must be set to a nonzero value (not equal to 0x0000 0000 0000). This mode is only needed when frequency accuracy of >48 bits is required. One example of a rational frequency synthesis requirement that requires >48 bits of accuracy is a carrier frequency of 1/3 the sample rate. When frequency accuracy of ≤48 bits is required, coherent mode must be used (see the NCO FTW/POW/MAW/ MAB Coherent Mode section). = 0x0000 0000 0300 0x0000 0000 1450 248 A 48-bit POW is available for each NCO to create a known phase relationship between multiple chips or individual DDC channels inside the chip. While in programmable modulus mode, the FTW and POW registers can be updated at any time while still maintaining deterministic phase results in the NCO. However, the following procedure must be followed to update the MAW and/or MBW registers to ensure proper operation of the NCO: 1. 2. Rev. A | Page 50 of 134 Write to the MAW and MBW registers for all the DDCs. Synchronize the NCOs either through the DDC soft reset bit accessible through the SPI or through the assertion of the SYSREF± pin (see the Memory Map section). Data Sheet AD9689 NCO FTW/POW/MAW/MAB Coherent Mode For the previous example, the actual carrier frequency (fC_ACTUAL) is For coherent mode, the NCO MAW must be set to zero (0x0000 0000 0000). In this mode, the NCO FTW can be calculated by the following equation: mod( f c , f s ) FTW = round 2 48 fs fC_ACTUAL = (5) where: FTW is the 48-bit twos complement number representing the NCO FTW. fC is the desired carrier frequency. fS is the ADC sampling frequency. mod(x) is a remainder function. For example mod(110,100) = 10 and for negative numbers, mod(−32,10) = −2. round(x) is a rounding function. For example round(3.6) = 4 and for negative numbers, round(−3.4)= −3. Note that Equation 5 applies to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). The MAW must be set to zero to use coherent mode. When MAW is zero, the programmable modulus logic is automatically disabled. For example, if the ADC sampling frequency (fS) is 2600 MSPS and the carrier frequency (fC) is 416.667 MHz, then mod(416.667,2600) NCO _ FTW = round 248 2600 = 0x2906 928F A997 416.667 × 2600 2 48 = 416.66699 MHz A 48-bit POW is available for each NCO to create a known phase relationship between multiple chips or individual DDC channels inside the chip. While in coherent mode, the FTW and POW registers can be updated at any time while still maintaining deterministic phase results in the NCO. NCO Channel Selection When configured in coherent mode, only one FTW is required in the NCO. In this mode, the user can switch to any tuning frequency without the need to reset the NCO by writing to the FTW directly. However, for fast switching applications, where either all FTWs are known beforehand or it is possible to queue up the next set of FTWs, the NCO contains 16 additional shadow registers (see Figure 113). These shadow registers are hereafter referred to as the NCO channels. Figure 114 shows a simplified block diagram of the NCO channel selection block. The gray lines in Figure 114 represent SPI control lines. Only one NCO channel is active at a time and NCO channel selection is controlled either by the CMOS GPIO pins or through the register map. Each NCO channel selector supports three different modes, as described in the following sections. The actual carrier frequency can be calculated based on the following equation: FTW × f S 2 48 NCO CHANNEL SELECTION IN GPIO CMOS PINS IN [3:0] GPIO SELECTION IN IN MUX REGISTER MAP [0] COUNTER INC NCO CHANNEL SELECTION NCO REGISTER MAP NCO CHANNEL SELECTION 0x0314, 0x0334, 0x0354, 0x0374 NCO CHANNEL MODE 15550-284 f C _ ACTUAL = Figure 114. NCO Channel Selection Block Rev. A | Page 51 of 134 AD9689 Data Sheet 2. GPIO Level Control Mode The GPIO pins determine the exact NCO channel selected. The following procedure must be followed to use GPIO level control for NCO channel selection: 2. 3. Configure one or more GPIO pins as NCO channel selection inputs. GPIO pins not configured as NCO channel selection are internally tied low. a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to 0x6 and Bits[3:0] in Register 0x0041 to 0x0. b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to 0x6 and Bits [7:4] in Register 0x0041 to 0x0. Configure the NCO channel selector in GPIO level control mode by setting Bits[7:4] in the NCO control registers (Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374) to 0x1 through 0x6, depending on the desired GPIO pin ordering. Select the desired NCO channel through the GPIO pins. GPIO Edge Control Mode A low to high transition on a single GPIO pin determines the exact NCO channel selected. The internal channel selection counter is reset by either SYSREF± or the DDC soft reset. The following procedure must be followed to use GPIO edge control for NCO channel selection: 1. Configure one or more GPIO pins as NCO channel selection inputs. a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to 0x6 and Bits[3:0] in Register 0x0041 to 0x0. b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to 0x6 and Bits[7:4] in Register 0x0041 to 0x0. f0 3. 4. Register Map Mode NCO channel selection is controlled directly through the register map. Figure 115 shows an example use case for coherent mode using three NCO channels. In this example, NCO Channel 0 is actively downconverting Bandwidth 0 (B0), while NCO Channel 1 and Channel 2 are in standby mode and are tuned to Bandwidth 1 and Bandwidth 2 (B1 and B2), respectively. The phase coherent NCO switching feature allows an infinite number of frequency hops that are all phase coherent. The initial phase of the NCO is established at time, t0, from SYSREF± synchronization. Switching the NCO FTW does not affect the phase. With this feature, only one FTW is required, but all 16 channels can be used to queue the next hop. After SYSREF± synchronization at startup, all NCOs across multiple chips are inherently synchronized. f1 f2 ACTIVE DDC DC B2 B1 B0 NCO CHANNEL 0 CARRIER FREQUENCY 0 (ACTIVE) NCO CHANNEL 1 CARRIER FREQUENCY 1 (STANDBY) NCO CHANNEL 2 CARRIER FREQUENCY 2 (STANDBY) Figure 115. NCO Coherent Mode with Three NCO Channels (B0 Selected) Rev. A | Page 52 of 134 fS/2 15550-285 1. Configure the NCO channel selector in GPIO edge control mode by setting Bits[7:4] in the NCO control registers (Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374) to 0x8 through 0xB, depending on the desired GPIO pin. Configure the wrap point for the NCO channel selection by setting Bits[3:0] in the NCO control registers (Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374). A value of 4 causes the channel selection to wrap at Channel 4 (0, 1, 2, 3, 4, 0, 1, 2, 3, 4, and so on). Transition the selected GPIO pin from low to high to increment the NCO channel selection. Data Sheet AD9689 Setting Up the Multichannel NCO Feature NCO Synchronization The first step to configure the multichannel NCO is to program the FTWs. The AD9689 memory map has an FTW index register for each DDC. This index determines which NCO channel receives the FTW from the register map. The following sequence describes the method for programming the FTWs: Each NCO contains a separate phase accumulator word (PAW). The initial reset value of each PAW is set to zero and incremented every clock cycle. The instantaneous phase of the NCO is calculated using the PAW, FTW, MAW, MBW, and POW. Due to this architecture, the FTW and POW registers can be updated at any time while still maintaining deterministic phase results in the PAW of the NCO. 1. 2. 3. Write the FTW index register with the desired DDC channel. Write the FTW with the desired value. This value is applied to the NCO channel index mentioned in Step 1. Repeat Step 1 and Step 2 for other NCO channels. After setting the FTWs, the user must then select an active NCO channel. This selection can be performed either through the SPI registers or through the external GPIO pins. The following sequence describes the method for selecting the active NCO channel using the SPI: 1. 2. Set the NCO channel select mode bits (Bits[7:4] in Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374) to 0x0 to enable SPI selection. Choose the active NCO channel using Bits[3:0] in Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374. Two methods can be used to synchronize multiple PAWs within the chip: • • The following sequence describes the method for selecting the active NCO channel using the GPIO CMOS pins: 1. 2. 3. Set the NCO channel select mode bits (Bits[7:4] in Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374) to a nonzero value to enable GPIO pin selection. Configure the GPIO pins as NCO channel selection inputs by writing to Register 0x0040, Register 0x0041, and Register 0x0042. NCO switching is performed by externally controlling the GPIO CMOS pins. Using the SPI. Use the DDC soft reset bit in the DDC synchronization control register (Register 0x0300, Bit 4) to reset all the PAWs in the chip. This reset is accomplished by setting the DDC soft reset bit high, and then setting this bit low. Note that this method can only be used to synchronize DDC channels within the same chip. Using the SYSREF± pin. When the SYSREF± pin is enabled in the SYSREF control registers (Register 0x0120 and Register 0x0121), and the DDC synchronization is enabled in the DDC synchronization control register (Register 0x0300, Bits[1:0]), any subsequent SYSREF± event resets all the PAWs in the chip. Note that this method can be used to synchronize DDC channels within the same chip or DDC channels within separate chips. NCO Multichip Synchronization In some applications, it is necessary to synchronize all the NCOs and local multiframe clocks (LMFCs) within multiple devices in a system. For applications requiring multiple NCO tuning frequencies in the system, a designer is likely to need to generate a single SYSREF pulse at all devices simultaneously. For many systems, generating or receiving a single-shot SYSREF pulse at all devices is challenging because of the following factors: • • Enabling or disabling the SYSREF pulse is often an asynchronous event. Not all clock generation chips support this feature. For these reasons, the AD9689 contains a synchronization triggering mechanism that allows the following: • • Rev. A | Page 53 of 134 Multichip synchronization of all NCOs and LMFCs at system startup. Multichip synchronization of all NCOs after applying new tuning frequencies during normal operation. AD9689 Data Sheet The synchronization triggering mechanism uses a master/slave arrangement, as shown in Figure 116. MNTO SNTI SNTI SNTI ADC DEVICE 0 (MASTER) ADC DEVICE 1 (SLAVE) ADC DEVICE 2 (SLAVE) ADC DEVICE 3 (SLAVE) 1 LINK, L LANES 1 LINK, L LANES Each device has an internal next synchronization trigger enable (NSTE) signal that controls whether the next SYSREF signal causes a synchronization event. Slave ADC devices must source their NSTE from an external slave next trigger input (SNTI) pin. Master devices can either use an external master next trigger output (MNTO) pin (default setting), or use an external SNTI pin. See Table 47 (Register 0x0041 and Register 0x0042) to configure the FD_x/GPIO pins for this operation. NCO Multichip Synchronization at Startup 1 LINK, L LANES Figure 117 shows a timing diagram along with the required sequence of events for NCO multichip synchronization using triggering and SYSREF at startup. Using this start-up sequence synchronizes all the NCOs and LMFCs in the system at once. 1 LINK, L LANES NCO Multichip Synchronization During Normal Operation See the Setting Up the Multichannel NCO Feature section. SYSREF± CLOCK GENERATION MNTO = MASTER NEXT TRIGGER OUTPUT (CMOS) SNTI = SLAVE NEXT TRIGGER INPUT (CMOS) 15550-286 DEVICE_CLOCK± Figure 116. System Using Master/Slave Synchronization Triggering CONFIGURE MASTER AND SLAVE DEVICES ENABLE TRIGGER IN MASTER DEVICES MNTO SET HIGH SNTI SET HIGH SYSTEM SYNCHRONIZATION ACHIEVED SYSREF IGNORED DEVICE CLOCK SYSREF MNTO BOARD PROPAGATION DELAY SNTI INPUT DELAY NSTE LMFCs DON’T CARE NCOs DON’T CARE LMFC SYNCHRONIZED NCO SYNCHRONIZED 15550-287 MNTO = MASTER NEXT TRIGGER OUTPUT (CMOS) SNTI = SLAVE NEXT TRIGGER INPUT (CMOS) NSTE = NEXT SYNCHRONIZATION TRIGGER ENABLE LMFC = LOCAL MULTIFRAME CLOCK NCO = NUMERICALLY CONTROLLED OSCILLATOR Figure 117. NCO Multichip Synchronization at Startup (Using Triggering and SYSREF) Rev. A | Page 54 of 134 Data Sheet AD9689 When mixing a complex input signal (where I and Q DDC inputs come from the different ADCs) down to baseband, the maximum value each I/Q sample is able to reach is 1.414 × full scale, after the sample passes through the complex mixer. To avoid overrange of the I/Q samples and to keep the data bit widths aligned with real mixing, −3.06 dB of loss is introduced in the mixer for complex signals. An additional −0.05 dB of loss is introduced by the NCO. The total loss of a complex input signal mixed down to baseband is −3.11 dB. DDC Mixer Description When not bypassed (Register 0x0200 ≠ 0x00), the digital quadrature mixer performs a similar operation to an analog quadrature mixer. It performs the downconversion of input signals (real or complex) by using the NCO frequency as a local oscillator. For real input signals, a real mixer operation (with two multipliers) is performed. For complex input signals, a complex mixer operation (with four multipliers and two adders) is performed. The selection of real or complex inputs can be controlled individually for each DDC block using Bit 7 of the DDC control registers (Register 0x0310, Register 0x0330, Register 0x0350, and Register 0x0370). The worst case spurious signal from the NCO is greater than 102 dBc SFDR for all output frequencies. DDC DECIMATION FILTERS DDC NCO + Mixer Loss and SFDR After the frequency translation stage, there are multiple decimation filter stages that reduce the output data rate. After the carrier of interest is tuned down to dc (carrier frequency = 0 Hz), these filters efficiently lower the sample rate, while providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. When mixing a real input signal down to baseband, −6 dB of loss is introduced in the signal due to filtering of the negative image. An additional −0.05 dB of loss is introduced by the NCO. The total loss of a real input signal mixed down to baseband is −6.05 dB. For this reason, it is recommended that the user compensate for this loss by enabling the 6 dB of gain in the gain stage of the DDC to recenter the dynamic range of the signal within the full scale of the output bits (see the DDC Gain Stage (Optional) section). Figure 118 shows a simplified block diagram of the decimation filter stage, and Table 16 describes the filter characteristics of the different finite impulse response (FIR) filter blocks. Table 17 shows the different filter configurations selectable by including different filters. In all cases, the DDC filtering stage provides 80% of the available output bandwidth, <±0.005 dB of pass-band ripple and >100 dB of stop band alias rejection. DCM = 3 DECIMATION FILTERS I DCM = 2 DCM = 3 TB2 FIR HB3 FIR DCM = 2 HB2 FIR FB2 FIR FB2 FIR I I Q Q I Q TB2 FIR DCM = 3 Q Q HB3 FIR HB4 FIR DCM = 2 DCM = 2 I HB1 FIR DCM = 5 Q I I DCM = 2 DCM = 5 I NCO AND MIXERS (OPTIONAL) HB4 FIR DCM = 2 HB2 FIR DCM = 2 COMPLEX TO REAL CONVERSION (OPTIONAL) I GAIN = 0dB OR +6dB I TB1 FIR HB1 FIR DCM = 2 Q Q Q TB1 FIR Q DCM = 3 15550-288 FIR = FINITE IMPULSE RESPONSE FILTER DCM = DECIMATION NOTES 1. TB1 IS ONLY SUPPORTED IN DDC0 AND DDC1 Figure 118. DDC Decimation Filter Block Diagram Rev. A | Page 55 of 134 AD9689 Data Sheet Table 16. DDC Decimation Filter Characteristics Filter Name HB4 HB3 HB2 HB1 TB2 TB1 1 FB2 1 Filter Type FIR low-pass FIR low-pass FIR low-pass FIR low-pass FIR low-pass FIR low-pass FIR low-pass Decimation Ratio 2 2 2 2 3 3 5 Pass Band (rad/sec) 0.1 x π/2 0.2 x π/2 0.4 x π/2 0.8 x π/2 0.4 x π/3 0.8 x π/3 0.4 x π/5 Stop Band (rad/sec) 1.9 x π/2 1.8 x π/2 1.6 x π/2 1.2 x π/2 1.6 x π/3 1.2 x π/3 1.6 x π/5 Pass-Band Ripple (dB) <±0.001 <±0.001 <±0.001 <±0.001 <±0.002 <±0.005 <±0.001 Stop Band Attenuation (dB) >100 >100 >100 >100 >100 >100 >100 TB1 is only supported in DDC0 and DDC1. Table 17. DDC Filter Configurations 1 ADC Sample Rate fS 1 2 3 DDC Filter Configuration HB1 TB1 3 HB2 + HB1 TB2 + HB1 HB3 + HB2 + HB1 FB2 + HB1 TB2 + HB2 + HB1 FB2 + TB13 HB4 + HB3 + HB2 + HB1 FB2 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 HB2 + FB2 + TB13 FB2 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 Real (I) Output Decimation Sample Ratio Rate 1 fS N/A N/A 2 fS/2 3 fS/3 4 fS/4 5 fS/5 6 fS/6 N/A N/A 8 fS/8 10 fS/10 12 fS/12 N/A N/A 20 fS/20 24 fS/24 Complex (I/Q) Outputs Decimation Ratio Sample Rate 2 fS/2 (I) + fS/2 (Q) 3 fS/3 (I) + fS/3 (Q) 4 fS/4 (I) + fS/4 (Q) 6 fS/6 (I) + fS/6 (Q) 8 fS/8 (I) + fS/8 (Q) 10 fS/10 (I) + fS/10 (Q) 12 fS/12 (I) + fS/12 (Q) 15 fS/15 (I) + fS/15 (Q) 16 fS/16 (I) + fS/16 (Q) 20 fS/20 (I) + fS/20 (Q) 24 fS/24 (I) + fS/24 (Q) 30 fS/30 (I) + fS/30 (Q) 40 fS/40 (I) + fS/40 (Q) 48 fS/48 (I) + fS/48 (Q) N/A means not applicable. Ideal SNR improvement due to oversampling + filtering = 10log(bandwidth/fS/2). TB1 is only supported in DDC0 and DDC1. Rev. A | Page 56 of 134 Alias Protected Bandwidth fS/2 × 80% fS/3 × 80% fS/4 × 80% fS/6 × 80% fS/8 × 80% fS/10 × 80% fS/12 × 80% fS/15 × 80% fS/16 × 80% fS/20 × 80% fS/24 × 80% fS/30 × 80% fS/40 × 80% fS/48 × 80% Ideal 2 SNR Improvement (dB) 1 2.7 4 5.7 7 8 8.8 9.7 10 11 11.8 12.7 14 14.8 Data Sheet AD9689 20 HB4 Filter Description 0 –20 MAGNITUDE (dB) The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB4 filter is only used when complex outputs (decimate by 16) or real outputs (decimate by 8) are enabled; otherwise, it is bypassed. Table 18 and Figure 119 show the coefficients and response of the HB4 filter. Table 18. HB4 Filter Coefficients Normalized Coefficient 0.006042 0 −0.049377 0 0.293335 0.5 Decimal Coefficient (15-Bit) 99 0 −809 0 4806 8192 –100 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED FREQUENCY (× Π RAD/s) Figure 120. HB3 Filter Response HB2 Filter Description The third decimate by 2, half-band, low-pass, FIR filter (HB2) uses a 19-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB2 filter is only used when complex or real outputs (decimate by 4, 8, or 16) are enabled; otherwise, it is bypassed. 0 –20 Table 20 and Figure 121 show the coefficients and response of the HB2 filter. –40 –60 Table 20. HB2 Filter Coefficients –100 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) 0.9 1.0 15550-289 –140 Figure 119. HB4 Filter Response HB3 Filter Description The second decimate by 2, half-band, low-pass, FIR filter (HB3) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB3 filter is only used when complex outputs (decimate by 8 or 16) or real outputs (decimate by 4 or 8) are enabled; otherwise, it is bypassed. Table 19 and Figure 120 show the coefficients and response of the HB3 filter. Table 19. HB3 Filter Coefficients HB3 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Normalized Coefficient 0.006638 0 −0.051056 0 0.294418 0.500000 Decimal Coefficient (17-Bit) 435 0 −3346 0 19295 32768 HB2 Coefficient Number C1, C19 C2, C18 C3, C17 C4, C16 C5, C15 C6, C14 C7, C13 C8, C12 C9, C11 C10 Normalized Coefficient 0.000671 0 −0.005325 0 0.022743 0 −0.074181 0 0.306091 0.5 Decimal Coefficient (18-Bit) 88 0 −698 0 2981 0 −9723 0 40120 65536 20 0 –20 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Figure 121. HB2 Filter Response Rev. A | Page 57 of 134 0.8 NORMALIZED FREQUENCY (× Π RAD/s) 0.9 1.0 15550-291 –80 MAGNITUDE (dB) MAGNITUDE (dB) –80 –120 20 –160 –60 15550-290 HB4 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 –40 AD9689 Data Sheet 20 HB1 Filter Description Decimal Coefficient (20-Bit) −10 0 38 0 −102 0 232 0 −467 0 862 0 −1489 0 2440 0 −3833 0 5831 0 −8679 0 12803 0 −19086 0 29814 0 −53421 0 166138 262144 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED FREQUENCY (× Π RAD/s) 15550-292 Normalized Coefficient −0.000019 0 0.000072 0 −0.000195 0 0.000443 0 −0.000891 0 0.001644 0 −0.002840 0 0.004654 0 −0.007311 0 0.011122 0 −0.016554 0 0.024420 0 −0.036404 0 0.056866 0 −0.101892 0 0.316883 0.5 –40 Figure 122. HB1 Filter Response TB2 Filter Description The TB2 filter uses a 26-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The TB2 filter is only used when decimation ratios of 6, 12, or 24 are required. Table 22 and Figure 123 show the coefficients and response of the TB2 filter. Table 22. TB2 Filter Coefficients TB2 Coefficient Number C1, C26 C2, C25 C3, C24 C4, C23 C5, C22 C6, C21 C7, C20 C8, C19 C9, C18 C10, C17 C11, C16 C12, C15 C13, C14 Normalized Coefficient −0.000191 −0.000793 −0.001137 0.000916 0.006290 0.009823 0.000916 −0.023483 −0.043152 −0.019318 0.071327 0.201172 0.297756 Decimal Coefficient (19-Bit) −50 −208 −298 240 1649 2575 240 −6156 −11312 −5064 18698 52736 78055 20 0 –20 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) Figure 123. TB2 Filter Response Rev. A | Page 58 of 134 0.9 1.0 15550-293 HB1 Coefficient Number C1, C63 C2, C62 C3, C61 C4, C60 C5, C59 C6, C58 C7, C57 C8, C56 C9, C55 C10, C54 C11, C53 C12, C52 C13, C51 C14, C50 C15, C49 C16, C48 C17, C47 C18, C46 C19, C45 C20, C44 C21, C43 C22, C42 C23, C41 C24, C40 C25, C39 C26, C38 C27, C37 C28, C36 C29, C35 C30, C34 C31, C33 C32 –20 MAGNITUDE (dB) Table 21. HB1 Filter Coefficients 0 MAGNITUDE (dB) The fourth and final decimate by 2, half-band, low-pass, FIR filter (HB1) uses a 63-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB1 filter is always enabled and cannot be bypassed. Table 21 and Figure 122 show the coefficients and response of the HB1 filter. Data Sheet AD9689 20 TB1 Filter Description TB1 Coefficient Number 1, 96 2, 75 3, 74 4, 73 5, 72 6, 71 7, 70 8, 69 9, 68 10, 67 11, 66 12, 65 13, 64 14, 63 15, 62 16, 61 17, 60 18, 59 19, 58 20, 57 21, 56 22, 55 23, 54 24, 53 25, 52 26, 51 27, 50 28, 49 29, 48 30, 47 31, 46 32, 45 33, 44 34, 43 35, 42 36, 41 37, 40 38, 39 Normalized Coefficient −0.000023 −0.000053 −0.000037 0.000090 0.000291 0.000366 0.000095 −0.000463 −0.000822 −0.000412 0.000739 0.001665 0.001132 −0.000981 −0.002961 −0.002438 0.001087 0.004833 0.004614 −0.000871 −0.007410 −0.008039 0.000053 0.010874 0.013313 0.001817 −0.015579 −0.021590 −0.005603 0.022451 0.035774 0.013541 −0.034655 −0.066549 −0.035213 0.071220 0.210777 0.309200 Decimal Coefficient (22-Bit) −96 −224 −156 379 1220 1534 398 −1940 −3448 −1729 3100 6984 4748 −4114 −12418 −10226 4560 20272 19352 −3652 −31080 −33718 222 45608 55840 7620 −65344 −90556 −23502 94167 150046 56796 −145352 −279128 −147694 298720 884064 1296880 –20 Rev. A | Page 59 of 134 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) Figure 124. TB1 Filter Response 0.9 1.0 15550-294 Table 23. TB1 Filter Coefficients 0 MAGNITUDE (dB) The TB1 decimate by 3, low-pass, FIR filter uses a 76-tap, symmetrical, fixed coefficient filter implementation. Table 23 shows the TB1 filter coefficients, and Figure 124 shows the TB1 filter response. TB1 is only supported in DDC0 and DDC1. AD9689 Data Sheet 20 FB2 Filter Description FB2 Coefficient Number 1, 48 2, 47 3, 46 4, 45 5, 44 6, 43 7, 42 8, 41 9, 40 10, 39 11, 38 12, 37 13, 36 14, 35 15, 34 16, 33 17, 32 18, 31 19, 30 20, 29 21, 28 22, 27 23, 26 24, 25 Normalized Coefficient 0.000007 −0.000004 −0.000069 −0.000244 −0.000544 −0.000870 −0.000962 −0.000448 0.000977 0.003237 0.005614 0.006714 0.004871 −0.001011 −0.010456 −0.020729 −0.026978 −0.023453 −0.005608 0.027681 0.072720 0.121223 0.162346 0.185959 Decimal Coefficient (21-Bit) 7 −4 −72 −256 −570 −912 −1009 −470 1024 3394 5887 7040 5108 −1060 −10964 −21736 −28288 −24592 −5880 29026 76252 127112 170232 194992 –20 Rev. A | Page 60 of 134 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) Figure 125. FB2 Filter Response 0.9 1.0 15550-295 Table 24. FB2 Filter Coefficients 0 MAGNITUDE (dB) The FB2 decimate by 5, low-pass, FIR filter uses a 48-tap, symmetrical, fixed coefficient filter implementation. Table 24 shows the FB2 filter coefficients, and Figure 125 shows the FB2 filter response. Data Sheet AD9689 DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION Each DDC contains an independently controlled gain stage. The gain is selectable as either 0 dB or 6 dB. When mixing a real input signal down to baseband, it is recommended that the user enable the 6 dB of gain to recenter the dynamic range of the signal within the full scale of the output bits. Each DDC contains an independently controlled complex to real conversion block. The complex to real conversion block reuses the last filter (HB1 FIR) in the filtering stage along with an fS/4 complex mixer to upconvert the signal. After upconverting the signal, the Q portion of the complex mixer is no longer needed and is dropped. The TB1 filter does not support complex to real conversion. When mixing a complex input signal down to baseband, the mixer has already recentered the dynamic range of the signal within the full scale of the output bits, and no additional gain is necessary. However, the optional 6 dB gain compensates for low signal strengths. The downsample by 2 portion of the HB1 FIR filter is bypassed when using the complex to real conversion stage. The TB1 filter does not have the 6 dB gain stage. HB1 FIR Figure 126 shows a simplified block diagram of the complex to real conversion. GAIN STAGE COMPLEX TO REAL ENABLE LOW-PASS FILTER I 2 0dB OR 6dB I 0 I/REAL 1 COMPLEX TO REAL CONVERSION 0dB OR 6dB I cos(ωt) + REAL 90° fS/4 0° – LOW-PASS FILTER 2 Q 0dB OR 6dB Q Q 15550-057 Q 0dB OR 6dB sin(ωt) HB1 FIR Figure 126. Complex to Real Conversion Block Rev. A | Page 61 of 134 AD9689 Data Sheet DDC MIXED DECIMATION SETTINGS The AD9689 also supports DDCs with different decimation rates. In this scenario, the chip decimation ratio must be set to the lowest decimation ratio of all the DDC channels. Samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Only mixed decimation ratios that are integer multiples of 2 are supported. For example, decimate by 1, 2, 4, 8, or 16 can be mixed together; decimate by 3, 6, 12, 24, or 48 can be mixed together; or decimate by 5, 10, 20, or 40 can be mixed together. Table 25 shows the DDC sample mapping when the chip decimation ratio is different than the DDC decimation ratio. For example, if the chip decimation ratio is set to decimate by 4, DDC0 is set to use the HB2 + HB1 filters (complex outputs are decimate by 4) and DDC1 is set to use the HB4 + HB3 + HB2 + HB1 filters (real outputs are decimate by 8), then DDC1 repeats its output data two times for every one DDC0 output. The resulting output samples are shown in Table 26. Table 25. Sample Mapping When the Chip Decimation Ratio (DCM) Does Not Match DDC DCM Sample Index 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DDC DCM = Chip DCM N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 N + 24 N + 25 N + 26 N + 27 N + 28 N + 29 N + 30 N + 31 DDC DCM = 2 × Chip DCM N N N+1 N+1 N+2 N+2 N+3 N+3 N+4 N+4 N+5 N+5 N+6 N+6 N+7 N+7 N+8 N+8 N+9 N+9 N + 10 N + 10 N + 11 N + 11 N + 12 N + 12 N + 13 N + 13 N + 14 N + 14 N + 15 N + 15 DDC DCM = 4 × Chip DCM N N N N N+1 N+1 N+1 N+1 N+2 N+2 N+2 N+2 N+3 N+3 N+3 N+3 N+4 N+4 N+4 N+4 N+5 N+5 N+5 N+5 N+6 N+6 N+6 N+6 N+7 N+7 N+7 N+7 Rev. A | Page 62 of 134 DDC DCM = 8 × Chip DCM N N N N N N N N N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+3 N+3 N+3 N+3 N+3 N+3 N+3 N+3 Data Sheet AD9689 Table 26. Chip DCM = 4, DDC0 DCM = 4 (Complex), and DDC1 DCM = 8 (Real) 1 DDC Input Samples N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 1 Output Port I I0[N] I0[N] I0[N] I0[N] I0[N + 1] I0[N + 1] I0[N + 1] I0[N + 1] I0[N + 2] I0[N + 2] I0[N + 2] I0[N + 2] I0[N + 3] I0[N + 3] I0[N + 3] I0[N + 3] DDC0 Output Port Q Q0[N] Q0[N] Q0[N] Q0[N] Q0[N + 1] Q0[N + 1] Q0[N + 1] Q0[N + 1] Q0[N + 2] Q0[N + 2] Q0[N + 2] Q0[N + 2] Q0[N + 3] Q0[N + 3] Q0[N + 3] Q0[N + 3] DCM means decimation. Rev. A | Page 63 of 134 Output Port I I1[N] I1[N] I1[N] I1[N] I1[N] I1[N] I1[N] I1[N] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] DDC1 Output Port Q Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable AD9689 Data Sheet DDC EXAMPLE CONFIGURATIONS Table 27 describes the register settings for multiple DDC example configurations. Table 27. DDC Example Configurations (Per ADC Channel Pair) Chip Application Layer One DDC Chip Decimation Ratio 2 DDC Input Type Complex DDC Output Type Complex Bandwidth Per DDC 1 40% × fS No. of Virtual Converters Required 2 Two DDCs 4 Complex Complex 20% × fS 4 Two DDCs 4 Complex Real 10% × fS 2 Two DDCs 4 Real Real 10% × fS 2 Rev. A | Page 64 of 134 Register Settings 0x0200 = 0x01 (one DDC; I/Q selected) 0x0201 = 0x01 (chip decimate by 2) 0x0310 = 0x83 (complex mixer; 0 dB gain; variable IF; complex outputs; HB1 filter) 0x0311 = 0x04 (DDC I Input = ADC Channel A; DDC Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0200 = 0x02 (two DDCs; I/Q selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x80 (complex mixer; 0 dB gain; variable IF; complex outputs; HB2 + HB1 filters) 0x0311, 0x0331 = 0x04 (DDC I input = ADC Channel A; DDC Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x89 (complex mixer; 0 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x0311, 0x0331 = 0x04 (DDC I Input = ADC Channel A; DDC Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 Data Sheet AD9689 Chip Application Layer Two DDCs Chip Decimation Ratio 4 DDC Input Type Real DDC Output Type Complex Bandwidth Per DDC 1 20% × fS No. of Virtual Converters Required 4 Two DDCs 8 Real Real 5% × fS 2 Four DDCs 8 Real Complex 10% × fS 8 Rev. A | Page 65 of 134 Register Settings 0x0200 = 0x02 (two DDCs; I/Q selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x40 (real mixer; 6 dB gain; variable IF; complex output; HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0200 = 0x03 (four DDCs; I/Q selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330, 0x0350, 0x0370 = 0x41 (real mixer; 6 dB gain; variable IF; complex output; HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC3 AD9689 Data Sheet Chip Application Layer Four DDCs Chip Decimation Ratio 8 DDC Input Type Real DDC Output Type Real Bandwidth Per DDC 1 5% × fS No. of Virtual Converters Required 4 Four DDCs 16 Real Complex 5% × fS 8 1 fS is the ADC sample rate. Rev. A | Page 66 of 134 Register Settings 0x0200 = 0x23 (four DDCs; I only selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330, 0x0350, 0x0370 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC3 0x0200 = 0x03 (four DDCs; I/Q selected) 0x0201 = 0x04 (chip decimate by 16) 0x0310, 0x0330, 0x0350, 0x0370 = 0x42 (real mixer; 6 dB gain; variable IF; complex output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC3 Data Sheet AD9689 DDC POWER CONSUMPTION Table 28 and Figure 28 describe the typical and maximum DVDD and DRVDD1 power consumption for certain DDC modes for 2.0 GSPS and 2.6 GSPS. Table 28. DDC Power Consumption for Example Configurations for 2.0 GSPS; fS = 2.0 GHz Number of DDCs 2 2 2 2 2 4 4 1 DDC Decimation Ratio 1 3 4 6 8 12 6 8 Number of Lanes (L) 8 8 4 4 2 8 8 Number of Virtual Converters (M) 4 4 4 4 4 8 8 Number of Octets per frame (F) 2 1 2 2 4 2 2 DVDD Power (mW) Typ Max 465 958 400 877 405 881 385 858 400 870 525 1040 485 970 DRVDD1 Power (mW) Typ Max 240 345 200 301 135 226 115 205 80 170 240 345 200 295 See Table 17 for details on decimation filter selection, the associated alias protected bandwidths, and SNR improvements. Table 29. DDC Power Consumption for Example Configurations for 2.6 GSPS; fS = 2.56 GHz Number of DDCs 2 2 2 2 2 4 4 1 DDC Decimation Ratio 1 3 4 6 8 12 6 8 Number of Lanes (L) 8 8 4 4 2 8 8 Number of Virtual Converters (M) 4 4 4 4 4 8 8 Number of Octets per frame (F) 2 1 2 2 4 2 2 DVDD Power (mW) Typ Max 575 995 520 930 515 925 500 905 510 912 655 1090 630 1090 See Table 17 for details on decimation filter selection, the associated alias protected bandwidths, and SNR improvements. Rev. A | Page 67 of 134 DRVDD1 Power (mW) Typ Max 280 375 230 325 155 238 135 211 95 165 280 380 230 325 AD9689 Data Sheet SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The results of the signal monitor block can be obtained either by reading back the internal values from the SPI port or by embedding the signal monitoring information into the JESD204B interface as separate control bits. A global, 24-bit programmable period controls the duration of the measurement. Figure 127 shows the simplified block diagram of the signal monitor block. SIGNAL MONITOR PERIOD REGISTER (SMPR) 0x0271, 00x272, 0x0273 CLEAR FROM INPUT MAGNITUDE STORAGE REGISTER LOAD DOWN COUNTER IS COUNT = 1? LOAD LOAD SIGNAL MONITOR HOLDING REGISTER COMPARE A>B TO SPORT OVER JESD204B AND MEMORY MAP 15550-049 FROM MEMORY MAP Figure 127. Signal Monitor Block The peak detector captures the largest signal within the observation period. The detector only observes the magnitude of the signal. The resolution of the peak detector is a 13-bit value, and the observation period is 24 bits and represents converter output samples. The peak magnitude can be derived by using the following equation: The magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal monitor period register (SMPR). The peak detector function is enabled by setting Bit 1 in the signal monitor control register (Register 0x0270). The 24-bit SMPR must be programmed before activating this mode. After enabling peak detection mode, the value in the SMPR is loaded into a monitor period timer, which decrements at the decimated clock rate. The magnitude of the input signal is compared with the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the SPORT over the JESD204B interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown restarts. In addition, the magnitude of the first input sample updates in the magnitude storage register, and the comparison and update procedure, as explained previously, continues. Peak Magnitude (dBFS) = 20log(Peak Detector Value/213) Rev. A | Page 68 of 134 Data Sheet AD9689 SPORT OVER JESD204B If only one control bit is to be inserted (CS = 1), only the most significant control bit is used (see Example Configuration 1 and Example Configuration 2 in Figure 128). To select the SPORT over JESD204B option, program Register 0x0559, Register 0x055A, and Register 0x058F. See Table 51 for more information on setting these registers. The signal monitor data can also be serialized and sent over the JESD204B interface as control bits. These control bits must be deserialized from the samples to reconstruct the statistical data. The signal control monitor function is enabled by setting Bits[1:0] of Register 0x0279 and Bit 1 of Register 0x027A. Figure 128 shows two different example configurations for the signal monitor control bit locations inside the JESD204B samples. A maximum of three control bits can be inserted into the JESD204B samples; however, only one control bit is required for the signal monitor. Control bits are inserted from MSB to LSB. Figure 129 shows the 25-bit frame data that encapsulates the peak detector value. The frame data is transmitted MSB first with five 5-bit subframes. Each subframe contains a start bit that can be used by a receiver to validate the deserialized data. Figure 130 shows the SPORT over JESD204B signal monitor data with a monitor period timer set to 80 samples. 16-BIT JESD204B SAMPLE SIZE (N' = 16) EXAMPLE CONFIGURATION 1 (N' = 16, N = 15, CS = 1) 1-BIT CONTROL BIT (CS = 1) 15-BIT CONVERTER RESOLUTION (N = 15) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S[14] X S[13] X S[12] X S[11] X S[10] X S[9] X S[8] X S[7] X S[6] X S[5] X S[4] X S[3] X S[2] X S[1] X S[0] X CTRL [BIT 2] X SERIALIZED SIGNAL MONITOR FRAME DATA 16-BIT JESD204B SAMPLE SIZE (N' = 16) 15 S[13] X 14 S[12] X 13 S[11] X 12 11 S[10] X 10 S[9] X 9 S[8] X 8 S[7] X 7 S[6] X 6 S[5] X 5 S[4] X S[3] X 4 S[2] X 3 S[1] X 2 1 0 S[0] X CTRL [BIT 2] X TAIL X SERIALIZED SIGNAL MONITOR FRAME DATA Figure 128. Signal Monitor Control Bit Locations 5-BIT SUBFRAMES 5-BIT IDLE SUBFRAME (OPTIONAL) 25-BIT FRAME IDLE 1 IDLE 1 IDLE 1 IDLE 1 IDLE 1 5-BIT IDENTIFIER START 0 SUBFRAME ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 5-BIT DATA MSB SUBFRAME START 0 P[12] P[11] P[10] P[9] 5-BIT DATA SUBFRAME START 0 P[8] P[7] P[6] P5] 5-BIT DATA SUBFRAME START 0 P[4] P[3] P[2] P1] 5-BIT DATA LSB SUBFRAME START 0 P[0] 0 0 0 P[x] = PEAK MAGNITUDE VALUE 15550-051 EXAMPLE CONFIGURATION 2 (N' = 16, N = 14, CS = 1) Figure 129. SPORT over JESD204B Signal Monitor Frame Data Rev. A | Page 69 of 134 15550-050 1 CONTROL BIT 1 TAIL (CS = 1) BIT 14-BIT CONVERTER RESOLUTION (N = 14) AD9689 Data Sheet SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00) 80 SAMPLE PERIOD PAYLOAD 25-BIT FRAME (N) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD PAYLOAD 25-BIT FRAME (N + 1) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE Figure 130. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples Rev. A | Page 70 of 134 15550-052 PAYLOAD 25-BIT FRAME (N + 2) Data Sheet AD9689 DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE • The AD9689 digital outputs are designed to the JEDEC standard JESD204B, serial interface for data converters. JESD204B is a protocol to link the AD9689 to a digital processing device over a serial interface with lane rates of up to 16 Gbps. The benefits of the JESD204B interface over LVDS include a reduction in required board area for data interface routing and an ability to enable smaller packages for converter and logic devices. • • • JESD204B OVERVIEW The JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8-bit/10-bit encoding as well as optional scrambling to form serial output data. Lane synchronization is supported through the use of separate control characters during the initial establishment of the link. Additional control characters are embedded in the data stream to maintain synchronization thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, refer to the JESD204B standard. The AD9689 JESD204B data transmit block maps up to two physical ADCs or up to eight virtual converters (when DDCs are enabled) over a link. A link can be configured to use one, two, four, or eight JESD204B lanes. The JESD204B specification refers to a number of parameters to define the link, and these parameters must match between the JESD204B transmitter (the AD9689 output) and the JESD204B receiver (the logic device input). The JESD204B link is described according to the following parameters: • • • • • L is the number of lanes per converter device (lanes per link); AD9689 value = 1, 2, 4, or 8. M is the number of converters per converter device (virtual converters per link); AD9689 value = 1, 2, 4, or 8. F is the octets per frame; AD9689 value = 1, 2, 4, 8, or 16. N΄ is the number of bits per sample (JESD204B word size); AD9689 value = 8 or 16. N is the converter resolution; AD9689 value = 7 to 16. CS is the number of control bits per sample; AD9689 value = 0, 1, 2, or 3. Figure 131 shows a simplified block diagram of the AD9689 JESD204B link. By default, the AD9689 is configured to use two converters and eight lanes. Converter A data is output to SERDOUT0±, SERDOUT1±, SERDOUT2± and SERDOUT3±; and Converter B is output to SERDOUT4±, SERDOUT5±, SERDOUT6±, and SERDOUT7±. The AD9689 allows other configurations, such as combining the outputs of both converters onto a single lane, or changing the mapping of the A and B digital output paths. These modes are set up via the SPI register map, along with additional customizable options. By default in the AD9689, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or as a pseudorandom number sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF±, or fast detect output. The two resulting octets can be scrambled. Scrambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. The scrambler uses a self synchronizing, polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver is a self synchronizing version of the scrambler polynomial. The two octets are then encoded with an 8-bit/10-bit encoder. The 8-bit/10-bit encoder works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. Figure 132 shows how the 14-bit data is taken from the ADC, how the tail bits are added, how the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. Figure 132 shows the default data format. CONVERTER 0 CONVERTER A INPUT ADC A MUX/ FORMAT (SPI REGISTERS 0x0561, 0x0564) CONVERTER B INPUT SYSREF± SYNCINB± JESD204B LINK CONTROL (L, M, F) (SPI REGISTER 0x058B, 0x058E, 0x058C) ADC B CONVERTER 1 LANE MUX AND MAPPING (SPI REGISTERS 0x05B0, 0x05B2, 0x05B3, 0x05B5, 0x05B6) SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SERDOUT4± SERDOUT5± SERDOUT6± SERDOUT7± 15550-058 • K is the number of frames per multiframe; AD9689 value = 4, 8, 12, 16, 20, 24, 28, or 32. S is the samples transmitted per single converter per frame cycle; AD9689 value is set automatically based on L, M, F, and N΄. HD is the high density mode; the AD9689 mode is set automatically based on L, M, F, and N΄. CF is the number of control words per frame clock cycle per converter device; AD9689 value = 0. Figure 131. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00) Rev. A | Page 71 of 134 AD9689 Data Sheet MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 A5 A4 A3 A2 A1 A0 C2 T OCTET1 OCTET1 TAIL BITS 0x0571[6] OCTET0 JESD204B SAMPLE CONSTRUCTION MSB S7 S6 S5 S4 S3 S2 S1 LSB S0 S7 S6 S5 S4 S3 S2 S1 S0 8-BIT/ 10-BIT ENCODER SERIALIZER a b i j a b SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± i j SYMBOL0 SYMBOL1 a b c d e f g h i j a b c d e f g h i j C2 C1 C0 15550-059 CONTROL BITS FRAME CONSTRUCTION SCRAMBLER 1 + x14 + x15 (OPTIONAL) OCTET0 ADC TEST PATTERNS (0x0550, 0x0551 TO 0x0558) MSB A13 A12 A11 A10 A9 ADC A8 A7 A6 A5 A4 A3 A2 A1 LSB A0 JESD204B DATA LINK LAYER TEST PATTERNS 0x0574[2:0] JESD204B INTERFACE TEST PATTERN (0x0573, 0x0551 TO 0x0558) JESD204B LONG TRANSPORT TEST PATTERN 0x0571[5] Figure 132. ADC Output Datapath Showing Data Framing TRANSPORT LAYER SAMPLE CONSTRUCTION FRAME CONSTRUCTION SCRAMBLER ALIGNMENT CHARACTER GENERATION 8-BIT/10-BIT ENCODER PHYSICAL LAYER CROSSBAR MUX SERIALIZER Tx OUTPUT 15550-060 PROCESSED SAMPLES FROM ADC DATA LINK LAYER SYSREF± SYNCINB± Figure 133. Data Flow FUNCTIONAL OVERVIEW Physical Layer The block diagram in Figure 133 shows the flow of data through the JESD204B hardware from the sample input to the physical output. The processing can be divided into layers that are derived from the open-source initiative (OSI) model widely used to describe the abstraction layers of communications systems. These layers are the transport layer, data link layer, and physical layer (serializer and output driver). The physical layer consists of the high speed circuitry clocked at the serial clock rate. In this layer, parallel data is converted into one, two, four, or eight lanes of high speed differential serial data. Transport Layer The transport layer handles packing the data (consisting of samples and optional control bits) into JESD204B frames that are mapped to 8-bit octets. These octets are sent to the data link layer. The transport layer mapping is controlled by rules derived from the link parameters. Tail bits are added to fill gaps where required. The following equation can be used to determine the number of tail bits within a sample (JESD204B word): T = N΄ − N − CS Data Link Layer The data link layer is responsible for the low level functions of passing data across the link. These functions include optionally scrambling the data, inserting control characters for multichip synchronization/lane alignment/monitoring, and encoding 8-bit octets into 10-bit symbols. The data link layer is also responsible for sending the initial lane alignment sequence (ILAS), which contains the link configuration data used by the receiver to verify the settings in the transport layer. JESD204B LINK ESTABLISHMENT The AD9689 JESD204B transmitter (Tx) interface operates in Subclass 1 as defined in the JEDEC Standard JESD204B (July 2011 specification). The link establishment process is divided into the following steps: code group synchronization (CGS) and SYNCINB±, initial lane alignment sequence, and user data and error correction. CGS and SYNCINB± CGS is the process in which the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit block transmits /K28.5/ characters. The receiver must locate /K28.5/ characters in its input data stream using clock and data recovery (CDR) techniques. The receiver issues a synchronization request by asserting the SYNCINB± pin of the AD9689 low. The JESD204B Tx then begins sending /K/ characters. After the receiver synchronizes, it waits for the correct reception of at least four consecutive /K/ symbols. It then deasserts SYNCINB±. The AD9689 then transmits an ILAS on the following LMFC boundary. For more information on the code group synchronization phase, refer to the JEDEC Standard JESD204B, July 2011, Section 5.3.3.1. Rev. A | Page 72 of 134 Data Sheet AD9689 User Data and Error Detection After the initial lane alignment sequence completes, the user data is sent. Normally, within a frame, all characters are considered to be user data. However, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is enabled by default; however, it can be disabled using the SPI. The SYNCINB± pin operation can also be controlled by the SPI. The SYNCINB± signal is a differential dc-coupled LVDS mode signal by default, but it can also be driven single-ended. For more information on configuring the SYNCINB± pin operation, refer to Register 0x0572. The SYNCINB± pins can also be configured to run in CMOS (single-ended) mode, by setting Bit 4 in Register 0x0572. When running SYNCINB± in CMOS mode, connect the CMOS SYNCINB signal to Pin N13 (SYNCINB+) and leave Pin P13 (SYNCINB−) floating. For scrambled data, any 0xFC character at the end of a frame is replaced by an /F/, and any 0x7C character at the end of a multiframe is replaced by an /A/. The JESD204B receiver (Rx) checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver handles the situation by using dynamic realignment or asserting the SYNCINB± signal for more than four frames to initiate a resynchronization. For unscrambled data, if the final character of two subsequent frames is equal, the second character is replaced with an /F/ if it is at the end of a frame, and an /A/ if it is at the end of a multiframe. Initial Lane Alignment Sequence (ILAS) The ILAS phase follows the CGS phase and begins on the next LMFC boundary. The ILAS consists of four multiframes, with an /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by 0 to 255 ramp data for one multiframe. On the second multiframe, the link configuration data is sent, starting with the third character. The second character is a /Q/ character to confirm that the link configuration data is to follow. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. The ILAS sequence construction is shown in Figure 134. The four multiframes include the following: • Insertion of alignment characters can be modified using the SPI. The frame alignment character insertion (FACI) is enabled by default. More information on the link controls is available in the Memory Map section, Register 0x0571. Multiframe 1 begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 2 begins with an /R/ character followed by a /Q/ character (/K28.4/), followed by link configuration parameters over 14 configuration octets (see Table 30) and ends with an /A/ character. Many of the parameter values are of the value − 1 notation. Multiframe 3 begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 4 begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). • • • K K R D ●●● D A R Q C ●●● C D ●●● 8-Bit/10-Bit Encoder The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 30. The 8-bit/10-bit encoding ensures that the signal is dc balanced by using the same number of ones and zeros across multiple symbols. The 8-bit/10-bit interface has options that can be controlled via the SPI. These operations include bypass and invert, and are troubleshooting tools for the verification of the digital front end (DFE). See the Memory Map section, Register 0x0572, Bits[2:1] for information on configuring the 8-bit/10-bit encoder. D A R D ●●● D A R D ●●● D A D END OF MULTIFRAME ●●● ●●● ●●● ●●● START OF LINK CONFIGURATION DATA START OF ILAS START OF USER DATA 15550-061 ●●● Figure 134. Initial Lane Alignment Sequence Table 30. AD9689 Control Characters Used in JESD204B Abbreviation /R/ /A/ /Q/ /K/ /F/ 1 Control Symbol /K28.0/ /K28.3/ /K28.4/ /K28.5/ /K28.7/ 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value, RD = −1 001111 0100 001111 0011 001111 0100 001111 1010 001111 1000 RD means running disparity. Rev. A | Page 73 of 134 10-Bit Value, RD = +1 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment AD9689 Data Sheet DRVDD SERDOUTx+ 100Ω DIFFERENTIAL TRACE PAIR 0.1µF 100Ω 0.1µF RECEIVER SERDOUTx– 15550-063 OUTPUT SWING = 0.85 × DRVDD1 V p-p DIFFERENTIAL ADJUSTABLE TO 1 × DRVDD1, 0.75 × DRVDD1 Figure 135. AC-Coupled Digital Output Termination Example PHYSICAL LAYER (DRIVER) OUTPUTS Place a 100 Ω differential termination resistor at each receiver input to result in a nominal 0.85 × DRVDD1 V p-p swing at the receiver (see Figure 135). The swing is adjustable through the SPI registers. AC coupling is recommended to connect to the receiver. See the Memory Map section (Register 0x05C0 to Register 0x05C3 in Table 51) for more details. The AD9689 digital outputs can interface with custom application specific integrated circuits (ASICs) and field programmable gate array (FPGA) receivers, providing superior switching performance in noisy environments. Single point to point network topologies are recommended with a single differential 100 Ω termination resistor placed as close to the receiver inputs as possible. If there is no far end receiver termination, or if there is poor differential trace routing, timing errors can result. To avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. 15550-306 Figure 136 to Figure 138 show an example of the digital output data eye, jitter histogram, and bathtub curve for one AD9689 lane running at 16 Gbps. The format of the output data is twos complement by default. To change the output data format, see the Memory Map section (Register 0x0561 in Table 51). Figure 136. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps Figure 137. Digital Outputs Jitter Histogram, External 100 Ω Terminations at 16 Gbps 15550-308 The AD9689 physical layer consists of drivers that are defined in the JEDEC Standard JESD204B, July 2011. The differential digital outputs are powered up by default. The drivers use a dynamic 100 Ω internal termination to reduce unwanted reflections. 15550-307 Digital Outputs, Timing, and Controls Figure 138. Digital Outputs Bathtub Curve, External 100 Ω Terminations at 16 Gbps De-Emphasis De-emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. Use the de-emphasis feature only when the receiver is unable to recover the clock due to excessive insertion loss. Under normal conditions, it is disabled to conserve power. Additionally, enabling and setting too high a de-emphasis value on a short link can cause the receiver eye diagram to fail. Use the de-emphasis setting with caution because it can increase electromagnetic interference (EMI). See the Memory Map section (Register 0x05C4 to Register 0x05CB in Table 51) for more details. Phase-Locked Loop (PLL) The PLL generates the serializer clock, which operates at the JESD204B lane rate. The status of the PLL lock can be checked in the PLL locked status bit (Register 0x056F, Bit 7). This read only bit notifies the user if the PLL achieved a lock for the specific setup. Register 0x056F also has a loss of lock (LOL) sticky bit (Bit 3) that notifies the user that a LOL is detected. The sticky bit can be reset by issuing a JESD204B link restart (Register 0x0571 = 0x15, followed by Register 0x0571 = 0x14). Refer to Table 32 for the reinitialization of the link following a link power cycle. The JESD204B lane rate control, Bits[7:4] of Register 0x056E, must be set to correspond with the lane rate. Table 31 shows the lane rates supported by the AD9689 using Register 0x056E. Rev. A | Page 74 of 134 Data Sheet AD9689 Table 31. AD9689 Register 0x056E Supported Lane Rates Value 0x00 0x10 0x30 0x50 Lane Rate Lane rate = 6.75 Gbps to 13.5 Gbps (default for AD9689) Lane rate = 3.375 Gbps to 6.75 Gbps Lane rate = 13.5 Gbps to 16 Gbps Lane rate = 1.6875 Gbps to 3.375 Gbps fS × 4 MODE fS × 4 mode adds a separate packing mode to a JESD204B transmitter/receiver to set the serial lane rate at four times the sample rate (fS). • • • In fS × 4 mode, five 12-bit ADC samples (along with an extra 4 bits) are packed into four 16-bit JESD204B samples to create a 64-bit frame. The following SPI writes are necessary to place the device in fS × 4 mode: • The JESD204B link settings are • • • • • • • • • • • L=8 M=2 F=2 S=5 N' = 12 N = 12 CS = 0 CF = 2 HD = 1 CS = 0 CF = 0 HD = 0 Register 0x0570 = 0xFE. This setting places the device in M = 2, L = 8, fS × 4 mode. Register 0x058B = 0x0F. This setting places the device CS = 0, N' = 16 mode. Register 0x058F = 0x2F. This setting places the device in Subclass 1 mode, N = 16. The transmit architecture of fS × 4 mode is shown in Figure 139, and the receive portion is shown in Figure 140. fS × 4 mode only works in full bandwidth mode (Register 0x0200 = 0x00). However, CF = 2 is not supported by the design; therefore, the following link parameters are used along with separate packing: L=8 M=2 F=2 S=4 N' = 16 N = 16 fS × 4 MODE (TRANSMIT) ADC0 ADC1 12 BITS AT fS ADC0 SAMPLE N (12 BITS) ADC1 SAMPLE N (12 BITS) 64 BITS AT fS/5 1/5 RATE EXCHANGE 64 BITS AT fS/5 ADC0 SAMPLE N (12 BITS) ADC0 SAMPLE N + 1 (12 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) CONVERTER 0 SAMPLE N (16 BITS) S[N][15:0] ADC0 SAMPLE N + 2 (12 BITS) ADC0 SAMPLE N + 3 (12 BITS) S[N + 1][7:0], S[N + 2][11:4] (16 BITS) CONVERTER 0 SAMPLE N + 1 (16 BITS) S[N + 1][15:0] 1/5 RATE EXCHANGE 0000 ADC0 SAMPLE N + 4 (12 BITS) S[N + 2][3:0], S[N + 3][11:0] (16 BITS) CONVERTER 0 SAMPLE N + 2 (16 BITS) S[N + 2][15:0] (4 BITS) S[N + 4][11:0], 0000 (16 BITS) CONVERTER 0 SAMPLE N + 3 (16 BITS) S[N + 3][15:0] ADC1 SAMPLE N (12 BITS) ADC1 SAMPLE N + 1 (12 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) CONVERTER 1 SAMPLE N (16 BITS) ADC1 SAMPLE N + 2 (12 BITS) S[N + 1][7:0], S[N + 2][11:4] (16 BITS) CONVERTER 1 SAMPLE N+1 (16 BITS) S[N][15:0] S[N + 1][15:0] JESD204B FRAMER + PHY (M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0) LANE 0 LANE 1 LANE 2 LANE 3 LANE 4 LANE 5 LANE 6 LANE 7 Figure 139. fS × 4 Mode (Transmit) Rev. A | Page 75 of 134 0000 ADC1 SAMPLE N + 3 (12 BITS) ADC1 SAMPLE N + 4 (12 BITS) S[N + 2][3:0], S[N + 3][11:0] (16 BITS) CONVERTER 1 SAMPLE N+2 (16 BITS) S[N + 2][15:0] (4 BITS) APPLICATION LAYER S[N + 4][11:0], 0000 (16 BITS) CONVERTER 1 SAMPLE N+3 (16 BITS) S[N + 3][15:0] TRANSPORT, DATA LINK, AND PHY LAYERS 15550-309 • • • • • • AD9689 Data Sheet fS × 4 MODE (RECEIVE) LANE 0 LANE 1 LANE 2 LANE 3 LANE 4 LANE 5 LANE 6 LANE 7 JESD204B FRAMER + PHY (M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0) 64 BITS AT fS/5 64 BITS AT fS/5 CONVERTER 0 SAMPLE N (16 BITS) CONVERTER 0 SAMPLE N + 1 (16 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) ADC0 SAMPLE N (12 BITS) ADC0 SAMPLE N + 1 (12 BITS) S[N + 3][15:0] S[N + 2][15:0] S[N + 1][15:0] S[N][15:0] CONVERTER 0 SAMPLE N + 2 (16 BITS) S[N + 1][7:0], S[N + 2][11:4] (16 BITS) ADC0 SAMPLE N + 2 (12 BITS) CONVERTER 0 SAMPLE N + 3 (16 BITS) S[N + 2][3:0], S[N + 3][11:0] (16 BITS) ADC0 SAMPLE N + 3 (12 BITS) ADC0 SAMPLE N + 4 (12 BITS) (4 BITS) CONVERTER 1 SAMPLE N + 1 (16 BITS) CONVERTER 1 SAMPLE N (16 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) S[N + 4][11:0], 0000 (16 BITS) ADC1 SAMPLE N (12 BITS) ADC1 SAMPLE N + 1 (12 BITS) S[N + 3][15:0] S[N + 2][15:0] S[N + 1][15:0] S[N][15:0] CONVERTER 1 SAMPLE N + 2 (16 BITS) S[N + 1][7:0], S[N + 2][11:4] (16 BITS) ADC1 SAMPLE N + 2 (12 BITS) CONVERTER 1 SAMPLE N + 3 (16 BITS) S[N + 2][3:0], S[N + 3][11:0] (16 BITS) ADC1 SAMPLE N + 3 (12 BITS) DATA LINK, TRANSPORT, AND PHY LAYERS S[N + 4][11:0], 0000 (16 BITS) ADC1 SAMPLE N + 4 (12 BITS) APPLICATION LAYER (4 BITS) 0000 15550-310 0000 USER APPLICATION Figure 140. fS × 4 Mode (Receive) SETTING UP THE AD9689 DIGITAL INTERFACE To ensure proper operation of the AD9689 at startup, some SPI writes are required to initialize the link. Additionally, these registers must be written every time the ADC is reset. Any one of the following resets warrants the initialization routine for the digital interface: • • • • • • Hard reset, as with power-up. Power-up using the PDWN pin. Power-up using the SPI via Register 0x0002, Bits[1:0]. SPI soft reset by setting Register 0x0000 = 0x81. Datapath soft reset by setting Register 0x0001 = 0x02. JESD204B link power cycle by setting Register 0x0571 = 0x15, then 0x14. The initialization SPI writes are as shown in Table 32. Value 0x4F 0x0F 0x00 0x04 0x00 0x08 0x00 Comment Reset JESD204B start-up circuit JESD204B start-up circuit in normal operation JESD204B PLL force normal operation Reset JESD204B PLL calibration JESD204B PLL normal operation Clear loss of lock bit Loss of lock bit normal operation The AD9689 has one JESD204B link. The serial outputs (SERDOUT0± to SERDOUT7±) are considered to be part of one JESD204B link. The basic parameters that determine the link setup are • • • Number of lanes per link (L) Number of converters per link (M) Number of octets per frame (F) The maximum lane rate allowed by the AD9689 is 16 Gbps. The lane rate is related to the JESD204B parameters using the following equation: 10 M × N ' × × f OUT 8 Lane Rate = L where fOUT = f ADC _ CLOCK Decimation Ratio The decimation ratio (DCM) is the parameter programmed in Register 0x0201. Use the following procedure to configure the output: Table 32. AD9689 JESD204B Initialization Register 0x1228 0x1228 0x1222 0x1222 0x1222 0x1262 0x1262 If the internal DDCs are used for on-chip digital processing, M represents the number of virtual converters. The virtual converter mapping setup is shown in Figure 102. 1. 2. 3. 4. 5. 6. 7. Power down the link. Select the JESD204B link configuration options. Configure the detailed options. Set output lane mapping (optional). Set additional driver configuration options (optional). Power up the link. Initialize the JESD204B link by issuing the commands described in Table 32. If the lane rate calculated is less than 6.25 Gbps, select the low lane rate option by programming a value of 0x10 to Register 0x056E. Table 33 and Table 35 show the JESD204B output configurations supported for both N΄ = 16 and N΄ = 8 for a given number of virtual converters. Take care to ensure that the serial lane rate for a given configuration is within the supported range of 3.4 Gbps to 16 Gbps. Rev. A | Page 76 of 134 Data Sheet AD9689 Table 33. JESD204B Output Configurations for N΄ = 16 1 37F Number of Virtual Converters Supported (Same as M) 1 Supported Decimation Rates JESD204B Serial Lane Rate 2 20 × fOUT Lane Rate = 6.75 Gbps to 13.5 Gbps 1, 2, 3, 4, 5, 6, 8 Lane Rate = 13.5 Gbps to 16 Gbps 1, 2, 3, 4 L 1 M 1 F 2 S 1 HD 0 N 8 to 16 N' 16 CS 0 to 3 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1 1 4 2 0 8 to 16 16 0 to 3 1, 2, 3, 4 1, 2 2 1 1 1 1 8 to 16 16 0 to 3 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 2 1 2 2 0 8 to 16 16 0 to 3 5 × fOUT 1, 2, 3, 4 1, 2 1 4 1 1 2 1 8 to 16 16 0 to 3 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 4 1 2 4 0 8 to 16 16 0 to 3 2.5 × fOUT 1, 2, 3, 4 1, 2 1 8 1 1 4 1 8 to 16 16 0 to 3 2.5 × fOUT 1, 2, 3, 4 1, 2 1 8 1 2 8 0 8 to 16 16 0 to 3 40 × fOUT 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1 2 4 1 0 8 to 16 16 0 to 3 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1 2 8 2 0 8 to 16 16 0 to 3 See Note 4 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 2 2 2 1 0 8 to 16 16 0 to 3 See Note 4 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 2 2 4 2 0 8 to 16 16 0 to 3 See Note 4 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 4 2 1 1 1 8 to 16 16 0 to 3 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 4 2 2 2 0 8 to 16 16 0 to 3 5 × fOUT 4, 8, 10, 12, 15, 16, 20, 24, 30, 40, 48 4, 8, 10, 12, 15, 16, 20, 24, 30, 40, 48 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 8 2 1 2 1 8 to 16 16 0 to 3 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 8 2 2 4 0 8 to 16 16 0 to 3 80 × fOUT 8, 16, 20, 24, 30, 40, 48 4, 8, 10, 12, 15, 16, 20, 24, 30, 40, 48 4, 8, 10, 12, 15, 16, 20, 24, 30, 40, 48 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 4, 8, 10, 12, 16, 20, 24, 30, 40, 48 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 2, 4, 6, 8, 10, 12, 16, 20, 24, 30 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 2, 4, 6, 8, 10, 12, 16 1, 2, 3, 4, 5, 6, 8 1 4 8 1 0 8 to 16 16 0 to 3 2 4 4 1 0 8 to 16 16 0 to 3 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 2 4 8 2 0 8 to 16 16 0 to 3 See Note 4 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 4 4 2 1 0 8 to 16 16 0 to 3 See Note 4 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 4 4 4 2 0 8 to 16 16 0 to 3 See Note 4 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 8 4 1 1 1 8 to 16 16 0 to 3 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 8 4 2 2 0 8 to 16 16 0 to 3 See Note 4 See Note 4 38F 10 × fOUT 10 × fOUT 40 × fOUT 20 × fOUT 20 × fOUT 10 × fOUT 10 × fOUT 4 39F Lane Rate = 3.375 Gbps to 6.75 Gbps 1, 2, 3, 4, 5, 6, 8, 10, 12 1, 2, 3, 4, 5, 6, 8, 10, 12 1, 2, 3, 4, 5, 6, 8 20 × fOUT 2 JESD204B Transport Layer Settings 3 Lane Rate = 1.6875 Gbps to 3.375 Gbps 2, 4, 5, 6, 8, 10, 12, 20, 24 2, 4, 5, 6, 8, 10, 12, 20, 24 1, 2, 3, 4, 5, 6, 8, 10, 12 1, 2, 3, 4, 5, 6, 8, 10, 12 1, 2, 3, 4, 5, 6, 8 40 × fOUT 40 × fOUT 20 × fOUT 20 × fOUT 10 × fOUT 10 × fOUT K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 40F Rev. A | Page 77 of 134 AD9689 Number of Virtual Converters Supported (Same as M) 8 Data Sheet Supported Decimation Rates JESD204B Serial Lane Rate 2 160 × fOUT 38F 80 × fOUT 40 × fOUT 40 × fOUT 20 × fOUT 20 × fOUT Lane Rate = 1.6875 Gbps to 3.375 Gbps 16, 40, 48 8, 16, 20, 24, 40, 48 4, 8, 10, 12, 16, 20, 24, 40, 48 4, 8, 10, 12, 16, 20, 24, 40, 48 2, 4, 6, 8, 10, 12, 16, 20, 24 2, 4, 6, 8, 10, 12, 16, 20, 24 Lane Rate = 3.375 Gbps to 6.75 Gbps 8, 16, 20, 24, 40, 48 4, 8, 10, 12, 16, 20, 24, 40, 48 2, 4, 6, 8, 10, 12, 16, 20, 24 2, 4, 6, 8, 10, 12, 16, 20, 24 2, 4, 6, 8, 10, 12, 16 2, 4, 6, 8, 10, 12, 16 Lane Rate = 6.75 Gbps to 13.5 Gbps 4, 8, 12, 16, 20, 24, 40, 48 2, 4, 6, 8, 10, 12, 16, 20, 24 2, 4, 6, 8, 10, 12, 16 2, 4, 6, 8, 10, 12, 16 2, 4, 6, 8 Lane Rate = 13.5 Gbps to 16 Gbps 4, 8, 12, 16, 20, 24 2, 4, 6, 8, 10, 12, 16 2, 4, 6, 8 2, 4, 6, 8 JESD204B Transport Layer Settings 3 39F L 1 M 8 F 16 S 1 HD 0 N 8 to 16 N' 16 CS 0 to 3 2 8 8 1 0 8 to 16 16 0 to 3 4 8 4 1 0 8 to 16 16 0 to 3 2, 4, 6, 8 4 8 8 2 0 8 to 16 16 0 to 3 2, 4 8 8 2 1 0 8 to 16 16 0 to 3 2, 4 8 8 4 2 0 8 to 16 16 0 to 3 1 K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 3 fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥1.6875 Gbps and SLR ≤15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤64. When the SLR is ≤16000 Mbps and >13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13500 Mbps and ≥6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and ≥1687.5 Mbps, Register 0x056E must be set to 0x50. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32. 2 Rev. A | Page 78 of 134 Data Sheet AD9689 Table 34. JESD204B Output Configurations (N' = 12) 1 41F Supported Decimation Rates No. of Virtual Converters Supported (Same Value as M) 1 JESD204B Transport Layer Settings 3 43F Serial Lane Rate 2 15 × fOUT Lane Rate = 1.6875 Gbps to 3.375 Gbps 3, 6, 12 Lane Rate = 3.375 Gbps to 6.75 Gbps 3, 6, 12 Lane Rate = 6.75 Gbps to 13.5 Gbps 3, 6 7.5 × fOUT 3, 6 3, 6 7.5 × fOUT 3, 6 5 × fOUT Lane Rate = 13.5 Gbps to 16 Gbps L 1 M 1 F 3 S 2 HD 0 N 8 to 12 N' 12 L 0 to 3 3 2 1 3 4 1 8 to 12 12 0 to 3 3, 6 3 2 1 6 8 0 8 to 12 12 0 to 3 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 3 1 1 2 1 8 to 12 12 0 to 3 30 × fOUT 3, 6, 12, 24 3, 6, 12, 24 3, 6, 12 1 2 3 1 0 8 to 12 12 0 to 3 15 × fOUT 3, 6, 12 3, 6, 12 3, 6 2 2 3 2 0 8 to 12 12 0 to 3 10 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 3 2 1 1 1 8 to 12 12 0 to 3 7.5 × fOUT 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 3, 6 3, 6 3 4 2 3 4 0 8 to 12 12 0 to 3 60 × fOUT 6, 12, 24, 48 3, 6, 12, 24, 48 3, 6, 12, 24 1 4 6 1 0 8 to 12 12 0 to 3 30 × fOUT 3, 6, 12, 24 3, 6, 12, 24 3, 6, 12 2 4 3 1 0 8 to 12 12 0 to 3 20 × fOUT 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 3, 6, 12 1, 2, 3, 4, 5, 6, 8 3, 6 3 4 2 1 1 8 to 12 12 0 to 3 15 × fOUT 2, 4, 5, 6, 8, 10, 12, 16, 20, 24 3, 6, 12 4 4 3 2 0 8 to 12 12 0 to 3 60 × fOUT 6, 12, 24, 48 6, 12, 24, 48 6, 12, 24 2 8 6 1 0 8 to 12 12 0 to 3 30 × fOUT 6, 12, 24 6, 12, 24 6, 12 4 8 3 1 0 8 to 12 12 0 to 3 42F K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 4F 2 4 8 1 1, 2 1, 2, 3, 4 1 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤64. When the SLR is ≤16000 Mbps and >13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13500 Mbps and ≥6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is <6750 Mbps and ≥3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and ≥1687.5 Mbps, Register 0x056E must be set to 0x50. 3 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32. 2 Rev. A | Page 79 of 134 AD9689 Data Sheet Table 35. JESD204B Output Configurations for N΄ = 8 1 45F Supported Decimation Rates JESD204B Transport Layer Settings 3 No. of Virtual Converters Supported (Same Value as M) 1 Serial Lane Rate 2 10 × fOUT 1 10 × fOUT 1 47F Lane Rate = 3.375 Gbps to 6.75 Gbps 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 Lane Rate = 6.75 Gbps to 13.5 Gbps 1, 2, 3, 4 Lane Rate = 13.5 Gbps to 16 Gbps 1, 2 L 1 M 1 F 1 S 1 HD 0 N 7 to 8 N' 8 CS 0 to 1 1, 2, 3, 4 1, 2 1 1 2 2 0 7 to 8 8 0 to 1 5 × fOUT Lane Rate = 1.6875 Gbps to 3.375 Gbps 1, 2, 3, 4, 5, 6, 8, 10, 12 1, 2, 3, 4, 5, 6, 8, 10, 12 1, 2, 3, 4, 5, 6, 8 1, 2 1 2 1 1 2 0 7 to 8 8 0 to 1 1 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 2 1 2 4 0 7 to 8 8 0 to 1 1 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 2 1 4 8 0 7 to 8 8 0 to 1 1 2.5 × fOUT 1, 2, 3, 4 1, 2 1 4 1 1 4 0 7 to 8 8 0 to 1 1 2.5 × fOUT 1, 2, 3, 4 1, 2 1 4 1 2 8 0 7 to 8 8 0 to 1 2 20 × fOUT 1, 2, 3, 4 1 2 2 1 0 7 to 8 8 0 to 1 10 × fOUT 1, 2, 3, 4 1, 2 2 2 1 1 0 7 to 8 8 0 to 1 2 10 × fOUT 1, 2, 3, 4 1, 2 2 2 2 2 0 7 to 8 8 0 to 1 2 5 × fOUT 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2, 3, 4, 5, 6, 8 2 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2 1 4 2 1 2 0 7 to 8 8 0 to 1 2 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 4 2 2 4 0 7 to 8 8 0 to 1 2 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 4 2 4 8 0 7 to 8 8 0 to 1 46F K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 48F 1 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥1.6875 Gbps and SLR ≤15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤16000 Mbps and >13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13500 Mbps and ≥6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is <6750 Mbps and ≥3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and ≥1687.5 Mbps, Register 0x056E must be set to 0x50. 3 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32. 2 Rev. A | Page 80 of 134 Data Sheet AD9689 Example 1—Full Bandwidth Mode 2560MSPS 12.8Gbps/LANE SYNC~ F=1 14-BIT ADC CORE L0 M0 L1 L2 JESD204B LINK (L = 8, M = 2, F = 1, S = 2, N´ = 16, N = 16, CS = 0, HD = 1) VIN_B REAL 14-BIT ADC CORE L3 L4 L5 L6 M1 L7 I = REAL COMPONENT Q = QUADRATURE COMPONENT DCM = DECIMATION C2R = COMPLEX TO REAL MX = VIRTUAL CONVERTER X LY = LANE Y SZ = SAMPLE Z INSIDE A JESD204B FRAME C = CONTROL BIT (OVERRANGE, AMONG OTHERS) T = TAIL BIT M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0] M1S0[15:8] M1S0[7:0] M1S1[15:8] M1S1[7:0] 15550-311 VIN_A REAL Figure 141. Full Bandwidth Mode The AD9689 is set up as shown in Figure 141, with the following configurations: • • • Two 14-bit converters at 2.56 GSPS. Full bandwidth application layer mode. Decimation filters bypassed. The JESD204B output configuration is as follows: • • Two virtual converters required (see Table 33). Output sample rate (fOUT) = 2560/1 = 2560 MSPS. The JESD204B supported output configurations are as follows (see Table 33): • • • • • • • N΄ = 16 bits. N = 14 bits. L = 8, M = 2, and F = 1, or L = 8, M = 2, and F = 2. CS = 0. K = 32. Output serial lane rate = 12.8 Gbps per lane. The PLL control register, Register 0x056E, is set to 0x00. Set up the AD9689 in this mode using the following sequence: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. Rev. A | Page 81 of 134 Write 0x81 to Register 0x0000 (SPI soft reset). Wait 5 ms to 10 ms. Write 0x00 to Register 0x0200 (full bandwidth mode). Write 0x00 to Register 0x0201 (chip decimation ratio = 1). Write 0x15 to Register 0x0571 (JESD204B link powerdown). Write 0x87 to Register 0x058B (scrambling enabled, L = 8). Write 0x01 to Register 0x058E (M = 2). Write0x00 to Register 0x058C (F = 1). Write 0x00 to Register 0x056E (lane rate = 6.75 Gbps to 13.5 Gbps). Write 0x14 to Register 0x0571 (JESD204B link power-up). Wait 5 ms to 10 ms. Read Register 0x056F (PLL status register). Write 0x4F to Register 0x1228. Write 0x0F to Register 0x1228. Write 0x00 to Register 0x1222. Write 0x04 to Register 0x1222. Write 0x00 to Register 0x1222. Write 0x08 to Register 0x1262. Write 0x00 to Register 0x1262. AD9689 Data Sheet Example 2—ADC with DDC Option (Two ADCs Plus Two DDCs) fS (MHz) fOUT = fS/10 (MHz) 40 × fOUT MbPS SYNC~ LAB1 M3(Q) 15550-312 I = REAL COMPONENT Q = QUADRATURE COMPONENT DCM = DECIMATION C2R = COMPLEX TO REAL MX = VIRTUAL CONVERTER X LY = LANE Y SZ = SAMPLE Z INSIDE A JESD204B FRAME C = CONTROL BIT (OVER RANGE, AMONG OTHERS) T = TAIL BIT M1(Q)S0[7:0] 14-BIT ADC CORE M3(Q)S0[7:0] M2(I) DDC 1 (REAL INPUT, DCM = 10 C2R = BYPASS) JESD204B LINK (L = 2 M = 4 F = 4, S = 1, N’ = 16, N = 16, CS = 0, HD = 0) M0(I)S0[7:0] M1(Q) M1(Q)S0[15:8] LAB0 M3(Q)S0[15:8] DDC 0 (REAL INPUT, DCM = 10 C2R = BYPASS) M0(I)S0[15:8] VIN_B REAL 14-BIT ADC CORE M2(I)S0[7:0] VIN_A REAL M2(I)S0[15:8] F=4 M0(I) Figure 142. Two ADCs Plus Two DDCs Mode (L = 2, M = 4, F = 4, S = 1) This example shows the flexibility in the digital and lane configurations for the AD9689. The sample rate is 2.4576 GSPS, whereas the outputs are all combined in a combination of either two, four, or eight lanes, depending on the input/output speed capability of the receiving device. The AD9689 is set up as shown in Figure 142, with the following configuration: • • • • Two 14-bit converters at 2.4576 GSPS. Two DDC application layer mode with complex outputs (I/Q). Chip decimation ratio = 10. DDC decimation ratio = 10 (see Table 33). The JESD204B output configuration is as follows: • • 1. 2. 3. 4. 5. 6. 7. 8. 9. Four virtual converters required (see Table 33). Output sample rate (fOUT) = 2457.6/10 = 245.76 MSPS. The JESD204B supported output configurations are as follows (see Table 33): • • • • • • Set up the AD9689 in this mode using the following sequence: N΄ = 16 bits. N = 14 bits. L = 2, M = 4, and F = 4, or L = 4, M = 4, and F = 2. CS = 0. K = 32. Output serial lane rate = 9.8304 Gbps per lane (L = 2), 4.9152 Gbps per lane (L = 4), or 2.4576 Gbps per lane (L = 8). For L = 2, set the PLL control register, Register 0x056E, to 0x00. For L = 4, set the PLL control register, Register 0x056E, to 0x10. For L = 8, set the PLL control register, Register 0x056E, to 0x50. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. Rev. A | Page 82 of 134 Write 0x81 to Register 0x0000 (SPI soft reset). Wait 5 ms to 10 ms. Write 0x02 to Register 0x0200 (two DDC mode). Write 0x06 to Register 0x0201 (chip decimation ratio = 10). Write 0x47 to Register 0x0310 (6 dB gain, decimation ratio set by Register 0x0311, Bits[7:4]). Write 0x20 to Register 0x0311 (decimate by 10, DDC0 inputs from Channel A). Register 0x0316 to Register 0x031B is the DDC0 NCO tuning word. Write 0x47 to Register 0x0330 (6 dB gain, decimation ratio set by Register 0x0331, Bits[7:4]). Write 0x25 to Register 0x0331 (decimate by 10, DDC1 inputs from Channel B). Register 0x0336 to Register 0x033B is the DDC0 NCO tuning word. Write 0x15 to Register 0x0571 (JESD204B link power down). Write 0x81 to Register 0x058B (scrambling enabled, L = 2). Write 0x03 to Register 0x058E (M = 4). Write 0x03 to Register 0x058C (F = 4). Write 0x00 to Register 0x056E (lane rate = 6.75 Gbps to 13.5 Gbps). Write 0x14 to Register 0x0571 (JESD204B link power up). Wait 5 ms to 10 ms. Read Register 0x056F (PLL status register). Write 0x4F to Register 0x1228. Write 0x0F to Register 0x1228. Write 0x00 to Register 0x1222. Write 0x04 to Register 0x1222. Write 0x00 to Register 0x1222. Write 0x08 to Register 0x1262. Write 0x00 to Register 0x1262. Data Sheet AD9689 DETERMINISTIC LATENCY SUBCLASS 1 OPERATION Both ends of the JESD204B link contain various clock domains distributed throughout each system. Data traversing from one clock domain to a different clock domain can lead to ambiguous delays in the JESD204B link. These ambiguities lead to nonrepeatable latencies across the link from one power cycle or link reset to the next. Section 6 of the JESD204B specification addresses the issue of deterministic latency with mechanisms defined as Subclass 1 and Subclass 2. The JESD204B protocol organizes data samples into octets, frames, and multiframes as described in the Transport Layer section. The LMFC is synchronous with the beginnings of these multiframes. In Subclass 1 operation, the SYSREF signal synchronizes the LMFCs for each device in a link or across multiple links (within the AD9689, SYSREF also synchronizes the internal sample dividers), as shown in Figure 143. The JESD204B receiver uses the multiframe boundaries and buffering to achieve consistent latency across lanes (or even multiple devices), and to achieve a fixed latency between power cycles and link reset conditions. The AD9689 supports JESD204B Subclass 0 and Subclass 1 operation. Register 0x0590, Bits[7:5] set the subclass mode for the AD9689 and its default is set for Subclass 1 operating mode (Register 0x0590, Bit 5 = 1). If deterministic latency is not a system requirement, Subclass 0 operation is recommended and the SYSREF signal may not be required. Even in Subclass 0 mode, the SYSREF signal may be required in an application where multiple AD9689 devices must be synchronized with each other. This topic is addressed in the Timestamp Mode section. Deterministic Latency Requirements Several key factors are required for achieving deterministic latency in a JESD204B Subclass 1 system. • • SUBCLASS 0 OPERATION If there is no requirement for multichip synchronization while operating in Subclass 0 mode (Register 0x0590, Bits[7:5] = 0 decimal), the SYSREF input can be left disconnected. In this mode, the relationship of the JESD204B clocks between the JESD204B transmitter and receiver are arbitrary, but does not affect the ability of the receiver to capture and align the lanes within the link. • SYSREF± signal distribution skew within the system must be less than the desired uncertainty for the system. SYSREF± setup and hold time requirements must be met for each device in the system. The total latency variation across all lanes, links, and devices must be ≤1 LMFC periods (see Figure 143). This includes both variable delays and the variation in fixed delays from lane to lane, link to link, and device to device in the system. SYSREF DEVICE CLOCK SYSREF ALIGNED GLOBAL LMFC SYSREF TO LMFC DELAY ALL LMFCs DATA ILAS Figure 143. SYSREF and LMFC Rev. A | Page 83 of 134 DATA 15550-313 POWER CYCLE VARIATION (MUST BE < tLMFC) AD9689 Data Sheet Setting Deterministic Latency Registers timing. Consult the applicable JESD204B receiver user guide for details on making this adjustment. The JESD204B receiver in the logic device buffers data starting on the LMFC boundary. If the total link latency in the system is near an integer multiple of the LMFC period, it is possible that from one power cycle to the next, the data arrival time at the receive buffer may straddle an LMFC boundary. To ensure deterministic latency in this case, a phase adjustment of the LMFC at either the transmitter or receiver must be performed. Typically, adjustments to accommodate the receive buffer are made to the LMFC of the receiver. Alternatively, this adjustment can be made in the AD9689 using the LMFC offset register (Register 0x0578, Bits[4:0]). This adjustment delays the LMFC in frame clock increments, depending on the F parameter (number of octets per lane per frame). For F = 1, every fourth setting (0, 4, 8, and so on) is valid and results in a four frame clock shift. For F = 2, every other setting (0, 2, 4, and so on) is valid and results in a two-frame clock shift. For all other values of F, each setting results in a one-frame clock shift. Figure 144 shows that, when the link latency is near an LMFC boundary, the local LMFC of the AD9689 can be adjusted to delay the data arrival time at the receiver. Figure 145 shows how the LMFC of the receiver is delayed to accommodate the receive buffer If the total latency in the system is not near an integer multiple of the LMFC period or if the appropriate adjustments have been made to the LMFC phase at the clock source, it is still possible to have variable latency from one power cycle to the next. By design, the AD9689 has circuitry in place to minimize this variation from power-up to power-up. In this case, the user must check for the possibility that the setup and hold time requirements for the SYSREF signal are not being met, by reading the SYSREF± setup/hold status bits (Register 0x0128). This function is fully described in the SYSREF± Setup/Hold Window Monitor section. If reading Register 0x0128 indicates there may be a timing problem, a few adjustments can be made in the AD9689. Changing the SYSREF level that is used for alignment is possible using the SYSREF± transition select bit (Register 0x0120, Bit 4). Also, changing which edge of CLK± is used to capture SYSREF can be done using the CLK± edge select bit (Register 0x0120, Bit 3). Both of these options are described in the SYSREF Control Features section. If neither of these measures helps to achieve an acceptable setup and hold time, adjusting the phase of SYSREF and/or the device clock (CLK±) may be required. POWER CYCLE VARIATION LMFCTX DELAY TIME SYSREF ALIGNED GLOBAL LMFC Tx LOCAL LMFC ILAS DATA (AT Rx INPUT) DATA ILAS DATA Tx LMFC MOVED (DELAYING THE ARRIVAL OF DATA RELATIVE TO THE GLOBAL LMFC) SO THE RECIEVE BUFFER RELEASE TIME IS ALWAYS REFERENCED TO THE SAME LMFC EDGE 15550-314 DATA (AT Tx INPUT) Figure 144. Adjusting the JESD204B Tx LMFC in the AD9689 LMFCRX DELAY TIME POWER CYCLE VARIATION SYSREF ALIGNED GLOBAL LMFC DATA (AT Tx INPUT) DATA (AT Rx INPUT) DATA ILAS ILAS ILAS DATA Rx LMFC MOVED SO THE RECEIVE BUFFER RELEASE TIME IS ALWAYS REFERENCED TO THE SAME LMFC EDGE Figure 145. Adjusting the JESD204B Rx LMFC in the Logic Device Rev. A | Page 84 of 134 15550-315 Rx LOCAL LMFC Data Sheet AD9689 MULTICHIP SYNCHRONIZATION The flowchart in Figure 147 shows the internal mechanism for multichip synchronization in the AD9689. There are two methods by which multichip synchronization can take place, as determined by the synchronization mode bit (Register 0x01FF, Bit 0). Each method involves different applications of the SYSREF signal. In this mode, SYSREF resets the sample dividers and the JESD204B clocking. When the chip sync mode is set to 1, the clocks are not reset; instead, the coinciding sample is timestamped using the JESD204B control bits of that sample. To operate in timestamp mode, these additional settings are necessary: NORMAL MODE • The default sate of the chip synchronization mode bit is 0, which configures the AD9689 for normal chip synchronization. The JESD204B standard specifies the use of SYSREF to provide for deterministic latency within a single link. This same concept, when applied to a system with multiple converters and logic devices, can also provide multichip synchronization referred to as normal mode (see Figure 147). Following the process in the flowchart ensures that the AD9689 is configured appropriately. The user must also consult the logic devices user IP guide to ensure that the JESD204B receivers are configured appropriately. TIMESTAMP MODE For all AD9689 full bandwidth operating modes, the SYSREF input can also be used to timestamp samples, another method by which multiple channels and multiple devices can achieve synchronization. This method is especially effective when synchronizing multiple devices to one or more logic devices. The logic devices buffer the data streams, identify the timestamped samples, and align them. When the synchronization mode bit (Register 0x01FF, Bit 0) is set to 1, the timestamp method is used for synchronization of multiple channels and/or devices. Continuous or N-shot SYSREF must be enabled (Register 0x0120, Bits[2:1] = 1 or 2 decimal). At least one control bit must be enabled (Register 0x058F, Bits[7:6] = 1, 2, or 3 decimal). Set the function for one of the control bits to SYSREF: Register 0x0559, Bits[3:0] = 5 decimal if using Control Bit 0, Register 0x0559, Bits[7:4] = 5 decimal if using Control Bit 1, Register 0x055A, Bits[3:0] = 5 decimal if using Control Bit 2. • • Figure 146 shows how the input sample coincident with SYSREF is timestamped and ultimately output from the ADC. In this example, there are two control bits, and Control Bit 0 is the bit indicating which sample was coincident with the SYSREF rising edge. Note that the pipeline latencies for each channel are identical. If so desired, the SYSREF± timestamp delay register (Register 0x0123) can be used to adjust the timing of which sample is time stamped. Note that time stamping is not supported by any AD9689 operating modes that use decimation. 14-BIT SAMPLES OUT N–1 N+1 N+2 N+3 N – 1 00 N CONTROL BIT 0 USED TO TIME STAMP SAMPLE N ENCODE CLK SYSREF AINB 01 N + 1 00 N + 2 00 N + 3 00 CHANNEL A N–1 N N+1 N+2 N+3 CHANNEL B N – 1 00 N 01 N + 1 00 N + 2 00 N + 3 00 2 CONTROL BITS 15550-316 AINA N Figure 146. AD9689 Timestamping Example—CS = 2 (Register 0x058F, Bits[7:6] = 2 Decimal), Control Bit 0 is SYSREF (Register 0x0559, Bits[3:0] = 5 Decimal) Rev. A | Page 85 of 134 AD9689 Data Sheet INCREMENT SYSREF IGNORE COUNTER START NO NO RESET SYSREF IGNORE COUNTER NO SYSREF ENABLED? (0x0120) YES SYSREF ASSERTED? SYSREF MODE (0x0120) YES SYSREF IGNORE COUNTER EXPIRED? (0x0121) N-SHOT MODE YES CONTINUOUS MODE CLEAR SYSREF IGNORE COUNTER AND DISABLE SYSREF (CLEAR BIT 2 IN 0x0120) UPDATE SETUP/HOLD DETECTOR STATUS (0x0128) ALIGN CLOCK DIVIDER PHASE TO SYSREF YES INPUT CLOCK DIVIDER ALIGNMENT REQUIRED? NO SYNCHRONIZATION MODE? (0x01FF) TIMESTAMP MODE SYSREF TIMESTAMP DELAY (0x0123) YES CLOCK DIVIDER AUTO ADJUST ENABLED? CLOCK DIVIDER >1? (0x010B) YES NO INCREMENT SYSREF COUNTER (0x012A) NO SYSREF ENABLED IN CONTROL BITS? (0x0559, 0x055A, 0x058F) SYSREF INSERTED IN JESD204B CONTROL BITS YES NO RAMP TEST MODE ENABLED? (0x0550) NORMAL MODE SYSREF RESETS RAMP TEST MODE GENERATOR YES BACK TO START NO JESD204B LMFC ALIGNMENT REQUIRED? YES ALIGN PHASE OF ALL INTERNAL CLOCKS (INCLUDING LMFC) TO SYSREF SEND INVALID 8-BIT/ 10-BIT CHARACTERS (ALL 0s) SYNC~ ASSERTED NO NO SEND K28.5 CHARACTERS NORMAL JESD204B INITIALIZATION NO YES ALIGN SIGNAL MONITOR COUNTERS DDC NCO ALIGNMENT ENABLED? (0x0300) YES ALIGN DDC NCO PHASE ACCUMULATOR BACK TO START NO 15550-317 SIGNAL MONITOR ALIGNMENT ENABLED? (0x026F) YES Figure 147. SYSREF Capture Scenarios and Multichip Synchronization Rev. A | Page 86 of 134 Data Sheet AD9689 HOLD REQUIREMENT 95ps SYSREF KEEP OUT WINDOW SYSREF Control Features Figure 148. SYSREF Setup and Hold Time Requirements—SYSREF Low to High Transition Using Rising Edge Clock (Default) SETUP REQUIREMENT –65ps HOLD REQUIREMENT 95ps SYSREF SAMPLE POINT CLK SYSREF Figure 149. SYSREF Low to High Transition Using Falling Edge Clock Capture (Register 0x0120, Bit 4 = 1’b0; Register 0x0120, Bit 3 = 1’b1) SETUP REQUIREMENT –65ps HOLD REQUIREMENT 95ps SYSREF SAMPLE POINT CLK SYSREF SYSREF is used, along with the input clock (CLK), as part of a source-synchronous timing interface and requires setup and hold timing requirements of −65 ps and 95 ps relative to the input clock (see Figure 148). The AD9689 has several features that aid the user in meeting these requirements. First, the SYSREF sample event can be defined as either a synchronous low to high transition or synchronous high to low transition. Second, the AD9689 allows the SYSREF signal to be sampled using either the rising edge or falling edge of the input clock. Figure 148, Figure 149, Figure 150, and Figure 151 show all four possible combinations. 15550-318 CLK where: S is the JESD204B parameter for number of samples per converter. K is the number of frames per multiframe. The input clock divider, DDCs, signal monitor block, and JESD204B link are all synchronized using the SYSREF± input when in normal synchronization mode (Register 0x01FF, Bit 0 = 0). The SYSREF± input can also be used to timestamp an ADC sample to provide a mechanism for synchronizing multiple AD9689 devices in a system. For the highest level of timing accuracy, SYSREF± must meet setup and hold requirements relative to the CLK± input. There are several features in the AD9689 that can be used to ensure these requirements are met; these features are described in the SYSREF Control Features section. SYSREF SAMPLE POINT 15550-319 LMFC = ADC clock/(S × K) SETUP REQUIREMENT –65ps 15550-320 The SYSREF input signal is used as a high accuracy system reference for deterministic latency and multichip synchronization. The AD9689 accepts a single-shot or periodic input signal. The SYSREF± mode select bits (Register 0x0120, Bits[2:1]) select the input signal type and arm the SYSREF state machine when set. If in single (or N) shot mode (Register 0x0120, Bits[2:1] = 2 decimal), the SYSREF± mode select bit self clears after the appropriate SYSREF transition is detected. The pulse width must have a minimum width of two CLK± periods. If the clock divider (Register 0x010B, Bits[3:0]) is set to a value other than divide by 1, multiply this minimum pulse width requirement by the divide ratio (that is, if set to divide by 8, the minimum pulse width is 16 CLK± cycles). When using a continuous SYSREF signal (Register 0x0120, Bits[2:1] = 1 decimal), the period of the SYSREF signal must be an integer multiple of the LMFC. LMFC can be derived using the following formula: The AD9689 is able to ignore N SYSREF events (note that the SYSREF ignore feature is enabled by setting the SYSREF± mode select bits (Register 0x0120, Bits[2:1]) to 2'b10, N-shot mode). This feature is useful for handling periodic SYSREF signals, which need time to settle after startup. Ignoring SYSREF until the clocks in the system have settled can avoid an inaccurate SYSREF trigger. Figure 152 shows an example of the SYSREF ignore feature when ignoring three SYSREF events. Figure 150. SYSREF High to Low Transition Using Rising Edge Clock Capture (Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b0) SETUP REQUIREMENT –65ps HOLD REQUIREMENT 95ps SYSREF SAMPLE POINT CLK SYSREF 15550-321 SYSREF INPUT Figure 151. SYSREF High to Low Transition Using Falling Edge Clock Capture (Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b1) The third SYSREF related feature available is the ability to ignore a programmable number (up to 16) of SYSREF events. Rev. A | Page 87 of 134 AD9689 Data Sheet SYSREF SAMPLE PART 1 SYSREF SAMPLE PART 2 SYSREF SAMPLE PART 3 SYSREF SAMPLE PART 4 SYSREF SAMPLE PART 5 CLK 15550-322 SYSREF SAMPLE THE FOURTH SYSREF IGNORE FIRST THREE SYSREFs Figure 152. SYSREF Ignore Example (SYSREF Ignore Count, Register 0x0121, Bits[3:0] = 3) SYSREF SKEW WINDOW = ±3 SYSREF SKEW WINDOW = ±2 SYSREF SKEW WINDOW = ±1 SYSREF SKEW WINDOW = 0 15550-323 SAMPLE CLOCK SYSREF Figure 153. SYSREF Skew Window When in continuous SYSREF mode (Register 0x0120, Bits[2:1] = 1), the AD9689 monitors the placement of the SYSREF leading edge compared to the internal LMFC. If the SYSREF signal is captured with a clock edge other than the one that is aligned with the LMFC, the AD9689 initiates a resynchronization of the link. Because input clock rates for AD9689 can be up to 4 GHz, the AD9689 provides another SYSREF related feature that makes it possible to accommodate periodic SYSREF signals where cycle accurate capture is not feasible or not required. For these scenarios, the AD9689 has a programmable SYSREF skew window that allows the internal dividers to remain undisturbed unless SYSREF occurs outside the skew window. The resolution of the SYSREF skew window is set in sample clock cycles. If the SYSREF negative skew window is 1 and the positive skew window is 1, the total skew window is ±1 sample clock cycles, meaning that, as long as SYSREF is captured within ±1 sample clock cycle of the clock that is aligned with the LMFC, the link continues to operate normally. If the SYSREF has jitter, which can cause a misalignment between SYSREF and LMFC, this feature allows the system to continue running without a resynchronization, while still allowing the device to monitor for larger errors not caused by jitter. For the AD9689, the positive and negative skew window is controlled by the SYSREF window negative bits (Register 0x0122, Bits[3:2]) and SYSREF window positive bits (Register 0x0122, Bits[1:0]). Figure 153 shows information on the location of the skew window settings relative to Phase 0 of the internal dividers. Negative skew is defined as occurring before the internal dividers reach Phase 0, and positive skew is defined after the internal dividers reach Phase 0. Rev. A | Page 88 of 134 Data Sheet AD9689 SYSREF± SETUP/HOLD WINDOW MONITOR To ensure a valid SYSREF signal capture, the AD9689 has a SYSREF± setup/hold window monitor. This feature allows the system designer to determine the location of the SYSREF± signals relative to the CLK± signals by reading back the amount of setup/hold margin on the interface through the memory map. Figure 154 and Figure 155 show the setup and hold status values for different phases of SYSREF±. The setup detector returns the status of the SYSREF± signal before the CLK± edge, and the hold detector returns the status of the SYSREF signal after the CLK± edge. Register 0x0128 stores the status of SYSREF± and notifies the user if the SYSREF± signal is captured by the ADC. Table 36 shows the description of the contents of Register 0x0128 and how to interpret them. 0xF 0xE 0xD 0xC 0xB 0xA 0x9 REG 0x0128[3:0] 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 CLK± INPUT FLIP FLOP HOLD (MIN) FLIP FLOP SETUP (MIN) FLIP FLOP HOLD (MIN) Figure 154. SYSREF± Setup Detector Rev. A | Page 89 of 134 15550-070 VALID SYSREF± INPUT AD9689 Data Sheet 0xF 0xE 0xD 0xC 0xB 0xA 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 REG 0x0128[7:4] 0x0 CLK± INPUT SYSREF± INPUT FLIP FLOP SETUP (MIN) FLIP FLOP HOLD (MIN) FLIP FLOP HOLD (MIN) 15550-071 VALID Figure 155. SYSREF± Hold Detector Table 36. SYSREF± Setup/Hold Monitor, Register 0x0128 Register 0x0128, Bits[7:4] Hold Status 0x0 0x0 to 0x8 0x8 0x8 0x9 to 0xF 0x0 Register 0x0128, Bits[3:0] Setup Status 0x0 to 0x7 0x8 0x9 to 0xF 0x0 0x0 0x0 Description Possible setup error. The smaller this number, the smaller the setup margin. No setup or hold error (best hold margin). No setup or hold error (best setup and hold margin). No setup or hold error (best setup margin). Possible hold error. The larger this number, the smaller the hold margin. Possible setup or hold error. Rev. A | Page 90 of 134 Data Sheet AD9689 LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS Total latency in the AD9689 is dependent on the chip application mode and the JESD204B configuration. For any given combination of these parameters, the latency is deterministic; however, the value of this deterministic latency must be calculated as described in the Example Latency Calculations section. Example Configuration 1 is as follows: Table 37 shows the combined latency through the ADC and digital signal processor (DSP) for the different chip application modes supported by the AD9689. Table 38 shows the latency through the JESD204B block for each application mode based on the M/L ratio. For Table 37 and Table 38, latency is typical and is in units of the encode clock. The latency through the JESD204B block does not depend on the output data type (real or complex). Therefore, data type is not included in Table 38. To determine the total latency, select the appropriate ADC + DSP latency from Table 37 and add it to the appropriate JESD204B latency from Table 38. Example calculations are provided in the following section. • • • • • ADC application mode = full bandwidth Real outputs L = 8, M = 2, F = 1, S = 2 (JESD204B mode) 20 × (M/L) = 5 Latency = 31 + 44 = 75 encode clocks Example Configuration 2 is as follows: • • • • • ADC application mode = DCM4 Complex outputs L = 4, M = 2, F = 1, S = 1 (JESD204B mode) 20 × (M/L) = 10 Latency = 162 + 88 = 250 encode clocks LMFC REFERENCED LATENCY Some FPGA vendors may require the end user to know the LMFC referenced latency to make appropriate deterministic latency adjustments. If they are required, use the latency values in Table 37 and Table 38 for the analog in to LMFC and LMFC to data out latency values. Table 37. Latency Through the ADC + DSP Blocks (Number of Sample Clocks) 1 Chip Application Mode Full Bandwidth DCM1 (Real) DCM2 (Complex) DCM3 (Complex) DCM2 (Real) DCM4 (Complex) DCM3 (Real) DCM6 (Complex) DCM4 (Real) DCM8 (Complex) DCM5 (Real) DCM10 (Complex) DCM6 (Real) DCM12 (Complex) DCM15 (Real) DCM8 (Real) DCM16 (Complex) DCM10 (Real) DCM20 (Complex) DCM12 (Real) DCM24 (Complex) DCM30 (Complex) DCM20 (Real) DCM40 (Complex) DCM24 (Real) DCM48 (Complex) 1 Enabled Filters Not applicable HB1 HB1 TB1 HB2 + HB1 HB2 + HB1 TB2 + HB1 TB2 + HB1 HB3 +HB2 + HB1 HB3 +HB2 + HB1 FB2 + HB1 FB2 + HB1 TB2 + HB2 + HB1 TB2 + HB2 + HB1 FB2 + TB1 HB4 + HB3 + HB2 + HB1 HB4 + HB3 + HB2 + HB1 FB2 + HB2 + HB1 FB2 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 HB2 + FB2 + TB1 FB2 + HB3 + HB2 + HB1 FB2 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 DCMx indicates the decimation ratio. Rev. A | Page 91 of 134 ADC + DSP Latency 31 90 90 102 162 162 212 212 292 292 380 380 424 424 500 552 552 694 694 814 814 836 1420 1420 1594 1594 AD9689 Data Sheet Table 38. Latency Through JESD204B Block (Number of Sample Clocks) 1 Chip Application Mode Full Bandwidth DCM1 DCM2 DCM3 DCM4 DCM5 DCM6 DCM8 DCM10 DCM12 DCM15 DCM16 DCM20 DCM24 DCM30 DCM40 DCM48 0.125 82 82 160 237 315 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.25 44 44 84 124 164 203 3 243 323 N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.5 25 25 46 67 88 1093 130 172 213 255 318 4 3394 N/A N/A N/A N/A N/A M/L Ratio 2 1 14 14 27 39 50 623 73 96 119 142 1764 1884 233 279 3484 N/A N/A N/A means not applicable and indicates that the application mode is not supported at the M/L ratio listed. M/L ratio is the number of converters divided by the number of lanes for the configuration. 3 The application mode at the M/L ratio listed is only supported in real output mode. 4 The application mode at the M/L ratio listed is only supported in complex output mode. 1 2 Rev. A | Page 92 of 134 2 7 7 14 21 27 433 39 50 62 73 904 964 119 142 1764 2334 2794 4 9 N/A 7 11 14 N/A 21 27 33 39 474 504 62 73 904 1194 1424 8 3 N/A N/A N/A 9 N/A 14 18 22 27 334 354 43 51 624 824 974 Data Sheet AD9689 TEST MODES ADC TEST MODES If the application mode is set to select a DDC mode of operation, the test modes must be enabled for each DDC enabled. The test patterns can be enabled via Bit 2 and Bit 0 of Register 0x0327, Register 0x0347, and Register 0x0367, depending on which DDC(s) are selected. The (I) data uses the test patterns selected for Channel A, and the (Q) data uses the test patterns selected for Channel B. For DDC3 only, the (I) data uses the test patterns from Channel A, and the (Q) data does not output test patterns. Bit 0 of Register 0x0387 selects the Channel A test patterns to be used for the (I) data. For more information, see the AN-877 Application Note. The AD9689 has various test options that aid in the system level implementation. The AD9689 has ADC test modes that are available in Register 0x0550. These test modes are described in Table 39. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks, and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The pseudorandom number (PN) generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0550. These tests can be performed with or without an analog signal (if present, the analog signal is ignored); however, they do require an encode clock. A5 A4 A3 A2 A1 A0 C2 T OCTET1 MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 OCTET0 TAIL BITS 0x0571[6] OCTET1 JESD204B SAMPLE CONSTRUCTION SCRAMBLER 1 + x14 + x15 (OPTIONAL) MSB S7 S6 S5 S4 S3 S2 S1 LSB S0 S7 S6 S5 S4 S3 S2 S1 S0 8-BIT/ 10-BIT ENCODER SERIALIZER a b i j a b SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± i j SYMBOL0 SYMBOL1 a b c d e f g h i j a b c d e f g h i j C2 C1 C0 15550-059 CONTROL BITS FRAME CONSTRUCTION OCTET0 ADC TEST PATTERNS (0x0550, 0x0551 TO 0x0558) MSB A13 A12 A11 A10 A9 ADC A8 A7 A6 A5 A4 A3 A2 A1 LSB A0 JESD204B DATA LINK LAYER TEST PATTERNS 0x0574[2:0] JESD204B INTERFACE TEST PATTERN (0x0573, 0x0551 TO 0x0558) JESD204B LONG TRANSPORT TEST PATTERN 0x0571[5] Figure 156. ADC Output Datapath Showing Test Pattern Injection Points Table 39. ADC Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 Pattern Name Off (default) Midscale short Positive full-scale short Negative full-scale short Checkerboard PN sequence long PN sequence short One-/zero-word toggle User input Expression Not applicable 0000 0000 0000 01 1111 1111 1111 10 0000 0000 0000 10 1010 1010 1010 x23 + x18 + 1 x9 + x5 + 1 11 1111 1111 1111 Register 0x0551 to Register 0x0558 1111 Ramp output (x) % 214 Default/ Seed Value Not applicable Not applicable Not applicable Not applicable Not applicable 0x3AFF 0x0092 Not applicable Not applicable Not applicable Rev. A | Page 93 of 134 Sample (N, N + 1, N + 2, …) Not applicable Not applicable Not applicable Not applicable 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6 0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000 User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2] … for repeat mode User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], 0x0000 … for single mode (x) % 214, (x +1) % 214, (x +2) % 214, (x +3) % 214 AD9689 Data Sheet JESD204B BLOCK TEST MODES In addition to the ADC pipeline test modes, the AD9689 also has flexible test modes in the JESD204B block. These test modes are listed in Register 0x0573 and Register 0x0574. These test patterns can be inserted at various points along the output datapath. These test insertion points are shown in Figure 156. Table 40 describes the various test modes available in the JESD204B block. For the AD9689, a transition from test modes (Register 0x0573 ≠ 0x00) to normal mode (Register 0x0573 = 0x00) requires an SPI soft reset, which is done by writing 0x81 to Register 0x0000 (self cleared). Transport Layer Sample Test Mode These tests are shown in Register 0x0571, Bit 5. The test pattern is equivalent to the raw samples from the ADC. Interface Test Modes The interface test modes are described in Register 0x0573, Bits[3:0]. These test modes are also explained in Table 40. The interface tests can be inserted at various points along the data. See Figure 156 for more information on the test insertion points. Register 0x0573, Bits[5:4] show where these tests are inserted. Table 41, Table 42, and Table 43 show examples of some of the test modes when inserted at the JESD204B sample input, physical 10bit input, and scrambler 8-bit input. UPx in Table 41 to Table 43 represent the user pattern control bits from the user register map. The transport layer samples are implemented in the AD9689 as defined by Section 5.1.6.3 in the JEDEC JESD204B specification. Table 40. JESD204B Interface Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1110 1111 Pattern Name Off (default) Alternating checker board 1/0 word toggle 31-bit PN sequence 23-bit PN sequence 15-bit PN sequence 9-bit PN sequence 7-bit PN sequence Ramp output Continuous/repeat user test Single user test Expression Not applicable 0x5555, 0xAAAA, 0x5555, … 0x0000, 0xFFFF, 0x0000, … x31 + x28 + 1 x23 + x18 + 1 x15 + x14 + 1 x9 + x 5 + 1 x7 + x 6 + 1 (x) % 216 Register 0x0551 to Register 0x0558 Register 0x0551 to Register 0x0558 Default Not applicable Not applicable Not applicable 0x0003AFFF 0x003AFF 0x03AF 0x092 0x07 Ramp size depends on test insertion point User Pattern 1 to User Pattern 4, then repeat User Pattern 1 to User Pattern 4, then zeros Table 41. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 2'b00) Frame Number 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 Converter Number 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Sample Number 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Alternating Checkerboard 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 1/0 Word Toggle 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 Ramp (x) % 216 (x) % 216 (x) % 216 (x) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 (x +4) % 216 (x +4) % 216 (x +4) % 216 (x +4) % 216 Rev. A | Page 94 of 134 PN9 0x496F 0x496F 0x496F 0x496F 0xC9A9 0xC9A9 0xC9A9 0xC9A9 0x980C 0x980C 0x980C 0x980C 0x651A 0x651A 0x651A 0x651A 0x5FD1 0x5FD1 0x5FD1 0x5FD1 PN23 0xFF5C 0xFF5C 0xFF5C 0xFF5C 0x0029 0x0029 0x0029 0x0029 0xB80A 0xB80A 0xB80A 0xB80A 0x3D72 0x3D72 0x3D72 0x3D72 0x9B26 0x9B26 0x9B26 0x9B26 User Repeat UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] User Single UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] 0x0000 0x0000 0x0000 0x0000 Data Sheet AD9689 Table 42. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 2'b01) 10-Bit Symbol Number 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 1/0 Word Toggle 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF Ramp (x) % 210 (x + 1) % 210 (x + 2) % 210 (x + 3) % 210 (x + 4) % 210 (x + 5) % 210 (x + 6) % 210 (x + 7) % 210 (x + 8) % 210 (x + 9) % 210 (x + 10) % 210 (x + 11) % 210 PN9 0x125 0x2FC 0x26A 0x198 0x031 0x251 0x297 0x3D1 0x18E 0x2CB 0x0F1 0x3DD PN23 0x3FD 0x1C0 0x00A 0x1B8 0x028 0x3D7 0x0A6 0x326 0x10F 0x3FD 0x31E 0x008 User Repeat UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] User Single UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 Table 43. Scrambler 8-Bit Input (Register 0x0573, Bits[5:4] = 2'b10) 8-Bit Octet Number 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 1/0 Word Toggle 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF Ramp (x) % 28 (x + 1) % 28 (x + 2) % 28 (x + 3) % 28 (x + 4) % 28 (x + 5) % 28 (x + 6) % 28 (x + 7) % 28 (x + 8) % 28 (x + 9) % 28 (x + 10) % 28 (x + 11) % 28 Data Link Layer Test Modes The data link layer test modes are implemented in the AD9689 as defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification. These tests are shown in Register 0x0574, Bits[2:0]. PN9 0x49 0x6F 0xC9 0xA9 0x98 0x0C 0x65 0x1A 0x5F 0xD1 0x63 0xAC PN23 0xFF 0x5C 0x00 0x29 0xB8 0x0A 0x3D 0x72 0x9B 0x26 0x43 0xFF User Repeat UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] User Single UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Test patterns inserted at this point are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINB± by writing 0xC0 to Register 0x0572. Rev. A | Page 95 of 134 AD9689 Data Sheet SERIAL PORT INTERFACE The AD9689 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the Serial Control Interface Standard (Rev. 1.0). CONFIGURATION USING THE SPI Three pins define the SPI of the AD9689 ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 44). The SCLK (serial clock) pin synchronizes the read and write data presented from/to the ADC. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 44. SPI Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input that is used to synchronize serial interface, reads, and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 4 and Table 5. Other modes involving the CSB pin are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued, which allows the SDIO pin to change direction from an input to an output. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the Serial Control Interface Standard (Rev. 1.0). HARDWARE INTERFACE The pins described in Table 44 comprise the physical interface between the user programming device and the serial port of the AD9689. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note. Do not activate the SPI port during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9689 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SPI ACCESSIBLE FEATURES Table 45 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the Serial Control Interface Standard (Rev. 1.0). The AD9689 device specific features are described in the Memory Map section. Table 45. Features Accessible Using the SPI Feature Mode Clock DDC Test Input/Output Output Mode Serializer/Deserializer (SERDES) Output Setup Description Allows the user to set either power-down mode or standby mode. Allows the user to access the clock divider via the SPI. Allows the user to set up decimation filters for different applications. Allows the user to set test modes to have known data on output bits. Allows the user to set up outputs. Allows the user to vary SERDES settings such as swing and emphasis. Rev. A | Page 96 of 134 Data Sheet AD9689 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Default Values Each address in the memory map register table has eight bit locations. The memory map is divided into the following sections: After the AD9689 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register tables, Table 46 to Table 53. • Logic Levels • • • • • • • Analog Devices SPI registers (Register 0x0000 to Register 0x000F) Clock/SYSREF/chip power-down pin control registers (Register 0x003F to Register 0x01FF) Chip operating mode control registers (Register 0x0200 to Register 0x0201) Fast detect and signal monitor control registers (Register 0x0245 to Register 0x027A) DDC function registers (Register 0x0300 to Register 0x03CD) Digital outputs and test modes registers (Register 0x0550 to Register 0x05CB and Register 0x1222 to Register 0x01262) Programmable filter control and coefficients registers (Register 0x0DF8 to Register 0x0F7F) VREF/analog input control registers (Register 0x18A6 to Register 0x1A4D and Register 0x0701 to Register 0x073B) The Memory Map Register Details section documents the default hexadecimal value for each hexadecimal address shown. For example, Address 0x0561, the output sample mode register, has a hexadecimal default value of 0x01, which means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see Table 46 to Table 53. Open and Reserved Locations All address and bit locations that are not included in Table 46 to Table 53 are not currently supported for this device. Write unused bits of a valid address location with 0s unless the default value is set otherwise. Writing to these locations is required only when part of an address location is unassigned (for example, Address 0x0561). If the entire address location is open (for example, Address 0x0013), do not write to this address location. An explanation of logic level terminology follows: • • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” X denotes a don’t care bit. Channel Specific Registers Some channel setup functions, such as the buffer control register (Register 0x1A4C), can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x0008. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an SPI read cycle, the device returns the value for Channel A. All other registers and bits are considered global, and changes to these registers and bits affect the entire device and the channel features for which independent settings are not allowed between channels. The settings in Register 0x0005 do not affect the global registers and bits. SPI Soft Reset After issuing a soft reset by programming 0x81 to Register 0x0000, the AD9689 requires 5 ms to recover. When programming the AD9689 for application setup, ensure that an adequate delay is programmed into the firmware after asserting the soft reset and before starting the device setup. Rev. A | Page 97 of 134 AD9689 Data Sheet MEMORY MAP REGISTER DETAILS All address locations that are not included in Table 46 to Table 53 are not currently supported for this device and must not be written. Analog Devices SPI Registers Table 46. Addr. Name Bit(s) Bit Name Soft reset mirror 0x0000 SPI Configuration A 7 (self clearing) 6 5 [4:3] 2 1 0 Setting 0 1 Description Whenever a soft reset is issued, the user must wait 5 ms before writing to any other register, to provide sufficient time for the boot loader to complete. Do nothing. Reset the SPI and registers (self clearing). 1 0 Least significant bit shifted first for all SPI operations. Most significant bit shifted first for all SPI operations. 0 1 Multibyte SPI operations cause addresses to auto-decrement. Multibyte SPI operations cause addresses to auto-increment. Reserved. LSB first mirror Address ascension mirror Reserved Address ascension 0 1 Multibyte SPI operations cause addresses to auto-decrement. Multibyte SPI operations cause addresses to auto-increment. 1 0 Least significant bit shifted first for all SPI operations. Most significant bit shifted first for all SPI operations. Whenever a soft reset is issued, the user must wait 5 ms before writing to any other register, to provide sufficient time for the boot loader to complete. Do nothing. Reset the SPI and registers (self clearing). Reserved. LSB first Soft reset (self clearing) 0 1 0x0001 SPI Configuration B [7:2] 1 Reserved Datapath soft reset (self clearing) 0 1 0 0x0002 Chip configuration [7:2] (local) [1:0] Normal operation. Datapath soft reset (self clearing). Reserved. Reserved. Reserved Reserved Channel power mode 00 10 11 0x0003 Chip type [7:0] Chip type 0x3 0x0004 Chip ID LSB [7:0] Chip ID LSB[7:0] 0xD9 0x0005 Chip ID MSB 0x0006 Chip grade [7:0] [7:4] Chip ID MSB[15:8] Chip speed grade 0x0 0x1 0x0008 Device index [3:0] [7:2] 1 0 Reserved Reserved Channel B Channel power modes. Normal mode (power-up). Standby mode; digital datapath clocks disabled; JESD204B interface enabled. Power-down mode; digital datapath clocks disabled; digital datapath held in reset; JESD204B interface disabled. Chip type. High speed ADC. Chip ID. AD9689. Chip ID. Chip speed grade. 2.6 GSPS. 2.0 GSPS. Reserved. Reserved. 0 1 ADC Core B does not receive the next SPI command. ADC Core B receives the next SPI command. 0 1 ADC Core A does not receive the next SPI command. ADC Core A receives the next SPI command. Channel A Rev. A | Page 98 of 134 Reset Access 0x0 R/WC 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/WC 0x0 0x0 R R/WC 0x0 0x0 R R 0x0 R/W 0x03 R 0xE2 R 0x0 0x0 R R 0x0 0x0 0x1 R R R/W 0x1 R/W Data Sheet AD9689 Addr. Name 0x000A Scratch pad Bit(s) Bit Name [7:0] Scratch pad 0x000B SPI revision [7:0] SPI revision 0x000C Vendor ID LSB 0x000D Vendor ID MSB 0x000F Transfer [7:0] [7:0] [7:1] 0 Vendor ID LSB Vendor ID MSB Reserved Chip transfer Setting Description Chip scratch pad register. This register is used to provide a consistent memory location for software debug. SPI revision register. 0x01: Revision 1.0. 00000001 Revision 1.0. Vendor ID[7:0]. Vendor ID[15:8]. Reserved. Self clearing chip transfer bit. This bit is used to update the DDC FTW/POW/MAW/MBW increment and phase offset registers when DDC phase update mode (Register 0x0300, Bit 7) = 1, which makes it possible to synchronously update the DDC mixer frequencies. This bit is also used to update the coefficients for the programmable filter (PFILT). 0 Do nothing. Bit is only cleared after transfer is complete. Self clearing bit used to synchronize the transfer of data from 1 master to slave registers. Reset Access 0x0 R/W 0x1 R 0x56 0x04 0x0 0x0 R R R R/W Clock/SYSREF/Chip Power-Down Pin Control Registers Table 47. Addr. Name 0x003F Chip PDWN pin (local) 0x0040 Chip Pin Control 1 Bit(s) Bit Name Local chip PDWN pin 7 disable [6:0] [7:6] Setting Description Function is determined by Register 0x0040, Bits[7:6]. 0 1 Power-down pin (PDWN/STBY) enabled (default). Power-down pin (PDWN/STBY) disabled/ignored. Reserved. 0x0 External power-down pin functionality. Assertion of the external 0x0 power-down pin (PDWN/STBY) has higher priority than the channel power mode bits (Register 0x0002, Bits[1:0]). The PDWN/ STBY pin is only used when Register 0x0040, Bits[7:6] = 00 or 01. Power-down pin (default). Assertion of external power-down pin (PDWN/STBY) causes the chip to enter full power-down mode. Standby pin. Assertion of external power-down pin (PDWN/STBY) causes the chip to enter standby mode. Pin disabled. Power-down pin (PDWN/STBY) is ignored. Fast Detect B/GPIO B0 pin functionality. 0x7 Reserved Chip PDWN pin functionality 00 01 10 [5:3] Chip FD_B/GPIO_B0 pin functionality 000 001 110 111 [2:0] Chip FD_A/GPIO_A0 pin functionality 000 001 110 111 0x0041 Chip Pin Control 2 [7:4] Chip FD_B/GPIO_B0 pin secondary functionality 0000 0001 1000 1001 [3:0] Chip FD_A/GPIO_A0 pin secondary functionality 0000 0001 1000 1001 Fast Detect B output. JESD204B LMFC output. Pin functionality determined by Register 0x0041, Bits[7:4]. Disabled. Configured as input with weak pull-down (default). Fast Detect A/GPIO A0 pin functionality. Fast Detect A output. JESD204B LMFC output. Pin functionality determined by Register 0x0041, Bits[3:0]. Disabled. Configured as an input with weak pull-down (default). Fast Detect B/GPIO B0 pin secondary functionality (only used when Register 0x0040, Bits[5:3] = 110). Chip GPIO B0 input (NCO channel selection). Chip transfer input. Master next trigger output (MNTO). Slave next trigger input (SNTI). Fast Detect A/GPIO B0 pin secondary functionality (only used when Register 0x0040, Bits[2:0] = 110). Chip GPIO A0 input (NCO channel selection). Chip transfer input. Master next trigger output (MNTO). Slave next trigger input (SNTI). Rev. A | Page 99 of 134 Reset Access 0x0 R/W R R/W R/W 0x7 R/W 0x0 R/W 0x0 R/W AD9689 Addr. Name 0x0042 Chip Pin Control 3 Data Sheet Bit(s) Bit Name [7:4] Chip GPIO_B1 pin functionality [3:0] Setting Description GPIO B1 pin functionality. Reset Access 0xF R/W 0000 1000 1001 1111 Chip GPIO B1 input (NCO channel selection). Master next trigger output (MNTO). Slave next trigger input (SNTI). Disabled (configured as input with weak pull-down). GPIO A1 pin functionality. 0xF R/W 0x0 0x0 R R/W 0x0 R 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W Chip GPIO_B1 pin functionality 0000 1000 1001 1111 0x0108 Clock divider control [7:3] [2:0] Reserved Input clock divider (CLK± pins) 00 01 11 0x0109 Clock divider phase [7:4] (local) [3:0] Reserved 7 Clock divider auto phase adjust enable 0 1 [6:4] [3:2] Reserved Clock divider negative skew window 00 01 10 11 [1:0] Divide by 1. Divide by 2. Divide by 4. Reserved. Clock divider phase offset 0000 0001 0010 … 1110 1111 0x010A Clock divider and SYSREF control Chip GPIO A1 input (NCO channel selection). Master next trigger output (MNTO). Slave next trigger input (SNTI). Disabled (configured as input with weak pull-down). Reserved. Clock divider positive skew window 00 01 10 11 0 input clock cycles delayed. ½ input clock cycles delayed (invert clock). 1 input clock cycles delayed. … 7 input clock cycles delayed. 7½ input clock cycles delayed. Clock divider auto phase adjust enable. When enabled, Register 0x0129, Bits[3:0] contain the phase of the divider when SYSREF was captured. The actual divider phase offset = Register 0x0129, Bits[3:0] + Register 0x0109, Bits[3:0]. Clock divider phase is not changed by SYSREF (disabled). Clock divider phase is automatically adjusted by SYSREF (enabled). Reserved. Clock divider negative skew window (measured in ½ input device clocks). Number of ½ clock cycles before the input device clock by which captured SYSREF transitions are ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]. The skew allows some uncertainty in the sampling of SYSREF without disturbing the input clock divider. Also, SYSREF must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. No negative skew; SYSREF must be captured accurately. ½ device clock of negative skew. 1 device clocks of negative skew. 1½ device clocks of negative skew. Clock divider positive skew window (measured in ½ input device clocks). Number of clock cycles after the input device clock by which captured SYSREF transitions are ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]. The skew allows some uncertainty in the sampling of SYSREF without disturbing the input clock divider. Also, SYSREF must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. No positive skew; SYSREF must be captured accurately. ½ device clock of positive skew. 1 device clocks of positive skew. 1½ device clocks of positive skew. Rev. A | Page 100 of 134 Data Sheet Addr. Name 0x010B Clock divider SYSREF status AD9689 Bit(s) Bit Name [7:4] Reserved [3:0] 0x0110 Clock delay control [7:3] [2:0] Setting Clock divider SYSREF offset Reserved Clock delay mode select 000 010 011 100 110 0x0111 Clock super fine delay (local) [7:0] Clock super fine delay adjust 0x00 … 0x08 … 0x80 0x0112 Clock fine delay (local) [7:0] Set clock fine delay 0x00 … 0x08 … 0xC0 0x011B Clock status [7:1] 0 Reserved Input clock detect 0 1 0x011C Clock Duty Cycle Stabilizer 1 control (local) [7:2] Reserved 1 DCS1 enable 0 1 0 DCS1 power up 0 1 0x011E Clock Duty Cycle Stabilizer 2 control [7:2] Reserved 1 DCS2 enable 0 1 0 DCS2 power up 0 1 Description Reserved. Reset Access 0x0 R Clock divider phase status (measured in ½ clock cycles). Internal clock divider phase of the captured SYSREF signal applied to the phase offset. Only used when Register 0x010A, Bit 7 = 1. When Register 0x010A, Bit 7 = 1 and Register 0x010A, Bits[3:2] = 0 decimal and Register 0x010A, Bits[1:0] = 0 decimal, clock divider SYSREF offset = Register 0x0129, Bits[3:0]. Reserved. Clock delay mode select. Used in conjunction with Register 0x0111 and Register 0x0112. No clock delay. Fine delay: only 0 to 16 delay steps are valid. Fine delay (lowest jitter): only 0 to 16 delay steps are valid. Fine delay: all 192 delay steps are valid. Fine delay enabled (all 192 delay steps are valid); super fine delay enabled (all 128 delay steps are valid). Clock super fine delay adjust. This is an unsigned control to adjust the super fine sample clock delay in 0.25 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 010 or 110. 0 delay steps. … 8 delay steps. … 128 delay steps. Clock fine delay adjust. This is an unsigned control to adjust the fine sample clock skew in 1.725 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6. Minimum = 0. Maximum = 192. Increment = 1. Unit is delay steps. 0 delay steps. … 8 delay steps. … 192 delay steps. Reserved. Clock detection status. Input clock not detected. Input clock detected/locked. Reserved. 0x0 R 0x0 0x0 R R/W 0x0 R/W 0xC0 R/W 0x0 0x0 R R 0x0 R/W Clock DCS1 enable. DCS1 bypassed. DCS1 enabled. Clock DCS1 power-up. DCS1 powered down. DCS1 powered up. Reserved. 0x1 R/W 0x1 R/W 0x0 R/W Clock DCS2 enable. DCS2 bypassed. DCS2 enabled. Clock DCS2 power-up. DCS2 powered down. DCS2 powered up. 0x1 R/W 0x1 R/W Rev. A | Page 101 of 134 AD9689 Addr. Name 0x0120 SYSREF Control 1 Data Sheet Bit(s) Bit Name 7 Reserved 6 SYSREF± flag reset 5 4 Setting Description Reserved. 0 1 Normal flag operation. SYSREF± flags held in reset (setup/hold error flags cleared). Reserved. Reserved SYSREF± transition select 1 [2:1] 0x0121 SYSREF Control 2 0 [7:4] [3:0] CLK± edge select 00 01 Captured on the rising edge of CLK± input. Captured on the falling edge of CLK± input. 0 1 10 Disabled. Continuous. N-shot. Reserved. Reserved. SYSREF± mode select Reserved Reserved SYSREF N-shot ignore counter select 0000 0001 0010 0011 … 1110 1111 0x0122 SYSREF Control 3 [7:4] [3:2] Reserved SYSREF window negative 00 01 10 11 [1:0] SYSREF window positive 00 01 10 11 0x0123 SYSREF Control 4 7 [6:0] Reserved SYSREF± timestamp delay, Bits[6:0] 0 1 … 111 1111 0x0128 SYSREF Status 1 [7:4] [3:0] SYSREF± hold status SYSREF± setup status 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 0x0 R R R/W 0x0 0x0 R R/W SYSREF± is valid on low to high transitions using the selected CLK± edge. When changing this setting, SYSREF± mode select must be set to disabled. SYSREF± is valid on high to low transitions using the selected CLK± edge. When changing this setting, SYSREF± mode select must be set to disabled. 0 3 Reset Access 0x0 R 0x0 R/W Next SYSREF± transition only (do not ignore). Ignore the first SYSREF± transition. Ignore the first two SYSREF± transitions. Ignore the first three SYSREF± transitions. … Ignore the first 14 SYSREF± transitions. Ignore the first 15 SYSREF± transitions. Reserved. Negative skew window (measured in sample clocks). Number of clock cycles before the sample clock by which captured SYSREF transitions are ignored. No negative skew; SYSREF must be captured accurately. One sample clock of negative skew. Two sample clocks of negative skew. Three sample clocks of negative skew. Positive skew window (measured in sample clocks). Number of clock cycles before the sample clock by which captured SYSREF transitions are ignored. No positive skew; SYSREF must be captured accurately. One sample clock of positive skew. Two sample clocks of positive skew. Three sample clocks of positive skew. Reserved. SYSREF± timestamp delay (in converter sample clock cycles). 0x0 R/W 0x0 0x00 R R/W 0 sample clock cycle delay. 1 sample clock cycle delay. … 127 sample clock cycle delay. SYSREF± hold status. SYSREF± setup status. 0x0 0x0 R R Rev. A | Page 102 of 134 Data Sheet Addr. Name 0x0129 SYSREF Status 2 0x012A SYSREF Status 3 0x01FF Chip sync mode AD9689 Bit(s) Bit Name Setting [7:4] Reserved [3:0] Clock divider phase when SYSREF± was captured 0000 0001 0010 0011 0100 … 1111 [7:0] SYSREF counter, Bits[7:0] increments when a SYSREF± is captured [7:1] 0 Reserved Synchronization mode Description Reserved. SYSREF divider phase. Represents the phase of the divider when SYSREF± was captured. In phase. SYSREF± is ½ cycle delayed from clock. SYSREF± is 1 cycle delayed from clock. SYSREF± is 1½ input clock cycles delayed. SYSREF± is 2 input clock cycles delayed. … SYSREF± is 7½ input clock cycles delayed. SYSREF count. Running counter that increments whenever a SYSREF± event is captured. Reset by Register 0x0120, Bit 6. Wraps around at 255. Read these bits only when Register 0x0120, Bits[2:1] are set to disabled. Reserved. Reset Access 0x0 R 0x0 R 0x0 R 0x0 0x0 R R/W JESD204B synchronization mode. The SYSREF signal resets all internal clock dividers. Use this mode when synchronizing multiple chips as specified in the JESD204B standard. If the phase of any of the dividers must change, the JESD204B link goes down. Timestamp mode. The SYSREF signal does not reset internal clock dividers. In this mode, the JESD204B link and the signal monitor are not affected by the SYSREF signal. The SYSREF signal timestamps a sample when it passes through the ADC and is used as a control bit in the JESD204B output word. 0 1 Chip Operating Mode Control Registers Table 48. Addr. Name 0x0200 Chip mode Bit(s) Bit Name [7:6] Reserved 5 Chip Q ignore Setting 0 1 4 [3:0] Reserved Chip application mode 0000 0001 0010 0011 0x0201 Chip decimation ratio [7:4] Reserved [3:0] Chip decimation ratio 0000 0001 1000 0010 0101 1001 0011 0110 1010 0111 0100 1101 1011 1110 1111 1100 Description Reserved. Chip real (I) only selection. Both real (I) and complex (Q) selected. Only real (I) selected; complex (Q) is ignored. Reserved. Full bandwidth mode (default). One DDC mode (DDC0 only). Two DDC mode (DDC0 and DDC1 only). Four DDC mode (DDC0, DDC1, DDC2, and DDC3). Reserved. Chip decimation ratio. Full sample rate (decimate by 1, DDCs are bypassed). Decimate by 2. Decimate by 3. Decimate by 4. Decimate by 5. Decimate by 6. Decimate by 8. Decimate by 10. Decimate by 12. Decimate by 15. Decimate by 16. Decimate by 20. Decimate by 24. Decimate by 30. Decimate by 40. Decimate by 48. Rev. A | Page 103 of 134 Reset Access 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R 0x0 R/W AD9689 Data Sheet Fast Detect and Signal Monitor Control Registers Table 49. Addr. Name 0x0245 Fast detect control (local) Bit(s) Bit Name [7:4] Reserved 3 2 1 0 Setting Description Reserved. 0x0 R/W 0 1 Normal operation of the fast detect pin. Force a value on the fast detect pin (see Bit 2). The fast detect output pin for this channel is set to this value when the output is forced. Reserved. 0x0 R/W 0x0 0x0 R R/W Fast detect disabled. Fast detect enabled. LSBs of fast detect upper threshold. This register contains the 8 LSBs of the programmable 13-bit upper threshold that is compared to the fine ADC magnitude. Reserved. 0x0 R/W 0x0 R LSBs of fast detect upper threshold. This register contains the 8 LSBS of the programmable 13-bit upper threshold that is compared to the fine ADC magnitude. LSBs of fast detect lower threshold. This register contains the 8 LSBS of the programmable 13-bit lower threshold that is compared to the fine ADC magnitude. Reserved. 0x0 R/W 0x0 R/W 0x0 R LSBs of fast detect lower threshold. This register contains the 8 LSBs of the programmable 13-bit lower threshold that is compared to the fine ADC magnitude. LSBs of fast detect dwell time counter target. This is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FD_x pins are reset to 0. LSBs of fast detect dwell time counter target. This is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FD_x pins are reset to 0. Reserved. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R Signal monitor next synchronization mode. 0x0 R/W Continuous mode. Next synchronization mode. Only the next valid edge of the SYSREF± pin is used to synchronize the signal monitor block. Subsequent edges of the SYSREF± pin are ignored. When the next SYSREF has been captured, Register 0x026F, Bit 0 is cleared. The SYSREF± pin must be an integer multiple of the signal monitor period for this function to operate correctly in continuous mode. Signal monitor synchronization enable. 0x0 R/W Synchronization disabled. If Register 0x026F, Bit 1 = 1, only the next valid edge of the SYSREF± pin is used to synchronize the signal monitor block. Subsequent edges of the SYSREF± pin are ignored. When the next SYSREF signal is received, this bit is cleared. The SYSREF± input pin must be enabled to synchronize the signal monitor blocks. Reserved. 0x0 R 0x0 R/W 0x0 R Force FD_A/FD_B pins Force value of FD_A/FD_B pins Reserved Enable fast detect output 0 1 0x0247 Fast detect up LSB (local) [7:0] Fast detect upper threshold 0x0248 Fast detect up MSB [7:5] (local) [4:0] Reserved 0x0249 Fast detect low LSB [7:0] (local) Fast detect lower threshold 0x024A Fast detect low MSB (local) [7:5] Reserved [4:0] Fast detect lower threshold 0x024B Fast detect dwell LSB (local) [7:0] Fast detect dwell time 0x024C Fast detect dwell MSB (local) [7:0] Fast detect dwell time 0x026F Signal monitor sync control [7:2] Reserved 1 Signal monitor next synchronization mode Fast detect upper threshold 0 1 0 Signal monitor synchronization mode 0 1 0x0270 Signal monitor control (local) [7:2] Reserved 1 Peak detector 0 1 0 Reserved Peak detector disabled. Peak detector enabled. Reserved. Rev. A | Page 104 of 134 Reset Access 0x0 R Data Sheet AD9689 Addr. Name 0x0271 Signal Monitor Period 0 (local) Bit(s) Bit Name [7:0] Signal monitor period[7:0] 0x0272 Signal Monitor Period 1 (local) [7:0] Signal monitor period[15:8] 0x0273 Signal Monitor Period 2 (local) [7:0] Signal monitor period[23:16] 0x0274 Signal monitor status control (local) [7:5] Reserved 4 Result update Setting Update signal monitor status registers, Register 0x0275 to Register 0x0278. Self clearing. Reserved. 1 3 [2:0] Reserved Result selection [7:0] Signal monitor result[7:0] Signal monitor result[15:8] Reserved 001 0x0275 Signal Monitor Status 0 (local) 0x0276 Signal Monitor Status 1 (local) 0x0277 Signal Monitor Status 2 (local) 0x0 R/W 0x0 R/W 0x0 R 0x0 R/WC 0x0 0x1 R R/W 0x0 R 0x0 R Reserved. 0x0 R Signal monitor status result. 0x0 R [7:0] Signal monitor result[19:16] Period count result[7:0] Signal monitor frame counter status bits. The frame counter increments whenever the period counter expires. 0x0 R [7:2] Reserved Reserved. 0x0 R [1:0] Signal monitor SPORT over JESD204B enable 0x0 R/W 0x0 R 0x1 R/W 0x0 R [7:4] [3:0] 00 11 0x027A SPORT over JESD204B input selection (local) Reset Access 0x80 R/W Peak detector placed on status readback signals. Signal monitor status result. This 20-bit value contains the status result calculated by the signal monitor block. Signal monitor status result. [7:0] 0x0278 Signal monitor status frame counter (local) 0x0279 Signal monitor serial framer control (local) Description Bits[7:0] of the 24-bit value that sets the number of output clock cycles over which the signal monitor performs its operation. Only even values are supported. Bits[15:8] of the 24-bit value that sets the number of output clock cycles over which the signal monitor performs its operation. Only even values are supported. Bits[23:16] of the 24-bit value that sets the number of output clock cycles over which the signal monitor performs its operation. Only even values are supported. Reserved. [7:6] Reserved 1 SPORT over JESD204B input selection 0 1 0 Reserved Disabled. Enabled. Reserved. Signal monitor serial framer input selection. When each individual bit is a 1, the corresponding signal statistics information is sent within the frame. Disabled. Peak detector data inserted in the serial frame. Reserved. DDC Function Registers (See the Digital Downconverter (DDC) Section) Table 50. Addr. Name 0x0300 DDC SYNC control Bit(s) Bit Name Setting DDC FTW/POW/MAW/ 7 MBW update mode 0 1 6:5 4 Reserved DDC NCO soft reset 0 1 [3:2] Reserved Description Select DDC FTW/POW/MAW/MBW update mode. Reset 0x0 Access R/W Instantaneous/continuous update. FTW/POW/MAW/MBW values are updated immediately. FTW/POW/MAW/MBW values are updated synchronously when the chip transfer bit (Register 0x000F, Bit 0) is set. Reserved. This bit can be used to synchronize all the NCOs inside the DDC blocks. Normal operation. DDC held in reset. Reserved. 0x0 0x0 R R/W 0x0 R Rev. A | Page 105 of 134 AD9689 Addr. Name Data Sheet Bit(s) Bit Name 1 DDC next sync Setting Description 0 Continuous mode. The SYSREF frequency must be an integer multiple of the NCO frequency for this function to operate correctly in continuous mode. Only the next valid edge of the SYSREF± pin is used to synchronize the NCO in the DDC block. Subsequent edges of the SYSREF± pin are ignored. When the next SYSREF signal is found, the DDC synchronization mode bit (Register 0x0300, Bit 0) is cleared. The SYSREF± input pin must be enabled to synchronize the DDCs. 0x0 1 0 0x0310 DDC0 control 7 6 DDC synchronization mode 0 1 Synchronization disabled. Synchronization enabled. If Register 0x0300, Bit 1 = 1, only the next valid edge of the SYSREF± pin is used to synchronize the NCO in the DDC block. Subsequent edges of the SYSREF± pin are ignored. When the next SYSREF signal is received, this bit is cleared. 0 1 Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate, real, and imaginary quadrature ADC receive channels; analog demodulator). Gain can be used to compensate for the 6 dB loss associated with mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). DDC0 mixer select DDC0 gain select 0 1 [5:4] DDC0 intermediate frequency (IF) mode 00 01 10 11 3 [2:0] DDC0 decimation rate select 000 001 010 011 100 101 110 111 Access R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Variable IF mode. 0 Hz IF mode. fS Hz IF mode. Test mode. DDC0 complex to real enable 0 1 Reset 0x0 Complex (I and Q) outputs contain valid data. Real (I) output only. Complex to real enabled. Uses extra fS mixing to convert to real. Decimation filter selection. HB1 + HB2 filter selection: decimate by 2 (complex to real enabled), or decimate by 4 (complex to real disabled). HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real enabled), or decimate by 8 (complex to real disabled). HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to real enabled), or decimate by 16 (complex to real disabled). HB1 filter selection: decimate by 1 (complex to real enabled), or decimate by 2 (complex to real disabled). HB1 + TB2 filter selection: decimate by 3 (complex to real enabled), or decimate by 6 (complex to real disabled). HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real enabled), or decimate by 12 (complex to real disabled). HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to real enabled), or decimate by 24 (complex to real disabled). Decimation determined by Register 0x0311, Bits[7:4]. Rev. A | Page 106 of 134 Data Sheet Addr. Name 0x0311 DDC0 input select AD9689 Bit(s) Bit Name Setting [7:4] DDC0 decimation rate select 0000 0010 0011 0100 0111 1000 1001 3 2 Reserved DDC0 Q input select 0 1 1 0 Reserved DDC0 I input select 0 1 0x0314 DDC0 NCO control [7:4] DDC0 NCO channel select mode 0000 0001 0010 0011 0100 0101 0110 1000 1001 1010 1011 [3:0] DDC0 NCO register map channel select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Only valid when Register 0x0310, Bits[2:0] = 3'b111. TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48 (complex to real disabled), or decimate by 24 (complex to real enabled). FB2 + HB1 filter selection: decimate by 10 (complex to real disabled), or decimate by 5 (complex to real enabled). FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real disabled), or decimate by 10 (complex to real enabled). FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to real disabled), or decimate by 20 (complex to real enabled). TB1 filter selection: decimate by 3 (decimate by 1.5 not supported). FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not supported). HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by 15 not supported). Reserved. Channel A. Channel B. Reserved. Channel A. Channel B. For edge control, the internal counter wraps after the Register 0x0314, Bits[3:0] value is reached. Use Register 0x0314, Bits[3:0]. GPIO_B0, GPIO_A0. GPIO_B1, GPIO_A1. GPIO_A1, GPIO_A0. GPIO_B1, GPIO_B0. GPIO_B1, GPIO_A1, GPIO_B0, GPIO_A0. GPIO_B1, GPIO_B0, GPIO_A1, GPIO_A0. Increment internal counter on rising edge of the GPIO_A0 pin. Increment internal counter on rising edge of the GPIO_A1 pin. Increment internal counter on rising edge of the GPIO_B0 pin. Increment internal counter on rising edge of the GPIO_B1 pin. NCO channel select register map control. Select NCO Channel 0. Select NCO Channel 1. Select NCO Channel 2. Select NCO Channel 3. Select NCO Channel 4. Select NCO Channel 5. Select NCO Channel 6. Select NCO Channel 7. Select NCO Channel 8. Select NCO Channel 9. Select NCO Channel 10. Select NCO Channel 11. Select NCO Channel 12. Select NCO Channel 13. Select NCO Channel 14. Select NCO Channel 15. Rev. A | Page 107 of 134 Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W AD9689 Addr. Name 0x0315 DDC0 phase control Data Sheet Bit(s) Bit Name [7:4] Reserved [3:0] Setting DDC0 phase update index 0000 0001 0010 0011 0x0316 DDC0 Phase Increment 0 0x0317 DDC0 Phase Increment 1 0x0318 DDC0 Phase Increment 2 0x0319 DDC0 Phase Increment 3 0x031A DDC0 Phase Increment 4 0x031B DDC0 Phase Increment 5 0x031D DDC0 Phase Offset 0 0x031E DDC0 Phase Offset 1 0x031F DDC0 Phase Offset 2 0x0320 DDC0 Phase Offset 3 0x0321 DDC0 Phase Offset 4 0x0322 DDC0 Phase Offset 5 0x0327 DDC0 test enable [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:3] 2 DDC0 phase increment[7:0] DDC0 phase increment[15:8] DDC0 phase increment[23:16] DDC0 phase increment[31:24] DDC0 phase increment[39:32] DDC0 phase increment[47:40] DDC0 phase offset[7:0] DDC0 phase offset[15:8] DDC0 phase offset[23:16] DDC0 phase offset[31:24] DDC0 phase offset[39:32] DDC0 phase offset[47:40] Reserved DDC0 Q output test mode enable 0 1 1 0 Reserved DDC0 I output test mode enable 0 1 0x0330 DDC1 control 7 DDC1 mixer select 0 1 6 DDC1 gain select 0 1 [5:4] DDC1 IF mode 00 01 10 11 Description Reserved. Reset 0x0 Access R Indexes the NCO channel whose phase and offset is updated. The update method is based on the DDC phase update mode, which can be continuous or require chip transfer. Update NCO Channel 0. Update NCO Channel 1. Update NCO Channel 2. Update NCO Channel 3. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. Twos complement POW for the NCO. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Reserved. 0x0 R Q samples always use Test Mode B block. The test mode is 0x0 selected using the channel dependent Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Reserved. 0x0 I samples always use Test Mode A block. The test mode is selected 0x0 using the channel dependent Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. 0x0 Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate, real, and imaginary quadrature ADC receive channels; analog demodulator). Gain can be used to compensate for the 6 dB loss associated with 0x0 mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). 0x0 Variable IF mode. 0 Hz IF mode. fS Hz IF mode. Test mode. Rev. A | Page 108 of 134 R/W R R/W R/W R/W R/W Data Sheet Addr. Name AD9689 Bit(s) Bit Name Setting DDC1 complex to real 3 enable 0 1 [2:0] DDC1 decimation rate select 000 001 010 011 100 101 110 111 0x0331 DDC1 input select [7:4] DDC1 decimation rate select 0000 0010 0011 0100 0111 1000 1001 3 2 Reserved DDC1 Q input select 0 1 1 0 Reserved DDC1 I input select 0 1 0x0334 DDC1 NCO control [7:4] DDC1 NCO channel select mode 0000 0001 0010 0011 0100 0101 0110 1000 1001 1010 1011 Description Reset 0x0 Access R/W Complex (I and Q) outputs contain valid data. Real (I) output only. Complex to real enabled. Uses extra fS mixing to convert to real. Decimation filter selection. 0x0 R/W HB1 + HB2 filter selection: decimate by 2 (complex to real enabled), or decimate by 4 (complex to real disabled). HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real enabled), or decimate by 8 (complex to real disabled). HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to real enabled), or decimate by 16 (complex to real disabled). HB1 filter selection: decimate by 1 (complex to real enabled), or decimate by 2 (complex to real disabled). HB1 + TB2 filter selection: decimate by 3 (complex to real enabled), or decimate by 6 (complex to real disabled). HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real enabled), or decimate by 12 (complex to real disabled). HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to real enabled), or decimate by 24 (complex to real disabled). Decimation determined by Register 0x0331, Bits[7:4]. Only valid when Register 0x0310, Bits[2:0] = 3'b111. 0x0 R/W 0x0 0x1 R R/W 0x0 0x1 R R/W 0x0 R/W TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48 (complex to real disabled), or decimate by 24 (complex to real enabled). FB2 + HB1 filter selection: decimate by 10 (complex to real disabled), or decimate by 5 (complex to real enabled). FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real disabled), or decimate by 10 (complex to real enabled). FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to real disabled), or decimate by 20 (complex to real enabled). TB1 filter selection: decimate by 3 (decimate by 1.5 not supported). FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not supported). HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by 15 not supported). Reserved. Channel A. Channel B. Reserved. Channel A. Channel B. For edge control, the internal counter wraps when the Register 0x0334, Bits[3:0] value is reached. Use Register 0x0334, Bits[3:0]. PIO_B0, GPIO_A0. GPIO_B1, GPIO_A1. GPIO_A1, GPIO_A0. GPIO_B1, GPIO_B0. GPIO_B1, GPIO_A1, GPIO_B0, GPIO_A0. GPIO_B1, GPIO_B0, GPIO_A1, GPIO_A0. Increment internal counter on rising edge of the GPIO_A0 pin. Increment internal counter on rising edge of the GPIO_A1 pin. Increment internal counter on rising edge of the GPIO_B0 pin. Increment internal counter on rising edge of the GPIO_B1 pin. Rev. A | Page 109 of 134 AD9689 Addr. Name 0x0335 DDC1 phase control Data Sheet Bit(s) Bit Name [3:0] DDC1 NCO register map channel select [7:4] Reserved [3:0] DDC1 phase update index Setting Description NCO channel select register map control. Reset 0x0 Access R/W 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Select NCO Channel 0. Select NCO Channel 1. Select NCO Channel 2. Select NCO Channel 3. Select NCO Channel 4. Select NCO Channel 5. Select NCO Channel 6. Select NCO Channel 7. Select NCO Channel 8. Select NCO Channel 9. Select NCO Channel 10. Select NCO Channel 11. Select NCO Channel 12. Select NCO Channel 13. Select NCO Channel 14. Select NCO Channel 15. Reserved. 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0000 0001 0010 0011 0x0336 DDC1 Phase Increment 0 0x0337 DDC1 Phase Increment 1 0x0338 DDC1 Phase Increment 2 0x0339 DDC1 Phase Increment 3 0x033A DDC1 Phase Increment 4 0x033B DDC1 Phase Increment 5 0x033D DDC1 Phase Offset 0 0x033E DDC1 Phase Offset 1 0x033F DDC1 Phase Offset 2 0x0340 DDC1 Phase Offset 3 0x0341 DDC1 Phase Offset 4 0x0342 DDC1 Phase Offset 5 0x0347 DDC1 test enable [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:3] 2 DDC1 phase increment[7:0] DDC1 phase increment[15:8] DDC1 phase increment[23:16] DDC1 phase increment[31:24] DDC1 phase increment[39:32] DDC1 phase increment[47:40] DDC1 phase offset[7:0] DDC1 phase offset[15:8] DDC1 phase offset[23:16] DDC1 phase offset[31:24] DDC1 phase offset[39:32] DDC1 phase offset[47:40] Reserved DDC1 Q output test mode enable 0 1 1 0 Reserved DDC1 I output test mode enable 0 1 Indexes the NCO channel whose phase and offset are updated. The update method is based on the DDC phase update mode, which can be continuous or require chip transfer. Update NCO Channel 0. Update NCO Channel 1. Update NCO Channel 2. Update NCO Channel 3. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. Twos complement POW for the NCO. 0x0 R/W 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Reserved. 0x0 R Q samples always use Test Mode B block. The test mode is 0x0 selected using the channel dependent Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Reserved. 0x0 I samples always use Test Mode A block. The test mode is selected 0x0 using the channel dependent Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Rev. A | Page 110 of 134 R/W R R/W Data Sheet Addr. Name 0x0350 DDC2 control AD9689 Bit(s) Bit Name 7 DDC2 mixer select 6 [5:4] 3 Setting Description 0 1 0 1 Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate, real and imaginary quadrature ADC receive channels; analog demodulator). Gain can be used to compensate for the 6 dB loss associated with mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). 00 01 10 11 Variable IF mode. 0 Hz IF mode. fS Hz IF mode. Test mode. DDC2 gain select DDC2 decimation rate select 001 010 011 100 101 110 111 [7:4] DDC2 decimation rate select 000 0010 011 100 3 2 Reserved DDC2 Q input select 0 1 1 0 0x0 R/W 0x0 R/W 0x0 R/W Complex (I and Q) outputs contain valid data. Real (I) output only. Complex to real enabled. Uses extra fS mixing to convert to real. Decimation filter selection. 0x0 R/W HB1 + HB2 filter selection: decimate by 2 (complex to real enabled), or decimate by 4 (complex to real disabled). HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real enabled), or decimate by 8 (complex to real disabled). HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to real enabled), or decimate by 16 (complex to real disabled). HB1 filter selection: decimate by 1 (complex to real enabled), or decimate by 2 (complex to real disabled). HB1 + TB2 filter selection: decimate by 3 (complex to real enabled), or decimate by 6 (complex to real disabled). HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real enabled), or decimate by 12 (complex to real disabled). HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to real enabled), or decimate by 24 (complex to real disabled). Decimation determined by Register 0x0351, Bits[7:4]. Only valid when Register 0x0310, Bits[2:0] = 3'b111. 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W DDC2 complex to real enable 000 0x0351 DDC2 input select Access R/W DDC2 IF mode 0 1 [2:0] Reset 0x0 Reserved DDC2 I input select 0 1 TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48 (complex to real disabled), or decimate by 24 (complex to real enabled). FB2 + HB1 filter selection: decimate by 10 (complex to real disabled), or decimate by 5 (complex to real enabled). FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real disabled), or decimate by 10 (complex to real enabled). FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to real disabled), or decimate by 20 (complex to real enabled). Reserved. Channel A. Channel B. Reserved. Channel A. Channel B. Rev. A | Page 111 of 134 AD9689 Addr. Name 0x0354 DDC2 NCO control Data Sheet Bit(s) Bit Name [7:4] DDC2 NCO channel select mode Setting 0000 0001 0010 0011 0100 0101 0110 1000 1001 1010 1011 [3:0] DDC2 NCO register map channel select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0x0355 DDC2 phase control [7:4] Reserved [3:0] DDC2 phase update index 0000 0001 0010 0011 0x0356 DDC2 Phase Increment 0 0x0357 DDC2 Phase Increment 1 0x0358 DDC2 Phase Increment 2 0x0359 DDC2 Phase Increment 3 0x035A DDC2 Phase Increment 4 0x035B DDC2 Phase Increment 5 0x035D DDC2 Phase Offset 0 0x035E DDC2 Phase Offset 1 0x035F DDC2 Phase Offset 2 0x0360 DDC2 Phase Offset 3 0x0361 DDC2 Phase Offset 4 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] DDC2 phase increment[7:0] DDC2 phase increment[15:8] DDC2 phase increment[23:16] DDC2 phase increment[31:24] DDC2 phase increment[39:32] DDC2 phase increment[47:40] DDC2 phase offset[7:0] DDC2 phase offset[15:8] DDC2 phase offset[23:16] DDC2 phase offset[31:24] DDC2 phase offset[39:32] Description For edge control, the internal counter wraps when the Register 0x0354, Bits[3:0] value is reached. Use Register 0x0354, Bits[3:0]. GPIO_B0, GPIO_A0. GPIO_B1, GPIO_A1. GPIO_A1, GPIO_A0. GPIO_B1, GPIO_B0. GPIO_B1, GPIO_A1, GPIO_B0, GPIO_A0. GPIO_B1, GPIO_B0, GPIO_A1, GPIO_A0. Increment internal counter on rising edge of the GPIO_A0 pin. Increment internal counter on rising edge of the GPIO_A1 pin. Increment internal counter on rising edge of the GPIO_B0 pin. Increment internal counter on rising edge of the GPIO_B1 pin. NCO channel select register map control. Select NCO Channel 0. Select NCO Channel 1. Select NCO Channel 2. Select NCO Channel 3. Select NCO Channel 4. Select NCO Channel 5. Select NCO Channel 6. Select NCO Channel 7. Select NCO Channel 8. Select NCO Channel 9. Select NCO Channel 10. Select NCO Channel 11. Select NCO Channel 12. Select NCO Channel 13. Select NCO Channel 14. Select NCO Channel 15. Reserved. Reset 0x0 Access R/W 0x0 R/W 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Indexes the NCO channel whose phase and offset are updated. The update method is based on the DDC phase update mode, which can be continuous or require chip transfer. Update NCO Channel 0. Update NCO Channel 1. Update NCO Channel 2. Update NCO Channel 3. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. Twos complement POW for the NCO. 0x0 R/W 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Rev. A | Page 112 of 134 Data Sheet Addr. Name 0x0362 DDC2 Phase Offset 5 0x0367 DDC2 test enable AD9689 Bit(s) Bit Name [7:0] DDC2 phase offset[47:40] [7:3] Reserved 2 Setting DDC2 Q output test mode enable 0 1 1 0 Reserved DDC2 I output test mode enable 0 1 0x0370 DDC3 control 7 DDC3 mixer select 0 1 6 DDC3 gain select 0 1 [5:4] DDC3 IF mode 00 01 10 11 3 DDC3 complex to real enable 0 1 [2:0] DDC3 decimation rate select 000 001 010 011 100 101 110 111 0x0371 DDC3 input select [7:4] DDC3 decimation rate select 000 010 011 100 3 Reserved Description Twos complement POW for the NCO. Reset 0x0 Access R/W Reserved. 0x0 R Q samples always use Test Mode B block. The test mode is 0x0 selected using the channel dependent Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Reserved. 0x0 I samples always use Test Mode A block. The test mode is selected 0x0 using the channel dependent Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. 0x0 Real mixer (I and Q inputs must be from the same real channel). Complex mixer (I and Q must be from separate, real, and imaginary quadrature ADC receive channels; analog demodulator). Gain can be used to compensate for the 6 dB loss associated with 0x0 mixing an input signal down to baseband and filtering out its negative component. 0 dB gain. 6 dB gain (multiply by 2). 0x0 Variable If mode. 0 Hz IF mode. fS Hz IF mode. Test mode. 0x0 R/W R R/W R/W R/W R/W R/W Complex (I and Q) outputs contain valid data. Real (I) output only. complex to real enabled. Uses extra fS mixing to convert to real. Decimation filter selection. 0x0 R/W HB1 + HB2 filter selection: decimate by 2 (complex to real enabled), or decimate by 4 (complex to real disabled). HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real enabled), or decimate by 8 (complex to real disabled). HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to real enabled), or decimate by 16 (complex to real disabled). HB1 filter selection: decimate by 1 (complex to real enabled), or decimate by 2 (complex to real disabled). HB1 + TB2 filter selection: decimate by 3 (complex to real enabled), or decimate by 6 (complex to real disabled). HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real enabled), or decimate by 12 (complex to real disabled). HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to real enabled), or decimate by 24 (complex to real disabled). Decimation determined by Register 0x0371, Bits[7:4]. Only valid when Register 0x0310, Bits[2:0] = 3'b111. 0x0 R/W TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48 (complex to real disabled), or decimate by 24 (complex to real enabled). FB2 + HB1 filter selection: decimate by 10 (complex to real disabled), or decimate by 5 (complex to real enabled). FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real disabled), or decimate by 10 (complex to real enabled). FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to real disabled), or decimate by 20 (complex to real enabled). Reserved. 0x0 R Rev. A | Page 113 of 134 AD9689 Addr. Name Data Sheet Bit(s) Bit Name 2 DDC3 Q input select 1 0 Setting Description 0 1 Channel A. Channel B. Reserved. Reserved DDC3 I input select 0 1 0x0374 DDC3 NCO control [7:4] DDC3 NCO channel select mode 0000 0001 0010 0011 0100 0101 0110 1000 1001 1010 1011 [3:0] DDC3 NCO register map channel select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0x0375 DDC3 phase control [7:4] Reserved [3:0] DDC3 phase update index 0000 0001 0010 0011 0x0376 DDC3 Phase Increment 0 0x0377 DDC3 Phase Increment 1 0x0378 DDC3 Phase Increment 2 0x0379 DDC3 Phase Increment 3 0x037A DDC3 Phase Increment 4 0x037B DDC3 Phase Increment 5 0x037D DDC3 Phase Offset 0 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] DDC3 phase increment[7:0] DDC3 phase increment[15:8] DDC3 phase increment[23:16] DDC3 phase increment[31:24] DDC3 phase increment[39:32] DDC3 phase increment[47:40] DDC3 phase offset[7:0] Channel A. Channel B. For edge control, the internal counter wraps when the Register 0x0374, Bits[3:0] value is reached. Use Register 0x0374, Bits[3:0]. GPIO_B0, GPIO_A0. GPIO_B1, GPIO_A1. GPIO_A1, GPIO_A0. GPIO_B1, GPIO_B0. GPIO_B1, GPIO_A1, GPIO_B0, GPIO_A0. GPIO_B1, GPIO_B0, GPIO_A1, GPIO_A0. Increment internal counter when rising edge of GPIO_A0 pin. Increment internal counter when rising edge of GPIO_A1 pin. Increment internal counter when rising edge of GPIO_B0 pin. Increment internal counter when rising edge of GPIO_B1 pin. NCO channel select register map control. Select NCO Channel 0. Select NCO Channel 1. Select NCO Channel 2. Select NCO Channel 3. Select NCO Channel 4. Select NCO Channel 5. Select NCO Channel 6. Select NCO Channel 7. Select NCO Channel 8. Select NCO Channel 9. Select NCO Channel 10. Select NCO Channel 11. Select NCO Channel 12. Select NCO Channel 13. Select NCO Channel 14. Select NCO Channel 15. Reserved. Indexes the NCO channel whose phase and offset gets updated. The update method is based on the DDC phase update mode, which can be continuous or require chip transfer. Update NCO Channel 0. Update NCO Channel 1. Update NCO Channel 2. Update NCO Channel 3. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248 FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. Twos complement POW for the NCO. Rev. A | Page 114 of 134 Reset 0x1 Access R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Addr. Name 0x037E DDC3 Phase Offset 1 0x037F DDC3 Phase Offset 2 0x0380 DDC3 Phase Offset 3 0x0381 DDC3 Phase Offset 4 0x0382 DDC3 Phase Offset 5 0x0387 DDC3 test enable AD9689 Bit(s) Bit Name [7:0] DDC3 phase offset[15:8] [7:0] DDC3 phase offset[23:16] [7:0] DDC3 phase offset[31:24] [7:0] DDC3 phase offset[39:32] [7:0] DDC3 phase offset[47:40] [7:3] Reserved 2 Setting DDC3 Q output test mode enable 0 1 1 0 Reserved DDC3 I output test mode enable 0 1 0x0390 DDC0 Phase Increment Frac A0 0x0391 DDC0 Phase Increment Frac A1 0x0392 DDC0 Phase Increment Frac A2 0x0393 DDC0 Phase Increment Frac A3 0x0394 DDC0 Phase Increment Frac A4 0x0395 DDC0 Phase Increment Frac A5 0x0398 DDC0 Phase Increment Frac B0 0x0399 DDC0 Phase Increment Frac B1 0x039A DDC0 Phase Increment Frac B2 0x039B DDC0 Phase Increment Frac B3 0x039C DDC0 Phase Increment Frac B4 0x039D DDC0 Phase Increment Frac B5 0x03A0 DDC1 Phase Increment Frac A0 0x03A1 DDC1 Phase Increment Frac A1 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] DDC0 Phase Increment Frac A[7:0] DDC0 Phase Increment Frac A[15:8] DDC0 Phase Increment Frac A[23:16] DDC0 Phase Increment Frac A[31:24] DDC0 Phase Increment Frac A[39:32] DDC0 Phase Increment Frac A[47:40] DDC0 Phase Increment Frac B[7:0] DDC0 Phase Increment Frac B[15:8] DDC0 Phase Increment Frac B[23:16] DDC0 Phase Increment Frac B[31:24] DDC0 Phase Increment Frac B[39:32] DDC0 Phase Increment Frac B[47:40] DDC1 Phase Increment Frac A[7:0] DDC1 Phase Increment Frac A[15:8] Description Twos complement POW for the NCO. Reset 0x0 Access R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Twos complement POW for the NCO. 0x0 R/W Reserved. 0x0 R Q samples always use Test Mode B block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Reserved. I samples always use Test Mode A block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. Test mode disabled. Test mode enabled. Numerator correction term for Phase Accumulator MAW 0x0 R/W 0x0 0x0 R R/W 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Denominator correction term for Phase Accumulator MBW 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Rev. A | Page 115 of 134 AD9689 Addr. Name 0x03A2 DDC1 Phase Increment Frac A2 0x03A3 DDC1 Phase Increment Frac A3 0x03A4 DDC1 Phase Increment Frac A4 0x03A5 DDC1 Phase Increment Frac A5 0x03A8 DDC1 Phase Increment Frac B0 0x03A9 DDC1 Phase Increment Frac B1 0x03AA DDC1 Phase Increment Frac B2 0x03AB DDC1 Phase Increment Frac B3 0x03AC DDC1 Phase Increment Frac B4 0x03AD DDC1 Phase Increment Frac B5 0x03B0 DDC2 Phase Increment Frac A0 0x03B1 DDC2 Phase Increment Frac A1 0x03B2 DDC2 Phase Increment Frac A2 0x03B3 DDC2 Phase Increment Frac A3 0x03B4 DDC2 Phase Increment Frac A4 0x03B5 DDC2 Phase Increment Frac A5 0x03B8 DDC2 Phase Increment Frac B0 0x03B9 DDC2 Phase Increment Frac B1 0x03BA DDC2 Phase Increment Frac B2 0x03BB DDC2 Phase Increment Frac B3 0x03BC DDC2 Phase Increment Frac B4 0x03BD DDC2 Phase Increment Frac B5 Data Sheet Bit(s) Bit Name [7:0] DDC1 Phase Increment Frac A[23:16] [7:0] DDC1 Phase Increment Frac A[31:24] [7:0] DDC1 Phase Increment Frac A[39:32] [7:0] DDC1 Phase Increment Frac A[47:40] [7:0] DDC1 Phase Increment Frac B[7:0] [7:0] DDC1 Phase Increment Frac B[15:8] [7:0] DDC1 Phase Increment Frac B[23:16] [7:0] DDC1 Phase Increment Frac B[31:24] [7:0] DDC1 Phase Increment Frac B[39:32] [7:0] DDC1 Phase Increment Frac B[47:40] [7:0] DDC2 Phase Increment Frac A[7:0] [7:0] DDC2 Phase Increment Frac A[15:8] [7:0] DDC2 Phase Increment Frac A[23:16] [7:0] DDC2 Phase Increment Frac A[31:24] [7:0] DDC2 Phase Increment Frac A[39:32] [7:0] DDC2 Phase Increment Frac A[47:40] [7:0] DDC2 Phase Increment Frac B[7:0] [7:0] DDC2 Phase Increment Frac B[15:8] [7:0] DDC2 Phase Increment Frac B[23:16] [7:0] DDC2 Phase Increment Frac B[31:24] [7:0] DDC2 Phase Increment Frac B[39:32] [7:0] DDC2 Phase Increment Frac B[47:40] Setting Description Numerator correction term for MAW. Reset 0x0 Access R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Rev. A | Page 116 of 134 Data Sheet Addr. Name 0x03C0 DDC3 Phase Increment Frac A0 0x03C1 DDC3 Phase Increment Frac A1 0x03C2 DDC3 Phase Increment Frac A2 0x03C3 DDC3 Phase Increment Frac A3 0x03C4 DDC3 Phase Increment Frac A4 0x03C5 DDC3 Phase Increment Frac A5 0x03C8 DDC3 Phase Increment Frac B0 0x03C9 DDC3 Phase Increment Frac B1 0x03CA DDC3 Phase Increment Frac B2 0x03CB DDC3 Phase Increment Frac B3 0x03CC DDC3 Phase Increment Frac B4 0x03CD DDC3 Phase Increment Frac B5 AD9689 Bit(s) Bit Name [7:0] DDC3 Phase Increment Frac A[7:0] [7:0] DDC3 Phase Increment Frac A[15:8] [7:0] DDC3 Phase Increment Frac A[23:16] [7:0] DDC3 Phase Increment Frac A[31:24] [7:0] DDC3 Phase Increment Frac A[39:32] [7:0] DDC3 Phase Increment Frac A[47:40] [7:0] DDC3 Phase Increment Frac B[7:0] [7:0] DDC3 Phase Increment Frac B[15:8] [7:0] DDC3 Phase Increment Frac B[23:16] [7:0] DDC3 Phase Increment Frac B[31:24] [7:0] DDC3 Phase Increment Frac B[39:32] [7:0] DDC3 Phase Increment Frac B[47:40] Setting Description Numerator correction term for MAW. Reset 0x0 Access R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Numerator correction term for MAW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Denominator correction term for MBW. 0x0 R/W Digital Outputs and Test Modes Table 51. Addr. Name 0x0550 ADC test mode control (local) Bit(s) Bit Name Setting 7 User pattern selection 0 1 6 5 Reserved Reset PN long generator 0 1 4 Reset PN short generator 0 1 Description Test mode user pattern selection. This bit is only used when Register 0x0550, Bits[3:0] = 4’b1000 (user input mode). Otherwise, it is ignored. User Pattern 1 is found in the User Patten 1 MSB (0x0552) and User Pattern 1 LSB (0x0551) registers. User Pattern 2 is found in the User Pattern 2 MSB (0x0554) and User Pattern 2 LSB (0x0553) registers, and so on. Continuous/repeat pattern. Place each user pattern (1, 2, 3, and 4) on the output for 1 clock cycle and then repeat. (Output the following user patterns: 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, and so on.) Single pattern. Place each user pattern (1, 2, 3, and 4) on the output for 1 clock cycle and then output all zeros. (Output the following user patterns: 1, 2, 3, 4, and then output all zeros.) Reserved. Test mode long pseudorandom number test generator reset. Reset 0x0 Access R/W 0x0 0x0 R R/W Long PN enabled. Long PN held in reset. Test mode short pseudorandom number test generator reset. 0x0 R/W Short PN enabled. Short PN held in reset. Rev. A | Page 117 of 134 AD9689 Addr. Name Data Sheet Bit(s) Bit Name [3:0] Test mode selection Setting [7:0] User Pattern 1[7:0] Description Reset Test mode generation selection. 0x0 Off (normal operation). Midscale short. Positive full scale. Negative full scale. Alternating checker board. PN sequence (long). PN sequence (short). 1/0 word toggle. User pattern test mode (used with Register 0x0550, Bit 7 and the User Pattern 1, User Pattern 2, User Pattern 3, and User Pattern 4 registers). Ramp output. User Test Pattern 1 least significant byte. 0x0 [7:0] User Pattern 1[15:8] User Test Pattern 1 least significant byte. 0x0 R/W [7:0] User Pattern 2[7:0] User Test Pattern 2 least significant byte. 0x0 R/W [7:0] User Pattern 2[15:8] User Test Pattern 2 least significant byte. 0x0 R/W [7:0] User Pattern 3[7:0] User Test Pattern 3 least significant byte. 0x0 R/W [7:0] User Pattern 3[15:8] User Test Pattern 3 least significant byte. 0x0 R/W [7:0] User Pattern 4[7:0] User Test Pattern 4 least significant byte. 0x0 R/W [7:0] User Pattern 4[15:8] User Test Pattern 4 least significant byte. 0x0 R/W [7:4] Converter control Bit 1 selection 0x0 R/W 0x0 R/W 0x0 R 0x1 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 R/W 0000 0001 0010 0011 0100 0101 0110 0111 1000 1111 0x0551 User Pattern 1 LSB 0x0552 User Pattern 1 MSB 0x0553 User Pattern 2 LSB 0x0554 User Pattern 2 MSB 0x0555 User Pattern 3 LSB 0x0556 User Pattern 3 MSB 0x0557 User Pattern 4 LSB 0x0558 User Pattern 4 MSB 0x0559 Output Mode Control 1 0000 0001 0010 0011 0101 [3:0] 0x055A Output Mode Control 2 [7:4] Reserved [3:0] Converter control Bit 2 selection 0000 0001 0010 0011 0101 0x0561 Out sample mode [7:3] Reserved 2 Sample invert [1:0] 0x0562 Out overrange [7:0] clear Tie low (1'b0). Overrange bit. Signal monitor bit. Fast detect (FD) bit. SYSREF. Reserved. Tie low (1'b0). Overrange bit. Signal monitor bit. Fast detect (FD) bit. SYSREF. Reserved. 0 1 ADC sample data is not inverted. ADC sample data is inverted. 00 01 Offset binary. Twos complement (default). Overrange clear bits (one bit for each virtual converter). Writing a 1 to the overrange clear bit clears the corresponding overrange sticky bit. Overrange bit enabled. Overrange bit cleared. Data format select Data format overrange clear 0 1 R/W Tie low (1'b0). Overrange bit. Signal monitor bit. Fast detect (FD) bit. SYSREF. Converter control Bit 0 selection 0000 0001 0010 0011 0101 Access R/W Rev. A | Page 118 of 134 Data Sheet AD9689 Addr. Name Bit(s) Bit Name 0x0563 Out overrange [7:0] Data format status overrange Setting 0 1 0x0564 Out channel select [7:1] Reserved 0 Converter channel swap control 0 1 0x056E PLL control [7:4] [3:0] 7 Reserved PLL lock status 0 1 [6:4] 3 Reserved PLL loss of lock 1 0x0570 fS × 4 configuration [2:0] [7:0] Reserved 0xFE 0xFF 0x0571 JESD204B Link 7 Control 1 6 5 4 [3:2] 1 Lane rate = 6.75 Gbps to 13.5 Gbps. Lane rate = 3.375 Gbps to 6.75 Gbps. Lane rate = 13.5 Gbps to 16 Gbps. Lane rate = 1.6875 Gbps to 3.375 Gbps. Reserved. Not locked. Locked. Reserved. Loss of lock sticky bit. Indicate a loss of lock has occurred at some time. Cleared by setting Register 0x0571, Bit 0. Reserved. See the fS × 4 Mode section. R 0x0 R/W 0x3 R/W 0x0 0x0 R R 0x0 R 0xFF R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x0 R/W fS × 4 mode enabled. L = 8; M = 2; F = 2; S = 4; N' = 16; N = 16; CS = 0; CF = 0; HD = 0. fS × 4 mode disabled. L, M, and F set by Register 0x058B, Bits[4:0]; Register 0x58E, Bits[7:0]; and Register 0x058C, Bits[7:0], respectively. Standby mode 0 1 Standby mode forces zeros for all converter samples. Standby mode forces code group synchronization (/K28.5/ characters). 0 1 Disable. Enable. Tail bit(t) PN Long transport layer test 0 1 JESD204B test samples disabled. JESD204B test samples enabled; long transport layer test sample sequence (as specified in JESD204B Section 5.1.6.3) sent on all link lanes. 0 1 Disable FACI uses /K28.7/. Enable FACI uses /K28.3/ and /K28.7/. 00 01 11 Initial lane alignment sequence disabled (JESD204B Section 5.3.3.5). Initial lane alignment sequence enabled (JESD204B Section 5.3.3.5). Initial lane alignment sequence always in test mode. JESD204B data link layer test mode where repeated lane alignment sequence (as specified in JESD204B Section 5.3.3.8.2) sent on all lanes. 0 Frame alignment character insertion enabled (JESD204B Section 5.3.3.4). Frame alignment character insertion disabled. For debug only (JESD204B Section 5.3.3.4). Lane synchronization ILAS sequence mode FACI 1 Access R Normal channel ordering. Channel swap enabled. JESD204B lane rate control 0000 0001 0011 0101 0x056F PLL status Description Reset Overrange sticky bit status (one bit for each virtual converter). Writing 0x0 a 1 to the overrange clear bit clears the corresponding overrange sticky bit. No overrange has occurred. Overrange has occurred. Reserved. 0x0 Rev. A | Page 119 of 134 AD9689 Addr. Name Data Sheet Bit(s) Bit Name 0 Link control Setting Description 0 JESD204B serial transmit link enabled. Transmission of the /K28.5/ characters for code group synchronization is controlled by the SYNC~ pin. JESD204B serial transmit link powered down (held in reset and clock gated). 1 0x0572 JESD204B Link [7:6] Control 2 5 4 3 2 1 0 0x0573 JESD204B Link [7:6] Control 3 SYNCINB± pin control 00 10 11 Normal mode. Ignore SYNCINB± (force CGS). Ignore SYNCINB± (force ILAS/user data). 0 1 SYNCINB± pin not inverted. SYNCINB± pin inverted. 0 1 LVDS differential pair SYNC~ input. CMOS single-ended SYNC~ input. SYNCINB+ used. Reserved. SYNCINB± pin invert SYNCINB± pin type Reserved 8-bit/10-bit bypass 0 1 8-bit/10-bit enabled. 8-bit/10-bit bypassed (most significant 2 bits are 0). 0 1 Normal. Invert a, b, c, d, e, f, g, h, i, j, symbols. Reserved. 8-bit/10-bit invert Reserved Checksum mode 10 11 Checksum is the sum of all 8-bit registers in the link configuration table. Checksum is the sum of all individual link configuration fields (LSB aligned). Checksum is disabled (set to zero). For test purposes only. Unused. 0 1 10 N' sample input. 10-bit data at 8-bit/10-bit output (for PHY testing). 8-bit data at scrambler input. 00 01 [5:4] [3:0] Test injection point JESD204B test mode patterns 0000 0001 0010 0011 0100 0101 0110 0111 1000 1110 1111 Normal operation (test mode disabled). Alternating checkerboard. 1/0 word toggle. 31-bit PN sequence: x31 + x28 + 1. 23-bit PN sequence: x23 + x18 + 1. 15-bit PN sequence: x15 + x14 + 1. 9-bit PN sequence: x9 + x5 + 1. 7-bit PN sequence: x7 + x6 + 1. Ramp output. Continuous/repeat user test. Single user test. Rev. A | Page 120 of 134 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 R/W Data Sheet AD9689 Addr. Name Bit(s) Bit Name 0x0574 JESD204B Link [7:4] ILAS delay Control 4 3 [2:0] Setting Description 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Transmit ILAS on first LMFC after SYNCINB± is deasserted. Transmit ILAS on second LMFC after SYNCINB± is deasserted. Transmit ILAS on third LMFC after SYNCINB± is deasserted. Transmit ILAS on fourth LMFC after SYNCINB± is deasserted. Transmit ILAS on fifth LMFC after SYNCINB± is deasserted. Transmit ILAS on sixth LMFC after SYNCINB± is deasserted. Transmit ILAS on seventh LMFC after SYNCINB± is deasserted. Transmit ILAS on eighth LMFC after SYNCINB± is deasserted. Transmit ILAS on ninth LMFC after SYNCINB± is deasserted. Transmit ILAS on tenth LMFC after SYNCINB± is deasserted. Transmit ILAS on eleventh LMFC after SYNCINB± is deasserted. Transmit ILAS on twelfth LMFC after SYNCINB± is deasserted. Transmit ILAS on thirteenth LMFC after SYNCINB± is deasserted. Transmit ILAS on fourteenth LMFC after SYNCINB± is deasserted. Transmit ILAS on fifteenth LMFC after SYNCINB± is deasserted. Transmit ILAS on sixteenth LMFC after SYNCINB± is deasserted. Reserved. Reserved Link layer test mode 000 001 010 011 100 101 110 111 0x0578 JESD204B LMFC offset Normal operation (link layer test mode disabled). Continuous sequence of /D21.5/ characters. Reserved. Reserved. Modified RPAT test sequence. JSPAT test sequence. JTSPAT test sequence. Reserved. Reserved. Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 R [7:5] Reserved [4:0] LMFC phase offset value JESD204B Tx DID value Reserved LMFC phase offset value (in frame clocks). Refer to the Deterministic Latency section. JESD204B serial device identification (DID) number. 0x0 R/W 0x0 R/W Reserved. 0x0 R JESD204B Tx BID value Reserved JESD204B serial bank identification (BID) number (extension to DID). 0x0 R/W Reserved. 0x0 R Lane 0 LID value Reserved JESD204B serial lane identification (LID) number for Lane 0. Reserved. 0x0 0x0 R/W R Lane 1 LID value Reserved JESD204B serial LID number for Lane 1. Reserved. 0x1 0x0 R/W R Lane 2 LID value Reserved JESD204B serial LID number for Lane 2. Reserved. 0x2 0x0 R/W R Lane 3 LID value Reserved JESD204B serial LID number for Lane 3. Reserved. 0x3 0x0 R/W R Lane 4 LID value Reserved JESD204B serial LID number for Lane 4. Reserved. 0x4 0x0 R/W R Lane 5 LID value Reserved JESD204B serial LID number for Lane 5. Reserved. 0x5 0x0 R/W R Lane 6 LID value Reserved JESD204B serial LID number for Lane 6. Reserved. 0x6 0x0 R/W R Lane 7 LID value JESD204B serial LID number for Lane 7. 0x7 R/W 0x0580 JESD204B DID [7:0] configuration 0x0581 JESD204B BID [7:4] configuration [3:0] 0x0583 JESD204B LID0 [7:5] configuration [4:0] 0x0584 JESD204B LID1 [7:5] configuration [4:0] 0x0585 JESD204B LID2 [7:5] configuration [4:0] 0x0586 JESD204B LID3 [7:5] configuration [4:0] 0x0587 JESD204B LID4 [7:5] configuration [4:0] 0x0588 JESD204B LID5 [7:5] configuration [4:0] 0x0589 JESD204B LID6 [7:5] configuration [4:0] 0x058A JESD204B LID7 [7:5] configuration [4:0] Rev. A | Page 121 of 134 AD9689 Addr. Name 0x058B JESD204B scrambling and number of lanes (L) configuration Data Sheet Bit(s) Bit Name JESD204B scrambling 7 (SCR) [6:5] [4:0] Setting Description 0 1 JESD204B scrambler disabled (SCR = 0). JESD204B scrambler enabled (SCR = 1). Reserved. Reserved JESD204B lanes (L) 0x0 0x1 0x3 0x7 0x058C JESD204B link [7:0] number of octets per frames (F) JESD204B F configuration 0000 0001 0010 0011 0101 0111 1111 0x058D JESD204B link [7:5] number of frames per multiframe (K) [4:0] 0x058E JESD204B link [7:0] number of converters (M) Reserved F = 1. F = 2. F = 3. F = 4. F = 6. F = 8. F = 16. Reserved. JESD204B K configuration JESD204B M configuration JESD204B number of frames per multiframe (K = 0x058C[4:0] + 1). Only values where F × K is divisible by 4 can be used. JESD204B number of converters per link per device (M = JESD204B M configuration). 000 001 011 111 0x058F JESD204B number of control bits (CS) and ADC resolution (N) [7:6] Reserved ADC converter resolution (N) 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Access R/W 0x0 0x7 R R/W 0x0 R/W 0x0 R 0x1F R/W 0x1 R/W 0x0 R/W 0x0 0xF R R/W Link connected to one virtual converter (M = 1). Link connected to two virtual converters (M = 2). Link connected to four virtual converters (M = 4). Link connected to eight virtual converters (M = 8). Number of control bits (CS) per sample 000 001 010 011 5 [4:0] One lane per link (L = 1). Two lanes per link (L = 2). Four lanes per link (L = 4). Eight lanes per link (L = 8). JESD204B number of octets per frame (F = 0x058C[7:0] + 1) Reset 0x1 No control bits (CS = 0). 1 control bit (CS = 1), Control Bit 2 only. 2 control bits (CS = 2), Control Bit 2 and Control Bit 1 only. 3 control bits (CS = 3), all control bits (Control Bit 2, Control Bit 1, and Control Bit 0). Reserved. N = 7-bit resolution. N = 8-bit resolution. N = 9-bit resolution. N = 10-bit resolution. N = 11-bit resolution. N = 12-bit resolution. N = 13-bit resolution. N = 14-bit resolution. N = 15-bit resolution. N = 16-bit resolution. Rev. A | Page 122 of 134 Data Sheet Addr. Name 0x0590 JESD204B SCV NP configuration AD9689 Bit(s) Bit Name [7:5] Subclass support [4:0] Setting Description 000 001 Subclass 0. Subclass 1. ADC number of bits per sample (N') 0 0111 0 1011 0 1111 0x0591 JESD204B JV S [7:5] configuration [4:0] 0x0592 JESD204B HD CF configuration 7 Reserved Samples per converter frame cycle (S) HD value Samples per converter frame cycle (S = 0x0591[4:0] + 1). 0 1 [6:5] [4:0] 0x05A0 JESD204B Checksum 0 configuration 0x05A1 JESD204B Checksum 1 configuration 0x05A2 JESD204B Checksum 2 configuration 0x05A3 JESD204B Checksum 3 configuration 0x05B0 JESD204B lane powerdown [7:0] [7:0] [7:0] [7:0] 7 Reserved Control words per frame clock cycle per link (CF) Checksum 0 checksum value for SERDOUT0± Checksum 1 checksum value for SERDOUT1± Checksum 2 checksum value for SERDOUT2± Checksum 3 checksum value for SERDOUT3± JESD204B Lane 7 power-down 0 1 6 JESD204B Lane 6 power-down 0 1 5 JESD204B Lane 5 power-down 0 1 4 JESD204B Lane 4 power-down 0 1 3 JESD204B Lane 3 power-down 0 1 2 N' = 8. N' = 12 N' = 16. Reserved. JESD204B Lane 2 power-down 0 1 Reset 0x1 Access R/W 0xF R/W 0x1 R 0x0 R 0x0 R High density format disabled. High density format enabled. Reserved. 0x0 Number of control words per frame clock cycle per link (CF = Register 0x0 0x0592, Bits[4:0]). R R Serial checksum value for Lane 0. Automatically calculated for each lane. Sum(all link configuration parameters for Lane 0) mod 256. 0xC3 R Serial checksum value for Lane 1. Automatically calculated for each lane. Sum(all link configuration parameters for Lane 1) mod 256. 0xC4 R Serial checksum value for Lane 2. Automatically calculated for each lane. Sum(all link configuration parameters for each lane) mod 256. 0xC5 R Serial checksum value for Lane 3. Automatically calculated for each lane. Sum(all link configuration parameters for Lane 3) mod 256. 0xC6 R Physical Lane 7 force power-down. 0x0 R/W SERDOUT7± normal operation. SERDOUT7± power-down. Physical Lane 6 force power-down. 0x0 R/W SERDOUT6± normal operation. SERDOUT6± power-down. Physical Lane 5 force power-down. 0x0 R/W SERDOUT5± normal operation. SERDOUT5± power-down. Physical Lane 4 force power-down. 0x0 R/W SERDOUT4± normal operation. SERDOUT4± power-down. Physical Lane 3 force power-down. 0x0 R/W SERDOUT3± normal operation. SERDOUT3± power-down. Physical Lane 2 force power-down. 0x0 R/W SERDOUT2± normal operation. SERDOUT2± power-down. Rev. A | Page 123 of 134 AD9689 Addr. Name Data Sheet Bit(s) Bit Name 1 JESD204B Lane 1 power-down 0 Setting Description Physical Lane 1 force power-down. Reset 0x0 Access R/W 0 1 SERDOUT1± normal operation. SERDOUT1± power-down. Physical Lane 0 force power-down. 0x0 R/W SERDOUT0± normal operation. SERDOUT0± power-down. Reserved. 0x0 R Physical Lane 1 assignment. 0x1 R/W Logical Lane 0. Logical Lane 1 (default). Logical Lane 2. Logical Lane 3. Logical Lane 4. Logical Lane 5. Logical Lane 6. Logical Lane 7. Reserved. Physical Lane 0 assignment. 0x0 0x0 R R/W Logical Lane 0 (default). Logical Lane 1. Logical Lane 2. Logical Lane 3. Logical Lane 4. Logical Lane 5. Logical Lane 6. Logical Lane 7. Reserved. 0x0 R Physical Lane 3 assignment. 0x3 R/W Logical Lane 0. Logical Lane 1. Logical Lane 2. Logical Lane 3 (default). Logical Lane 4. Logical Lane 5. Logical Lane 6. Logical Lane 7. Reserved. Physical Lane 2 assignment. 0x0 0x2 R R/W JESD204B Lane 0 power-down 0 1 0x05B2 JESD204B Lane Assign 1 7 Reserved [6:4] SERDOUT1± lane assignment 000 001 010 011 100 101 110 111 3 [2:0] Reserved SERDOUT0± lane assignment 000 001 010 011 100 101 110 111 0x05B3 JESD204B Lane Assign 2 7 Reserved [6:4] SERDOUT3± lane assignment 000 001 010 011 100 101 110 111 3 [2:0] Reserved SERDOUT2± lane assignment 000 001 010 011 100 101 110 111 Logical Lane 0. Logical Lane 1. Logical Lane 2 (default). Logical Lane 3. Logical Lane 4. Logical Lane 5. Logical Lane 6. Logical Lane 7. Rev. A | Page 124 of 134 Data Sheet Addr. Name 0x05B5 JESD204B Lane Assign 3 AD9689 Bit(s) Bit Name 7 Reserved [6:4] Setting SERDOUT5± lane assignment 000 001 010 011 100 101 110 111 3 [2:0] Reserved SERDOUT4± lane assignment 000 001 010 011 100 101 110 111 0x05B6 JESD204B Lane Assign 4 7 Reserved [6:4] SERDOUT7± lane assignment 000 001 010 011 100 101 110 111 3 [2:0] Reserved SERDOUT6± lane assignment 000 001 010 011 100 101 110 111 0x05BF SERDOUTx± data invert 7 Invert SERDOUT7± data 0 1 6 Invert SERDOUT6± data 0 1 5 Invert SERDOUT5± data 0 1 4 Invert SERDOUT4± data 0 1 Description Reserved. Reset 0x0 Access R Physical Lane 5 assignment. 0x5 R/W Logical Lane 0. Logical Lane 1. Logical Lane 2. Logical Lane 3. Logical Lane 4. Logical Lane 5 (default). Logical Lane 6. Logical Lane 7. Reserved. Physical Lane 4 assignment. 0x0 0x4 R R/W Logical Lane 0. Logical Lane 1. Logical Lane 2. Logical Lane 3. Logical Lane 4 (default). Logical Lane 5. Logical Lane 6. Logical Lane 7. Reserved. 0x0 R Physical Lane 7 assignment. 0x7 R/W Logical Lane 0. Logical Lane 1. Logical Lane 2. Logical Lane 3. Logical Lane 4. Logical Lane 5. Logical Lane 6. Logical Lane 7 (default). Reserved. Physical Lane 6 assignment. 0x0 0x6 R R/W Logical Lane 0. Logical Lane 1. Logical Lane 2. Logical Lane 3. Logical Lane 4. Logical Lane 5. Logical Lane 6 (default). Logical Lane 7. Invert SERDOUT7± data. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Normal. Invert. Invert SERDOUT6± data. Normal. Invert. Invert SERDOUT5± data. Normal. Invert. Invert SERDOUT4± data. Normal. Invert. Rev. A | Page 125 of 134 AD9689 Addr. Name 0x05C0 JESD204B Swing Adjust 1 Data Sheet Bit(s) Bit Name Setting 3 Invert SERDOUT3± data 0 1 2 Invert SERDOUT2± data 0 1 1 Invert SERDOUT1± data 0 1 0 Invert SERDOUT0± data 0 1 7 Reserved [6:4] SERDOUT1± voltage swing adjust 000 001 010 3 [2:0] Reserved SERDOUT0± voltage swing adjust 000 001 010 0x05C1 JESD204B 7 Swing Adjust 2 [6:4] Reserved SERDOUT3± voltage swing adjust 000 001 010 3 [2:0] Reserved SERDOUT2± voltage swing adjust 000 001 010 0x05C2 JESD204B 7 Swing Adjust 3 [6:4] Reserved SERDOUT5± voltage swing adjust 000 001 010 3 [2:0] Reserved SERDOUT4± voltage swing adjust 000 001 010 0x05C3 JESD204B 7 Swing Adjust 4 [6:4] Reserved SERDOUT7± voltage swing adjust 000 001 010 3 Reserved Description Invert SERDOUT3± data. Normal. Invert. Invert SERDOUT2± data. Normal. Invert. Invert SERDOUT1± data. Normal. Invert. Invert SERDOUT0± data. Normal. Invert. Reserved. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R Output swing level for SERDOUT1±. 0x1 R/W 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. Output swing level for SERDOUT0±. 0x0 0x1 R R/W 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. 0x0 R Output swing level for SERDOUT3±. 0x1 R/W 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. Output swing level for SERDOUT2±. 0x0 0x1 R R/W 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. 0x0 R Output swing level for SERDOUT5±. 0x1 R/W 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. Output swing level for SERDOUT4±. 0x0 0x1 R R/W 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. 0x0 R Output swing level for SERDOUT7±. 0x1 R/W 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Reserved. 0x0 R Rev. A | Page 126 of 134 Data Sheet Addr. Name 0x05C4 SERDOUT0 de-emphasis select AD9689 Bit(s) Bit Name [2:0] SERDOUT6± voltage swing adjust 7 Setting Description Output swing level for SERDOUT6±. Reset 0x1 Access R/W 000 001 010 1.0 × DRVDD1. 0.850 × DRVDD1. 0.750 × DRVDD1. Posttap enable. 0x0 R/W Disable. Enable. Set posttap level. 0x0 R/W 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Posttap enable. 0x0 0x0 R/W R/W Disable. Enable. Set posttap level. 0x0 R/W 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Posttap enable. 0x0 0x0 R/W R/W Disable. Enable. Set posttap level. 0x0 R/W 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Posttap enable. 0x0 0x0 R/W R/W Disable. Enable. Set posttap level. 0x0 R/W 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. 0x0 R/W Posttap enable 0 1 [6:4] Set posttap level for SERDOUT0± 000 001 010 011 100 0x05C5 SERDOUT1 de-emphasis select [3:0] 7 Reserved Posttap enable 0 1 [6:4] Set posttap level for SERDOUT1± 000 001 010 011 100 0x05C6 SERDOUT2 de-emphasis select [3:0] 7 Reserved Posttap enable 0 1 [6:4] Set posttap level for SERDOUT2± 000 001 010 011 100 0x05C7 SERDOUT3 de-emphasis select [3:0] 7 Reserved Posttap enable 0 1 [6:4] Set posttap level for SERDOUT3± 000 001 010 011 100 [3:0] Reserved Rev. A | Page 127 of 134 AD9689 Addr. Name 0x05C8 SERDOUT4 de-emphasis select Data Sheet Bit(s) Bit Name 7 Posttap enable [6:4] Setting Description Posttap enable. Reset 0x0 Access R/W 0 1 Disable. Enable. Set posttap level. 0x0 R/W 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Posttap enable. 0x0 0x0 R/W R/W Disable. Enable. Set posttap level. 0x0 R/W 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Posttap enable. 0x0 0x0 R/W R/W Disable. Enable. Set posttap level. 0x0 R/W 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. Posttap enable. 0x0 0x0 R/W R/W Disable. Enable. Set posttap level. 0x0 R/W 0 dB. 3 dB. 6 dB. 9 dB. 12 dB. Reserved. See Table 32. 0x0 0x00 R/W R/W JESD204B PLL normal operation. Reset JESD204B PLL calibration. See Table 32. 0x0F R/W Set posttap level for SERDOUT4± 000 001 010 011 100 0x05C9 SERDOUT5 preemphasis select [3:0] 7 Reserved Posttap enable 0 1 [6:4] Set posttap level for SERDOUT5± 000 001 010 011 100 0x05CA SERDOUT6 preemphasis select [3:0] 7 Reserved Posttap enable 0 1 [6:4] Set posttap level for SERDOUT6± 000 001 010 011 100 0x05CB SERDOUT7 preemphasis select [3:0] 7 Reserved Posttap enable 0 1 [6:4] Set posttap level for SERDOUT7± 000 001 010 011 100 [3:0] 0x1222 JESD204B PLL [7:0] calibration Reserved JESD204B PLL calibration reset 0x00 0x04 0x1228 JESD204B PLL [7:0] startup control JESD204B PLL calibration startup circuit reset 0x0F 0x4F JESD204B start-up circuit in normal operation. Reset JESD204B startup circuit. Rev. A | Page 128 of 134 Data Sheet AD9689 Addr. Name Bit(s) Bit Name 0x1262 JESD204B PLL [7:0] JESD204B PLL loss of lock bit clear LOL bit control Setting Description See Table 32. 0x00 0x80 Loss of lock bit normal operation. Clear loss of lock bit. Reset 0x00 Access R/W Programmable Filter (PFILT) Control and Coefficients Registers Table 52. Addr. Name 0x0DF8 Programmable filter control Bit(s) Bit Name [7:3] Reserved [2:0] Setting Programmable filter mode 000 001 010 100 101 110 111 0x0DF9 PFILT gain 7 [6:4] Reserved PFILT Y gain 110 111 000 001 010 3 [2:0] Reserved PFILT X gain 110 111 000 001 010 0x0E00 Programmable Filter X to 0x0E7F Coefficient x [7:0] Programmable Filter X Coefficient 0 to 127 0x0F00 Programmable to Filter Y Coefficient 0x0F7F x [7:0] Programmable Filter Y Coefficient 0 to 127 Description Reserved. Reset Access 0x0 R PFILT mode. The asterisk symbol (*) denotes convolution. 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W Disabled (filters bypassed). Single filter (X only). DOUT_I[n] = DIN_I[n] * X_I[n] DOUT_Q[n] = DIN_Q[n] * X_Q[n] Single filter (X and Y together) DOUT_I[n] = DIN_I[n] * XY_I[n] DOUT_Q[n] = DIN_Q[n] * XY_Q[n] Cascaded filters (X to Y). DOUT_I[n] = DIN_I[n] * X_I[n] * Y_I[n] DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n] DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n] Complex filters. DOUT_I[n] = DIN_I[n] * X_I[n] + DIN_Q[n] * Y_Q[n] DOUT_Q[n] = DIN_Q[n] * X_Q[n] + DIN_I[n] * Y_I[n] Half complex filter. DOUT_I[n] = DIN_I[n] DOUT_Q[n] = DIN_Q[n] * XY_Q[n] + DIN_I[n] * XY_I[n] Real 96-tap filter. DOUT_I[n] = DIN_I[n] * XY_I[n]. DOUT_Q[n] = DIN_Q[n] * XY_Q[n] Reserved. PFILT Y gain. −12 dB loss. −6 dB loss. 0 dB gain. +6 dB gain. +12 dB gain. Reserved. PFILT X gain. −12 dB loss. −6 dB loss. 0 dB gain. +6 dB gain. +12 dB gain. Refer to the I coefficient table (Table 14) and the Q coefficient table (Table 15) in the Programmable FIR Filters section for details. Coefficients are only applied after the chip transfer bit (Register 0x000F, Bit 0) is set. Refer to the I coefficient table (Table 14) and the Q coefficient table (Table 15) in the Programmable FIR Filters section for details. Coefficients are only applied after the chip transfer bit (Register 0x000F, Bit 0) is set. Rev. A | Page 129 of 134 AD9689 Data Sheet VREF/Analog Input Control Registers Table 53. Addr. 0x0701 Name DC offset calibration control (local) 0x073B DC Offset Calibration Control 2 (local) Bit(s) Bit Name [7:0] DC offset calibration control [7:0] Setting Description 0x06 0x86 Disable. Enable. Synchronously reset dc offset calibration accumulator. DC offset calibration accumulator reset 0xB7 0x37 0x18A6 VREF control [7:1] 0 Reserved VREF control 0 1 0x18E3 External VCM buffer control 7 Reserved 6 External VCM buffer Internal reference. External reference. Reserved. 0 1 0x18E6 [5:0] Temperature diode [7:0] export Disable. Enable. See the Input Common Mode section. External VCM buffer[5:0] Temperature diode location select 0x00 0x01 0x02 0x03 0x40 0x41 0x42 0x43 0x50 0x51 0x52 0x53 0x1908 Analog input control (local) [7:3] Reserved 2 Enable dc coupling 0 1 0x1910 Input full-scale control (local) [1:0] [7:4] Reserved Reserved [3:0] Full-scale voltage Accumulator held in reset (use when 0x0701 = 0x06). Accumulator reset released (use when 0x0701 = 0x86). Reserved. Central diode output. VREF pin = high-Z. Central diode output. VREF pin = 1× diode voltage output. Central diode output. VREF pin = 20× diode voltage output. Central diode output. VREF pin = GND. Channel A diode output. VREF pin = high-Z. Channel A diode output. VREF pin = 1× diode voltage output. Channel A diode output. VREF pin = 20× diode voltage output. Channel A diode output. VREF pin = GND. Channel B diode output VREF pin = high-Z. Channel B diode output VREF pin = 1× diode voltage output. Channel B diode output VREF pin = 20× diode voltage output. Channel B diode output VREF pin = GND. Reserved. Analog input is optimized for ac coupling. Analog input is optimized for dc coupling. Reserved. Reserved. 1000 1001 1101 1110 1111 0000 Full-scale voltage setting. 1.13 V p-p differential. 1.25 V p-p differential. 1.7 V p-p differential. 1.81 V p-p differential. 1.93 V p-p differential. 2.04 V p-p differential. Rev. A | Page 130 of 134 Reset Access 0x06 R/W 0xB7 R/W 0x0 0x0 R R/W 0x0 R 0x0 R/W 0x0 0x0 R/W R/W 0x0 R 0x0 R/W 0x0 0x0 R R 0xD R/W Data Sheet Addr. Name 0x1A48 High frequency setting (local) AD9689 Bit(s) Bit Name Setting [7:0] High frequency setting 0x14 0x54 0x1A4C Buffer Control 1 (local) [7:6] Reserved [5:0] Buffer Control 1 00 1111 00 0100 00 1001 01 1110 10 0011 10 1000 10 1101 11 0010 0x1A4D Buffer Control 2 (local) [7:6] Reserved [5:0] Buffer Control 2 00 1111 00 0100 00 1001 01 1110 10 0011 10 1000 10 1101 11 0010 Description First Nyquist operation. Second or higher Nyquist operation. Reserved. Reset Access 0x14 R/W 0x0 R Input Buffer Main Current 1. See the Analog Input Buffer Controls and SFDR Optimization section. Buffer current set to 300 μA Buffer current set to 400 μA. Buffer current set to 500 μA. Buffer current set to 600 μA. Buffer current set to 700 μA. Buffer current set to 800 μA. Buffer current set to 900 μA. Buffer current set to 1000 μA. Reserved. 0x0F R/W 0x0 R Input Buffer Main Current 2. See the Analog Input Buffer Controls and SFDR Optimization section. Buffer current set to 300 μA Buffer current set to 400 μA. Buffer current set to 500 μA. Buffer current set to 600 μA. Buffer current set to 700 μA. Buffer current set to 800 μA. Buffer current set to 900 μA. Buffer current set to 1000 μA. 0x0F R/W Rev. A | Page 131 of 134 AD9689 Data Sheet APPLICATIONS INFORMATION It is not necessary to split all of these power domains in all cases. The recommended solution shown in Figure 157 provides the lowest noise, highest efficiency power delivery system for the AD9689. If only one 0.975 V supply is available, route to AVDD1 first and then tap it off and isolate it with a ferrite bead or a filter choke, preceded by decoupling capacitors for AVDD1_SR, DVDD, and DRVDD1, in that order. Figure 158 shows the simplified schematic. The dc resistance (DCR) of the ferrite bead must be taken into consideration when choosing the appropriate ferrite bead. Otherwise, excessive loss across the ferrite bead can lead to a malfunctioning ADC. Adjustable LDOs can be employed to output a higher voltage to account for the drop across the ferrite bead. POWER SUPPLY RECOMMENDATIONS The power supplies required to power the AD9689 are shown in Table 54. A power-on sequence is not required to operate the AD9689. The power supply domains can be powered up in any order. Table 54. Typical Power Supplies for the AD9689 Voltage (V) 0.975 0.975 0.975 0.975 1.9 1.9 1.9 2.5 Tolerance (%) ±2.5 ±2.5 ±2.5 ±2.5 ±2.5 ±2.5 ±2.5 ±2.5 For applications requiring an optimal high power efficiency and low noise performance, it is recommended that the ADP5054 quad switching regulator be used to convert an input voltage in the 6.0 V to 15 V range to intermediate rails (1.3 V, 2.4 V, and 3.0 V). These intermediate rails are then postregulated by very low noise, low dropout (LDO) regulators (ADP1763, ADP7159, and LT3045). Figure 157 shows the recommended power supply scheme for the AD9689. 6.0V TO 15.0V 1.3V ANALOG ADP5054 1.3V DIGITAL ADP1763 ADP1763 Alternatively, the LDOs can be bypassed altogether and the AD9689 can be driven directly from the dc-to-dc converter. Note that this approach has risks in that there may be more power supply noise inserted into the power supply domains of the ADC. To minimize noise, follow the layout guidelines of the dc-to-dc converter. 12V FROM FMC OR 6.0V FROM WALL SUPPLY SW1 1.3V ANALOG ADP1763 SW2 ADP5054 AVDD1 0.975V SW3 AVDD1_SR 0.975V OPTIONAL DVDD 0.975V SW4 1.3V DIGITAL DVDD 0.975V DRVDD1 0.975V 2.4V LT3045 LT3045 LT3045 AVDD2 1.9V SPIVDD 1.9V OPTIONAL DRVDD2 1.9V FERRITE BEAD LDO SWITCHER OPTIONAL PATH LT3045 3.0V LT3045 AVDD3 2.5V NOTES 1. ALL VOLTAGES REFERENCED TO AGND. SPIVDD 1.9V 3.0V AVDD2 1.9V DRVDD2 1.9V DRVDD1 0.975V 2.4V AVDD1 0.975V AVDD1_SR 0.975V Figure 158. Simplified Power Solution for the AD9689 AVDD3 2.5V 15550-072 LDO SWITCHER OPTIONAL PATH REFERENCED TO AGND The user can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors must be located close to the point of entry at the PCB level and close to the devices, with minimal trace lengths. Figure 157. High Efficiency, Low Noise Power Solution for the AD9689 Rev. A | Page 132 of 134 15550-327 Domain AVDD1 AVDD1_SR DVDD DRVDD1 AVDD2 DRVDD2 SPIVDD AVDD3 Data Sheet AD9689 LAYOUT GUIDELINES AVDD1_SR (PIN E7) AND AGND (PIN E6 AND PIN E8) The ADC evaluation board can be used as a guide to follow good layout practices. The evaluation board layout is set up in such a way as to Use AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8) to provide a separate power supply node to the SYSREF± circuits of the AD9689. If running in Subclass 1, the AD9689 can support periodic one-shot or gapped signals. To minimize the coupling of this supply into the AVDD1 supply node, adequate supply bypassing is needed. • • • • Minimize coupling between the analog inputs (Channel A to Channel B and Channel B to Channel A). Minimize clock coupling to the analog inputs. Provide enough power and ground planes for the various supply domains while reducing cross coupling. Provide adequate thermal relief to the ADC. Figure 159 shows the overall layout scheme used for the AD9689 evaluation boards. CH.A ADC CH.B JESD204B LANES POWER Figure 159. Recommended PCB Layout for the AD9689 Rev. A | Page 133 of 134 15550-328 CLK± AD9689 Data Sheet OUTLINE DIMENSIONS 7.50 SQ 11.20 SQ TOP VIEW 1.53 1.42 1.31 A B C D E F G H J K L M N P 10.40 REF SQ 0.80 BOTTOM VIEW 0.80 REF DETAIL A SIDE VIEW 0.71 REF DETAIL A 1.19 1.09 0.99 0.38 0.33 0.28 0.34 REF SEATING PLANE PKG-004807 A1 BALL PAD CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.50 0.45 0.40 BALL DIAMETER COPLANARITY 0.12 COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1. 12-07-2015-B A1 BALL PAD CORNER 12.10 12.00 SQ 11.90 Figure 160. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] 12 mm × 12 mm (BP-196-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9689BBPZ-2000 AD9689BBPZRL-2000 AD9689BBPZ-2600 AD9689BBPZRL-2600 AD9689-2000EBZ AD9689-2600EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] Evaluation Board Evaluation Board Z = RoHS Compliant Part. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15550-0-10/17(A) Rev. A | Page 134 of 134 Package Option BP-196-4 BP-196-4 BP-196-4 BP-196-4