www.fairchildsemi.com Application Note AN-3012 High Speed Logic Compatible, Half-Pitch Mini-Flat Optocoupler, FODM8061 Introduction FODM8061’s Electrical Operation The FODM8061, a high-speed, high noise immunity optocoupler, is constructed in a high insulation voltage SO5 mini-flat package. This optocoupler’s optical input uses an aluminum gallium arsenide, AlGaAs, LED. The LED is coupled to a high-speed bipolar integrated logic compatible receiver. One major advantage of this product is that the high speed optical IC is specified with guaranteed performance at both 3.3V and 5V logic supplies. The optocoupler’s open collector Schottky-clamped transistor output insures compatibility with a wide range of logic families. The optocoupler’s key AC and DC characteristics are guaranteed over an operating temperature range of -40°C to +110°C. The FODM8061 is a two chip optical hybrid. The input chip is a high speed, low input current, infrared light emitting diode, LED. The LED generates an optical flux in direct relationship to the LED’s forward current, IF. The LED’s output is coupled to a high speed bipolar optical receiver through a low capacitance, “co-planar” optical coupling. The receiver IC converts the optical energy into electrical current and amplifies it to drive a load. This application note highlights the key electrical and switching performances of the high speed optocoupler, FODM8061. It also explores the data communication signal quality by examining the eye diagrams and the optocoupler’s common usage in logic interfacing applications. The SO5 Mini-Flat Package Improves PCB Layout The FODM8061 optocoupler is an enhanced version of the industry standard 6N137. The 6N137 optocoupler’s package is an 8-pin dual in-line DIP leadform configuration. [Refer to the Fairchild Semiconductor Optocoupler Selection Catalog for additional package selections.] The FODM8061’s smaller SO5 package results in a more condensed PCB footprint. This small footprint enhances multi-channel packaging density without sacrificing channel-to-channel and input-to-output insulation safety. This is a primary consideration when isolation is needed for parallel and bidirectional data communication and logic interfacing. This package utilizes Fairchild's patented “Optoplanar®” co-planar packaging technology. This packaging technology enhances the superior common mode transient immunity of the shielded optical integrated receiver. This package has received Underwriter’s Laboratories 1577 (UL1577) safety approval for an insulation test voltage (VISO) of 3,750Vac(RMS), and pending IEC60747-5-2 approval status. This mini-flat package is also compatible with 260°C surface mount solder reflow assembly processes. Figure 1 shows the block diagram of the FODM8061 optocoupler. The input consists of the anode and cathode of an IR LED. This LED has a typical forward voltage, VF , of 1.45V when the forward current, IF , is 10mA. The photo flux is coupled to a reverse-biased photodiode. The photodiode generates a photocurrent which flows from its anode into the bipolar amplifier. This linear amplifier has a typical current gain of 60dB and a 40MHz bandwidth. The output of this amplifier is a Schottky clamped opencollector NPN transistor. High levels of power supply and common mode power noise rejection is insured by including a bias and regulator circuit function. This circuit isolates the photodiode from power supply, common mode noise that can be coupled into the VCC, and output of the optocoupler. Anode 1 Bias & Regulator 6 VCC Amp 5 VO Cathode 3 4 GND Figure 1. FODM8061 Block Diagram This optocoupler functions as a logic inverter. A logic input signal which forces a forward current greater than 5mA through the LED will cause the output transistor to sink current supplied by an external load. Table 1 illustrates the truth table for positive logic. Table 1. Truth Table LED Output Off High On Low REV. 1.0 3/9/10 APPLICATION NOTE The “Optoplanar” package increases the common mode noise rejection by reducing the package and common mode coupling capacitance, CCM. The CCM is further reduced by a proprietary electric shield that covers the receiver IC. The shield shunts common mode noise away from the input of the optical amplifier to the ground connection of the optical amplifier. This shield is shown as the dotted line between the LED and receiver IC. The combination of “Optoplanar” construction and the electric shield provides a common mode transient immunity, CMTI, in excess of 20kV/us for a 1kV pulse. More details are discussed in application note, “Common Mode Transient Immunity (CMTI) of High Performance Optocoupler” ICE – COLLECTOR-EMITTER CURRENT (mA) AN-3012 ICE – COLLECTOR-EMITTER CURRENT (mA) 70 60 50 40 30 20 IF = 1mA 0 1.0 2.0 3.0 VCE = 1.5V 40 30 20 VCE = 0.4V 10 0 2.0 4.0 6.0 8.0 4.0 5.0 VCE – COLLECTOR-EMITTER VOLTAGE (V) Figure 3. Saturated & Non-Saturated ICE vs IF Figure 4 shows the saturated and non-saturated CTR for the FODM8061. This curve illustrates the consistency of the saturated CTR (approx 160%) over an LED forward current of 4mA through 10mA. This curve can be used to estimate the minimum LED current required to force a specific load into saturation at a given operating VCC. The data sheet uses a 350Ω collector load resistor for most of the switching specifications. If the VCC is 3.3V, then the saturated, (VCE = 0.4V) ICE is 8.3mA for a 350Ω load. The saturated CTR from Figure 4 is 160%. Recall that the LED current is equal to the ICE divided by the CTR, or 8.3mA/160%. Given this, the LED current should be 5.2mA or greater to insure a logic level low at room temperature. When the VCC is increased to 5V and the same load is used, the LED current must be increased to insure saturated operation. With VCC = 5V, the 350Ω load current is 13mA. Again, assuming a typical saturated CTR (VCE = 0.4V) of 160%, the LED current should be 8.2mA or greater. Figure 2. ICE vs VCE Family , IF = 1mA steps 700 CTR – CURRENT TRANSFER RATIO (%) Figure 2 shows the family of collector-emitter current, ICE, vs collector-emitter voltage, VCE , as a function of LED forward current, IF . The LED is stepped in 1mA increments. Figure 2 shows the near linear operation for LED current operation from 1mA through 4mA. Figure 3 sweeps the LED current and shows the resulting collector current under the linear (VCE = 1.5V, upper curve)) and saturated (VCE = 0.4V, lower curve) operation. Note that the output ICE when in saturation (VCE = 0.4V) is 8.05mA with a LED current of 5mA. The non saturated ICE is 33mA under the same LED drive. This difference in output current is a function of the output transistor, not the photo-amplifier. VCE(UNSAT) 600 500 400 300 200 VCE(SAT) 100 0 0 2.0 4.0 6.0 8.0 IF – FORWARD CURRENT (mA) Figure 4. Saturated and non-saturated CTR 2 10.0 IF – FORWARD CURRENT (mA) The FODM8061 is an optocoupler that includes a linear amplifier that drives the output transistor into saturation. Given this characteristic, it is appropriate to discuss current transfer ratio under non saturated and saturated VCE conditions. 0 50 0 Current Transfer Ratio 10 60 REV. 1.0 3/9/10 10.0 APPLICATION NOTE AN-3012 The data sheet offers a minimum CTR of 260% and a typical CTR of 380% for VCE = 6V. This data is consistent with the expected CTR sensitivity to VCE operation as presented in Figure 4. LED Forward Current Switching Threshold VCE – COLLECTOR-EMITTER VOLTAGE (V) The CTR of the FODM8061 can be discussed in terms of an LED threshold current. Figure 5 illustrates the required LED current for an IOL of 10mA, under the condition of VCC = 3.3V (lower curve) and 5V (upper curve). These curves illustrate that VCC has a minor effect on the LED switching threshold. Switching Performance The FODM8061 is an optocoupler that contains a linear optical amplifier which is designed to function as an isolated logic inverter. The switching performance of the FODM8061 optocoupler is quantified in terms of propagation delay, pulse width distortion, and pulse skew. 6 IF = 7.5mA 5 VCC = 3.3V 3 6 R1 100Ω 5 2 R3 350Ω VO – Output R2 100Ω 15pF 3 1 VCC = 3.3V, 5V C1 0.1µF Pulse Generator ZO = 50Ω tR = tF = 5ns Period = 200ns DF = 50% 4 4 Figure 7. Switching Test Circuit 0 1.0 2.0 3.0 4.0 5.0 IF – FORWARD CURRENT (mA) Figure 5. LED Threshold Current at VCC= 3.3 and 5V The threshold does have modest temperature dependence. This is shown in Figure 6. 6 1 VCC = 5V 0 IOL = 13mA Propagation delay through this optocoupler is related to peak LED drive, power supply voltage, load resistor, and temperature. As shown in Figure 7, this device is optimized for operation with 7.5mA of LED drive, a 5V supply voltage, and a 350Ω load resistor. Under this condition, a typical device offers a symmetrical high-to-low and low-to- high propagation delay of approximately 36ns. Figure 8 shows the typical delay performance over the recommended operating temperature range of -40ºC to 110ºC. 70 5 4 t P – PROPAGATION DELAY (ns) IFHT – THRESHOLD INPUT CURRENT (mA) The LED’s light output will decrease with increased junction temperature when driven by a constant drive current. The photo amplifier’s DC gain increases with increased ambient temperature. In most cases, these two relationships are designed to cancel each other, as is the case for the FODM8061. VCC = 5.0V VCC = 3.3V 3 2 1 -40 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 Figure 6. Input Threshold Current vs. Ambient Temperature Frequency = 5MHz Duty Cycle = 50% IF = 10mA RL = 350Ω 60 50 tPLH @ VCC = 3.3V tPLH @ VCC = 5.0V 40 tPHL @ VCC = 3.3V t PHL@ VCC = 5.0V 120 30 -40 -20 0 20 40 60 80 100 120 TA – AMBIENT TEMPERATURE (°C) Figure 8. Propagation Delay vs Temperature REV. 1.0 3/9/10 3 AN-3012 APPLICATION NOTE Figure 9 provides insight on how the pulse width distortion changes with temperature. The typical pulse width distortion, PWD, [tPHL – tPLH] is 2ns. These performance characteristics allow high serial data (> 20Mbaud) communication through the optocoupler. (tPHL – tPLH) – PULSE WIDTH DISTORTION (ns) 10 Frequency = 5MHz Duty Cycle = 50% IF = 10mA RL= 350Ω 5 0 VCC = 5.0V Signal Performance One of the best indicators of data communication signal quality is an eye diagram. The eye diagram is created by driving the LED with a pseudorandom binary data sequence, PRBS, and triggering the scope with the serial data clock. Figure 10 shows a 10MBd eye diagram using the test circuit found in Figure 7. This diagram shows a duty cycle distortion of only 2.18ns. This is very close to the typical PWD of 2ns. The LED current was adjusted for optimal crossing, under this condition, the rise and fall times are symmetrical and less than 20ns. -5 VCC = 3.3V -10 -15 -20 -25 -40 -20 0 20 40 60 80 100 120 TA – AMBIENT TEMPERATURE (°C) Figure 9. Pulse Width Distortion vs Temperature There are various assumptions which are made in relation of switching speed to baud rate, such as binary Non-Return-Zero (NRZ) data stream, 1 bit time equating 1 baud (or signaling rate) and a square wave pattern. Therefore, a 5MHz square wave (duty factor of 50%) is a 10Mbit or 10MBaud signal. For serial communications (RS standards), propagation delay only affects latency or data throughput. The maximum data rate is related to PWD performance and the number of samples per bit used by the UART to validate the 1 or 0 data. The minimum acceptable sample rate is 4, which is half the Nyquist recommended rate. Thus, the recommended maximum data rate is usually 4 times that of the PWD. In the case of FODM8061, with a maximum PWD of 25ns the maximum data rate is 10MBd. Ideally, the delay skew, tPSK, should be specified at about 2 times the maximum PWD. It is important to note that tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between any two units from the same manufacturing date code that are operated at same operating conditions; same case temperature, equal loads (RL = 350Ω and CL = 15pF), and with an input rise time less than 5ns. 4 Figure 10. 10MBd Eye Diagram Figure 11 illustrates the typical and respectable eye diagram for 20MBd PRBS data. Figure 11. 20MBd Eye Diagram REV. 1.0 3/9/10 APPLICATION NOTE AN-3012 Output Power Consumption versus Propagation Delay When a non-inverting interface is needed, the LED shunt drive is used. This circuit schematic is shown in Figure 14. tpHL, tpLH – PROPAGATION DELAY (ns) The passive resistive pull-up resistor does dissipate power when the output of the optocoupler is switched into the logic low state. Increasing the collector load resistor does reduce power consumption at the price of longer turn-off delay and larger pulse width distortion. Figure 12 shows the expected increase propagation delay from the logic low to logic high. VDD1 = 3.0V–3.6V C1 0.1µF VDD2 = 3.3V–5V Input 160 tA = 23°C VCC = 3.3V IF = 10mA Period = 1ms PW = 100µs 140 R1 220Ω 1 6 R2 350Ω 74LCX07 Output 5 120 tpLH (ns) 100 C2 0.1µF 3 80 4 FODM8061 tpHL (ns) 60 Figure 14. Non-inverting Logic interface 40 0 2 4 6 8 RLOAD – COLLECTOR LOAD RESISTOR (kΩ) 10 12 Figure 12. Propagation vs Collector Load Resistor Logic Interfacing The FODM8061 is a versatile logic-to-logic interface optocoupler. The low forward voltage of the LED permits operation among logic families with supply ranges from 2.3V to 15V. Figure 13 shows an inverting interface between a 3V 74LCX07 open drain buffer to output logic families from 3.3V to 5V. The current to the LED is set by R1 (82Ω) to approximately 10mA. R2 (430Ω) provides the pull-up needed by the open drain ’07 gate. VDD1 = 3.0V–3.6V VDD2 = 3.3V–5V 1 6 C1 100nF R3 350Ω R2 430Ω R1 82Ω Input Interface Circuit for VCC Greater than 5.5V Industrial systems today still use the 15V CD4xxx logic gates, which offer exceptional logic noise immunity, mainly due to their high switching thresholds and slow operating speed. When a low voltage high speed optocoupler is needed to interface into logic families with supply voltages greater than 5.5V, a buffer transistor is needed. Figure 15 shows the use of a cascode amplifier interface, which uses an inexpensive bipolar 2N2222 NPN transistor with a Schottky “Baker Clamp”. This circuit switches a 25mA load from a 25V supply. The cascode circuit maintains the same logic sense as the original optocoupler interface and as Figure 20 shows the rise and fall times, and the propagation delays well under 100ns. The 5V supply voltage of the optocoupler can be supplied by a Zener diode, from a regulated supply. C2 100nF 3 74LCX07 Output 5 The output transistor of the 74LCX07 shunts the drive current away from the LED when its output is forced low. This type of interface offers the lowest LED off-state impedance resulting in improved LED noise immunity. 4 FODM8061 Figure 13. Inverting Series LED drive REV. 1.0 3/9/10 5 AN-3012 APPLICATION NOTE V = 25V C3 22µF C2 0.1µF D1 1N5712 R4 1k2Ω Output Q1 2N222 R3 220Ω 1 LED Current = 10mA 6 VCC = 5.0V C1 0.1µF R1 100Ω 5 R2 100Ω 3 4 FODM8061 Figure 15. Bipolar Cascode Interface Figure 16. Bipolar HV Cascode Timing 6 REV. 1.0 3/9/10 APPLICATION NOTE AN-3012 Interfacing to Voltages Greater than 25V Using a high voltage low current signal MOSFET, it is possible to drive loads with supply voltages much greater than 25V. The BSS123 can be used for supplies up to 100V. If higher interface voltages are needed the BSS125 can support supplies to 600V. Figure 17 shows a MOSFET cascode interface operating from a 50V source. The load current is 25mA. The 5V supply voltage needed by the FODM8061 can be supplied from an external regulated power supply or via a Zener or other regulator deriving its power from the high voltage source. V = 25V C3 22µF C2 0.1µF R4 2kΩ Output D G BSS123 1 LED Current = 10mA 6 VCC = 5.0V R3 1kΩ R1 100Ω S C1 0.1µF 5 R2 100Ω 3 4 FODM8061 Figure 17. Optocoupler MOSFET Cascode Interface Figure 18 shows the timing performance of the MOSFET high voltage cascode interface. The dv/dt of the leading falling edge is about 1.5kV/µs, which is a respectable transition time. Conclusion The FODM8061 high speed optocoupler is an easy to use, multi-purpose optocoupler ideal for isolating communication links with bandwidths of 10MBaud. The FOM8061’s compact package and proven reliable galvanic isolation makes it ideal ensuring safe operation in terms of both safety and signal integrity. Figure 18. HV MOSFET Cascode Interface REV. 1.0 3/9/10 7 AN-3012 APPLICATION NOTE DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. 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