DA9061 Entry level PMIC for applications requiring up to 6 A General description DA9061 is a power management integrated circuit (PMIC) optimised for supplying systems with single- and dual-core processors, I/O, DDR memory, and peripherals. It targets mobile device, medical equipment, entry level IVI system, and FPGA based applications. DA9061 features three buck converters providing a total current of 6 A. High efficiency is achieved over a wide load range by using automatic Pulse Frequency Modulation (PFM) mode. All power switches are integrated, therefore, external Schottky diodes are not required. Furthermore, lowprofile inductors can be used with DA9061. The four LDO regulators with programmable output voltage provide up to 300 mA. Dynamic voltage control (DVC) allows dynamic control of DA9061 supply voltages according to the 2 operating point of the system. It is controlled by writing directly to the registers using the I C compatible 2-wire interface or the GPIOs. DA9061 features a programmable power sequencer that handles start-up and shutdown sequences. Power mode transitions can be triggered with software control, GPIOs, or with the on-key. Several types of on-key presses can be detected to trigger different power mode transitions. An integrated watchdog timer monitors the system. Five GPIOs are able to perform system functions, including: keypad supervision, application buck, and timing-controlled external regulators/power switches or other ICs. DA9061 is also available as an automotive AEC-Q100 Grade 3 version. Key features ■ Input voltage 2.8 to 5.5 V ■ Three buck converters with dynamic voltage ■ Programmable power mode sequencer ■ System supply and junction temperature control: □ □ □ □ monitoring Buck1: 0.3 to 1.57 V, 2.5 A Buck2: 0.8 to 3.34 V, 2 A Buck3: 0.53 to 1.8 V, 1.5 A 3 MHz switching frequency (enables low profile inductors) ■ Four LDO regulators: □ LDO1: 0.9 to 3.6 V, 100 mA □ LDO2, LDO3, LDO4: 0.9 to 3.6 V, 300 mA ■ ■ ■ ■ ■ Watchdog timer Five GPIOs -40 to +85 °C temperature range 40-pin QFN, 6×6 mm package, 0.5 mm pitch Automotive AEC-Q100 Grade 3 variant available Applications ■ Supply for single and dual core application processors such as ARM Cortex or i.MX6 series ■ Power supply for entry-level FPGAs Datasheet CFR0011-120-00 Rev 5 ■ Automotive infotainment ■ Portable industrial and medical devices ■ E-book readers Revision 3.2 1 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Block diagram CVDDCORE VDDCORE VDDIO VSYS LDO1 BUCK1 CLDO1 VDD_BUCK1 LBUCK1 VDD_LDO2 CBUCK1 LDO2 CLDO2 BUCK2 VDD_LDO34 VDD_BUCK2 LBUCK2 LDO3 CLDO3 CBUCK2 LDO4 CLDO4 DA9061 BUCK3 VDD_BUCK3 LBUCK3 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 CBUCK3 GPIO nONKEY nRESETREQ nRESET nIRQ VREF Power Sequencer Control And Status Registers Interrupt Control 2-Wire Interface CVREF IREF RIREF WD SCL SDA TP Figure 1: DA9061 block diagram Datasheet CFR0011-120-00 Rev 5 Revision 3.2 2 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Contents General description ............................................................................................................................. 1 Key features ......................................................................................................................................... 1 Applications ......................................................................................................................................... 1 Block diagram ...................................................................................................................................... 2 Contents ............................................................................................................................................... 3 1 Package information ..................................................................................................................... 6 1.1 Pin list .................................................................................................................................... 6 1.2 Package outline drawing ....................................................................................................... 8 2 Absolute maximum ratings .......................................................................................................... 9 3 Recommended operating conditions .......................................................................................... 9 4 Electrical characteristics ............................................................................................................ 10 4.1 Digital I/O ............................................................................................................................ 10 4.2 Watchdog ............................................................................................................................ 11 4.3 2-wire interface .................................................................................................................... 11 4.4 LDOs ................................................................................................................................... 12 4.4.1 LDO1.................................................................................................................... 12 4.4.2 LDO2, LDO3, LDO4 ............................................................................................. 14 4.4.3 LDOCORE ........................................................................................................... 15 4.5 Buck converters .................................................................................................................. 16 4.5.1 Buck1 ................................................................................................................... 16 4.5.2 Buck2 ................................................................................................................... 18 4.5.3 Buck3 ................................................................................................................... 20 4.6 Internal oscillator ................................................................................................................. 21 4.7 System supply voltage supervision ..................................................................................... 22 4.8 Junction temperature supervision ....................................................................................... 22 4.9 Current consumption ........................................................................................................... 23 5 Typical characteristics ................................................................................................................ 24 6 Functional description ................................................................................................................ 26 6.1 Control signals .................................................................................................................... 26 6.1.1 nONKEY .............................................................................................................. 26 6.1.2 nRESETREQ ....................................................................................................... 26 6.1.3 nRESET ............................................................................................................... 27 6.1.4 nIRQ..................................................................................................................... 27 6.2 2-wire interface .................................................................................................................... 27 6.2.1 Register map paging............................................................................................ 28 6.2.2 Details of the 2-wire protocol ............................................................................... 28 6.3 GPIOs.................................................................................................................................. 30 6.3.1 GPI functionality................................................................................................... 31 6.3.2 GPO functionality ................................................................................................. 32 6.3.3 Alternate functions ............................................................................................... 32 6.3.4 GPIO forwarding .................................................................................................. 33 6.4 Dynamic voltage control ...................................................................................................... 33 6.5 Regulator voltage A and B selection ................................................................................... 33 6.6 LDOs ................................................................................................................................... 34 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 3 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.6.1 Control ................................................................................................................. 34 6.6.2 Current limit ......................................................................................................... 34 6.6.3 Output pull-down .................................................................................................. 34 Switching regulators ............................................................................................................ 35 6.7.1 Control ................................................................................................................. 35 6.7.2 Output voltage slewing ........................................................................................ 35 6.7.3 Soft-start .............................................................................................................. 35 6.7.4 Active discharge .................................................................................................. 35 6.7.5 Peak current limit ................................................................................................. 35 6.7.6 Operating mode ................................................................................................... 36 6.7.7 Half-current mode ................................................................................................ 36 Power modes ...................................................................................................................... 37 6.8.1 NO-POWER mode............................................................................................... 37 6.8.2 RESET mode ....................................................................................................... 38 6.8.3 POWERDOWN mode .......................................................................................... 39 6.8.4 Power-up, power-down, and shutdown sequences ............................................. 40 6.8.5 ACTIVE mode ...................................................................................................... 40 Power supply sequencer ..................................................................................................... 41 6.9.1 Sub-sequences .................................................................................................... 42 6.9.2 Regulator control ................................................................................................. 42 6.9.3 GPO control ......................................................................................................... 43 6.9.4 Wait step .............................................................................................................. 44 6.9.5 Power-down disable ............................................................................................ 44 Junction temperature supervision ....................................................................................... 44 System supply voltage supervision ..................................................................................... 44 Internal oscillator ................................................................................................................. 45 Watchdog ............................................................................................................................ 45 7 Register map ................................................................................................................................ 46 7.1 Register page control .......................................................................................................... 46 7.2 Overview ............................................................................................................................. 46 8 Application information .............................................................................................................. 49 8.1 Component selection .......................................................................................................... 49 8.1.1 Resistors .............................................................................................................. 49 8.1.2 Capacitors ............................................................................................................ 49 8.1.3 Inductors .............................................................................................................. 50 8.2 PCB layout .......................................................................................................................... 51 8.2.1 General recommendations .................................................................................. 51 8.2.2 LDOs and switched mode supplies ..................................................................... 52 8.2.3 Optimising thermal performance ......................................................................... 52 9 Ordering information .................................................................................................................. 53 Appendix A Register descriptions ................................................................................................... 54 A.1 PAGE 0 ............................................................................................................................... 54 A.1.1 Page control ......................................................................................................... 54 A.1.2 Power manager control and monitoring (except IRQs and events)..................... 54 A.1.3 IRQ events ........................................................................................................... 55 A.1.4 IRQ masks ........................................................................................................... 56 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 4 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A A.2 A.3 A.1.5 System control ..................................................................................................... 57 A.1.6 GPIO control ........................................................................................................ 59 A.1.7 Power supply control ........................................................................................... 62 PAGE 1 ............................................................................................................................... 67 A.2.1 Power sequencer ................................................................................................. 67 A.2.2 Power supply control ........................................................................................... 71 PAGE 2 ............................................................................................................................... 74 A.3.1 Customer trim and configuration ......................................................................... 74 A.3.2 Customer device specific ..................................................................................... 78 Revision history ................................................................................................................................. 81 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 5 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 1 1.1 Package information Pin list Table 1: DA9061 pin description Pin Name Type Table 2 Description Paddle GND GND Power grounds of the bucks, digital ground 1 VLDO1 AO LDO1 output voltage 2 VLDO2 AO LDO2 output voltage 3 VDD_LDO2 PS LDO2 supply 4 IREF AO Reference current 5 VREF AIO Reference voltage 6 NC 7 VSS_ANA 8 NC 9 VLDO3 AO LDO3 output voltage 10 VDD_LDO34 PS LDO3 and LDO4 supply 11 VLDO4 AO LDO4 output voltage 12 NC 13 SDA DIO Data signal of the 2-wire interface 14 SCL DI Clock signal of the 2-wire interface 15 nONKEY DI Input for power-on key 16 nRESETREQ DI Reset request input 17 VLX_BUCK3 AO Switching node of Buck3 18 VDD_BUCK3 PS Buck3 supply 19 VDD_BUCK2 PS Buck2 supply 20 VLX_BUCK2 AO Switching node of Buck2 21 GPIO0 DIO General purpose I/O, WDKICK 22 GPIO1 DIO General purpose I/O 23 VDDIO PS IO supply 24 VBUCK3 AI Voltage feedback of Buck3 25 VBUCK2 AI Voltage feedback of Buck2 26 VBUCK1 AI Voltage feedback of Buck1 27 NC 28 GPIO2 DIO General purpose I/O, PWR_EN 29 GPIO3 DIO General purpose I/O 30 GPIO4 DIO General purpose I/O, SYS_EN 31 VLX_BUCK1 AO Switching node of Buck1 32 VDD_BUCK1 PS Buck1 supply 33 NC Datasheet CFR0011-120-00 Rev 5 Do not use. Leave floating. GND Analog ground Do not use. Leave floating. Do not use. Leave floating. Do not use. Leave floating. Do not use. Leave floating. Revision 3.2 6 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Pin Name Type Table 2 Description 34 NC Do not use. Leave floating. 35 NC Do not use. Leave floating. 36 TP DIO Test pin 37 nIRQ DO Interrupt signal to host processor 38 nRESET DO Reset output 39 VDDCORE AO Internal supply 40 VSYS PS System supply, LDO1 supply Table 2: Pin type definitions Pin type Description Pin type Description DI Digital Input AI Analog Input DO Digital Output AO Analog Output DIO Digital Input/Output AIO Analog Input/Output PS Power Supply GND Ground connection Datasheet CFR0011-120-00 Rev 5 Revision 3.2 7 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 1.2 Package outline drawing Figure 2: DA9061 package outline drawing Datasheet CFR0011-120-00 Rev 5 Revision 3.2 8 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 2 Absolute maximum ratings Table 3 lists the absolute maximum ratings of the device. Exceeding these ratings may cause permanent damage to the device. Device functionality is only guaranteed under the conditions listed in Sections 3 and 4. Operating the device in conditions exceeding those listed in Sections 3 and 4, but compliant with the absolute maximum ratings listed in Table 3, for extended periods of time may affect device reliability. Table 3: Absolute maximum ratings Parameter Symbol Test conditions Storage temperature Min Typ Max Unit -65 +150 °C Operating junction temperature TJ -40 +150 Note 1 °C Supply voltage VSYS -0.3 5.5 V All other pins -0.3 VSYS + 0.3 Note 2 V ESD protection HBM 2000 ESD protection CDM Corner pins 750 All other pins 500 V V Note 1 See Sections 4.8 and 6.10 for more detail. Note 2 Voltage must not exceed 5.5 V. 3 Recommended operating conditions Table 4: Recommended operating conditions Parameter Symbol Ambient operating temperature TA Supply voltage VSYS Supply voltage IO VDDIO Maximum power dissipation Note 2 Test conditions IO supply voltage Note 1 Derating factor above Min Typ Max Unit -40 +85 °C 0 5.5 V 1.2 3.6 V 3000 mW TA = 70 °C: 56 mW/°C Note 1 VDDIO must not exceed VSYS. Note 2 Obtained from package thermal simulation, board dimension 76 mm x 114 mm x 1.6 mm (JEDEC), 6layer board, 35 μm thick copper top/bottom layers, 17 μm thick copper inside layers, natural convection (still air). Datasheet CFR0011-120-00 Rev 5 Revision 3.2 9 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 4 4.1 Electrical characteristics Digital I/O Unless otherwise noted, the following is valid for T A = -40 to +85 ºC, VSYS = 2.8 to 5.5 V. Table 5: Digital I/O electrical characteristics Parameter Symbol Test conditions Min Input high voltage (GPI0-GPI4, nRESETREQ) VIH VDDCORE mode Input low voltage (GPI0–GPI4, nRESETREQ) VIL Input high voltage (nONKEY) VIH Input low voltage (nONKEY) VIL Input high voltage (SCL, SDA) VIH Input low voltage (SCL, SDA) VIL Output high voltage (GPO0–GPO4, nRESET, nIRQ) VOH ILOAD = 1 mA Push-pull mode Output low voltage (GPO0–GPO4, nRESET, nIRQ) VOL ILOAD = 1 mA 0.3 V Output low voltage (SDA) VOL ILOAD = 20 mA 0.4 V ILOAD = 3 mA 0.24 Source current capability (GPO0–GPO4) IOH VOUT = 0.7 * VDDIO VDDIO ≥ 1.8 V -1 mA Sink current capability (GPO0–GPO4) IOL VOUT = 0.3 V 1 mA Input capacitance (SCL, SDA) CIN Pull-down resistance (GPI0–GPI4) RPD Pull-up resistance (GPO0–GPO4) RPU Datasheet CFR0011-120-00 Rev 5 Max Unit 1.0 VSYS V 0.7 * VDDIO VSYS VDDCORE mode -0.3 0.4 VDDIO mode -0.3 0.3 * VDDIO VDDCORE mode 1.0 VSYS V V VDDIO mode VDDIO mode Typ V 0.7 * VDDIO VDDCORE mode -0.3 0.4 VDDIO mode -0.3 0.3 * VDDIO VDDCORE mode 1.0 VDDIO mode V 0.7 * VDDIO VDDCORE mode 0.4 VDDIO mode V 0.3 * VDDIO 0.7 * VDDIO V 10 pF 50 100 250 kΩ VDDIO = 1.5 V 60 180 310 k VDDIO = 1.8 V 45 120 190 VDDIO = 3.3 V 20 40 60 Revision 3.2 10 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 4.2 Watchdog Unless otherwise noted, the following is valid for T A = -40 to +85 ºC, VSYS = 2.8 to 5.5 V. Table 6: Watchdog electrical characteristics Parameter Symbol Minimum watchdog time tWDMIN Test conditions Min Typ Internal 25 kHz oscillator Maximum watchdog time 4.3 Unit 200 ms tWDMAX Internal 25 kHz oscillator Minimum assert time of WDKICK Max 2.5 s tWDKICKMIN 150 µs 2-wire interface Figure 3: 2-wire interface timing Unless otherwise noted, the following is valid for T A = -40 to +85 ºC, VSYS = 2.8 to 5.5 V. Table 7: 2-wire interface electrical characteristics Parameter Symbol Bus free time STOP to START tBUF Bus line capacitive load CB Test conditions Min Typ Max 0.5 Unit µs 150 pF 1000 kHz Standard/Fast/Fast+ Mode SCL clock frequency fSCL Start condition set-up time tSU_STA 0.26 µs Start condition hold time tH_STA 0.26 µs SCL low time tLOW 0.5 µs SCL high time tHIGH 0.26 µs 2-WIRE SCL and SDA rise time tR (input requirement) 1000 ns 2-WIRE SCL and SDA fall time tF (input requirement) 300 ns Data set-up time tSU_D 50 ns Data hold-time tH_D 0 ns Data valid time tVD_D Datasheet CFR0011-120-00 Rev 5 Note 1 0 0.45 Revision 3.2 11 of 82 µs 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Parameter Symbol Data valid time acknowledge tVD_ACK Stop condition set-up time tSU_STO Test conditions Min Typ Max Unit 0.45 µs 0.26 µs High Speed Mode Requires VDDIO ≥ 1.8 V Note 1 SCL clock frequency fSCL Start condition set-up time tSU_STA 160 ns Start condition hold time tH_STA 160 ns SCL low time tLOW 160 ns SCL high time tHIGH 60 ns 2-wire SCL and SDA rise time tR (input requirement) 160 ns 2-wire SCL and SDA fall time tF (input requirement) 160 ns Data set-up time tSU_D 10 ns Data hold-time tH_D 0 ns Stop condition set-up time tSU_STO 160 ns Note 1 4.4 0 3400 kHz Minimum clock frequency is 10 kHz if TWOWIRE_TO is enabled in register CONFIG_J. LDOs 4.4.1 LDO1 Unless otherwise noted, the following is valid for T A = -40 to +85 ºC. Table 8: LDO1 electrical characteristics Parameter Symbol Test conditions Input voltage VDD VDD = VSYS Output voltage VLDO Output accuracy Max Unit 2.8 5.5 V Programmable in 50 mV steps 0.9 3.6 V IOUT = IMAX including static line/load regulation -3% +3% -55% Stabilisation capacitor COUT Including voltage and temperature coefficient Output capacitor ESR RCOUT_ESR f > 1 MHz including wiring parasitics Output current IOUT VDD ≥ 1.8 V Short circuit current ISHORT Dropout voltage VDROPOUT Min Typ 1.0 0 +35% µF 300 mΩ 100 mA 200 IOUT = IMAX mA 100 150 mV IOUT = IMAX/3 for VDD = 1.5 V Static line regulation VS_LINE VDD = 3.0 to 5.5 V IOUT = IMAX 5 20 mV Static load regulation VS_LOAD IOUT = 1 mA to IMAX 5 20 mV Line transient response VTR_LINE VDD = 3.0 to 3.6 V IOUT = IMAX tr = tf = 10 µs 5 20 mV Datasheet CFR0011-120-00 Rev 5 Revision 3.2 12 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Parameter Symbol Test conditions Load transient response VTR_LOAD VDD = 3.6 V IOUT = 1 mA to IMAX tr = tf = 1 µs Power supply rejection ratio PSRR VDD = 3.6 V VDD – VLDO ≥ 0.6 V IOUT = IMAX/2 f = fVDDLDO f = 10 Hz to 10 kHz Output noise N VDD = 3.6 V, VLDO = 2.8 V Min Typ Max 30 40 50 Unit mV 60 dB 70 μV rms IOUT = 5 mA to IMAX, f = 10 Hz to 100 kHz Quiescent current in ON mode IQ_ON 9+ 0.9% IOUT μA Quiescent current in SLEEP mode IQ_SLEEP 1.5 + 1.6% IOUT μA Quiescent current in OFF mode IQ_OFF TA = 25 ºC VLDO < 0.5 V Turn-on time tON 1 μA 10 to 90 % 350 μs SLEEP mode 450 Turn-off time tOFF 90 to 10% Pull-down enabled Pull-down resistance in OFF mode ROFF VLDO = 0.5 V Can be disabled via LDO1_PD_DIS Datasheet CFR0011-120-00 Rev 5 Revision 3.2 13 of 82 1 100 ms Ω 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 4.4.2 LDO2, LDO3, LDO4 Unless otherwise noted, the following is valid for T A = -40 to +85 ºC. Table 9: LDO2, LDO3, LDO4 electrical characteristics Parameter Symbol Input voltage VDD Output voltage VLDO Output accuracy Test conditions Min Typ Max Unit 5.5 V V 2.8 Power stage supplied from buck 1.5 Programmable in 50 mV steps 0.9 3.6 IOUT = IMAX including static line/load regulation -3% +3% -55% Stabilisation capacitor COUT Including voltage and temperature coefficient Output capacitor ESR RCOUT_ESR f > 1 MHz including wiring parasitics Output current IOUT VDD ≥ 1.8 V Short circuit current ISHORT Dropout voltage VDROPOUT IOUT= IMAX IOUT = IMAX/3 for VDD = 1.5 V Static line regulation VS_LINE Static load regulation 2.2 0 +35% µF 300 mΩ 300 mA 600 mA 100 150 mV VDD = 3.0 to 5.5 V IOUT = IMAX 5 20 mV VS_LOAD IOUT = 1 mA to IMAX 5 20 mV Line transient response VTR_LINE VDD = 3.0 to 3.6 V IOUT = IMAX tR = tF = 10 µs 5 20 mV Load transient response VTR_LOAD VDD = 3.6 V IOUT = 1 mA to IMAX tR = tF = 1 µs 30 50 mV Power supply rejection ratio PSRR VDD = 3.6 V VDD – VLDO ≥ 0.6 V IOUT = IMAX/2 f = fVDDLDO f = 10 Hz to 1 kHz f = 1 to 10 kHz f = 10 to 100 kHz 80 70 50 dB 50 μV rms Output noise N Quiescent current in ON mode IQ_ON 9+ 0.34% IOUT μA Quiescent current in SLEEP mode IQ_SLEEP 2+ 0.7% IOUT μA Quiescent current in OFF mode IQ_OFF TA = 25 ºC VLDO < 0.5 V Turn-on time TON Datasheet CFR0011-120-00 Rev 5 VDD = 3.6 V VLDO = 2.8 V IOUT = 5 mA to IMAX f = 10 Hz to 100 kHz 70 60 40 1 μA 10 to 90 % 200 µs SLEEP mode 300 Revision 3.2 14 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Parameter Symbol Test conditions Turn-off time TOFF 90 to 10 % Pull-down enabled Pull-down resistance in OFF mode ROFF VLDO = 0.5 V Can be disabled via LDO<x>_PD_DIS 4.4.3 Min Typ Max Unit 1 ms Ω 100 LDOCORE Unless otherwise noted, the following is valid for T A = -40 to +85 ºC, VSYS = 2.8 to 5.5 V. Table 10: LDOCORE electrical characteristics Parameter Symbol Test conditions Min Typ Max Unit Output voltage VDDCORE Note 1 2.45 2.5 2.55 V RESET mode Stabilisation capacitor COUT Including voltage and temperature coefficient Output capacitor ESR RCOUT_ESR f > 1 MHz including wiring parasitics Dropout voltage VDROPOUT Note 2 2.2 -55% V 2.2 0 50 +35% µF 300 mΩ 100 mV Note 1 Setting VDD_FAULT_LOWER ≥ 2.65 V avoids LDOCORE dropout. See Section 4.7 for more detail. Note 2 The LDOCORE supply, VSYS, must be maintained above VDDCORE + VDROPOUT NOTE LDOCORE is only used to supply internal circuits. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 15 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 4.5 Buck converters 4.5.1 Buck1 Unless otherwise noted, the following is valid for T A = -40 to +85 ºC. Table 11: Buck1 electrical characteristics Parameter Symbol Input voltage VDD Output capacitor COUT Test conditions Min 2.8 Half-current mode including voltage and temperature coefficient -50% Full-current mode including voltage and temperature coefficient Output capacitor ESR Inductor value Inductor resistance RCOUT_ESR LBUCK RL_DCR Typ 2 * 22 Max Unit 5.5 V +30% µF m 2 * 47 COUT = 2 * 22 µF f > 100 kHz including wiring parasitics 15 50 COUT = 2 * 47 µF f > 100 kHz including wiring parasitics 7.5 25 Half-current mode, including current and temperature dependence 0.6 1.0 1.3 Full-current mode, including current and temperature dependence 0.5 1.0 1.3 Half-current mode 80 120 Full-current mode 60 100 Output voltage VBUCK Programmable in 10 mV steps 0.7 1.57 Output voltage accuracy VBUCK_ACC VDD = 4.2 V VBUCK = 1.03 V excluding static line/load regulation and voltage ripple -1% +1% Including static line/load regulation and voltage ripple -3% +3% µH m V Note 1 Transient load regulation VTR_LOAD VDD = 3.6 V VBUCK = 1.15 V IOUT = 200 to 1000 mA dI/dt = 3 A/µs L = 1 µH 30 45 mV Transient line regulation VTR_LINE VDD = 3.0 to 3.6 V IOUT = 500 mA tR = tF = 10 µs 0.2 3 mV Output current IOUT Datasheet CFR0011-120-00 Rev 5 Half-current mode L > 0.6 µH 900 Half-current mode L > 0.9 µH 1250 Full-current mode L > 0.9 µH 2500 Revision 3.2 16 of 82 mA 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Parameter Symbol Test conditions Min Current limit ILIM Controlled in BUCK<x>_ILIM in 200 mA steps. In half-current mode each step is 100 mA. Current limit accuracy ILIM_ACC Quiescent current in OFF mode IQ_OFF Quiescent current in PWM mode IQ_ON Unit 500 2000 mA -20 20 % 1 µA 9 Full-current mode IOUT = 0 mA 11 f Switching duty cycle DC Turn-on time tON VBUCK = 1.15 V BUCK_SLOWSTART = disabled SLEW_RATE = 10 mV/1 µs BUCK<x>_ILIM = 1500 mA Output pull-down resistance RPD PMOS ON resistance RPMOS RNMOS Max Half-current mode IOUT = 0 mA Switching frequency NMOS ON resistance Typ mA 2.85 3 3.15 MHz 83 % 0.37 1.2 ms VBUCK = 0.5 V, disabled via BUCK<x>_PD_DIS 100 200 Ω Half-current mode, including pin and routing, VSYS = 3.6 V 160 Full-current mode including pin and routing, VSYS = 3.6 V 80 Half-current mode, including pin and routing, VSYS = 3.6 V 60 Full-current mode, including pin and routing, VSYS = 3.6 V 30 14 mΩ mΩ PFM mode Output voltage VBUCK_PFM Programmable in 10 mV steps. Output voltages below 0.7 V force the buck to stay in PFM mode. Mode transition current threshold (PFM to PWM) in AUTO mode IAUTO_THR VIN = 3.6 V VBUCK = 1.15 V RTRACK ~ 45 mΩ including bondwire, PCB, and inductor ESR Output current IOUT_PFM Forced PFM mode Current limit ILIM_PFM Quiescent current IQ_PFM Mode transition time Note 1 tAUTO 0.3 1.57 400 V mA 300 1000 mA mA Forced PFM mode, IOUT = 0 mA 27 32 AUTO mode, IOUT = 0 mA 35 42 AUTO mode 6 µA µs Minimum tolerance 35 mV Datasheet CFR0011-120-00 Rev 5 Revision 3.2 17 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 4.5.2 Buck2 Unless otherwise noted, the following is valid for T A = -40 to +85 ºC. Table 12: Buck2 electrical characteristics Parameter Symbol Input voltage VDD Output capacitor COUT Test conditions Min Typ Max IOUT ≤ 1.5 A 2.8 5.5 IOUT > 1.5 A 3.3 5.5 Unit V IOUT ≤ 1.5 A including voltage and temperature coefficient -50% 2 * 22 +30% IOUT > 1.5 A including voltage and temperature coefficient -50% 2 * 47 +30% COUT = 2 * 22 µF f > 100 kHz including wiring parasitics 15 50 COUT = 2 * 47 µF f > 100 kHz including wiring parasitics 7.5 25 1.0 1.3 µH 80 120 m V µF Output capacitor ESR RCOUT_ESR Inductor value LBUCK Inductor resistance RL_DCR Output voltage VBUCK Programmable in 20 mV steps 0.8 3.34 Output voltage accuracy VBUCK_ACC Including static line and load regulation and voltage ripple Note 1 -3% +3% Transient load regulation VTR_LOAD VDD = 3.6 V VBUCK = 1.8 V IOUT = 200 to 1000 mA dI/dt = 3 A/µs L = 1 µH 30 45 VDD = 3.6 V VBUCK = 1.8 V IOUT = 200 to 2000 mA dI/dt = 3 A/µs L = 1 µH 60 90 VDD = 5.0 V VBUCK = 3.34 V IOUT = 200 to 2000 mA dI/dt = 3 A/µs L = 1 µH 60 90 VDD = 3.0 to 3.6 V IOUT = 500 mA tr = tf = 10 µs 0.2 3 Transient line regulation VTR_LINE Output current IOUT Datasheet CFR0011-120-00 Rev 5 Including current and temperature dependence 0.6 mV VDD - VBUCK ≥ 1.25 V L > 0.9 µH 2000 VDD - VBUCK ≥ 1.00 V L > 0.9 µH 1250 VDD - VBUCK ≥ 0.75 V L > 0.6 µH 900 Revision 3.2 18 of 82 m mV mA 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Parameter Symbol Test conditions Min Typ Max Unit Current limit ILIM Controlled in BUCK2_ILIM in 100 mA steps 1500 3000 mA Current limit accuracy ILIM_ACC -20% 20% Quiescent current in OFF mode IQ_OFF Quiescent current in PWM mode IQ_ON Switching frequency F 2.85 Switching duty cycle DC 15% Turn-on time tON VBUCK = 1.80 V BUCK_SLOWSTART = disabled SLEW_RATE = 20 mV/2 µs BUCK2_ILIM = 2500 mA 0.44 1.5 ms Output pull-down resistance RPD VBUCK = 0.5 V, disabled via BUCK2_PD_DIS 100 200 Ω PMOS ON resistance RPMOS Including pin and routing VSYS = 3.6 V 150 mΩ NMOS ON resistance RNMOS Including pin and routing VSYS = 3.6 V 60 mΩ Output voltage VBUCK_PFM Programmable in 20 mV steps Mode transition current threshold (PFM to PWM) in AUTO mode IAUTO_THR VIN = 3.6 V VBUCK = 1.8 V RTRACK ~ 45 mΩ including bondwire, PCB, and inductor ESR Current limit ILIM_PFM Output current IOUT_PFM Forced PFM mode Quiescent current IQ_PFM Forced PFM mode, IOUT = 0 mA 22 25 AUTO mode, IOUT = 0 mA 30 35 AUTO mode 6 1 IOUT = 0 mA 9 3 µA mA 3.15 MHz 100% PFM mode Mode transition time Note 1 tAUTO 0.8 3.34 V 400 mA 1000 mA 300 mA µA µs Minimum tolerance 35 mV Datasheet CFR0011-120-00 Rev 5 Revision 3.2 19 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 4.5.3 Buck3 Unless otherwise noted, the following is valid for T A = -40 to +85 ºC. Table 13: Buck3 electrical characteristics Parameter Symbol Test conditions Input voltage VDD Output capacitor COUT Including voltage and temperature coefficient Output capacitor ESR RCOUT_ESR f > 100 kHz including wiring parasitics Inductor value LBUCK Including current and temperature dependence Inductor resistance RL_DCR Output voltage VBUCK Programmable in 10 mV steps Output voltage accuracy VBUCK_ACC Including static line/load regulation and voltage ripple Min Typ Max Unit 5.5 V 2 * 22 +30% µF 15 50 m 1.0 1.3 µH 80 120 m 0.7 1.8 V -3% +3% 2.8 -50% 0.6 Note 1 Transient load regulation Transient line regulation VTR_LOAD VTR_LINE Output current IOUT Current limit ILIM Current limit accuracy ILIM_ACC Quiescent current in OFF mode IQ_OFF Quiescent current in PWM mode IQ_ON Switching frequency f Switching duty cycle DC Datasheet CFR0011-120-00 Rev 5 VDD = 3.6 V VBUCK = 1.35 V IOUT = 200 to 1000 mA dI/dt = 3 A/µs 25 40 mV VDD = 3.6 V VBUCK = 1.35 V IOUT = 200 to 1500 mA dI/dt = 3 A/µs 40 60 mV VDD = 3.0 to 3.6 V IOUT = 500 mA tR = tF = 10 µs 0.2 3 mV VDD - VBUCK ≥ 1.25 V L > 0.9 µH 1500 VDD - VBUCK ≥ 1.00 V L > 0.9 µH 1250 VDD - VBUCK ≥ 1.00 V L > 0.6 µH 900 Controlled in BUCK3_ILIM in 100 mA steps 500 2000 mA -20 +20 % 1 µA IOUT = 0 mA 9 2.85 14 Revision 3.2 20 of 82 mA 3 mA 3.15 MHz 83 % 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Parameter Symbol Test conditions Turn-on time tON Output pull-down resistance Min Typ Max Unit VBUCK = 1.35 V BUCK_SLOWSTART = disabled SLEW_RATE = 10 mV/1 µs BUCK3_ILIM = 1500 mA 0.39 1.2 ms RPD VBUCK = 0.5 V, disabled via BUCK3_PD_DIS 100 200 Ω PMOS ON resistance RPMOS Including pin and routing VSYS = 3.6 V 150 mΩ NMOS ON resistance RNMOS Including pin and routing VSYS = 3.6 V 60 mΩ Output voltage VBUCK_PFM Programmable in 10 mV steps. Output voltages below 0.7 V force the buck to stay in PFM mode. Mode transition current threshold (PFM to PWM) in AUTO mode IAUTO_THR VIN = 3.6 V VBUCK = 1.35 V RTRACK ~ 45 mΩ including bondwire, PCB, and inductor ESR Output current IOUT_PFM Current limit ILIM_PFM Quiescent current IQ_PFM PFM mode Mode transition time Note 1 4.6 tAUTO 0.53 1.8 400 V mA 300 1000 mA mA Forced PFM mode IOUT = 0 mA 22 25 AUTO mode IOUT = 0 mA 30 35 AUTO mode 6 µA µs Minimum tolerance 35 mV Internal oscillator Unless otherwise noted, the following is valid for TA = -40 to +85 ºC, VSYS = 2.8 to 5.5 V. Table 14: Internal oscillator electrical characteristics Parameter Symbol Oscillator frequency fOSC Datasheet CFR0011-120-00 Rev 5 Test conditions Revision 3.2 21 of 82 Min Typ Max Unit 5.7 6 6.3 MHz 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 4.7 System supply voltage supervision Unless otherwise noted, the following is valid for T A = -40 to +85 ºC, VSYS = 2.8 to 5.5 V. Table 15: System supply voltage supervision electrical characteristics Parameter Symbol Test conditions Min Typ Max Under-voltage lockout lower threshold VPOR_LOWER 2.0 V Under-voltage lockout upper threshold VPOR_UPPER 2.3 V VSYS undervoltage lower threshold VDD_FAULT_LOWER Note 1 2.5 VSYS undervoltage lower threshold accuracy VSYS_LOWER -2% VSYS hysteresis VDD_FAULT_HYS 100 200 450 2.8 3.25 Unit V +2% mV Note 2 VSYS upper threshold VDD_FAULT_UPPER -2% VDD_FAULT_LOWER + VDD_FAULT_HYS +2% Reference voltage VREF -1% 1.2 +1% VREF decoupling capacitor CVREF Reference current resistor RIREF 2.2 -1% µF 200 +1% Note 1 Can be set in 50 mV steps via VDD_FAULT_ADJ in register CONFIG_B, setting VDD_FAULT_LOWER ≥ 2.65 V avoids LDOCORE dropout, see Section 4.4.3 for more detail Note 2 Can be set in 50 mV steps via VDD_HYST_ADJ in register CONFIG_B 4.8 V k Junction temperature supervision Unless otherwise noted, the following is valid for T A = -40 to +85 ºC, VSYS = 2.8 to 5.5 V. Table 16: Junction temperature supervision electrical characteristics Parameter Symbol Test conditions Min Typ Max Unit POR temperature threshold TPOR Note 1 135 150 165 °C Critical temperature threshold TCRIT Note 1 125 140 155 °C Warning temperature threshold TWARN Note 1 110 125 140 °C Note 1 Thermal thresholds are non-overlapping. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 22 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 4.9 Current consumption Unless otherwise noted, the following is valid for T A = -40 to +85 ºC, VSYS = 2.8 to 5.5 V. Table 17: Current consumption electrical characteristics Operating mode Symbol Test conditions POWERDOWN mode IDDPD ACTIVE mode IDDACT Datasheet CFR0011-120-00 Rev 5 VSYS (Typ) Unit VSYS > 3.0 V LDOCORE enabled Bucks and LDOs disabled 40 µA All bucks and LDOs enabled 400 µA Revision 3.2 23 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 5 Typical characteristics Figure 4: Buck1 efficiency in AUTO mode (VIN = 3.60 V, VOUT = 1.15 V) Figure 5: Buck2 efficiency in AUTO mode (VIN = 3.60 V, VOUT = 1.80 V) Datasheet CFR0011-120-00 Rev 5 Revision 3.2 24 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Figure 6: Buck2 efficiency in AUTO mode (VIN = 5.00 V, VOUT = 3.34 V) Figure 7: Buck3 efficiency in AUTO mode (VIN = 3.60 V, VOUT = 1.35 V) Datasheet CFR0011-120-00 Rev 5 Revision 3.2 25 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6 6.1 Functional description Control signals Each of the input signals described below feature a debounce filter. They share a common debounce time control (DEBOUNCING). 6.1.1 nONKEY nONKEY is an edge-sensitive signal that controls the power mode of DA9061. Both falling and rising edges are detected and the time between the edges is measured. This enables different lengths of key press detection. The detection circuitry is enabled in all power modes of the device. The status of the signal after debouncing can be read from NONKEY (reg. STATUS_A). The mask bit M_NONKEY prevents interrupt and wakeup events that would normally be caused by an nONKEY event. nONKEY has four modes of operation, see Table 18, which can be selected by NONKEY_PIN. NONKEY_LOCK controls the wakeup event generation of the nONKEY. If NONKEY_LOCK is asserted (depends on NONKEY_PIN), a short nONKEY press (shorter than KEY_DELAY) will not generate a wakeup. Table 18: nONKEY functions nONKEY_PIN Function 00 An event (E_nONKEY) is generated when nONKEY is asserted. If not masked, the event causes an interrupt. A wakeup is triggered if the device is in POWERDOWN mode. 01 A timer is started when nONKEY is asserted. If the signal is de-asserted before the time programmed in KEY_DELAY, an event (E_nONKEY) is generated at the rising edge. If the signal stays asserted and the timer reaches the programmed value, an event is generated and nONKEY_LOCK is asserted. 10 A timer is started when nONKEY is asserted. If the signal is de-asserted before the time programmed in KEY_DELAY, an event (E_nONKEY) is generated at the rising edge. If the signal stays asserted and the timer reaches the programmed value, an event is generated, nONKEY_LOCK is asserted, and a power down is triggered by automatically clearing SYSTEM_EN. 11 A timer is started when nONKEY is asserted. If the signal is de-asserted before the time programmed in KEY_DELAY, an event (E_nONKEY) is generated at the rising edge, SYSTEM_EN is cleared, and STANDBY is asserted. If the signal stays asserted and the timer reaches the programmed value, an event is generated, nONKEY_LOCK is asserted, and SYSTEM_EN and STANDBY are cleared. Whenever nONKEY_LOCK is asserted, a long key press (longer than the time programmed in KEY_DELAY) is required to wakeup from POWERDOWN mode. If the wakeup is also desired after a short key press, nONKEY_LOCK has to be cleared before entering the POWERDOWN mode. 6.1.2 nRESETREQ nRESETREQ is an active-low reset request that causes DA9061 to enter RESET mode. The transition to the RESET mode is handled by the power sequencer and it can be sped up by setting the HOST_SD_MODE bit. Before entering the RESET mode, a fault log bit is set (nRESETREQ) and nRESET is asserted. nRESETREQ should be tied to an always-on rail that is supplied in all modes of the DA9061 such as VSYS. It is not recommended to tie nRESETREQ to any of the regulator outputs. An internal pull-up resistor to VDDIO can be enabled from nRESETREQ_PU. However, care should be taken to ensure that the VDDIO is supplied in all power modes. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 26 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.1.3 nRESET nRESET is an active-low reset output intended for resetting the host processor of the system. The signal can be configured as either push-pull or open drain output (PM_O_TYPE). nRESET is always asserted upon a cold boot from the no-power mode. It is always asserted at the beginning of a shutdown sequence to the RESET mode. nRESET may also be asserted at the beginning of the sequence to the POWERDOWN mode, if configured in nRES_MODE. De-assertion of nRESET is controlled by a reset timer. After being asserted, nRESET remains low until the reset timer, which was started from the selected trigger signal, expires. The reset timer trigger can be selected via RESET_EVENT and set to one of the following: an external signal triggering the wakeup (EXT_WAKEUP), an internal signal indicating the end of the first power-up sub-sequence (SYS_UP), an internal signal indicating the end of the second power-up sub-sequence (PWR_UP), or the transition of DA9061 from reset to POWERDOWN mode. The expiry time can be configured via RESET_TIMER from 1 ms to 1 s. If RESET_TIMER is set to 0 ms, nRESET is deasserted immediately after the trigger selected with RESET_EVENT. 6.1.4 nIRQ nIRQ is a level-sensitive interrupt signal. It can be configured either as a push-pull or an open drain output (selected via PM_O_TYPE). The polarity of nIRQ can be selected with IRQ_TYPE. nIRQ is asserted when an unmasked event has occurred. The nIRQ will not be released until all event registers have been cleared. New events that occur while reading an event register are saved until the event register is cleared, ensuring that the host processor captures them. The same will happen to all events occurring when the power sequencer is in transition. 6.2 2-wire interface The 2-wire interface provides access to the control and status registers. The interface supports 2 operations compatible to the standard, fast, fast-plus, and high-speed modes of the I C bus specification Rev. 3. Communication on the 2-wire bus is always between two devices; one acting as the master and the other as the slave. The DA9061 only operates as a slave. SCL transmits 2-wire clock data and SDA transmits the bidirectional data. The 2-wire interface is open-drain supporting multiple devices on one line. The bus lines have to be pulled high by an external pull-up resistor (2 to 20 kΩ). The attached devices drive the bus lines low by connecting them to ground. As a result, two devices can drive the bus simultaneously without conflict. In standard/fast mode the highest frequency of the bus is 400 kHz. The exact frequency can be determined by the application and it does not have any relation to the DA9061 internal clock signals. DA9061 stays within the described host clock speed limitations and does not initiate clock slowdown. An automatic interface reset is triggered when the clock signal ceases toggling for >35 ms (controlled in TWOWIRE_TO). When the SDA is stuck, the bus clears after receiving nine clock pulses. Operation in high-speed mode at 3.4 MHz requires a minimum interface supply voltage of 1.8 V and a mode change in order to enable slope-control. The high-speed mode can be enabled on a transfer-by-transfer basis by sending the master code (0000 1XXX) at the beginning of the transfer. The DA9061 does not make use of clock stretching and delivers read data without delay up to 3.4 MHz. Alternatively, the interface can be configured to use high-speed mode continuously via PM_IF_HSM, so that the master code is not required at the beginning of every transfer. This reduces communication overhead on the bus and limits the attachable bus slaves to compatible devices. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 27 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.2.1 Register map paging The 2-wire interface has direct access to two pages of the DA9061 register map (up to 256 addresses). The register at address zero on each page is used as a page control register (the LSB of control PAGE is ignored). Writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 is selected using control REVERT. Unless REVERT was asserted after modifying the active page, it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. DA9061 also offers an alternative way to access register pages which avoids writing explicitly to PAGE. DA9061 responds to multiple consecutive slave addresses and updates PAGE automatically based on the slave address. For example, when IF_BASE_ADDR[7:4] = 0xB the slave address changes PAGE as follows: Slave address = 0xB0 PAGE = 0x00 Slave address = 0xB2 PAGE = 0x02 6.2.2 Details of the 2-wire protocol All data is transmitted across the 2-wire bus in 8-bit groups. To send a bit, the SDA line is driven at the intended state while the SCL is low. Once the SDA has settled, the SCL line is brought high and then low. This pulse on SCL stores the SDA bit in the receiver’s shift register. A 2-byte serial protocol is used: one address byte and one data byte. Data and address transfer transmits the MSB first for both read and write operations. All transmissions begin with the START condition from the master during which the bus is in IDLE state (the bus is free). It is initiated by a high-to-low transition on the SDA line while the SCL is in high state. A STOP condition is indicated by a low-to-high transition on the SDA line while the SCL is in high state. The START and STOP conditions are illustrated in Figure 8. SDA SCL START Transaction STOP Figure 8: Timing of the START and STOP conditions DA9061 monitors the 2-wire bus for a valid slave address whenever the interface is enabled. It responds immediately when it receives its own slave address. This is acknowledged by pulling the SDA line low during the following clock cycle (white blocks marked with ‘A’ in the following figures). The protocol for a register write from master to slave consists of a START condition, a slave address, a read/write-bit, 8-bit address, 8-bit data, and a STOP condition. DA9061 responds to all bytes with an ACK. A register write operation is illustrated in Figure 9. S SLAVEadr 7-bits W A 1-bit REGadr 8-bits Master to Slave S = START condition P = STOP condition A DATA A P 8-bits Slave to Master A = Acknowledge (low) W = Write (low) Figure 9: Byte write operation Datasheet CFR0011-120-00 Rev 5 Revision 3.2 28 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A When the host reads register data the DA9061 first has to access the target register address with write access and then with read access and a repeated START, or alternatively a second START, condition. After receiving the data, the host sends NACK and terminates the transmission with a STOP condition, see Figure 10. S SLAVEadr W A 7-bits S 1-bit SLAVEadr W A 7-bits 1-bit REGadr A Sr SLAVEadr 8-bits 7-bits REGadr A P S A * DATA A P 8-bits SLAVEadr 8-bits Master to Slave R 1-bit 7-bits R A 1-bit * DATA A P 8-bits Slave to Master S = START condition Sr = Repeated START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 10: Examples of byte read operations Consecutive (page) read-out mode is initiated from the master by sending an ACK instead of NACK after receiving a byte, see Figure 11. The 2-wire control block then increments the address pointer to the next register address and sends the data to the master. The data bytes are read continuously until the master sends a NACK followed by a subsequent STOP condition directly after receiving the data. If a non-existent 2-wire address is read out then the DA9061 will return code zero. S SLAVEadr W A 7-bits 1 bit S SLAVEadr W A 7-bits 1-bit REGadr A Sr SLAVEadr R A 8-bits REGadr 7-bits 1-bit A DATA 8-bits 7-bits A 8-bits S SLAVEadr R A A P 8-bits Master to Slave DATA DATA 1-bit * DATA A P 8-bits A DATA 8-bits * A P 8-bits Slave to Master S = START condition Sr = Repeat START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 11: 2-wire page read The slave address after the repeated START condition must be the same as the previous slave address. Consecutive (page) write mode is supported if the master sends several data bytes after sending the register address. The 2-wire control block then increments the address pointer to the next 2-wire address, stores the received data, and sends an ACK until the master sends a STOP condition. The page write mode is illustrated in Figure 12. S SLAVEadr W A 7-bits 1 bit REGadr 8-bits Master to Slave S = START condition Sr = Repeat START condition P = STOP condition A DATA 8-bits A DATA 1-bit A 8-bits DATA 8-bits A ………. A P Repeated writes Slave to Master A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 12: 2-wire page write Datasheet CFR0011-120-00 Rev 5 Revision 3.2 29 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A A repeated write mode can be enabled with WRITE_MODE control. In this mode, the master can execute back-to-back write operations to non-consecutive addresses by transmitting register addresses and data pairs. The data is stored in the address specified by the preceding byte. The repeated write mode is illustrated in Figure 13. S SLAVEadr W A 7-bits 1 bit REGadr A DATA 8-bits Master to Slave 8-bits A REGadr 1-bit 8-bits A DATA ………. A 8-bits A P Repeated writes Slave to Master S = START condition Sr = Repeat START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 13: 2-wire repeated write If a new START or STOP condition occurs within a message, the bus returns to idle mode. 6.3 GPIOs DA9061 features five general purpose IO pins. The basic structure of the GPIOs is depicted in Figure 14. As illustrated, there are several additional functions: ● ● ● ● ● ● analog function alternate function forwarding regulator control sequencer WAIT_STEP interrupt and wakeup generation The GPIOs are operational in POWERDOWN and ACTIVE modes. However, GPIs can be configured as disabled in POWERDOWN mode in register PD_DIS (control GPI_DIS). In other modes, the GPIO is disabled and all ports are configured as open drain outputs in high impedance state. The level transitions on inputs will no longer be detected, but I/O drivers will keep their configuration and programmed levels. Alternate function Analog function Forwarding output Sequencer (WAIT_STEP), regulator control Interrupt GPIOx_MODE GPIOx_PIN GPIOx_TYPE Debounce GPI Edge detection GPIx GPIOx_PUPD M_GPIOx E_GPIOx Mask GPIOx_PIN GPIOx_WKUP_MODE Wakeup selection VDDIO Wakeup enable Wakeup GPIOx_WEN GPIOx_OUT GPIOx_PUPD GPIOx_MODE GPO OD 0 1 Forwarding input Output function Sequencer VDD_FAULT VDDIO GPO push-pull Figure 14: General GPIO block diagram The functionality of a GPIO is configured in GPIO<x>_PIN, as listed in Table 19. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 30 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 19: GPIO functions GPIO<x>_ PIN Function GPIO<x>_MODE GPIO<x>_TY PE GPIO<x>_WKUP_MO DE GPIO<x>_WEN 0 Alternate function No effect No effect No effect No effect 1 GPI 0: Debounce off 1: Debounce on 0: Active low 1: Active high 0: Edge-sensitive wakeup 0: Wakeup disabled 1: Wakeup enabled 1: Level-sensitive wakeup 2 3 6.3.1 GPO 0: Output low Open drain 1: Output high GPO 0: Output low Push-pull 1: Output high No effect No effect No effect No effect No effect No effect GPI functionality In GPI mode, the polarity of the input can be selected with GPIO<x>_TYPE. A debouncing filter can be applied on the input signals with a configurable debouncing time (DEBOUNCING). An event is generated at the active edge of the input. The active edge is determined by the signal polarity configured in GPIO<x>_TYPE. The event can be further configured to generate a wakeup via GPIO<x>_WKUP_MODE and GPIO<x>_WEN. An internal pull-down can be activated for the inputs in GPIO<x>_PUPD. A level sensitive wakeup event can also be configured for each GPI via GPIO<x>_WKUP_MODE and GPIO<x>_WEN. The functionality of the level-sensitive wakeup is described in Table 22. 6.3.1.1 Regulator control GPIO1, GPIO2, and GPIO3 can be used for controlling DA9061 regulators. When configured as GPIs, they can be used to enable regulators or select between their two output voltage settings. As seen in Figure 14, the regulator control is branched after the GPIO<x>_TYPE control allowing active edge delegation for the regulator control. Finally, the functionality for the GPI is selected with the regulator controls BUCK<x>_GPI, LDO<x>_GPI, VBUCK<x>_GPI, and VLDO<x>_GPI. One GPI can be used to control the same function on multiple regulators simultaneously. When a regulator is controlled by a GPI, the same function (on/off or voltage selection) can no longer be controlled by the power supply sequencer. The regulator still responds normally to register writes to the control bit. Enable/disable control A GPI is used for enabling/disabling regulators when it is selected in one of the BUCK<x>_GPI or LDO<x>_GPI controls. A passive to active transition sets the regulator enable bit (BUCK<x>_EN, LDO<x>_EN), and an active to passive transition clears it. Output voltage control A GPI is used for the output voltage selection when it is selected in one of the VBUCK<x>_GPI or VLDO<x>_GPI controls. A passive to active transition sets the voltage selection bit (VBUCK<x>_SEL, VLDO<x>_SEL), and an active to passive edge clears it. 6.3.1.2 Sequencer WAIT_STEP GPIO3 can be used for the WAIT_STEP functionality. The power sequencer can be programmed to wait for either a rising or falling edge of the WAIT_STEP input, see Section 6.9.4. The active edge is selected from GPIO<x>_TYPE. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 31 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.3.2 GPO functionality The outputs can be configured as push-pull or open drain outputs, see Table 19. An internal pull-up can be enabled/disabled from GPIO<x>_PUPD (open drain mode). The GPIO<x>_MODE settings can control the output state. Instead of controlling the output with GPIO<x>_MODE, a selection of alternatives is available in the GPIO<x>_OUT controls. These include: the forwarding function, see Section 6.3.4, the power supply sequencer, see Section 6.9, and the status of the voltage supervision (VDD_FAULT). When the GPIO is configured as an output and GPIO<x>_OUT is set to 0x0, the GPIO<x>_MODE determines the state of the ouput. 6.3.2.1 nVDD_FAULT nVDD_FAULT gives the status of the system supply monitoring, see Section 6.11. The assertion of nVDD_FAULT indicates that the main supply input voltage is low (VSYS < VDD_FAULT_UPPER) and therefore informs the host processor that the power will soon shut down. It can be configured to drive a GPO from the GPIO<x>_OUT controls. The driver type (push-pull, open drain) selection and pull-up resistor control function normally. The GPIO<x>_MODE can be used to invert the incoming VDD_FAULT signal. 6.3.3 Alternate functions GPIO0, GPIO2, and GPIO4 can be used for alternate functions. These are digital control signals that don’t employ the debouncing, event detection, or interrupt generation functions. Only the input buffer of the GPIO block is employed. The alternate functions of DA9061 are listed in Table 20 and described in the following subsections. A debouncing filter can be applied also on the alternate functions with a configurable debouncing time (DEBOUNCING). Table 20: GPIO alternate input functions GPIO Alternate function Description GPIO0 WDKICK Watchdog kick or disable GPIO1 - GPIO2 PWR_EN GPIO3 - GPIO4 SYS_EN 6.3.3.1 Power mode control Power mode control SYS_EN SYS_EN (pin GPIO4) controls the SYSTEM_EN bit and thereby the power mode of DA9061. It is part of the power supply sequencer functionality described in Section 6.9. SYS_EN is an edgesensitive signal and its polarity can be chosen in the GPIO4_TYPE control. Asserting SYS_EN causes an interrupt (E_GPIx) and a wakeup event. De-asserting SYS_EN triggers a power down sequence but no interrupt. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 32 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.3.3.2 PWR_EN PWR_EN (pin GPIO2) controls the POWER_EN bit and thereby the power mode of DA9061. It is part of the power supply sequencer functionality described in Section 6.9. PWR_EN is an edgesensitive signal and its polarity can be chosen in the GPIO2_TYPE control. A wakeup event can be generated after assertion of PWR_EN if so configured in GPIO2_WEN. 6.3.3.3 WDKICK A rising edge of the WDKICK signal resets the watchdog counter. The polarity of the signal can be chosen in the GPIO0_TYPE control. If the signal is kept asserted, the watchdog is disabled as the counter is not incremented (WDG_MODE), see Section 6.13. 6.3.4 GPIO forwarding GPIO forwarding works between GPIOs 0, 1, 2, and 3. Any of these GPIs can be routed directly to GPO0, 1, and 3 after debouncing. Forwarding is one of the options for the GPIO<x>_OUT control. 6.4 Dynamic voltage control All of DA9061’s buck converters can be controlled in several ways to achieve dynamic voltage control (DVC). The buck converters feature a voltage ramping feature that enables smooth transition from one voltage setting to another. All output voltages can be controlled with SW via the 2-wire interface (VBUCK<x>_A). The 2-wire interface is operational when the device is in ACTIVE mode. 6.5 Regulator voltage A and B selection In addition, all regulators feature A and B settings which can be programmed with different voltages (VBUCK<x>_A, VBUCK<x>_B), one of which is chosen according to the operating mode of the system (VBUCK<x>_SEL, VLDO<x>_SEL). In addition to the output voltage, the A and B settings include a bit to force the regulator into SLEEP mode which reduces the quiescent current. The selection between the A and B settings can be done either with SW via the 2-wire interface or by the power sequencer, see Section 6.9. Furthermore, each regulator can be enabled with a GPI pin, see Section 6.3.1.1, and the selection between the A and B settings done with another GPI. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 33 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.6 LDOs All LDOs employ Dialog Semiconductor’s Smart Mirror™ dynamic biasing technology, see Figure 15, which maintains high performance over a wide range of operating conditions and a power saving mode (SLEEP mode) to minimise the quiescent current during very low output current. The circuit technique offers significantly higher gain bandwidth performance than conventional designs, enabling higher power supply rejection performance at higher frequencies. PSRR is maintained across the full operating current range however quiescent current consumption is scaled to demand improved efficiency when current demand is low. Vin Vref Vout Cout Smart Mirror TM LDO ESR Figure 15: Smart Mirror 6.6.1 TM voltage regulator Control The LDOs can be enabled by writing directly to a control bit (LDO<x>_EN), controlling it via a GPI, see Section 6.3.1.1, or assigning it to a power sequencer step, see Section 6.9.2. Each LDO features two voltage control registers (VLDO<x>_A/VLDO<x>_B) that allow two output voltage preconfigurations. The active setting can then be selected either with a control bit (VLDO<x>_SEL), via a GPI, see Section 6.3.1.1, or automatically based on the DA9061 power mode. The SLEEP mode of the LDOs can be linked to either the A or B setting (LDO<x>_SL_A/LDO<x>_SL_B). Therefore, the LDO will switch to SLEEP mode when the setting is active. LDO1 differs from the other LDOs because it can be configured as an always-on regulator. This means that it is also enabled in RESET mode, see Section 6.8.2. 6.6.2 Current limit Each LDO provides over-current detection. The current limit is fixed for each LDO based on their current capability. If any of the LDOs’ current limit is exceeded for longer than 10 ms, an event, E_LDO_LIM, is triggered. The status of the limit comparator can be observed from LDO<x>_ILIM (reg. STATUS_D). If an LDO’s current limit is exceeded for longer than 200 ms, the LDO is automatically disabled. This shutdown feature can be disabled by clearing the LDO_SD control. Once disabled due to an over-current, the LDO must be re-enabled by one of the sources described in Section 6.6.1. 6.6.3 Output pull-down When overvoltage (1.06 * VLDOx) occurs, the voltage regulators enable an internal load to discharge the output back to its configured voltage. This feature can be disabled in LDO<x>_PD_DIS. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 34 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.7 Switching regulators DA9061 includes four step-down switching regulators operating at 3 MHz. All switching regulators employ a synchronous topology with an internal NFET, thus eliminating the need for an external Schottky diode. The output voltage can be set in 10 mV steps (20 mV steps for Buck2) and the regulation accuracy is ±3 % over the whole operating temperature range. Static line and load regulation are also considered in this accuracy. The switching frequency (3 MHz) is high enough to warrant the use of a small 1.0 µH inductor. The programming of the converter current limit depends on the coil parameters, as illustrated in Table 21. Table 21: Buck current limit 6.7.1 Min. ISAT (mA) Frequency (MHz) Buck current limit (mA) 1750 3 1500 1460 3 1200 1180 3 950 940 3 750 Control The buck can be enabled manually by writing directly to a control register, with an external signal connected to GPI, see Section 6.3.1.1, or by assigning it to a power sequencer step, see Section 6.9.2. Each buck converter features two voltage control registers (VBUCK<x>_A/VBUCK<x>_B) which can be programmed with two different voltages. The active setting can then be selected via a control bit (VBUCK<x>_SEL), via a GPI, see Section 6.3.1.1, or automatically based on the power mode of DA9061. 6.7.2 Output voltage slewing To limit in-rush current from the input supply, the buck converters can achieve a new output voltage with controlled ramping. Ramping is achieved by stepping through all the VBUCK values between the old and new settings, at a rate defined by SLEW_RATE. The actual output slew rate, in mV/µs, for a particular buck converter is then defined by the minimum voltage step of that buck and the common step time programmed in SLEW_RATE. During PFM mode, the negative slew rate is load dependent and might be lower than the one mentioned above. An event E_DVC_RDY is triggered when all buck converters have reached their target voltage. 6.7.3 Soft-start The buck converter supports two options for starting up. The normal startup option ramps up the power rail as fast as possible, typically within 1 ms. This implies a high in-rush current. The slow startup is selected by setting BUCK_SLOWSTART, which increases the startup time and limits the input current. 6.7.4 Active discharge When switching off a buck converter the output rail can be actively discharged. This feature is enabled by setting BUCK_ACTV_DISCHRG. The discharge is implemented by ramping down the output voltage using DVC. 6.7.5 Peak current limit All buck converters feature a programmable current limit (BUCK<x>_ILIM). The current limit protects the inductor and the pass devices from excessive current. If the current limit is exceeded, the buck continues to run normally but the duty cycle is limited. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 35 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.7.6 Operating mode The operating mode of each converter can be set via the buck control (BUCK<x>_MODE) to synchronous (PWM), sleep (PFM), or auto. In auto mode the buck converter switches between PWM and PFM depending on the load current. This mode is recommended for applications that require fast transitions from synchronous to sleep operation. The current consumption during PWM operation is 10 mA and drops to <1 µA in shutdown. In addition, the buck mode can be controlled with the A and B setting. If BUCK<x>_SL_B is set, the buck is forced to SLEEP mode when the B setting is active. Similarly, if BUCK<x>_SL_A is set, the buck is forced to SLEEP mode when the A setting is active. 6.7.7 Half-current mode Buck1 can operate in half-current mode where the quiescent current is reduced by disabling half of the pass devices. As the name implies, enabling this option halves the output current, and therefore, this feature is valuable in applications where quiescent current is critical and full current is not needed. This feature is controlled with BUCK1_FCM. If the bit is asserted (BUCK1_FCM = 1), the corresponding buck is in full-current mode and the full current is available. If the bit is de-asserted, the corresponding buck is in half-current mode. Operating the bucks in full-current mode requires twice as much output capacitance (2 x 47 µF) as the half-current mode (2 x 22 µF). Datasheet CFR0011-120-00 Rev 5 Revision 3.2 36 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.8 Power modes VDDCORE < VPOR_UPPER No-Power VDDCORE > VPOR_UPPER Active functions · VDDCORE comparator Any state ( nONKEY press || nRESETREQ ) && ( ! Temp error && ! VSYS error ) Reset Sequence done || time-out Active functions · VDDCORE comparator · nONKEY · Internal supplies · LDO1 Shut-down sequence VSYS error · nRESET asserted Any state time > RESET_DURATION && ( ! Temp error && ! VSYS error ) nRESETREQ || nONKEY (long) Shut-down sequence Power-Down Temp error Active functions · VDDCORE comparator · nONKEY · Internal supplies · LDO1 · Selected supplies Any state Sequence done || time-out Re-try count != 0 Power-down sequence Re-try count == 0 nRESETREQ || nONKEY (long) Sequence done || time-out nONKEY press || GPIO wake-up event Power-Down (Freezed) Shut-down sequence nRESETREQ || nONKEY (long) Power-up sequence nONKEY (short) || GPIO power-down event || Watchdog time-out Sequence done || time-out Active Active functions · VDDCORE comparator · nONKEY · Internal supplies · All supplies · Watchdog Watchdog alive Figure 16: DA9061 power modes (state transition conditions follow C-language syntax) 6.8.1 NO-POWER mode The NO-POWER mode is initial state when powering up the DA9061 for the first time. When the system supply rises above a threshold, DA9061 enters RESET mode. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 37 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.8.2 RESET mode In RESET mode, the internal supplies, and LDO1 (if configured as an always-on supply) are enabled. All other DA9061 supplies are disabled. DA9061 is in RESET mode whenever a complete application shutdown is required. RESET mode can be triggered by the user, a host processor, or an internal event. RESET mode can be triggered by the user: ● from a long press of nONKEY (interruptible by host) ● by pressing a reset switch that is connected to port nRESETREQ (non-interruptible) RESET mode can be forced from the host processor (non-interruptible): ● by asserting port nRESETREQ (falling edge) ● by writing to register bit SHUTDOWN DA9061 error conditions that force RESET mode (non-interruptible) are: ● no WATCHDOG write (WDKICK signal assertion) from the host inside the watchdog time window (if watchdog was enabled) ● an undervoltage detected at VSYS (VSYS < VDD_FAULT_LOWER) ● an internal die over-temperature With the INT_SD_MODE, HOST_SD_MODE and KEY_SD_MODE controls, the shutdown sequences from internal fault, host or user triggered, are individually configured to either implement the reverse timing of the power-up sequence or transfer immediately to the RESET mode by skipping any delay from sequencer or dummy slot timers. For the host to determine the reason for the reset a FAULT_LOG register stores the root cause (either KEY_RESET or NRESETREQ). The host processor resets this register by writing asserted bits with ‘1’. KEY_SD_MODE = 1 triggers a complete power on reset (POR) (instead of entering RESET mode) after the related keys are pressed extendedly. If an OTP read is aborted, DA9061 enters RESET mode without an asserted bit inside register FAULT_LOG. A shutdown sequence to RESET mode will start with the assertion of the nRESET port. After the sequencer completes the power down sequence (sequencer position 0), DA9061 continues to RESET mode with only the following active circuits: LDOCORE (at reduced output voltage 2.2 V), control interfaces and GPIOs, BCD counter, band-gap and over-temperature/VSYS comparators. All regulators, except for LDO1, are automatically disabled to avoid battery drainage. As described in Section 6.1.3, nRESET is always asserted at the beginning of a shutdown sequence to RESET mode, and remains asserted when DA9061 is in RESET mode. When entering the reset state, all user and system events are cleared and the DA9061’s register configuration will be re-loaded from OTP when leaving the RESET mode (with the exception of AUTO_BOOT in case of a VDD_START fault). FAULT_LOG, GP_ID_10 to GP_ID_19 and other non-OTP loaded registers will not be changed when leaving the RESET mode. Some reset conditions like asserting SHUTDOWN via register write, watchdog error, or junction overtemperature will automatically expire. Other reset triggers, like asserting nRESETREQ, need to be released to proceed from reset to POWERDOWN mode. If the application requires regulators to discharge completely before a power-up sequence, a minimum duration of the RESET mode can be selected via RESET_DURATION. If the reset was initiated by a user’s long press of nONKEY, initially only KEY_RESET is set and the nIRQ port will be asserted. KEY_RESET signals the host that a shutdown sequence is started. If the host does not then clear KEY_RESET within 1 second by writing a ‘1’ to the related bit in register FAULT_LOG, the shutdown sequence will complete. When the reset condition has disappeared, DA9061 requires a supply (VSYS > VDD_FAULT_UPPER) that provides enough power to start-up from the POWERDOWN mode. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 38 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.8.3 POWERDOWN mode The POWERDOWN mode is a low-power state where most of the regulators are disabled. The transition from active to POWERDOWN mode (and vice versa) is handled by the programmable sequencer. Entry to POWERDOWN mode from ACTIVE mode is triggered by the de-assertion of SYSTEM_EN (either via SYS_EN or register access) or by a short press of nONKEY. The POWERDOWN mode is also passed during start-up and shutdown to RESET mode sequences. In POWERDOWN mode the internal supplies are enabled, and the control interface and GPIOs are operational. The power state machine features a retry counter that limits the number of transitions from POWERDOWN to ACTIVE under certain conditions. A watchdog timeout triggers POWERDOWN mode entry, but it does not necessarily clear the conditions that trigger a transition back to the ACTIVE mode. This could cause an endless loop between the ACTIVE and POWERDOWN modes. Therefore, after each watchdog timeout the retry counter is decremented, and after the retry counter reaches zero, DA9061 blocks all wakeup events and stays in POWERDOWN mode. This freeze function can be regarded as a substate of the POWERDOWN mode that is undetectable from outside the DA9061. Table 22 describes the state transitions with a level-sensitive wakeup and the freeze function. Table 22: State transitions with a level-sensitive (LS) GPI Current state LS GPI SYS_EN PWR_EN Freeze Note 2 Next state POWERDOWN x x x 1 POWERDOWN POWERDOWN 0 0 x 0 POWERDOWN POWERDOWN x 1 0 0 SYSTEM POWERDOWN x 1 1 0 ACTIVE POWERDOWN 1 x 0 0 SYSTEM POWERDOWN 1 x 1 0 ACTIVE SYSTEM 0 0 x x POWERDOWN SYSTEM x 1 0 x SYSTEM SYSTEM x 1 1 x ACTIVE SYSTEM 1 x 0 x SYSTEM SYSTEM 1 x 1 x ACTIVE ACTIVE 0 0 x x POWERDOWN ACTIVE x 1 0 x SYSTEM ACTIVE x 1 1 x ACTIVE ACTIVE 1 x 0 x SYSTEM ACTIVE 1 x 1 x ACTIVE Note 2 In this table, “Freeze” represents the result of the comparison retry count = 0. The following events will reset the retry counter and release the state machine from the freeze state: ● De-assertion of all blocked level-sensitive wakeup conditions ● Entry to the RESET mode (over-temperature error, nRESETREQ or long press of nONKEY) The freeze operation is illustrated in Figure 17. Once the freeze state is cleared, DA9061 continues operating normally. The freeze function can be enabled in the FREEZE_EN register and the number of retries triggering the freeze can be configured in NFREEZE. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 39 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Retry count 1 Power mode ACTIVE 0 NFREEZE POWERDOWN ACTIVE TWD_ERROR GPI The level sensitive wake-up condition is blocked The watchdog expires The retry count is decremented and reaches zero The level sensitive wake-up condition is de-asserted which resets the retry count The system operates normally upon the next wake-up event Figure 17: Freeze function 6.8.4 Power-up, power-down, and shutdown sequences The power-up, power-down, and shutdown sequences, see Figure 16, are handled by the power supply sequencer, see Section 6.9. All power-up sequences are identical, and the power-down sequences mirror the power-up sequences. The shutdown sequences are also identical to the power-down sequence, but after reaching POWERDOWN mode, the state machine automatically proceeds to RESET mode. The shutdown sequences caused by an internal error or nRESETREQ can be sped up from the INT_SD_MODE and HOST_SD_MODE controls: see Section 6.8.2. 6.8.5 ACTIVE mode In the ACTIVE mode, all supplies and functions are active. The transition from POWERDOWN to ACTIVE mode is handled by the programmable sequencer. DA9061 enters ACTIVE mode after the sequence has completed and the watchdog is enabled (if configured to use watchdog). Status information can be read from the host processor via the 2-wire interface and DA9061 can flag interrupt requests to the host via a dedicated interrupt port (nIRQ). Datasheet CFR0011-120-00 Rev 5 Revision 3.2 40 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.9 Power supply sequencer DA9061 features a programmable power sequencer that handles the system power-up, power-down, and shutdown sequences. The sequencer has a step-up counter, a timer that controls the step period, and a set of comparators that trigger power-on/off events at specific steps of the counter. The structure of the sequencer is depicted in Figure 18. The sequencer is composed of 16 steps, and the step time can be programmed between 32 µs and 8.192 ms. The sequencer will step until it reaches a programmable maximum value (MAX_COUNT), whereupon an interrupt is issued. At each step, the sequencer will enable all the functions that are pointing to that particular step. The power-up and -down sequences cannot be configured separately. When DA9061 is powering down, the sequencer will execute whatever was configured for the power-up sequence but in reverse order. Supplies can also be configured to stay on in POWERDOWN mode. In this case, the sequencer does not disable the regulator but switches to its B-configuration, see Section 6.4. If any pointer is programmed to a step higher than MAX_COUNT, the function is no longer controlled by the sequencer. Only the regulator control pointers (LDO<x>_STEP, BUCK<x>_STEP) are allowed to point to step 0. Setting any other pointer to step 0, effectively disables that function. POWERDOWN mode STANDBY mode ACTIVE mode Wake-up Watchdog alive System Power Power1 9 10 11 MAX_COUNT 12 13 14 15 BUCK3 8 POWER1_EN POWER_END 7 BUCK2 PD_DIS_STEP 6 BUCK1 WAIT_STEP 5 LDO4 4 LDO3 3 LDO2 2 LDO1 1 POWER_EN SYSTEM_END PART_DOWN SYSTEM_EN GPx_RISE 0 GPx_FALL OTPREAD_EN OTP_RD2 Figure 18: Structure of the power sequencer NOTE STANDBY mode can only be reached on power-down, not power-up. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 41 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.9.1 Sub-sequences As illustrated in Figure 18, the sequencer is partitioned into three sub-sequences. These three subsequences can be used to define three power modes for the target application and to move between them in a controlled sequence as a response to control signals or register writes. The first sub-sequence starts from step 0 and ends at a step defined by the SYSTEM_END pointer. After the power-up is triggered, DA9061 performs a partial OTP read (OTP_RD2) if OTPREAD_EN is set. It then waits for SYSTEM_EN to trigger the first sub-sequence. If SYSTEM_EN is already set in the OTP the first sub-sequence starts automatically after the power-up trigger. Alternatively, SYSTEM_EN can be asserted through the SYS_EN input. When the sequencer reaches the SYSTEM_END step the first sub-sequence is completed and the sequencer starts waiting for POWER_EN to trigger the second sub-sequence. If POWER_EN is already set in the OTP, the sequencer does not stop after the first sub-sequence. Alternatively, POWER_EN can be asserted through the PWR_EN input or via a register access. The second sub-sequence starts from the step following SYSTEM_END and stops at a step defined by the POWER_END pointer. When the sequencer reaches the POWER_END step (and the watchdog is active), DA9061 enters ACTIVE mode. The final sub-sequence is triggered by asserting POWER1_EN via a register write. The third sub-sequence starts from the step following POWER_END and stops at a step defined by the MAX_COUNT pointer. If MAX_COUNT points to an earlier step than SYSTEM_END or POWER_END the remaining steps of the sequencer are disabled. The power-down sequences are executed in reverse order to the power-up sequences. If the powerdown sequence is triggered from the ACTIVE mode by de-asserting POWER_EN, the sequencer stops after reversing to the SYSTEM_END step. However, if the power-down sequence is triggered by de-asserting SYSTEM_EN, the sequencer does not stop and reverses back to step 0. Furthermore, if the power-down sequence is triggered by a watchdog timeout, the sequencer reverses to step 0 immediately. A partial power-down can be achieved by setting STANDBY. This makes the sequencer stop at the step pointed to by the PART_DOWN pointer. The next power-up will then start from the PART_DOWN step, instead of step 0. The PART_DOWN pointer has to point to a step smaller than the SYSTEM_END pointer. 6.9.2 Regulator control Each of DA9061’s buck converters and LDOs can be assigned to any of the sequencer steps. In general, when the sequencer reaches a step to which a regulator is assigned, that regulator is enabled by the sequencer. Likewise, when the sequencer reaches the same step on the way down, the regulator is disabled. Multiple supplies can point to the same counter step, however, enabling multiple regulators in the same slot can lead to increased in-rush currents. In the simplest scheme, the sequencer enables regulators during a power-up, and disables them during a power-down. This functionality is achieved by setting BUCK<x>_AUTO/LDO<x>_AUTO and clearing BUCK<x>_CONF/LDO<x>_CONF. Alternatively, the sequencer can be configured to keep the regulator enabled, but switch between the A and B settings in ACTIVE and POWERDOWN modes. The functionality of the BUCK<x>_AUTO/LDO<x>_AUTO and BUCK<x>_CONF/LDO<x>_CONF controls is summarised in Table 23. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 42 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 23: Regulator control functionality of the power supply sequencer Power-up (sequencer direction up) POWERDOWN mode (before) ACTIVE mode (after) AUTO CONF EN SEL EN SEL Sequencer functionality 0 0 x x 0 0 The regulator is disabled at the step pointed to by BUCK<x>_STEP/LDO<x>_STEP and the A-setting (VBUCK<x>_A/VLDO<x>_A) is activated. x 1 x x 1 0 1 x x x 1 0 The regulator is enabled at the step pointed to by BUCK<x>_STEP/LDO<x>_STEP and the A-setting (VBUCK<x>_A/VLDO<x>_A) is activated. Power-down (sequencer direction down) ACTIVE mode (before) POWERDOWN mode (after) AUTO CONF EN SEL EN SEL x 0 x x 0 0 The regulator is disabled at the step pointed to by BUCK<x>_STEP/LDO<x>_STEP and the A-setting (VBUCK<x>_A/VLDO<x>_A) is activated. x 1 x x 1 1 The regulator stays enabled but it is switched to the B-setting (VBUCK<x>_B/VLDO<x>_B). Step 0 of the sequencer has a special meaning. If DEF_SUPPLY is set, the sequencer treats all regulators pointing to step 0 as default supplies. This means that the regulators are enabled automatically when entering the POWERDOWN mode. Regulators assigned to other steps are only enabled after a wakeup condition occurs. Apart from this, step 0 acts the same as steps 1 to 15. If DEF_SUPPLY is ‘0’, step 0 of the sequencer does not have any affect. As mentioned in Section 6.6.1, LDO1 can be programmed as an always-on supply. This is achieved by setting DEF_SUPPLY, LDO1_CONF, and LDO1_EN in the OTP. In normal operation, when the sequencer moves between ACTIVE and POWERDOWN modes, LDO1 behaves as presented in Table 23. However, if DA9061 moves to the RESET mode, this configuration keeps LDO1 enabled. This is not the case for any other regulator. 6.9.3 GPO control Any GPO can be asserted or de-asserted in a sequencer step (GP_RISE<x>_STEP, GP_FALL<x>_STEP). The GPO control is summarised in Table 24. If a GPO is controlled by the sequencer, it is driven to its inactive state when DA9061 is in RESET mode. The GPIO control only works in sequencer steps greater than zero. Table 24: GPO control functionality of the power supply sequencer GPIO<x>_MODE GPO state after reset Sequencer direction Previous GPO state GPO transition at GP_RISE<x> GPO transition at GP_FALL<x> 0 (active low) High Up High High to low - Low - Low to high High - High to low Low Low to high - High - High to low Low Low to high - High High to low - Low - Low to high Down 1 (active high) Low Up Down Datasheet CFR0011-120-00 Rev 5 Revision 3.2 43 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.9.4 Wait step One of the sequencer steps (any step greater than zero) can be configured as a wait step, in which the sequencer stays until an event is detected in the GPI3 input, see Section 6.3.1.2. NOTE The E_GPI3 event has to be cleared after the power-up sequence completes. Otherwise, the wait step in the next power-up sequence will be ineffective. The wait step features an optional 500 ms timeout, which can be used when the wait event never occurs. If the timeout occurs, the steps following the wait step are not executed and a shutdown sequence to RESET mode is triggered. The shutdown reason is signalled with the WAIT_SHUT bit. Alternatively, the wait step can be used as a configurable delay in the sequence (WAIT_MODE, WAIT_TIME). 6.9.5 Power-down disable The PD_DIS_STEP pointer can be used to define a step in the power-up sequence above which a group of functions will be enabled. The functions concerned can be controlled in the PD_DIS register. Similarly, in the power-down sequence, the same groups of functions will be disabled when the sequencer proceeds below the PD_DIS_STEP. 6.10 Junction temperature supervision To protect DA9061 from damage due to excessive power dissipation, the junction temperature is continuously monitored. The monitoring is split into three temperature ranges TEMP_WARN (125 °C), TEMP_CRIT (140 °C), and TEMP_POR (150 °C). If the junction temperature rises above the first threshold (TEMP_WARN), the event E_TEMP is asserted. If the event is not masked, this will issue an interrupt. This first level of temperature supervision is intended for non-invasive temperature control, where the necessary measures for cooling the system down are left to the host software. If the junction temperature increases even further and crosses the second threshold (TEMP_CRIT) a temperature error flag is issued and a shutdown sequence to RESET mode is triggered, see Section 6.8.2. The nRESET output is asserted at the beginning of the shutdown sequence. Therefore, the second level of the temperature supervision does not rely on the host software to take counter-measures. The fault flag can be evaluated by the application after the next power up. There is also a third temperature threshold (TEMP_POR) which causes DA9061 to enter RESET mode without any sequencing and stop all functions. This prevents possible permanent damage due to fast temperature increases. 6.11 System supply voltage supervision Two comparators supervise the system supply VSYS. One is monitoring the undervoltage level (VDD_FAULT_LOWER) and the other is indicating a good system supply (VDD_FAULT_UPPER). The VDD_FAULT_LOWER threshold is OTP configurable and can be set via the VDD_FAULT_ADJ control from 2.5 to 3.25 V in 50 mV steps. The VDD_FAULT_UPPER level is also OTP configurable and can be set via the VDD_HYST_ADJ control from 100 to 450 mV higher than the VDD_FAULT_LOWER threshold. The high-to-low transition of the VDD_FAULT_UPPER signal asserts the event E_VDD_WARN. If the event is not masked, this will issue an interrupt, which can be used by the host processor as an indication to decrease its activity. The status can also be signalled with a dedicated nVDD_FAULT signal, see Section 6.3.2.1. If VSYS drops below VDD_FAULT_LOWER, the error flag VDD_FAULT is asserted and a shutdown sequence to RESET mode is triggered, see Section 6.8.2. The nRESET output is asserted at the beginning of the shutdown sequence. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 44 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 6.12 Internal oscillator An internal oscillator provides a nominal 6.0 MHz clock that is divided to 3.0 MHz for the buck converters. The frequency of the internal oscillator is adjusted during the initial start-up sequence of DA9061 to within 5 % of the nominal 6.0 MHz. It can be further adjusted (±10 %) via a control OSC_FRQ. The tolerance of this frequency will affect most absolute timer values and PWM repetition rates. 6.13 Watchdog The watchdog provides system monitoring functionality. A watchdog timeout triggers shutdown to POWERDOWN mode, signalled in register FAULT_LOG. The watchdog can also be configured to control a secondary reset output in addition to nRESET. This requires that one of the GPIOs is configured as a GPO, controlled by the sequencer. The assertion/de-assertion is used as a reset, and the GPIO is configured as a sequencer controlled GPO. This way, after the watchdog triggers the power-down, the reset output is asserted by the sequencer during the power-down sequence. Once enabled, the watchdog cannot be stopped and it runs in ACTIVE mode (this feature can be bypassed with an OTP configuration). The source clock of the watchdog is the internally generated slow frequency clock. After a cold boot, the watchdog is activated when entering ACTIVE mode. This first watchdog kick is required for DA9061 to move to the ACTIVE mode after a cold boot, as illustrated in Figure 16. After the watchdog is activated, the host must kick the watchdog periodically within the watchdog period programmed with the TWDSCALE control. An interrupt can be generated to warn the host processor of the watchdog timeout. The time for the warning interrupt is half of the watchdog period. The kick can be done by a register write to control WATCHDOG (reg. CONTROL_F) or with the WDKICK input. If the WDKICK input (pin GPIO0) is asserted constantly, the watchdog is virtually disabled as the counter is not incremented (WDG_MODE). If the host processor fails to feed the watchdog, DA9061 will assert a fault bit and enter POWERDOWN mode. The watchdog timeout can also be configured to assert a reset output. This requires that one of the GPIOs is configured as a reset output and assigned to a power sequencer step, see Section 6.9. After each watchdog timeout a retry counter is decremented. If the retry counter reaches zero, DA9061 will stay in POWERDOWN mode, as described in Section 6.8.3. The number of allowed retries can be programmed in the NFREEZE control. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 45 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 7 Register map 7.1 Register page control The device register map is larger than the address range directly addressable from the host interface. The page control register provides the higher address bits and control for using the paging mechanism. There are several copies of this register, one per host interface. These copies are mirrored to addresses 0x080, 0x100 and 0x180. 7.2 Overview Table 25 provides a summary of the registers. A description of each register is provided in Appendix A. Table 25: Register summary Addr Register 7 6 5 REVERT WRITE_MODE PAGE 4 3 2 1 0 GPI4 GPI3 GPI2 GPI1 GPI0 LDO4_ILIM LDO3_ILIM LDO2_ILIM LDO1_ILIM VDD_FAULT POR TWD_ERROR E_NONKEY Page Control 0x000 PAGE_CON Power Manager Control and Monitoring (except IRQs and events) 0x001 STATUS_A DVC_BUSY 0x002 STATUS_B 0x004 STATUS_D 0x005 FAULT_LOG WAIT_SHUT NONKEY NRESETREQ KEY_RESET TEMP_CRIT VDD_START EVENTS_C EVENTS_B E_SEQ_RDY E_WDG_WARN E_ALARM E_LDO_LIM E_TEMP IRQ Events 0x006 EVENT_A 0x007 EVENT_B E_VDD_WARN E_DVC_RDY 0x008 EVENT_C E_GPI4 E_GPI3 M_SEQ_RDY E_GPI2 E_GPI1 E_GPI0 M_WDG_WARN M_ALARM M_NONKEY M_LDO_LIM M_TEMP IRQ Masks 0x00A IRQ_MASK_A 0x00B IRQ_MASK_B M_VDD_WARN M_DVC_RDY 0x00C IRQ_MASK_C M_GPI4 M_GPI3 M_GPI2 M_GPI1 M_GPI0 M_SYSTEM_EN STANDBY POWER1_EN POWER_EN SYSTEM_EN NFREEZE nONKEY_LOCK NRES_MODE FREEZE_EN WATCHDOG_PD SLEW_RATE OTPREAD_EN AUTO_BOOT DEBOUNCING System control 0x00E CONTROL_A 0x00F CONTROL_B 0x010 CONTROL_C M_POWER1_EN BUCK_SLOWST ART DEF_SUPPLY M_POWER_EN 0x011 CONTROL_D 0x012 CONTROL_E TWDSCALE V_LOCK 0x013 CONTROL_F 0x014 PD_DIS WAKE_UP PMCONT_DIS BBAT_DIS CLDR_PAUSE SHUTDOWN PMIF_DIS WATCHDOG GPI_DIS GPIO control 0x015 GPIO_0_1 GPIO1_WEN GPIO1_TYPE GPIO1_PIN GPIO0_WEN GPIO0_TYPE GPIO0_PIN 0x016 GPIO_2_3 GPIO3_WEN GPIO3_TYPE GPIO3_PIN GPIO2_WEN GPIO2_TYPE GPIO2_PIN GPIO4_WEN GPIO4_TYPE GPIO4_PIN 0x017 GPIO_4 0x01C GPIO_WKUP_MOD GPIO4_WKUP_M GPIO3_WKUP_M GPIO2_WKUP_MO GPIO1_WKUP_MO GPIO0_WKUP_MOD E ODE ODE DE DE E GPIO4_MODE GPIO3_MODE GPIO2_MODE GPIO1_MODE GPIO0_MODE 0x01D GPIO_MODE0_4 0x01E GPIO_OUT0_2 GPIO2_OUT GPIO1_OUT 0x01F GPIO_OUT3_4 GPIO0_OUT GPIO4_OUT GPIO3_OUT Power supply control 0x021 BUCK1_CONT VBUCK1_GPI BUCK1_CONF BUCK1_GPI BUCK1_EN 0x022 BUCK3_CONT VBUCK3_GPI BUCK3_CONF BUCK3_GPI BUCK3_EN 0x024 BUCK2_CONT VBUCK2_GPI BUCK2_CONF BUCK2_GPI BUCK2_EN 0x026 LDO1_CONT LDO1_CONF VLDO1_GPI LDO1_PD_DIS LDO1_GPI LDO1_EN 0x027 LDO2_CONT LDO2_CONF VLDO2_GPI LDO2_PD_DIS LDO2_GPI LDO2_EN 0x028 LDO3_CONT LDO3_CONF VLDO3_GPI LDO3_PD_DIS LDO3_GPI LDO3_EN 0x029 LDO4_CONT LDO4_CONF VLDO4_GPI LDO4_PD_DIS LDO4_GPI LDO4_EN 0x032 DVC_1 VLDO4_SEL VLDO3_SEL VBUCK2_SEL VBUCK3_SEL VBUCK1_SEL VLDO2_SEL VLDO1_SEL Power Sequencer 0x081 SEQ NXT_SEQ_START SEQ_POINTER 0x082 SEQ_TIMER SEQ_DUMMY SEQ_TIME Datasheet CFR0011-120-00 Rev 5 Revision 3.2 46 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Addr Register 7 6 5 4 3 0x083 ID_2_1 LDO2_STEP LDO1_STEP 0x084 ID_4_3 LDO4_STEP LDO3_STEP 0x088 ID_12_11 PD_DIS_STEP 0x089 ID_14_13 2 1 0 BUCK1_STEP 0x08A ID_16_15 BUCK2_STEP BUCK3_STEP 0x08D ID_22_21 GP_FALL1_STEP GP_RISE1_STEP 0x08E ID_24_23 GP_FALL2_STEP GP_RISE2_STEP 0x08F ID_26_25 GP_FALL3_STEP GP_RISE3_STEP 0x090 ID_28_27 GP_FALL4_STEP GP_RISE4_STEP 0x091 ID_30_29 GP_FALL5_STEP GP_RISE5_STEP 0x092 ID_32_31 WAIT_STEP 0x095 SEQ_A POWER_END 0x096 SEQ_B PART_DOWN SYSTEM_END 0x097 WAIT WAIT_DIR TIME_OUT 0x099 RESET RESET_EVENT RESET_TIMER MAX_COUNT WAIT_MODE WAIT_TIME Power supply control 0x09A BUCK_ILIM_A BUCK2_ILIM 0x09B BUCK_ILIM_B BUCK3_ILIM 0x09C BUCK_ILIM_C BUCK1_ILIM 0x09E BUCK1_CFG BUCK1_MODE BUCK1_PD_DIS 0x09F BUCK3_CFG BUCK3_MODE BUCK3_PD_DIS 0x0A0 BUCK2_CFG BUCK2_MODE 0x0A4 VBUCK1_A BUCK1_SL_A VBUCK1_A 0x0A5 VBUCK3_A BUCK3_SL_A VBUCK3_A 0x0A7 VBUCK2_A BUCK2_SL_A VBUCK2_A 0x0A9 VLDO1_A LDO1_SL_A VLDO1_A 0x0AA VLDO2_A LDO2_SL_A VLDO2_A 0x0AB VLDO3_A LDO3_SL_A VLDO3_A 0x0AC VLDO4_A LDO4_SL_A 0x0B5 VBUCK1_B BUCK1_SL_B VBUCK1_B 0x0B6 VBUCK3_B BUCK3_SL_B VBUCK3_B 0x0B8 VBUCK2_B BUCK2_SL_B VBUCK2_B 0x0BA VLDO1_B LDO1_SL_B VLDO1_B 0x0BB VLDO2_B LDO2_SL_B VLDO2_B 0x0BC VLDO3_B LDO3_SL_B VLDO3_B 0x0BD VLDO4_B LDO4_SL_B VLDO4_B BUCK2_PD_DIS VLDO4_A BBAT charger control 0x0C5 BBAT_CONT BCHG_ISET BCHG_VSET Customer Trim and Configuration 0x105 INTERFACE IF_BASE_ADDR 0x106 CONFIG_A PM_IF_HSM 0x107 CONFIG_B VDD_HYST_ADJ VDD_FAULT_ADJ 0x108 CONFIG_C BUCK2_CLK_INV BUCK3_CLK_INV BUCK1_CLK_INV 0x109 CONFIG_D PM_IF_FMP PM_IF_V IRQ_TYPE FORCE_RESET 0x10A CONFIG_E 0x10C CONFIG_G HRG NIRQ_MODE BUCK3_AUTO GPI_V BUCK1_AUTO LDO4_AUTO LDO3_AUTO LDO2_AUTO nONKEY_SD NONKEY_PIN LDO1_AUTO BUCK1_FCM 0x10E CONFIG_I LDO_SD INT_SD_MODE HOST_SD_MODE KEY_SD_MODE WATCHDOG_SD 0x10F CONFIG_J IF_RESET TWOWIRE_TO RESET_DURATION SHUT_DELAY 0x110 CONFIG_K 0x112 CONFIG_M PM_I_V BUCK_ACTV_DISC SYSTEM_EN_RD BUCK2_AUTO 0x10D CONFIG_H PM_O_TYPE GPIO4_PUPD OSC_FRQ GPIO3_PUPD WDG_MODE KEY_DELAY GPIO2_PUPD GPIO1_PUPD GPIO0_PUPD NRESETREQ_PU Customer device specific 0x121 GP_ID_0 GP_0 0x122 GP_ID_1 GP_1 0x123 GP_ID_2 GP_2 0x124 GP_ID_3 GP_3 0x125 GP_ID_4 GP_4 0x126 GP_ID_5 GP_5 0x127 GP_ID_6 GP_6 0x128 GP_ID_7 GP_7 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 47 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Addr Register 7 0x129 GP_ID_8 GP_8 0x12A GP_ID_9 GP_9 0x12B GP_ID_10 GP_10 0x12C GP_ID_11 GP_11 0x12D GP_ID_12 GP_12 0x12E GP_ID_13 GP_13 0x12F GP_ID_14 GP_14 0x130 GP_ID_15 GP_15 0x131 GP_ID_16 GP_16 0x132 GP_ID_17 GP_17 0x133 GP_ID_18 GP_18 0x134 GP_ID_19 GP_19 0x181 DEVICE_ID DEV_ID 0x182 VARIANT_ID MRC 0x183 CUSTOMER_ID CUST_ID 0x184 CONFIG_ID CONFIG_REV Datasheet CFR0011-120-00 Rev 5 6 5 4 3 2 1 0 VRC Revision 3.2 48 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 8 Application information 8.1 Component selection The following recommended components are examples selected from requirements of a typical application. The final component selection will be dependent on the specific application. The electrical characteristics (for example, supported voltage/current range) have to be cross-checked and component types may need to be adapted from the individual needs of the target circuitry. 8.1.1 Resistors Table 26: Recommended resistors Pin Value Tol. Size (mm) Rating (mW) Part IREF 200 kΩ ±1% 1005 100 Panasonic ERJ2RKF2003x 8.1.2 Capacitors Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a capacitor, especially ones with high capacitance and small size, the DC bias characteristic has to be taken into account. On the VSYS main supply rail, a minimum distributed capacitance of 40 μF (actual capacitance after voltage and temperature derating) is required. Buck input capacitors should be within 1.5 mm distance from the supply pin, and the output capacitor should be close to the inductor. Table 27: Recommended capacitors Pin Value Tol. Size (mm) Height (mm) Temp. char. Rating (V) Part VLDO1 1 µF ±10% 1005 0.55 X5R 10 GRM155R61A105KE15 VLDOx 2.2 µF ±20% 1005 0.55 X5R 10 GRM155R60J225ME95# VBUCK2 IOUT ≤ 1.5 A 2 x 22 µF ±20% 2012 0.95 X5R 6.3 GRM219R60J226M*** ±20% 1005 0.5 X5R 4.0 CL05A226MR5NZNC VBUCK2 2 x 47 µF ±20% 2012 0.95 X5R 4.0 GRM219R60G476M*** ±20% 1608 0.8 X5R 4.0 CL10A476MR8NZN ±20% 1608 1 X5R 6.3 GRM188R60J226MEA0 ±20% 1005 0.5 X5R 4.0 CL05A226MR5NZNC ±20% 1608 1 X5R 6.3 GRM188R60J226MEA0 ±20% 1005 0.5 X5R 4.0 CL05A226MR5NZNC ±20% 2012 0.95 X5R 4.0 GRM219R60G476M***61 ±20% 1608 0.8 X5R 4.0 CL10A476MR8NZN IOUT > 1.5 A VBUCK3 2 x 22 µF VBUCK1 (half-current mode) 2 x 22 µF VBUCK1 (full-current mode) 2 x 47 µF VSYS 1 x 1 µF ±10% 1005 0.5 X5R 10 GRM155R61A105KE15D VDD_BUCKx 2 x 22 µF ±20% 2012 1.25 X5R 10 LMK212BJ226MG-T 4 x 10 µF ±20% 1005 0.5 X5R 10 GRM155R61A106ME21 VDD_LDO2 1 x 1 µF ±10% 1005 0.5 X5R 10 GRM155R61A105KE15D VDD_LDO34 1 x 1 µF ±10% 1005 0.5 X5R 10 GRM155R61A105KE15D Datasheet CFR0011-120-00 Rev 5 Revision 3.2 49 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Pin Value Tol. Size (mm) Height (mm) Temp. char. Rating (V) Part VDDCORE, VREF 2.2 µF ±20% 1005 0.55 X5R 6.3 GRM155R60J225ME95# 8.1.3 Inductors Inductors should be selected based upon the following parameters: ● ISAT specifies the current causing a reduction in the inductance by a specific amount, typically 30 % ● IRMS specifies the current causing a temperature rise of a specific amount ● DC resistance (DCR) is critical for converter efficiency and should be therefore minimised. ● ESR at the buck switching frequency is critical to converter efficiency in PFM mode and should be therefore minimised. Inductance is given in Table 28. Table 28: Recommended inductors Buck Value ISAT (A) IRMS (A) DCR (typ. mΩ) Size (W×L×H mm) Part Buck1 (half-current mode), Buck2, Buck3 1 µH 2.7 2.3 55 2.0×1.6×1.0 Toko 1285AS-H-1R0N 2.65 2.45 60 2.0×1.6×1.0 Tayo Yuden MAKK2016T1R0M 2.9 2.2 60 2.0×1.6×1.0 TDK TFM201610A-1R0M 3.4 3 60 2.5×2.0×1.0 Toko1269AS-H-1R0N 3.6 3.1 45 2.5×2.0×1.2 Tayo Yuden MAMK2520T1R0M 3.8 3.5 45 2.5×2.0×1.2 Toko 1239AS-H-1R0N 3.9 3.1 48 3.2×2.5×1.0 Toko1276AS-H-1R0N 3.5 2.5 54 2.5×2.0×1.0 TDK TFM252010A-1R0M 3.35 2.5 52 3.0×3.0×1.2 Cyntec PST031B-1R0MS 5.4 11 10.8 4.0×4.0×2.1 Coilcraft XFL4020-102ME Buck1 (full-current mode) Datasheet CFR0011-120-00 Rev 5 1 µH Revision 3.2 50 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 8.2 PCB layout 1005 1005 2016 1608 1005 VLX BUCK1 VDD BUCK1 TP nIRQ nRST VDDCO RE 1005 VSYS LX1 VLDO1 GPIO4 VLDO2 GPIO3 1005 VDD LDO2 GPIO2 1005 IREF GND VREF 1005 VBUCK1 VBUCK3 VSS ANA Quiet ground VBUCK4 VBUCK2 VLX BUCK2 VDD BUCK2 VDD BUCK3 VLX BUCK3 nRESET REQ GPIO0 nONKEY VDD LDO34 SCL GPIO1 VLDO4 1005 VLDO3 SDA 1005 VDDIO 2016 1608 1005 2016 1005 1005 VBUCK3 1608 Figure 19: PCB layout for DA9061 8.2.1 General recommendations Appropriate trace width and quantity of vias should be used for all power supply paths. Too high trace resistances can prevent the system from achieving the best performance, for example, the efficiency and the current ratings of switching converters might be degraded. Furthermore, the PCB may be exposed to thermal hot spots, which can lead to critical overheating due to the positive temperature coefficient of copper. Special care must be taken with the DA9061 pad connections. The traces connecting the pads should of the same width as the pads and they should become wider as soon as possible. It is recommended to create a separate quiet ground to which the VREF capacitor, IREF resistor, and the crystal capacitors are connected. The PCB layout should ensure these component grounds are kept quiet, that is, they should be separated from the main ground return path for the noisy power Datasheet CFR0011-120-00 Rev 5 Revision 3.2 51 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A ground. The quiet ground can then be connected to the main ground at the paddle, as shown in Figure 19. All traces carrying high discontinuous currents should be kept as short as possible. Noise sensitive analog signals, such as feedback lines or crystal connections, should be kept away from traces carrying pulsed analog or digital signals. This can be achieved by separation or shielding with quiet signals or ground traces. 8.2.2 LDOs and switched mode supplies The placement of the distributed capacitors on the VSYS rail must ensure that all VDD inputs and VSYS are connected to a bypass capacitor close to the pad. It is recommended placing at least two 1 µF capacitors close to the VDD_LDOx pads and at least one 10 µF close to the VDD_BUCKx pads. Using a local power plane underneath the device for VSYS might be considered. Transient current loops in the area of the switching converters should be minimised. The common references (IREF, VREF) should be placed close to the device and cross-coupling to any noisy digital or analog trace must be avoided. Output capacitors of the LDOs can be placed close to the input pins of the supplied devices (remote from the DA9061). Care must be taken with trace routing to ensure that no current is carried on feedback lines of the buck output voltages (VBUCKx). The inductor placement is less critical since parasitic inductances have negligible effect. 8.2.3 Optimising thermal performance DA9061 features a ground paddle which should be connected with as many vias as possible to the PCB’s main ground plane in order to achieve good thermal performance. Solder mask openings for the ball landing pads must be arranged to prohibit solder balls flowing into vias. Datasheet CFR0011-120-00 Rev 5 Revision 3.2 52 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A 9 Ordering information The ordering number consists of the part number followed by a suffix indicating the packing method. The “xx” represents a placeholder for the specific OTP variant. For details and availability, please consult Dialog Semiconductor’s customer portal or your local sales representative. Table 29: Ordering information Part number Package Package description DA9061-xxAM1 QFN40, 6 x 6 mm Tray, 490 pcs DA9061-xxAM1-A QFN40, 6 x 6 mm Tray, 490 pcs DA9061-xxAM2 QFN40, 6 x 6 mm T&R, 4000 pcs DA9061-xxAM2-A QFN40, 6 x 6 mm T&R, 4000 pcs Datasheet CFR0011-120-00 Rev 5 Revision 3.2 53 of 82 Comment Automotive AEC-Q100 Grade 3 Automotive AEC-Q100 Grade 3 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Appendix A Register descriptions This appendix describes the registers summarised in Section 7. A.1 PAGE 0 A.1.1 Page control Table 30: PAGE_CON (0x000) Field Slice Description Reset REVERT 7:7 0: PAGE switches the regmap page until rewritten. 1: PAGE reverts to 0 after one access. 0 WRITE_MODE 6:6 2-WIRE sequential write style. 0: Write data to consecutive addresses 1: Write data to random addresses using address/data pairs 0 PAGE 5:0 The top 6 bits of the register address. For 2-WIRE, PAGE[0] is ignored. 0x0 A.1.2 Power manager control and monitoring (except IRQs and events) Table 31: STATUS_A (0x001) Field Slice Description Reset Reserved 7:3 Reserved DVC_BUSY 2:2 One or more DVC capable supplies are ramping Reserved 1:1 Reserved NONKEY 0:0 0 0 Table 32: STATUS_B (0x002) Field Slice Description Reset Reserved 7:5 Reserved GPI4 4:4 GPI level 0 GPI3 3:3 GPI level 0 GPI2 2:2 GPI level 0 GPI1 1:1 GPI level 0 GPI0 0:0 GPI level 0 Reset Table 33: STATUS_D (0x004) Field Slice Description Reserved 7:4 Reserved LDO4_ILIM 3:3 LDO over-current indicator 0 LDO3_ILIM 2:2 LDO over-current indicator 0 LDO2_ILIM 1:1 LDO over-current indicator 0 LDO1_ILIM 0:0 LDO over-current indicator 0 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 54 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 34: FAULT_LOG (0x005) Field Slice Description Reset WAIT_SHUT 7:7 Power-down due to PSS WAIT slot timeout. 0 NRESETREQ 6:6 Power-down due to nRESETREQ or SHUTDOWN register. 0 KEY_RESET 5:5 Power-down due to nONKEY. 0 TEMP_CRIT 4:4 Junction over-temperature 0 VDD_START 3:3 Power-down due to VSYS undervoltage before or within 16 sec after nRESET. 0 VDD_FAULT 2:2 Power-down due to VSYS undervoltage. 0 POR 1:1 DA9061 starts up from no power. 1 TWD_ERROR 0:0 Watchdog timeout 0 Reset A.1.3 IRQ events Table 35: EVENT_A (0x006) Field Slice Description Reserved 7:7 Reserved EVENTS_C 6:6 Event in register EVENT_C is active. 0 EVENTS_B 5:5 Event in register EVENT_B is active. 0 E_SEQ_RDY 4:4 Sequencer reached final position. 0 E_WDG_WARN 3:3 Watchdog timeout warning 0 Reserved 2:1 Reserved E_NONKEY 0:0 nONKEY 0 Table 36: EVENT_B (0x007) Field Slice Description Reset E_VDD_WARN 7:7 VSYS dropped below VDD_FAULT_UPPER threshold. 0 Reserved 6:6 Reserved E_DVC_RDY 5:5 All supplies have finished DVC ramping. Reserved 4:4 Reserved E_LDO_LIM 3:3 Any LDO over-current Reserved 2:2 Reserved E_TEMP 1:1 Junction over-temperature Reserved 0:0 Reserved Datasheet CFR0011-120-00 Rev 5 Revision 3.2 55 of 82 0 0 0 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 37: EVENT_C (0x008) Field Slice Description Reserved 7:5 Reserved E_GPI4 4:4 GPI event according to ACTIVE state setting 0 E_GPI3 3:3 GPI event according to ACTIVE state setting 0 E_GPI2 2:2 GPI event according to ACTIVE state setting 0 E_GPI1 1:1 GPI event according to ACTIVE state setting 0 E_GPI0 0:0 GPI event according to ACTIVE state setting 0 A.1.4 Reset IRQ masks Table 38: IRQ_MASK_A (0x00A) Field Slice Description Reset Reserved 7:5 Reserved M_SEQ_RDY 4:4 Sequencer final position indication 0 M_WDG_WARN 3:3 Watchdog timeout warning 0 Reserved 2:1 Reserved M_NONKEY 0:0 nONKEY 0 Table 39: IRQ_MASK_B (0x00B) Field Slice Description Reset M_VDD_WARN 7:7 VSYS dropped below VDD_FAULT_UPPER threshold. 0 Reserved 6:6 Reserved M_DVC_RDY 5:5 All supplies have finished DVC ramping. Reserved 4:4 Reserved M_LDO_LIM 3:3 Any LDO over-current Reserved 2:2 Reserved M_TEMP 1:1 Junction over-temperature Reserved 0:0 Reserved 0 0 0 Table 40: IRQ_MASK_C (0x00C) Field Slice Description Reserved 7:5 Reserved M_GPI4 4:4 GPI IRQ mask 0 M_GPI3 3:3 GPI IRQ mask 0 M_GPI2 2:2 GPI IRQ mask 0 M_GPI1 1:1 GPI IRQ mask 0 M_GPI0 0:0 GPI IRQ mask 0 Datasheet CFR0011-120-00 Rev 5 Reset Revision 3.2 56 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A A.1.5 System control Table 41: CONTROL_A (0x00E) Field Slice Description Reset Reserved 7:7 Reserved M_POWER1_EN 6:6 Write mask for POWER1_EN 0 M_POWER_EN 5:5 Write mask for POWER_EN 0 M_SYSTEM_EN 4:4 Write mask for SYSTEM_EN 0 STANDBY 3:3 Clearing SYSTEM_EN / releasing SYS_EN or powering down domain SYSTEM by nONKEY will ... 0: ... completely power down to slot 0. 1: ... stop at PART_DOWN. 0 POWER1_EN 2:2 Target status of power domain POWER1. Bus write masked with M_POWER1_EN. 0 POWER_EN 1:1 Target status of power domain POWER. Bus write masked with M_POWER_EN. 0 SYSTEM_EN 0:0 Target status of power domain SYSTEM. Bus write masked with M_SYSTEM_EN. 0 Table 42: CONTROL_B (0x00F) Field Slice Description Reset BUCK_SLOWSTART 7:7 Enable buck slow start (reduced inrush current; increased startup time). 0 NFREEZE 6:5 Block all wakeups after NFREEZE watchdog restart trials. 00 nONKEY_LOCK 4:4 0: normal POWERDOWN mode 1: POWERDOWN controlled by KEY_DELAY 1 NRES_MODE 3:3 If powering down / up ... 0: ... keep nRESET not asserted. 1: ... assert / clear nRESET when entering / leaving POWERDOWN. 1 FREEZE_EN 2:2 Enable watchdog restart limit NFREEZE. 0 WATCHDOG_PD 1:1 Watchdog timer is on (1) / off (0) in POWERDOWN mode. 0 Reserved 0:0 Reserved Datasheet CFR0011-120-00 Rev 5 Revision 3.2 57 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 43: CONTROL_C (0x010) Field Slice Description Reset DEF_SUPPLY 7:7 1: OTP enables / disables all supplies (except LDOCORE) when PSS enters slot 0. 0 SLEW_RATE 6:5 Buck DVC slew rate step width [10 mV/step (20 mV/step for Buck2)] 0: 4 µs 1: 2 µs 2: 1 µs 3: 0.5 µs 10 OTPREAD_EN 4:4 When leaving POWERDOWN mode supplies are configured from OTP. 1 AUTO_BOOT 3:3 After progressing from RESET mode the PSS ... 0: ... requires a wakeup event to start-up. 1: ... starts up automatically. 0 DEBOUNCING 2:0 GPI, nONKEY and nRESETREQ debounce time 0: no debouncing 1: 0.1 ms 2: 1.0 ms 3: 10.24 ms 4: 51.2 ms 5: 256 ms 6: 512 ms 7: 1024 ms 011 Reset Table 44: CONTROL_D (0x011) Field Slice Description Reserved 7:3 Reserved TWDSCALE 2:0 Watchdog timeout scaling 0: Watchdog disabled other: Timeout = 2.5 * 2^(TWDSCALE-1) s 000 Table 45: CONTROL_E (0x012) Field Slice Description Reset V_LOCK 7:7 Prevent host from writing to registers 0x81 - 0x120 except 0x100. 0 Reserved 6:0 Reserved Datasheet CFR0011-120-00 Rev 5 Revision 3.2 58 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 46: CONTROL_F (0x013) Field Slice Description Reset Reserved 7:3 Reserved WAKE_UP 2:2 Wake-up from POWERDOWN mode. Cleared automatically. 0 SHUTDOWN 1:1 POWERDOWN to RESET mode. Cleared automatically. 0 WATCHDOG 0:0 Reset watchdog timer. Cleared automatically. 0 Table 47: PD_DIS (0x014) Field Slice Description Reset PMCONT_DIS 7:7 Disable SYS_EN, PWR_EN and PWR1_EN in POWERDOWN mode. 0 Reserved 6:5 Reserved 0 CLDR_PAUSE 4:4 Disable calendar update in POWERDOWN mode. 0 Reserved 3:3 Reserved PMIF_DIS 2:2 Disable 2-WIRE interface in POWERDOWN mode. Reserved 1:1 Reserved GPI_DIS 0:0 Disable E_GPIx events in POWERDOWN mode. 0 A.1.6 0 GPIO control Table 48: GPIO_0_1 (0x015) Field Slice Description Reset GPIO1_WEN 7:7 0: Passive-to-active transition triggers wakeup. 1: No wakeup 0 GPIO1_TYPE 6:6 GPI: active high (1) / low (0) 1 GPIO1_PIN 5:4 Function of GPIO pad (see GPIO*_OUT if output) 0: reserved (pad configured as analog IO) 1: input (opt. regul. HW ctrl.) 2: output (open drain) 3: output (push-pull) 01 GPIO0_WEN 3:3 0: Passive-to-active transition triggers wakeup. 1: No wakeup 0 GPIO0_TYPE 2:2 GPI: active high (1) / low (0) 1 GPIO0_PIN 1:0 Function of GPIO pad (see GPIO*_OUT if output) 0: Watchdog trigger input 1: input 2: output (open drain) 3: output (push-pull) 01 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 59 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 49: GPIO_2_3 (0x016) Field Slice Description Reset GPIO3_WEN 7:7 0: Passive-to-active transition triggers wakeup. 1: No wakeup 0 GPIO3_TYPE 6:6 GPI: active high (1) / low (0) 1 GPIO3_PIN 5:4 Function of GPIO pad (see GPIO*_OUT if output) 0: reserved (pad configured as analog IO) 1: input (opt. regul. HW ctrl.) 2: output (open drain) 3: output (push-pull) 01 GPIO2_WEN 3:3 0: Passive-to-active transition triggers wakeup. 1: No wakeup 0 GPIO2_TYPE 2:2 GPI: active high (1) / low (0) 1 GPIO2_PIN 1:0 Function of GPIO pad (see GPIO*_OUT if output) 0: Sequencer control input 1: input (opt. regul. HW ctrl.) 2: output (open drain) 3: VDD_FAULT 01 Reset Table 50: GPIO_4 (0x017) Field Slice Description Reserved 7:4 Reserved GPIO4_WEN 3:3 0: Passive-to-active transition triggers wakeup. 1: No wakeup 0 GPIO4_TYPE 2:2 GPI: active high (1) / low (0) 1 GPIO4_PIN 1:0 Function of GPIO pad (see GPIO*_OUT if output) 0: Sequencer control input 1: input 2: output (open drain) 3: output (push-pull) 01 Table 51: GPIO_WKUP_MODE (0x01C) Field Slice Description Reserved 7:5 Reserved GPIO4_WKUP_MODE 4:4 GPI wakeup is edge (0) / level (1) sensitive. 0 GPIO3_WKUP_MODE 3:3 GPI wakeup is edge (0) / level (1) sensitive. 0 GPIO2_WKUP_MODE 2:2 GPI wakeup is edge (0) / level (1) sensitive. 0 GPIO1_WKUP_MODE 1:1 GPI wakeup is edge (0) / level (1) sensitive. 0 GPIO0_WKUP_MODE 0:0 GPI wakeup is edge (0) / level (1) sensitive. 0 Datasheet CFR0011-120-00 Rev 5 Reset Revision 3.2 60 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 52: GPIO_MODE0_4 (0x01D) Field Slice Description Reset Reserved 7:5 Reserved GPIO4_MODE 4:4 Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) 0 GPIO3_MODE 3:3 Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) 0 GPIO2_MODE 2:2 Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) 0 GPIO1_MODE 1:1 Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) 0 GPIO0_MODE 0:0 Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) 0 Table 53: GPIO_OUT0_2 (0x01E) Field Slice Description Reset GPIO2_OUT 7:6 GPIO output function 0: Static value according GPIO*_MODE 1: VDD_FAULT 2: Reserved 3: Sequencer controlled 00 GPIO1_OUT 5:3 GPIO output function 0: Static value according GPIO*_MODE 1: VDD_FAULT 2: Reserved 3: Sequencer controlled 4: Forward GPI0 5: reserved 6: Forward GPI2 7: Forward GPI3 000 GPIO0_OUT 2:0 GPIO output function 0: Static value according GPIO*_MODE 1: VDD_FAULT 2: Reserved 3: Sequencer controlled 4: reserved 5: Forward GPI1 6: Forward GPI2 7: Forward GPI3 000 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 61 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 54: GPIO_OUT3_4 (0x01F) Field Slice Description Reserved 7:5 Reserved GPIO4_OUT 4:3 GPIO output function 0: Static value according GPIO*_MODE 1: VDD_FAULT 2: Reserved 3: Sequencer controlled 00 GPIO3_OUT 2:0 GPIO output function 0: Static value according GPIO*_MODE 1: VDD_FAULT 2: Reserved 3: Sequencer controlled 4: Forward GPI0 5: Forward GPI1 6: Forward GPI2 7: reserved 000 A.1.7 Reset Power supply control Table 55: BUCK1_CONT (0x021) Field Slice Description Reserved 7:7 Reserved VBUCK1_GPI 6:5 Voltage controlling GPI (passive to active transition: VB*_B, act. to pas.: VB*_A) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 Reserved 4:4 Reserved BUCK1_CONF 3:3 Default supply, or sequenced and on in POWERDOWN 0 BUCK1_GPI 2:1 Enabling GPI (passive to active transition: enable, act. to pas.: disable) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 BUCK1_EN 0:0 Enable (dependent on on/off priority order) 0 Datasheet CFR0011-120-00 Rev 5 Reset Revision 3.2 62 of 82 00 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 56: BUCK3_CONT (0x022) Field Slice Description Reserved 7:7 Reserved VBUCK3_GPI 6:5 Voltage controlling GPI (passive to active transition: VB*_B, act. to pas.: VB*_A) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 Reserved 4:4 Reserved BUCK3_CONF 3:3 Default supply, or sequenced and on in POWERDOWN 0 BUCK3_GPI 2:1 Enabling GPI (passive to active transition: enable, act. to pas.: disable) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 BUCK3_EN 0:0 Enable (dependent on on/off priority order) 0 Datasheet CFR0011-120-00 Rev 5 Reset Revision 3.2 63 of 82 00 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 57: BUCK2_CONT (0x024) Field Slice Description Reset Reserved 7:7 Reserved VBUCK2_GPI 6:5 Voltage controlling GPI (passive to active transition: VB*_B, act. to pas.: VB*_A) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 Reserved 4:4 Reserved BUCK2_CONF 3:3 Default supply, or sequenced and on in POWERDOWN 0 BUCK2_GPI 2:1 Enabling GPI (passive to active transition: enable, act. to pas.: disable) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 BUCK2_EN 0:0 Enable (dependent on on/off priority order) 0 00 Table 58: LDO1_CONT (0x026) Field Slice Description Reset LDO1_CONF 7:7 Default supply, or sequenced and on in POWERDOWN 0 VLDO1_GPI 6:5 Voltage controlling GPI (passive to active transition: VLDO*_B, act. to pas.: VLDO*_A) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 Reserved 4:4 Reserved LDO1_PD_DIS 3:3 Disable pull-down resistor when disabled. 0 LDO1_GPI 2:1 Enabling GPI (passive to active transition: enable, act. to pas.: disable) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 LDO1_EN 0:0 Enable (dependent on on/off priority order) 0 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 64 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 59: LDO2_CONT (0x027) Field Slice Description Reset LDO2_CONF 7:7 Default supply, or sequenced and on in POWERDOWN 0 VLDO2_GPI 6:5 Voltage controlling GPI (passive to active transition: VLDO*_B, act. to pas.: VLDO*_A) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 Reserved 4:4 Reserved LDO2_PD_DIS 3:3 Disable pull-down resistor when disabled. 0 LDO2_GPI 2:1 Enabling GPI (passive to active transition: enable, act. to pas.: disable) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 LDO2_EN 0:0 Enable (dependent on on/off priority order) 0 Table 60: LDO3_CONT (0x028) Field Slice Description Reset LDO3_CONF 7:7 Default supply, or sequenced and on in POWERDOWN 0 VLDO3_GPI 6:5 Voltage controlling GPI (passive to active transition: VLDO*_B, act. to pas.: VLDO*_A) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 Reserved 4:4 Reserved LDO3_PD_DIS 3:3 Disable pull-down resistor when disabled. 0 LDO3_GPI 2:1 Enabling GPI (passive to active transition: enable, act. to pas.: disable) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 LDO3_EN 0:0 Enable (dependent on on/off priority order) 0 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 65 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 61: LDO4_CONT (0x029) Field Slice Description Reset LDO4_CONF 7:7 Default supply, or sequenced and on in POWERDOWN 0 VLDO4_GPI 6:5 Voltage controlling GPI (passive to active transition: VLDO*_B, act. to pas.: VLDO*_A) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 Reserved 4:4 Reserved LDO4_PD_DIS 3:3 Disable pull-down resistor when disabled. 0 LDO4_GPI 2:1 Enabling GPI (passive to active transition: enable, act. to pas.: disable) 0: Sequencer controlled 1: Select GPI1 2: Select GPI2 3: Select GPI3 00 LDO4_EN 0:0 Enable (dependent on on/off priority order) 0 Table 62: DVC_1 (0x032) Field Slice Description Reset VLDO4_SEL 7:7 Select VLDO4_A (0) / VLDO4_B (1). 0 VLDO3_SEL 6:6 Select VLDO3_A (0) / VLDO3_B (1). 0 VLDO2_SEL 5:5 Select VLDO2_A (0) / VLDO2_B (1). 0 VLDO1_SEL 4:4 Select VLDO1_A (0) / VLDO1_B (1). 0 VBUCK2_SEL 3:3 Select VBUCK2_A (0) / VBUCK2_B (1). 0 VBUCK3_SEL 2:2 Select VBUCK3_A (0) / VBUCK3_B (1). 0 Reserved 1:1 Reserved 0 VBUCK1_SEL 0:0 Select VBUCK1_A (0) / VBUCK1_B (1). 0 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 66 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A A.2 PAGE 1 A.2.1 Power sequencer Table 63: SEQ (0x081) Field Slice Description Reset NXT_SEQ_START 7:4 Start position of next sequence 0x0 SEQ_POINTER 3:0 Actual power sequencer position 0x0 Table 64: SEQ_TIMER (0x082) Field Slice Description Reset SEQ_DUMMY 7:4 Waiting time for power sequencer slots which do not have an associated power supply. 0: 32 µs 1: 64 µs 2: 96 µs 3: 128 µs 4: 160 µs 5: 192 µs 6: 224 µs 7: 256 µs 8: 288 µs 9: 384 µs 10: 448 µs 11: 512 µs 12: 1.024 ms 13: 2.048 ms 14: 4.096 ms 15: 8.192 ms 0xD SEQ_TIME 3:0 Length of each PSS sequencer time slot 0: 32 µs 1: 64 µs 2: 96 µs 3: 128 µs 4: 160 µs 5: 192 µs 6: 224 µs 7: 256 µs 8: 288 µs 9: 384 µs 10: 448 µs 11: 512 µs 12: 1.024 ms 13: 2.048 ms 14: 4.096 ms 15: 8.192 ms 0xC Datasheet CFR0011-120-00 Rev 5 Revision 3.2 67 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 65: ID_2_1 (0x083) Field Slice Description Reset LDO2_STEP 7:4 Sequencer step for LDO2 0x0 LDO1_STEP 3:0 Sequencer step for LDO1 0x0 Table 66: ID_4_3 (0x084) Field Slice Description Reset LDO4_STEP 7:4 Sequencer step for LDO4 0x0 LDO3_STEP 3:0 Sequencer step for LDO3 0x0 Table 67: ID_12_11 (0x088) Field Slice Description Reset PD_DIS_STEP 7:4 Sequencer step for Power-down Disable 0x0 Reserved 3:0 Reserved Table 68: ID_14_13 (0x089) Field Slice Description Reset Reserved 7:4 Reserved 0x0 BUCK1_STEP 3:0 Sequencer step for Buck1 0x0 Table 69: ID_16_15 (0x08A) Field Slice Description Reset BUCK2_STEP 7:4 Sequencer step for Buck2 0x0 BUCK3_STEP 3:0 Sequencer step for Buck3 0x0 Table 70: ID_22_21 (0x08D) Field Slice Description Reset GP_FALL1_STEP 7:4 Sequencer step for de-assert GPO0 0x0 GP_RISE0_STEP 3:0 Sequencer step for assert GPO0 0x0 Table 71: ID_24_23 (0x08E) Field Slice Description Reset GP_FALL2_STEP 7:4 Sequencer step for de-assert GPO1 0x0 GP_RISE1_STEP 3:0 Sequencer step for assert GPO1 0x0 Table 72: ID_26_25 (0x08F) Field Slice Description Reset GP_FALL3_STEP 7:4 Sequencer step for de-assert GPO2 0x0 GP_RISE2_STEP 3:0 Sequencer step for assert GPO2 0x0 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 68 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 73: ID_28_27 (0x090) Field Slice Description Reset GP_FALL4_STEP 7:4 Sequencer step for de-assert GPO3 0x0 GP_RISE3_STEP 3:0 Sequencer step for assert GPO3 0x0 Table 74: ID_30_29 (0x091) Field Slice Description Reset GP_FALL5_STEP 7:4 Sequencer step for de-assert GPO4 0x0 GP_RISE4_STEP 3:0 Sequencer step for assert GPO4 0x0 Table 75: ID_32_31 (0x092) Field Slice Description Reset Reserved 7:4 Reserved 0x0 WAIT_STEP 3:0 Sequencer step for WAIT 0x0 Table 76: SEQ_A (0x095) Field Slice Description Reset POWER_END 7:4 End of POWER power domain in the PSS sequencer SYSTEM_END <= POWER_END <= MAX_COUNT must be true. 0x3 SYSTEM_END 3:0 End of SYSTEM power domain in the PSS sequencer PART_DOWN <= SYSTEM_END <= POWER_END must be true. 0x2 Table 77: SEQ_B (0x096) Field Slice Description Reset PART_DOWN 7:4 PSS sequencer slot to stop at, when going down into STANDBY state. 1 <= PART_DOWN <= SYSTEM_END must be true. 0x1 MAX_COUNT 3:0 End of POWER1 power domain in the PSS sequencer POWER_END <= MAX_COUNT must be true. 0x4 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 69 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 78: WAIT (0x097) Field Slice Description Reset WAIT_DIR 7:6 WAIT STEP power sequence selection 0: Do not wait during WAIT_STEP of power sequencer except for normal slot time. 1: Wait during up sequence. 2: Wait during down sequence. 3: Wait during up and down sequence. 00 TIME_OUT 5:5 Timeout when WAIT_MODE = 0 0: no timeout when waiting for external signal (GPIO3). 1: 500 ms timeout when waiting for external signal (GPIO3). 0 WAIT_MODE 4:4 0: Wait for external signal (GPIO3) to be active. 1: Start timer and wait for expiration. 1 WAIT_TIME 3:0 Wait timer during WAIT STEP of power sequencer (+/- 10%) 0: Do not wait during WAIT_STEP of power sequencer except for normal slot time. 1: 512 µs 2: 1.0 ms 3: 2.0 ms 4: 4.1 ms 5: 8.2 ms 6: 16.4 ms 7: 32.8 ms 8: 65.5 ms 9: 128 ms 10: 256 ms 11: 512 ms 12: 1.0 s 13: 2.0 s 14: 4.1 s 15: 8.2 s 0xB Datasheet CFR0011-120-00 Rev 5 Revision 3.2 70 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 79: RESET (0x099) Field Slice Description Reset RESET_EVENT 7:6 Reset timer started by: 0: EXT_WAKEUP 1: SYS_UP (register control or pin) 2: PWR_UP (register control or pin) 3: Leaving PMIC RESET mode 01 RESET_TIMER 5:0 0: Release nRESET immediately after the event selected by RESET_EVENT. 1 - 31: 1.024 ms * RESET_TIMER 32-63: 1.024 ms * 32 * (RESET_TIMER-31) 0x5 A.2.2 Power supply control Table 80: BUCK_ILIM_A (0x09A) Field Slice Description Reset Reserved 7:4 Reserved BUCK2_ILIM 3:0 Buck current limit = (1500 + n * 100) mA 0xA Table 81: BUCK_ILIM_B (0x09B) Field Slice Description Reset Reserved 7:4 Reserved BUCK3_ILIM 3:0 Buck current limit = (500 + n * 100) mA 0xA Table 82: BUCK_ILIM_C (0x09C) Field Slice Description Reset Reserved 7:4 Reserved 0xA BUCK1_ILIM 3:0 Buck current limit = (500 + n * 100) mA In full-current mode the limit is internally doubled. 0xA Table 83: BUCK1_CFG (0x09E) Field Slice Description Reset BUCK1_MODE 7:6 0: Controlled by B*_SL_A/B 1: Sleep 2: Synchronous 3: Automatic 11 BUCK1_PD_DIS 5:5 Disable pull-down resistor when disabled. 0 Reserved 4:1 Reserved Reserved 0:0 Reserved Datasheet CFR0011-120-00 Rev 5 Revision 3.2 71 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 84: BUCK3_CFG (0x09F) Field Slice Description Reset BUCK3_MODE 7:6 0: Controlled by B*_SL_A/B 1: Sleep 2: Synchronous 3: Automatic 11 BUCK3_PD_DIS 5:5 Disable pull-down resistor when disabled. 0 Reserved 4:0 Reserved Table 85: BUCK2_CFG (0x0A0) Field Slice Description Reset BUCK2_MODE 7:6 0: Controlled by B*_SL_A/B 1: Sleep 2: Synchronous 3: Automatic 11 BUCK2_PD_DIS 5:5 Disable pull-down resistor when disabled. 0 Reserved 4:0 Reserved Table 86: VBUCK1_A (0x0A4) Field Slice Description Reset BUCK1_SL_A 7:7 Force sync (0) / sleep (1) mode if B*_MODE==VSELCTL and VB*_A is active. 0 VBUCK1_A 6:0 From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV 0x50 Table 87: VBUCK3_A (0x0A5) Field Slice Description Reset BUCK3_SL_A 7:7 Force sync (0) / sleep (1) mode if B*_MODE==VSELCTL and VB*_A is active. 0 VBUCK3_A 6:0 From 0.53 V (0x00) to 1.8 V (0x7F) in steps of 10 mV 0x43 Table 88: VBUCK2_A (0x0A7) Field Slice Description Reset BUCK2_SL_A 7:7 Force sync (0) / sleep (1) mode if B*_MODE==VSELCTL and VB*_A is active. 0 VBUCK2_A 6:0 From 0.80 V (0x00) to 3.34 V (0x7F) in steps of 20 mV 0x14 Table 89: VLDO1_A (0x0A9) Field Slice Description Reset LDO1_SL_A 7:7 Force LDO sleep mode if VLDO*_A is active. 0 Reserved 6:6 Reserved VLDO1_A 5:0 From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Datasheet CFR0011-120-00 Rev 5 Revision 3.2 72 of 82 0x31 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 90: VLDO2_A (0x0AA) Field Slice Description Reset LDO2_SL_A 7:7 Force LDO sleep mode if VLDO*_A is selected. 0 Reserved 6:6 Reserved VLDO2_A 5:0 From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V 0x31 Table 91: VLDO3_A (0x0AB) Field Slice Description Reset LDO3_SL_A 7:7 Force LDO sleep mode if VLDO*_A is selected. 0 Reserved 6:6 Reserved VLDO3_A 5:0 From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V 0x31 Table 92: VLDO4_A (0x0AC) Field Slice Description Reset LDO4_SL_A 7:7 Force LDO sleep mode if VLDO*_A is selected. 0 Reserved 6:6 Reserved VLDO4_A 5:0 From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V 0x31 Table 93: VBUCK1_B (0x0B5) Field Slice Description Reset BUCK1_SL_B 7:7 Force sync (0) / sleep (1) mode if B*_MODE==VSELCTL and VB*_B is active. 1 VBUCK1_B 6:0 From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV 0x3C Table 94: VBUCK3_B (0x0B6) Field Slice Description Reset BUCK3_SL_B 7:7 Force sync (0) / sleep (1) mode if B*_MODE==VSELCTL and VB*_B is active. 1 VBUCK3_B 6:0 From 0.53 V (0x00) to 1.8 V (0x7F) in steps of 10 mV 0x43 Table 95: VBUCK2_B (0x0B8) Field Slice Description Reset BUCK2_SL_B 7:7 Force sync (0) / sleep (1) mode if B*_MODE==VSELCTL and VB*_B is active. 1 VBUCK2_B 6:0 From 0.80 V (0x00) to 3.34 V (0x7F) in steps of 20 mV 0x14 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 73 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 96: VLDO1_B (0x0BA) Field Slice Description Reset LDO1_SL_B 7:7 Force LDO sleep mode if VLDO*_B is selected. 0 Reserved 6:6 Reserved VLDO1_B 5:0 From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V 0x31 Table 97: VLDO2_B (0x0BB) Field Slice Description Reset LDO2_SL_B 7:7 Force LDO sleep mode if VLDO*_B is selected. 0 Reserved 6:6 Reserved VLDO2_B 5:0 From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V 0x31 Table 98: VLDO3_B (0x0BC) Field Slice Description Reset LDO3_SL_B 7:7 Force LDO sleep mode if VLDO*_B is selected. 0 Reserved 6:6 Reserved VLDO3_B 5:0 From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V 0x31 Table 99: VLDO4_B (0x0BD) Field Slice Description Reset LDO4_SL_B 7:7 Force LDO sleep mode if VLDO*_B is selected. 0 Reserved 6:6 Reserved VLDO4_B 5:0 From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V A.3 0x31 PAGE 2 A.3.1 Customer trim and configuration Table 100: INTERFACE (0x105) Field Slice Description Reset IF_BASE_ADDR 7:4 2-WIRE slave address MSBs. The LSBs of the slave address are “000”. The complete slave address is then 3 IF_BASE_ADDR * 2 . However, the device also responds to 3 IF_BASE_ADDR * 2 +1. 0xB Reserved 3:0 Reserved Datasheet CFR0011-120-00 Rev 5 Revision 3.2 74 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 101: CONFIG_A (0x106) Field Slice Description Reset Reserved 7:7 Reserved PM_IF_HSM 6:6 2-WIRE interface permanently in high speed mode 0 PM_IF_FMP 5:5 2-WIRE interface selects fast-mode+ timings 0 PM_IF_V 4:4 2-WIRE supplied from VDDCORE (0) / VDDIO (1). 0 IRQ_TYPE 3:3 nIRQ is active low (0) / high (1). 0 PM_O_TYPE 2:2 nRESET and nIRQ are push pull (0) / open drain (1). 1 Reserved 1:1 Reserved PM_I_V 0:0 nRESETREQ, SYS_EN, PWR_EN and KEEPACT supplied from VDDCORE (0) / VDDIO (1). 0 Reset Table 102: CONFIG_B (0x107) Field Slice Description Reserved 7:7 Reserved VDD_HYST_ADJ 6:4 VDD_FAULT comparator hysteresis from 100 mV (0x0) to 450 mV (0x7) in 50 mV steps 001 VDD_FAULT_ADJ 3:0 VDD_FAULT comparator level from 2.5 V (0x0) to 3.25 V (0xF) in 50 mV steps 0x6 Reset Table 103: CONFIG_C (0x108) Field Slice Description Reserved 7:7 Reserved BUCK2_CLK_INV 6:6 Buck clock polarity inverted. Reserved 5:5 Reserved BUCK3_CLK_INV 4:4 Buck clock polarity inverted. 1 BUCK1_CLK_INV 3:3 Buck clock polarity inverted. 0 BUCK_ACTV_DISCHRG 2:2 Enable active discharging of buck rails. 1 Reserved 1:0 Reserved Datasheet CFR0011-120-00 Rev 5 Revision 3.2 75 of 82 0 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 104: CONFIG_D (0x109) Field Slice Description Reset Reserved 7:6 Reserved FORCE_RESET 5:5 Keep nRESET always asserted Reserved 4:3 Reserved SYSTEM_EN_RD 2:2 Suppress loading SYSTEM_EN during OTP_RD2 0 NIRQ_MODE 1:1 nIRQ will be asserted from events during POWERDOWN ... 0 GPI_V 0:0 GPIs, except power manager controls, supplied from VDDCORE (0) / VDDIO (1). 0 Reset 0 Table 105: CONFIG_E (0x10A) Field Slice Description Reserved 7:5 Reserved BUCK2_AUTO 4:4 When powering up, enable and select VBUCK2_A. Reserved 3:3 Reserved BUCK3_AUTO 2:2 When powering up, enable and select VBUCK3_A. 0 Reserved 1:1 Reserved 0 BUCK1_AUTO 0:0 When powering up, enable and select VBUCK1_A. 0 Reset 0 Table 106: CONFIG_G (0x10C) Field Slice Description Reserved 7:4 Reserved LDO4_AUTO 3:3 When powering up, enable and select VLDO4_A. 0 LDO3_AUTO 2:2 When powering up, enable and select VLDO3_A. 0 LDO2_AUTO 1:1 When powering up, enable and select VLDO2_A. 0 LDO1_AUTO 0:0 When powering up, enable and select VLDO1_A. 0 Table 107: CONFIG_H (0x10D) Field Slice Description Reserved 7:7 Reserved BUCK1_FCM 6:6 Buck full-current mode (double pass device and current limit). 0 Reserved 5:5 Reserved 0 Reserved 4:0 Reserved Datasheet CFR0011-120-00 Rev 5 Reset Revision 3.2 76 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 108: CONFIG_I (0x10E) Field Slice Description Reset LDO_SD 7:7 Enable switching off an LDO if an over-current is detected longer than 200 ms. 0 INT_SD_MODE 6:6 Skip seq and dummy slot on shutdown from internal fault. 0 HOST_SD_MODE 5:5 Skip seq and dummy slot on shutdown from SHUTDOWN or nRESETREQ. 1 KEY_SD_MODE 4:4 Enable power-on reset on shutdown from nONKEY. 0 WATCHDOG_SD 3:3 Enable shutdown instead of power-down on watchdog timeout. 1 nONKEY_SD 2:2 Enable shutdown via long pressing nONKEY. 0 NONKEY_PIN 1:0 nONKEY function 01 Table 109: CONFIG_J (0x10F) Field Slice Description Reset IF_RESET 7:7 Enable host interface reset via nRESETREQ pin 0 TWOWIRE_TO 6:6 Enable 35 ms timeout for 2-wire interfaces 0 RESET_DURATION 5:4 Minimum RESET mode duration: 0x00 = 22 ms 0x01 = 100 ms 0x10 = 500 ms 0x11 = 1 s 00 SHUT_DELAY 3:2 Shut down delay (+ KEY_DELAY) for nONKEY 10 KEY_DELAY 1:0 nONKEY locking threshold 10 Reset Table 110: CONFIG_K (0x110) Field Slice Description Reserved 7:5 Reserved GPIO4_PUPD 4:4 GPI: pull-down enabled open drain GPO: pull-up enabled 0 GPIO3_PUPD 3:3 GPI: pull-down enabled open drain GPO: pull-up enabled 0 GPIO2_PUPD 2:2 GPI: pull-down enabled open drain GPO: pull-up enabled 0 GPIO1_PUPD 1:1 GPI: pull-down enabled open drain GPO: pull-up enabled 0 GPIO0_PUPD 0:0 GPI: pull-down enabled open drain GPO: pull-up enabled 0 Table 111: CONFIG_M (0x112) Field Slice Description Reset OSC_FRQ 7:4 Modify HF oscillator frequency by about ±10 % (-8/+7 steps). 0x0 WDG_MODE 3:3 Select watchdog Halt operation mode. 0 Reserved 2:2 Reserved NRESETREQ_PU 1:1 nRESETREQ: pull-up enabled Reserved 0:0 Reserved Datasheet CFR0011-120-00 Rev 5 Revision 3.2 77 of 82 0 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A A.3.2 Customer device specific Table 112: GP_ID_0 (0x121) Field Slice Description Reset GP_0 7:0 General purpose register 0x0 Table 113: GP_ID_1 (0x122) Field Slice Description Reset GP_1 7:0 General purpose register 0x0 Table 114: GP_ID_2 (0x123) Field Slice Description Reset GP_2 7:0 General purpose register 0x0 Table 115: GP_ID_3 (0x124) Field Slice Description Reset GP_3 7:0 General purpose register 0x0 Table 116: GP_ID_4 (0x125) Field Slice Description Reset GP_4 7:0 General purpose register 0x0 Table 117: GP_ID_5 (0x126) Field Slice Description Reset GP_5 7:0 General purpose register 0x0 Table 118: GP_ID_6 (0x127) Field Slice Description Reset GP_6 7:0 General purpose register 0x0 Table 119: GP_ID_7 (0x128) Field Slice Description Reset GP_7 7:0 General purpose register 0x0 Table 120: GP_ID_8 (0x129) Field Slice Description Reset GP_8 7:0 General purpose register 0x0 Table 121: GP_ID_9 (0x12A) Field Slice Description Reset GP_9 7:0 General purpose register 0x0 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 78 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 122: GP_ID_10 (0x12B) Field Slice Description Reset GP_10 7:0 General purpose register 0x0 Table 123: GP_ID_11 (0x12C) Field Slice Description Reset GP_11 7:0 General purpose register 0x0 Table 124: GP_ID_12 (0x12D) Field Slice Description Reset GP_12 7:0 General purpose register 0x0 Table 125: GP_ID_13 (0x12E) Field Slice Description Reset GP_13 7:0 General purpose register 0x0 Table 126: GP_ID_14 (0x12F) Field Slice Description Reset GP_14 7:0 General purpose register 0x0 Table 127: GP_ID_15 (0x130) Field Slice Description Reset GP_15 7:0 General purpose register 0x0 Table 128: GP_ID_16 (0x131) Field Slice Description Reset GP_16 7:0 General purpose register 0x0 Table 129: GP_ID_17 (0x132) Field Slice Description Reset GP_17 7:0 General purpose register 0x0 Table 130: GP_ID_18 (0x133) Field Slice Description Reset GP_18 7:0 General purpose register 0x0 Table 131: GP_ID_19 (0x134) Field Slice Description Reset GP_19 7:0 General purpose register 0x0 Table 132: DEVICE_ID (0x181) Field Slice Description Reset DEV_ID 7:0 Device ID 0x0 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 79 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Table 133: VARIANT_ID (0x182) Field Slice Description Reset MRC 7:4 Mask revision code 0x0 VRC 3:0 Chip variant code Table 134: CUSTOMER_ID (0x183) Field Slice Description Reset CUST_ID 7:0 Customer ID 0x0 Table 135: CONFIG_ID (0x184) Field Slice Description Reset CONFIG_REV 7:0 OTP settings revision 0x0 Datasheet CFR0011-120-00 Rev 5 Revision 3.2 80 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Revision history Table 136: Revision history Revision Date Changes 3.2 01-Mar-2016 Table 3: Absolute maximum ratings ● replaced TA parameter with TJ ● replaced Note 1 ● ESD tolerance renamed to ESD protection HBM and moved the value to Min ● added ESD protection CDM parameters Table 4: Recommended operating conditions ● added Maximum power dissipation ● added Note 2 Table 5: Digital I/O electrical characteristics ● RPU: values aligned with characterisation results: ○ VDDIO = 1.5 V: Min value changed from 100 to 60 kΩ ○ VDDIO = 1.5 V: Max value changed from 340 to 310 kΩ ○ ○ ○ VDDIO = 1.8 V: Min value changed from 65 to 45 kΩ VDDIO = 1.8 V: Max value changed from 175 to 190 kΩ VDDIO = 3.3 V: Min value changed from 25 to 20 kΩ Table 10: LDOCORE electrical characteristics ● removed VDD parameter ● added VDROPOUT parameter ● added Note 1 and Note 2 ● added NOTE Table 11, Table 12, Table 13: Buck1 to Buck3 electrical characteristics ● VBUCK_ACC: added Note 1 Table 15: System supply voltage supervision electrical characteristics ● added Note 1 and Note 2 ● VDD_FAULT_LOWER: removed test condition ● VHYS: renamed to VDD_FAULT_HYS and removed test condition ● added VREF, CVREF, RIREF parameters Table 16: Junction temperature supervision electrical characteristics ● added Note 1 Figure 18: Structure of the power sequencer ● added STANDBY mode ● added NOTE Register map ● Table 25 CONFIG_A control names corrected to PM_IF_HSM, PM_IF_FMP, and PM_IF_V ● Table 43: SLEW_RATE: 20 mV/step for Buck2 added ● Table 81: BUCK_ILIM_B and BUCK3_ILIM: Note removed regarding full-current mode Other: ● REG_PAGE corrected to PAGE ● NSHUTDOWN corrected to NRESETREQ ● Editorial changes 3.1 20-Oct-2015 Datasheet CFR0011-120-00 Rev 5 Initial release Revision 3.2 81 of 82 01-Mar-2016 © 2016 Dialog Semiconductor DA9061 Entry level PMIC for applications requiring up to 6 A Status definitions Revision Datasheet status Product status Definition 1.<n> Target Development This datasheet contains the design specifications for product development. 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Contacting Dialog Semiconductor United Kingdom (Headquarters) Dialog Semiconductor (UK) LTD Phone: +44 1793 757700 North America Dialog Semiconductor Inc. Phone: +1 408 845 8500 Singapore Dialog Semiconductor Singapore Phone: +65 64 8499 29 China (Shenzhen) Dialog Semiconductor China Phone: +86 755 2981 3669 Germany Dialog Semiconductor GmbH Phone: +49 7021 805-0 Japan Dialog Semiconductor K. K. Phone: +81 3 5425 4567 Hong Kong Dialog Semiconductor Hong Kong Phone: +852 3769 5200 China (Shanghai) Dialog Semiconductor China Phone: +86 21 5424 9058 The Netherlands Dialog Semiconductor B.V. Phone: +31 73 640 8822 Taiwan Dialog Semiconductor Taiwan Phone: +886 281 786 222 Korea Dialog Semiconductor Korea Phone: +82 2 3469 8200 Email: [email protected] Web site: www.dialog-semiconductor.com Datasheet CFR0011-120-00 Rev 5 Revision 3.2 82 of 82 01-Mar-2016 © 2016 Dialog Semiconductor