TI1 OPA1662AIDRQ1 Operational amplifier Datasheet

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OPA1662-Q1
SLOS805C – JULY 2012 – REVISED AUGUST 2016
OPA1662-Q1 Dual, 3.3 nV/√Hz Noise, 0.00006% THD+N, RRO, Bipolar-Input Audio
Operational Amplifier
1 Features
3 Description
•
•
The OPA1662-Q1 is a dual, bipolar-input operational
amplifier which is well suited for premium audio
external amplifier applications in infotainment and
cluster systems. In audio systems, the main concern
is to ensure a clear, quality output signal which
means minimuzing any noise introduced to the signal.
The OPA1662-Q1 offers low noise density with an
ultra-low distortion of 0.00006% at 1 kHz that
maximizes the signal output. Additionally, this op amp
offers rail-to-rail output swing to within 600 mV with 2kΩ load. The wide headroom ensures that the output
signal does not clip, and therefore preserves the
audio quality.
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 3: –40°C to 85°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
Low Noise: 3.3 nV/√Hz at 1 kHz
Low Distortion: 0.00006% at 1 kHz
Low Quiescent Current: 1.5 mA per Channel
Slew Rate: 17 V/μs
Wide Gain Bandwidth: 22 MHz (G = 1)
Unity Gain Stable
Rail-to-Rail Output
Wide Supply Range: ±1.5 V to ±18 V,
or 3 V to 36 V
Small Package Sizes:
Dual: 8-Pin SOIC and VSSOP
2 Applications
•
•
•
•
•
Automotive
Car Audio
Premium Audio
External Audio Amplifiers
Body Control Modules
the OPA1662-Q1 operates over a very wide supply
range of ±1.5 V to ±18 V, or 3 V to 36 V, on only
1.5 mA of supply current per channel. The wide
supply range enables design flexibility for the device
as it can be integrated from a power amplifier driven
by the battery to being driven from an ADC to DAC
for low-power applications. Additionally, this device
also has a high-output drive capability of ±30 mA and
can act as the sole audio amplifier for low-power
applications, such as for cluster chimes.
Device Information(1)
PART NUMBER
OPA1662-Q1
BODY SIZE (NOM)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Input Voltage Noise Density and Input Current
Noise Density vs Frequency
THD+N Ratio vs Frequency
0.01
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V, RL = 600Ω
G = +1V/V, RL = 2kΩ
G = −1V/V, RL = 600Ω
G = −1V/V, RL = 2kΩ
100
100
10
1
1
THD+N (%)
10
Current Noise (pA/ Hz)
Voltage Noise
Current Noise
Voltage Noise (nV/ Hz)
PACKAGE
SOIC (8)
0.001
0.0001
VOUT = 3VRMS
BW = 80kHz
0.1
1
10
100
1k
Frequency (Hz)
10k
0.1
100k
0.00001
G001
20
100
1k
Frequency (Hz)
10k
20k
G007
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1662-Q1
SLOS805C – JULY 2012 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description Continued ..........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
3
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VS = ±15 V.......................
Electrical Characteristics: VS = 5 V...........................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
11.3 Power Dissipation ................................................. 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2012) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Removed Ordering Information table, see POA at the end of the data sheet........................................................................ 1
•
Changed the Description section............................................................................................................................................ 1
Changes from Revision A (September 2012) to Revision B
Page
•
Changed top-side marking for OPA1662AIDRQ1 from preview to O1662Q in Ordering Information table........................... 1
•
Changed Grade 1 to Grade 3 in Features.............................................................................................................................. 1
Changes from Original (July 2012) to Revision A
•
2
Page
Device going from 2-page preview to production status, full-length document included in this revision. .............................. 1
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5 Description Continued
The device also features completely independent circuitry for each of the two channels to enable low crosstalk
and freedom from interactions between each channel, even when overdriven or overloaded. This feature enables
customers to drive two different audio signals with ease of mind that the signals are not affected by each other.
The OPA1662-Q1 offers a wide bandwidth of 22 MHz and high slew rate of 17 V/µs which is applicable as a high
and low side sensing for ripple currents in SMPS devices or motor drives. As a current sensor, the OPA1662-Q1
can be used as peak current mode control, with the op amps offering stability and enabling higher bandwidth for
the system. The OPA1662-Q1 is applicable in body control modules and HEV or EV converters where motors
typically are used.
6 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
1
-IN A
2
+IN A
3
V-
4
A
B
8
V+
7
OUT B
6
-IN B
5
+IN B
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input channel A
–IN A
2
I
Inverting input channel A
+IN B
5
I
Noninverting input channel B
–IN B
6
I
Inverting input channel B
OUT_A
1
O
Output, channel A
OUT_B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
40
V
(V–) – 0.5
(V+) + 0.5
V
±10
mA
Supply voltage, (V+) – (V–)
Input voltage
Input current (all pins except power-supply pins)
Output short-circuit (2)
Continuous
Operating ambient temperature
–40
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
125
°C
200
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
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7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VS
Supply voltage, (V+) – (V–)
TA
Operating ambient temperature
MIN
MAX
3 (±1.5)
36 (±18)
UNIT
V
–40
125
°C
7.4 Thermal Information
OPA1662-Q1
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
225.4
°C/W
RθJA
Junction-to-ambient thermal resistance
156.3
RθJC(top)
Junction-to-case (top) thermal resistance
85.5
78.8
°C/W
RθJB
Junction-to-board thermal resistance
64.9
110.5
°C/W
ψJT
Junction-to-top characterization parameter
33.8
14.6
°C/W
ψJB
Junction-to-board characterization parameter
64.3
108.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics: VS = ±15 V
TA = 25°C, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
THD+N
IMD
Total harmonic distortion + noise
Intermodulation distortion
0.00006%
G = 1, f = 1 kHz, VO = 3 VRMS
G = 1, VO = 3 VRMS
–124
SMPTE two-tone, 4:1 (60 Hz
and 7 kHz)
0.00004%
DIM 30 (3-kHz square wave
and 15-kHz sine wave)
0.00004%
CCIF twin-tone (19 kHz and
20 kHz)
0.00004%
–128
–128
–128
dB
dB
dB
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
G=1
22
SR
Slew rate
G = –1
17
MHz
V/µs
Full power bandwidth (1)
VO = 1 VP
2.7
MHz
Overload recovery time
G = –10
Channel separation (dual and quad)
f = 1 kHz
Input voltage noise
f = 20 Hz to 20 kHz
2.8
µVPP
f = 1 kHz
3.3
nV/√Hz
f = 100 Hz
5
nV/√Hz
f = 1 kHz
1
pA/√Hz
f = 100 Hz
2
pA/√Hz
1
µs
–120
dB
NOISE
en
Input voltage noise density
In
(1)
4
Input current noise density
Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
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SLOS805C – JULY 2012 – REVISED AUGUST 2016
Electrical Characteristics: VS = ±15 V (continued)
TA = 25°C, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
VS = ±1.5 V to ±18 V
±0.5
±1.5
VS = ±1.5 V to ±18 V, TA = –40°C to 85° (2)
2
8
µV/°C
mV
VS = ±1.5 V to ±18 V
1
3
µV/V
INPUT BIAS CURRENT
IB
Input bias current
VCM = 0 V
600
1200
nA
IOS
Input offset current
VCM = 0 V
±25
±100
nA
INPUT VOLTAGE
VCM
Common-mode voltage
CMRR
Common-mode rejection ratio
(V–) + 0.5
106
(V+) – 1
V
114
dB
170
kΩ
INPUT IMPEDANCE
Differential resistance
Differential capacitance
2
pF
Common-mode resistance
600
kΩ
Common-mode capacitance
2.5
pF
114
dB
OPEN-LOOP GAIN
Open-loop voltage gain
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V, RL = 2 kΩ
VOUT
Output voltage
RL = 2 kΩ
IOUT
Output current
See Typical Characteristics
ZO
Open-loop output impedance
See Typical Characteristics
ISC
Short-circuit current (3)
±50
mA
CLOAD
Capacitive load drive
200
pF
AOL
106
OUTPUT
(V–) + 0.6
(V+) – 0.6
V
mA
Ω
POWER SUPPLY
VS
Specified voltage
Quiescent current
(per channel)
IQ
±1.5
IOUT = 0 A
1.5
IOUT = 0 A, TA = –40°C to 85° (2)
±18
V
1.8
mA
2
mA
85
°C
TEMPERATURE
Specified temperature
(2)
(3)
–40
Specified by design and characterization.
One channel at a time.
7.6 Electrical Characteristics: VS = 5 V
TA = 25°C, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETERTEST
CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
THD+N
IMD
Total harmonic distortion + noise
Intermodulation distortion
G = 1, f = 1 kHz, VO = 3 VRMS
G = 1, VO = 3 VRMS
0.0001%
–120
SMPTE two-tone, 4:1 (60 Hz
and 7 kHz)
0.00004%
DIM 30 (3-kHz square wave
and 15-kHz sine wave)
0.00004%
CCIF twin-tone (19 kHz and
20 kHz)
0.00004%
–128
–128
–128
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dB
dB
dB
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Electrical Characteristics: VS = 5 V (continued)
TA = 25°C, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETERTEST
CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
G=1
20
SR
Slew rate
G = –1
13
MHz
V/µs
Full power bandwidth (1)
VO = 1 VP
2
MHz
Overload recovery time
G = –10
Channel separation (dual and quad)
f = 1 kHz
Input voltage noise
f = 20 Hz to 20 kHz
3.3
µVPP
f = 1 kHz
1
µs
–120
dB
NOISE
en
Input voltage noise density
In
Input current noise density
3.3
nV/√Hz
f = 100 Hz
5
nV/√Hz
f = 1 kHz
1
pA/√Hz
f = 100 Hz
2
pA/√Hz
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
VS = ±1.5 V to ±18 V
±0.5
±1.5
VS = ±1.5 V to ±18 V, TA = –40°C to 85° (2)
2
8
µV/°C
mV
VS = ±1.5 V to ±18 V
1
3
µV/V
INPUT BIAS CURRENT
IB
Input bias current
VCM = 0 V
600
1200
nA
IOS
Input offset current
VCM = 0 V
±25
±100
nA
INPUT VOLTAGE
VCM
Common-mode voltage
CMRR
Common-mode rejection ratio
(V–) + 0.5
86
(V+) – 1
V
100
dB
170
kΩ
INPUT IMPEDANCE
Differential resistance
Differential capacitance
2
pF
Common-mode resistance
600
kΩ
Common-mode capacitance
2.5
pF
100
dB
OPEN-LOOP GAIN
Open-loop voltage gain
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V, RL = 2 kΩ
VOUT
Output voltage
RL = 2 kΩ
IOUT
Output current
ZO
Open-loop output impedance
ISC
Short-circuit current (3)
±40
mA
CLOAD
Capacitive load drive
200
pF
AOL
90
OUTPUT
(V–) + 0.6
(V+) – 0.6
See \
V
mA
See Typical Characteristics
Ω
POWER SUPPLY
VS
IQ
Specified voltage
Quiescent current (per channel)
±1.5
IOUT = 0 A
1.4
IOUT = 0 A, TA = –40°C to 85° (2)
±18
V
1.7
mA
2
mA
85
°C
TEMPERATURE
Specified temperature
(1)
(2)
(3)
6
–40
Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
Specified by design and characterization.
One channel at a time.
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7.7 Typical Characteristics
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
100
100
10
1
1
0.1
1
10
100
1k
Frequency (Hz)
Voltage Noise ( 50nV/div)
10
Current Noise (pA/ Hz)
Voltage Noise (nV/ Hz)
Voltage Noise
Current Noise
0.1
100k
10k
Time (1s/div)
G001
Figure 1. Input Voltage Noise Density and Input Current
Noise Density vs Frequency
15
10k
E2o = e2n + (inRS)2 + 4KTRS
RS
Output Voltage (V)
Voltage Noise (nV/ Hz)
VS = ± 15 V
12
EO
1k
OPA166x
100
OPA165x
10
8
VS = ± 5 V
5
10
2
Resistor Noise
1
100
1k
10k
100k
VS = ± 1.5 V
0
10k
1M
Source Resistance (W)
100k
1M
Frequency (Hz)
G003
180
140
Gain = −1V/V
Gain = +1V/V
Gain = +10V/V
120
135
40
Gain (dB)
90
60
Phase (°)
20
80
0
45
20
Gain
Phase
0
−20
G004
40
CL = 100pF
100
10M
Figure 4. Maximum Output Voltage vs Frequency
Figure 3. Voltage Noise vs Source Resistance
Gain (dB)
G002
Figure 2. 0.1-Hz to 10-Hz Noise
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
−20
0
100M
1k
10k
G005
Figure 5. Gain and Phase vs Frequency
100k
1M
Frequency (Hz)
10M
100M
G006
Figure 6. Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
0.01
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V, RL = 600Ω
G = +1V/V, RL = 2kΩ
G = −1V/V, RL = 600Ω
G = −1V/V, RL = 2kΩ
0.001
THD+N (%)
THD+N (%)
0.01
0.0001
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V, RL = 600Ω
G = +1V/V, RL = 2kΩ
G = −1V/V, RL = 600Ω
G = −1V/V, RL = 2kΩ
0.001
0.0001
VOUT = 1VRMS
BW = 80kHz
VS = ± 2.5V
VOUT = 3VRMS
BW = 80kHz
0.00001
20
100
1k
Frequency (Hz)
10k
0.00001
20k
20
100
Figure 7. THD+N Ratio vs Frequency
THD+N (%)
0.0001
0.001
0.0001
VOUT = 1VRMS
BW = 500kHz
VS = ± 2.5V
20
100
1k
Frequency (Hz)
10k
0.00001
100k
20
100
1k
Frequency (Hz)
G009
Figure 9. THD+N Ratio vs Frequency
10k
G039
0.01
RS = 0 W
RS = 30 W
RS = 60 W
RS = 1 kW
+15V
RSOURCE OPA1662-Q1
-15V
RL
VOUT = 3 VRMS
BW = 500 kHz
+15V
RSOURCE OPA1662-Q1
-15V
THD+N (%)
0.001
0.0001
0.001
RL
0.0001
RS = 0 W
RS = 30 W
RS = 60 W
RS = 1 kW
VOUT = 3 VRMS
BW = 80 kHz
0.00001
100k
Figure 10. THD+N Ratio vs Frequency
0.01
THD+N (%)
G038
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V, RL = 600Ω
G = +1V/V, RL = 2kΩ
G = −1V/V, RL = 600Ω
G = −1V/V, RL = 2kΩ
VOUT = 3VRMS
BW = 500kHz
20
100
1k
Frequency (Hz)
10k
20k
0.00001
20
G008
Figure 11. THD+N Ratio vs Frequency
8
20k
0.01
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V, RL = 600Ω
G = +1V/V, RL = 2kΩ
G = −1V/V, RL = 600Ω
G = −1V/V, RL = 2kΩ
0.001
0.00001
10k
Figure 8. THD+N Ratio vs Frequency
0.01
THD+N (%)
1k
Frequency (Hz)
G007
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100
1k
Frequency (Hz)
10k
100k
G010
Figure 12. THD+N Ratio vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
0.01
0.01
f = 1 kHz
BW = 80 kHz
RS = 0 Ω
0.001
0.001
THD+N (%)
THD+N (%)
DIM 30: 3 kHz - Square Wave, 15 kHz Sine Wave
CCIF Twin Tone: 19 kHz and 20 kHz
SMPTE: Two - Tone 4:1, 60 Hz and 7 kHz
G = 10V/V, RL = 600Ω
G = 10V/V, RL = 2kΩ
G = +1V/V, RL = 600Ω
G = +1V/V, RL = 2kΩ
G = −1V/V, RL = 600Ω
G = −1V/V, RL = 2kΩ
0.0001
0.00001
1m
10m
0.0001
100m
1
Output Amplitude (Vrms)
G = +1 V/V
1E-5
0.1
10 20
10
20
D001
Figure 14. Intermodulation Distortion vs Output Amplitude
Figure 13. THD+N Ratio vs Output Amplitude
140
−80
VOUT = 3 VRMS
Gain = +1 V/V
120
CMRR, PSRR (dB)
−100
Crosstalk (dB)
1
Output Amplitude (Vrms)
G011
−120
−140
100
80
60
40
+PSRR
−PSRR
CMRR
20
−160
100
1k
10k
0
100
100k
Frequency (Hz)
1k
G013
Figure 15. Channel Separation vs Frequency
10k
100k
1M
Frequency (Hz)
100M
G014
Figure 16. CMRR and PSRR vs Frequency
(Referred to Input)
VIN
VOUT
VIN
VOUT
G = +1 V/V
CL = 10 pF
VS = ±1.5 V
Voltage (25 mV/div)
Voltage (25 mV/div)
10M
G = +1 V/V
CL = 10 pF
Time (1 ms/div)
Time (1 ms/div)
G015
Figure 17. Small-Signal Step Response
G040
Figure 18. Small-Signal Step Response
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
G = −1 V/V
CL = 10 pF
VS = ±1.5 V
VIN
VOUT
Voltage (25 mV/div)
Voltage (25 mV/div)
VIN
VOUT
G = −1 V/V
CL = 10 pF
Time (1 ms/div)
Time (1 ms/div)
G041
Figure 20. Small-Signal Step Response
VIN
VOUT
VIN
VOUT
Voltage (2.5 V/div)
Voltage (250 mV/div)
G = +1 V/V
CL = 10 pF
RF = 1 kW
Time (1 ms/div)
Time (1 ms/div)
VIN
VOUT
G = −1 V/V
CL = 10 pF
Time (1 ms/div)
VIN
VOUT
G = −1 V/V
CL = 10 pF
VS = ±1.5 V
Time (1 ms/div)
G018
Figure 23. Large-Signal Step Response
G032
Figure 22. Large-Signal Step Response
Voltage (250 mV/div)
Voltage (2.5 V/div)
G = +1 V/V
CL = 10 pF
VS = ±1.5 V
G017
Figure 21. Large-Signal Step Response
10
G016
Figure 19. Small-Signal Step Response
G035
Figure 24. Large-Signal Step Response
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
50
50
VOUT = 100 mVPP
G = +1 V/V
+15 V
45
RS
35
RL
-15 V
CL
30
RS = 0 W
RS = 25 W
RS = 50 W
25
20
RS
OPA1662-Q1
CL
35
-15 V
30
25
20
15
15
10
10
5
0
0
50
100
150
200
250
Capacitance (pF)
300
350
0
400
0
50
100
150
200
250
Capacitance (pF)
G019
300
350
400
G020
Figure 25. Small-Signal Overshoot vs Capacitive Load
Figure 26. Small-Signal Overshoot vs Capacitive Load
50
50
+15 V
RS = 0 W
RS = 25 W
RS = 50 W
45
RS
40
40
OPA1662-Q1
35
RL
-15 V
CL
Overshoot (%)
Overshoot (%)
RS = 0 W
RS = 25 W
RS = 50 W
VOUT = 100 mVPP
G = −1 V/V
5
45
RS = 0 W
RS = 25 W
RS = 50 W
30
25
VOUT = 100 mVPP
G = +1 V/V
VS = ±1.5 V
20
15
30
25
20
5
100
150
200
250
Capacitance (pF)
300
350
0
400
+15 V
OPA1662-Q1
CL
-15 V
0
50
100
150
200
250
Capacitance (pF)
G034
Figure 27. Small-Signal Overshoot vs Capacitive Load
300
350
400
G033
Figure 28. Small-Signal Overshoot vs Capacitive Load
50
50
VS = ±18 V
VS = ±1.5 V
CF
RI = 2 kW
40
VOUT = 100 mVPP
G = +1 V/V
CL = 100 pF
35
30
25
+15 V
RS
OPA1662-Q1
CL
-15 V
20
15
40
35
30
25
20
15
10
10
5
5
0
0
1
2
3
Capacitance (pF)
G = +1 V/V
VIN = 100 mVPP
45
RF = 2 kW
Percent Overshoot (%)
45
0
RF = 2 kW
RS
5
50
RI = 2 kW
15
10
0
VOUT = 100 mVPP
G = −1 V/V
VS = ±1.5 V
35
10
0
Overshoot (%)
RF = 2 kW
+15 V
40
OPA1662-Q1
Overshoot (%)
Overshoot (%)
40
RI = 2 kW
45
4
5
VS = ± 18 V
VS = ± 1.5 V
0
G021
Figure 29. Small-Signal Overshoot vs Feedback Capacitor
50
100
150
200
250
Capacitance (pF)
300
350
400
G037
Figure 30. Percent Overshoot vs Capacitive Load
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
90
4
80
3.5
3
2.5
60
AOL (µV)
Phase Margin (°)
70
50
40
30
2
1.5
1
0.5
20
0
VS = ± 18 V
VS = ± 1.5 V
10
0
RL = 10 kΩ
RL = 2 kΩ
RL = 600 Ω
0
50
100
−0.5
150
200
250
Capacitance (pF)
300
350
−1
−40
400
Figure 31. Phase Margin vs Capacitive Load
35
60
Temperature (°C)
85
110
0
−200
−400
−600
G022
0
−200
−400
−Ib
+Ib
Ios
−600
−800
−1000
−40
−15
10
35
60
Temperature (°C)
85
110
−800
−18
135
1.8
3
1.7
2.5
Supply Current (mA)
Supply Current (mA)
−10
−6
−2
2
6
10
Common−Mode Voltage (V)
14
18
G024
Figure 34. IB and IOS vs Common-Mode Voltage
1.6
1.5
1.4
1.3
2
1.5
1
0.5
−15
10
35
60
Temperature (°C)
85
110
135
0
0
G025
Figure 35. Supply Current vs Temperature
12
−14
G023
Figure 33. IB and IOS vs Temperature
1.2
−40
135
200
IOS
IBP
IBN
Ib and Ios Current (nA)
Ib and Ios Current (nA)
10
Figure 32. Open-Loop Gain vs Temperature
400
200
−15
G036
4
8
12
16
20
24
28
Supply Voltage (V)
32
36
40
G026
Figure 36. Supply Current vs Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
20
15
55
Output Volage Swing (V)
Short Circuit Current (mA)
60
50
45
40
35
10
0
−5
−10
+Isc
−Isc
30
−40
−15
−55°C
−40°C
−25°C
0°C
+25°C
+85°C
5
−15
10
35
60
Temperature (°C)
85
110
−20
135
20
25
30
G027
Figure 37. Short-Circuit Current vs Temperature
35
40
45
Output Current (mA)
50
55
60
G028
Figure 38. Output Voltage vs Output Current
VIN
VOUT
Output Voltage (5V /div)
Output Voltage (5 V/div)
VIN
VOUT
G = −10 V/V
G = −10 V/V
Time (0.5 ms/div)
Time (0.5 ms/div)
G029
Figure 39. Positive Overload Recovery
G031
Figure 40. Negative Overload Recovery
1k
Voltage (5 V/div)
Impedance (Ω)
VOUT
VIN
100
10
1
10
100
1k
10k
Frequency (Hz)
100k
1M
G030
Figure 41. Open-Loop Output Impedance vs Frequency
Time (250 ms/div)
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Figure 42. No Phase Reversal
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8 Detailed Description
8.1 Overview
The OPA1662-Q1 operational amplifier achieves a low 3.3 nV/√Hz noise density with an ultra-low distortion of
0.00006% at 1 kHz that makes the device suitable for audio application. This device has a wide supply range
with excellent PSRR, making it a suitable option for applications that are battery powered without regulation.
8.2 Functional Block Diagram
V+
IN-
IN+
Pre-Output Driver
OUT
V-
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Figure 43. OPA1662-Q1 Simplified Schematic
8.3 Feature Description
8.3.1 Operating Voltage
The OPA1662-Q1 op amp operates from ±1.5-V to ±18-V supplies while maintaining excellent performance. The
OPA1662-Q1 can operate with as little as 3 V between the supplies and up to 36 V between the supplies.
However, some applications do not require equal positive and negative output voltage swing. With the
OPA1662‑Q1 device, power-supply voltages do not need to be equal. For example, the positive supply could be
set to 25 V with the negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. In addition, key
parameters are assured over the specified temperature of TA = –40°C to 85°C. Parameters that vary significantly
with operating voltage or temperature are shown in the Typical Characteristics.
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Feature Description (continued)
8.3.2 Input Protection
The input terminals of the OPA1662-Q1 are protected from excessive differential voltage with back-to-back
diodes, as Figure 44 illustrates. In most circuit applications, the input protection circuitry has no consequence.
However, in low-gain or G = 1 circuits, fast ramping input signals can forward bias these diodes because the
output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to
create this forward bias condition, the input signal current must be limited to 10 mA or less. If the input signal
current is not inherently limited, an input series resistor (RI) or a feedback resistor (RF) can be used to limit the
signal input current. This resistor degrades the low-noise performance of the OPA1662-Q1 and is examined in
Noise Performance. Figure 44 shows an example configuration when both current-limiting input and feedback
resistors are used.
RF
-
OPA1662-Q1
RI
Input
Output
+
Figure 44. Pulsed Operation
8.3.3 Noise Performance
Figure 45 shows the total circuit noise for varying source impedances with the op amp in a unity-gain
configuration (no feedback resistor network, and therefore no additional noise contributions).
The OPA1662-Q1 (GBW = 22 MHz, G = 1) is shown with total circuit noise calculated. The op amp itself
contributes both a voltage noise component and a current noise component. The voltage noise is commonly
modeled as a time-varying component of the offset voltage. The current noise is similarly modeled as the timevarying component of the input bias current and reacts with the source resistance to create a voltage component
of noise. Therefore, the lowest noise op amp for a given application depends on the source impedance. For low
source impedance, current noise is negligible, and voltage noise generally dominates. The low voltage noise of
the OPA1662-Q1 op amp makes them a better choice for low source impedances of less than 1 kΩ.
10k
E2o = e2n + (inRS)2 + 4KTRS
Voltage Noise (nV/ Hz)
EO
1k
RS
OPA166x
100
OPA165x
10
Resistor Noise
1
100
1k
10k
100k
Source Resistance (W)
1M
G003
The equation calculates total circuit noise, where:
•
en is the voltage noise
•
in is the current noise
•
RS is the source impedance
•
k is Boltzmann’s constant = 1.38 × 10–23 J/K
•
T is the temperature in Kelvins (K)
Figure 45. Noise Performance of the OPA1662-Q1 in Unity-Gain Buffer Configuration
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Feature Description (continued)
8.3.4 Basic Noise Calculations
Design of low-noise op amp circuits requires careful consideration of a variety of possible noise contributors:
noise from the signal source, noise generated in the op amp, and noise from the feedback network resistors. The
total noise of the circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. Figure 45 plots this equation. The source impedance is usually fixed; consequently, select the op
amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 46 illustrates both inverting and noninverting op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. The current noise of the op amp
reacts with the feedback resistors to create additional noise components. The feedback resistor values can
generally be chosen to make these noise sources negligible. The equations for total noise are shown for both
configurations.
A) Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
2
O
E
R1
R2
= 1+
R1
2
R2
2
n
e +
2
2
R1
2
e1 + e2 + 1 +
R2
R1
es2
EO
RS
Where eS =
4kTRS = thermal noise of RS
e1 =
4kTR1 = thermal noise of R1
e2 =
4kTR2 = thermal noise of R2
VS
B) Noise in Inverting Gain Configuration
Noise at the output:
R2
2
2
EO
R1
= 1+
R2
R1 + RS
2
2
en +
R2
R 1 + RS
2
2
1
2
e + e2 +
R2
R 1 + RS
e s2
EO
RS
VS
Where eS =
4kTRS = thermal noise of RS
e1 =
4kTR1 = thermal noise of R1
e2 =
4kTR2 = thermal noise of R2
For the OPA1662-Q1 op amp at 1 kHz, en = 3.3 nV/√Hz.
Figure 46. Noise Calculation in Gain Configurations
8.3.5 Total Harmonic Distortion Measurements
The OPA1662-Q1 op amp has excellent distortion characteristics. THD + noise is below 0.0006% (G = 1,
VO = 3 VRMS, BW = 80 kHz) throughout the audio frequency range, 20 Hz to 20 kHz, with a 2-kΩ load (see
Figure 7 for characteristic performance).
The distortion produced by the OPA1662-Q1 op amp is below the measurement limit of many commercially
available distortion analyzers. However, a special test circuit (such as Figure 47 shows) can be used to extend
the measurement capabilities.
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Op amp distortion can be considered an internal error source that can be referred to the input. Figure 47 shows a
circuit that causes the op amp distortion to be gained up (see the table in Figure 47 for the distortion gain factor
for various signal gains). The addition of R3 to the otherwise standard noninverting amplifier configuration alters
the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged, but the feedback available for
error correction is reduced by the distortion gain factor, thus extending the resolution by the same amount. The
input signal and load applied to the op amp are the same as with conventional feedback without R3. The value of
R3 must be kept small to minimize its effect on the distortion measurements.
The validity of this technique can be verified by duplicating measurements at high gain or high frequency where
the distortion is within the measurement capability of the test equipment. Measurements for this data sheet were
made with an Audio Precision System Two distortion and noise analyzer, which greatly simplifies such repetitive
measurements. The measurement technique can, however, be performed with manual distortion measurement
instruments.
8.3.6 Capacitive Loads
The dynamic characteristics of the OPA1662-Q1 have been optimized for commonly encountered gains, loads,
and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the
phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads
must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (RS equal to
50 Ω, for example) in series with the output.
This small series resistor also prevents excess power dissipation if the output of the device becomes shorted.
Figure 25 illustrates a graph of Small-Signal Overshoot vs Capacitive Load for several values of RS. Also see
Applications Bulletin: Feedback Plots Define Op Amp AC Performance for details of analysis techniques and
application circuits.
R1
R2
SIGNAL DISTORTION
GAIN
GAIN
R3
Signal Gain = 1+
OPA1662-Q1
VO = 3 VRMS
R2
R1
R2
Distortion Gain = 1+
R1 II R3
Generator
Output
R1
R2
R3
¥
1 kW
10 W
+1
101
-1
101
4.99 kW 4.99 kW 49.9 W
+10
110
549 W 4.99 kW 49.9 W
Analyzer
Input
Audio Precision
System Two(1)
with PC Controller
(1)
Load
For measurement bandwidth, see Figure 7 through Figure 12.
Figure 47. Distortion Test Circuit
8.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress
event. Figure 48 illustrates the ESD circuits contained in the OPA1662-Q1 (indicated by the dashed line area).
The ESD protection circuitry involves several current-steering diodes connected from the input and output pins
and routed back to the internal power-supply lines, where they meet at an absorption device internal to the
operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
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An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device internal to the OPA1662-Q1 triggers when a fast ESD voltage pulse is impressed across
the supply pins. Once triggered, it quickly activates, clamping the ESD pulse to a safe voltage level.
When the operational amplifier connects into a circuit such as that illustrated in Figure 48, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occurs, there is a risk that some of the internal ESD protection circuits may be biased on, and
conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption
device.
Figure 48 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, TI recommends that applications limit the input current to
10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings. In extreme but rare cases, the absorption
device triggers on while +VS and –VS are applied. If this event happens, a direct current path is established
between the +VS and –VS supplies. The power dissipation of the absorption device is quickly exceeded, and the
extreme internal heating destroys the operational amplifier.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. Again, it depends on the supply characteristic while at 0 V, or at a
level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier
supply current may be supplied by the input source through the current steering diodes. This state is not a
normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then
the current through the steering diodes can become quite high. The current level depends on the ability of the
input source to deliver current, and any resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be
added to the supply pins as shown in Figure 48.
The Zener voltage must be selected such that the diode does not turn on during normal operation. However, its
Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above the
safe operating supply voltage level.
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TVS
RF
+VS
+V
OPA1662-Q1
RI
ESD CurrentSteering Diodes
-In
RS
+In
Op-Amp
Core
Edge-Triggered ESD
Absorption Circuit
ID
VIN
Out
RL
(1)
-V
-VS
TVS
(1)
VIN = +VS + 500 mV.
Figure 48. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application (Single
Channel Shown)
8.4 Device Functional Modes
The OPA1662-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
3 V (±1.5 V). The maximum power supply voltage for the OPA1662-Q1 is 36 V (±18 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPA1662-Q1 is a unity-gain stable, precision dual op amp with very low noise. Applications with noisy or
high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate. Figure 43 shows a simplified schematic of the OPA1662-Q1 (one channel shown) while
Figure 49 shows an additional application idea.
9.2 Typical Application
820 W
R
2200 pF
+VA
(+15 V)
C
0.1 mF
330 W
IOUTL+
OPA1662-Q1
-VA
(-15 V)
0.1 mF
Audio DAC
with Differential
Current
Outputs
R3
680 W
620 W
+VA
(+15 V)
R2
R1
2700 pF
C2
0.1 mF
100 W
820 W
OPA1662-Q1
PCM1794A-Q1
C1
VO
8200 pF
2200 pF
-VA
(-15 V)
0.1 mF
0.1 mF
+VA
(+15 V)
IOUTLOPA1662-Q1
L Ch
Output
680 W
620 W
R1
R2
R3
330 W
C2
2700 pF
-VA
(-15 V)
0.1 mF
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Figure 49. Audio DAC Current to Voltage Converter and Output Filter
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Typical Application (continued)
9.2.1 Design Requirements
Table 1 lists the design parameters for this example.
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Supply voltage
±15 V to ±36 V
Differential input currents
0 mA to 30 mA
Resistors value tolerance
1%
Ceramic capacitor
XR5 or XR7 50 V
9.2.2 Detailed Design Procedure
This circuit is designed for converting differential input current into a single ended output voltage. The resistor
values are chosen to be relatively low for minimizing the total circuit noise. The filtering capacitors are chosen to
maintain adequate bandwidth from 10 Hz to 20 kHz for audio signals.
The first stage converts the audio DAC output current into a voltage with a gain calculated by Equation 1:
R
1+ RCS
where
•
•
•
R = 820 Ω
C = 2200 pF
S is Laplace variable
(1)
1
RC filters the audio DAC output ripple and cutoff frequency = 2pRC = 80 KHz
The second differential stage transfer function is calculated by Equation 2:
æ
ö
÷
R3 ç
1
ç
÷
R
R
2
3
R1 ç
C 2S + 2R 2R 3C1C 2S 2 ÷÷
ç 1+
R1/ / R 2 / / R 3
è
ø
The denominator of this transfer function
general form is calculated by Equation 3:
1+
1+
(2)
R 2R 3
C 2S + 2R 2R 3C1C 2S 2
R1/ / R 2 / / R 3
is a quadratic equation and the
S
S2
+
Qwo Qwo2
where
•
•
ωo = 2πFo is the resonance frequency
and Q is the quality factor
(3)
The gain peak depends on the quality factor in Equation 4:
Q = R1/ / R 2 / / R 3 2
C1
1
´
R 2R 3 C 2
(4)
The resonance frequency is calculated by Equation 5:
wo = 2pFo =
1
2R 2R 3C1C 2
(5)
These equations help to maintain adequate bandwidth and keep the differential gain flat so the quality factor is
from 0.7 to 1. The resonance frequency must be at least twice the desired bandwidth.
The chosen components give a quality factor of 0.89 and a resonance frequency of 53 KHz.
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The overall transfer function is shown in Equation 6:
vo
R
R3
1
=
´
´
R 2R 3
IoutL + - IoutL - 1 + RCS R1
C 2S + 2R 2R 3C1C 2S 2
1+
R1/ / R 2 / / R 3
The
DC gain =
(6)
RR 3
R1 and is 398 mV/mA.
The poles are at 53 KHz and 80 KHz.
9.2.3 Application Curves
CH1 = positive input current IOUTL+ = 1.5 V / 150 Ω
CH2 = negative input current IOUTL– = 1.5 V / 150 Ω
CH3 = output single-ended voltage
Figure 50. Output Voltage at 10 mApp and 10 Hz
CH1 = positive input current IOUTL+ = 1.5 V / 150 Ω
CH2 = negative input current IOUTL– = 1.5 V / 150 Ω
CH3 = output single-ended voltage
Figure 51. Output Voltage at 10 mApp and 20 KHz
10 Power Supply Recommendations
The OPA1662-Q1 is specified for operation from 3 V to 36 V (±1.5 V to 18 V) and at an ambient operating
temperature from –40°C to 85°C. Parameters that can exhibit significant variance with regard to operating
voltage or temperature are presented in Typical Characteristics.
11 Layout
11.1 Layout Guidelines
The OPA1662-Q1 is a unity-gain stable, precision dual op amp with very low noise. To realize the full operational
performance of the device, good high-frequency printed-circuit board (PCB) layout practices are required. Lowloss, 0.1-µF bypass capacitors must be connected between each supply pin and ground as close to the device
as possible. The bypass capacitor traces must be designed for minimum inductance.
22
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11.2 Layout Example
1
8
0.1 PF
2
7
3
6
4
5
0.1 PF
GND plan
Figure 52. Layout Recommendation
11.3 Power Dissipation
The OPA1662-Q1 op amp is capable of driving 2-kΩ loads with a power-supply voltage up to ±18 V and full
operating temperature range. Internal power dissipation increases when operating at high supply voltages.
Copper leadframe construction used in the OPA1662-Q1 op amp improves heat dissipation compared to
conventional materials. Circuit board layout can also help minimize junction temperature rise. Wide copper traces
help dissipate the heat by acting as an additional heat sink. Temperature rise can be further minimized by
soldering the devices to the circuit board rather than using a socket.
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Applications Bulletin: Feedback Plots Define Op Amp AC Performance (SBOA015)
• A High-Power High-Fidelity Headphone Amplifier for Current Output Audio DACs Reference Design
(TIDU672)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA1662AIDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
OUUI
OPA1662AIDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1662Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA1662-Q1 :
• Catalog: OPA1662
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Mar-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA1662AIDGKRQ1
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA1662AIDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Mar-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA1662AIDGKRQ1
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA1662AIDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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