TI1 CSD18510KTT Csd18510ktt 40-v n-channel nexfet power mosfet Datasheet

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CSD18510KTT
SLPS638 – NOVEMBER 2016
CSD18510KTT 40-V N-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
1
Product Summary
Ultra-Low Qg and Qgd
Low-Thermal Resistance
Avalanche Rated
Lead-Free Terminal Plating
RoHS Compliant
Halogen Free
D2PAK Plastic Package
TA = 25°C
TYPICAL VALUE
Drain-to-Source Voltage
40
V
Qg
Gate Charge Total (10 V)
132
nC
Qgd
Gate Charge Gate-to-Drain
RDS(on)
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
Secondary Side Synchronous Rectifier
Motor Control
DEVICE
QTY
CSD18510KTT
500
CSD18510KTTT
3 Description
2
This 40-V, 1.4-mΩ, D PAK (TO-263) NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
.
24
nC
VGS = 4.5 V
2.0
VGS = 10 V
1.4
mΩ
1.7
V
Device Information(1)
2 Applications
•
•
UNIT
VDS
Drain (Pin 2)
Source (Pin 3)
.
PACKAGE
SHIP
13-Inch Reel
D2PAK
Plastic Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
40
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package Limited)
200
Continuous Drain Current (Silicon Limited),
TC = 25°C
237
Continuous Drain Current (Silicon Limited),
TC = 100°C
167
IDM
Pulsed Drain Current(1)
400
A
PD
Power Dissipation
188
W
TJ,
Tstg
Operating Junction,
Storage Temperature
–55 to 175
°C
EAS
Avalanche Energy, Single Pulse
ID = 81 A, L = 0.1 mH, RG = 25 Ω
328
mJ
ID
Gate
(Pin 1)
50
MEDIA
A
(1) Max RθJC = 0.8°C/W, pulse duration ≤ 100 μs, duty cycle ≤
1%.
RDS(on) vs VGS
Gate Charge
10
TC = 25°C, I D = 100 A
TC = 125°C, I D = 100 A
7
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
8
6
5
4
3
2
1
0
ID = 100 A, VDS = 20 V
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
0
20
40
60
80
100
Qg - Gate Charge (nC)
120
140
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD18510KTT
SLPS638 – NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
6.2
6.3
6.4
6.5
1
1
1
2
3
7
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1 KTT Package Dimensions ........................................ 8
7.2 Recommended PCB Pattern..................................... 9
7.3 Recommended Stencil Opening (0.125 mm Stencil
Thickness).................................................................. 9
Device and Documentation Support.................... 7
6.1 Receiving Notification of Documentation Updates.... 7
4 Revision History
2
DATE
REVISION
NOTES
November 2016
*
Initial release.
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 32 V
1
μA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = 250 μA
V
RDS(on)
Drain-to-source on resistance
gfs
Transconductance
40
1.4
V
1.7
2.3
VGS = 4.5 V, ID = 100 A
2.0
2.6
VGS = 10 V, ID = 100 A
1.4
1.7
VDS = 4 V, ID = 100 A
330
mΩ
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
8770
11400
pF
832
1080
pF
Crss
RG
Reverse transfer capacitance
424
551
pF
Series gate resistance
0.9
1.8
Ω
Qg
Gate charge total (4.5 V)
66
85
nC
Qg
Gate charge total (10 V)
132
171
nC
Qgd
Gate charge gate-to-drain
Qgs
Gate charge gate-to-source
Qg(th)
Gate charge at Vth
Qoss
Output charge
td(on)
Turnon delay time
tr
Rise time
td(off)
Turnoff delay time
tf
Fall time
VGS = 0 V, VDS = 20 V, ƒ = 1 MHz
VDS = 20 V, ID = 100 A
VDS = 20 V, VGS = 0 V
VDS = 20 V, VGS = 10 V,
IDS = 100 A, RG = 0 Ω
24
nC
32
nC
17
nC
36
nC
10
ns
8
ns
29
ns
8
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
ISD = 100 A, VGS = 0 V
0.85
VDS= 20 V, IF = 100 A,
di/dt = 300 A/μs
70
1.0
nC
V
41
ns
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
MAX
UNIT
RθJC
Junction-to-case thermal resistance
THERMAL METRIC
MIN
TYP
0.8
°C/W
RθJA
Junction-to-ambient thermal resistance
62
°C/W
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
200
200
180
180
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
Figure 1. Transient Thermal Impedance
160
140
120
100
80
60
40
VGS = 4.5 V
VGS = 6 V
VGS = 10 V
20
160
140
120
100
80
60
40
TC = 125°C
TC = 25°C
TC = -55°C
20
0
0
0
0.05
0.1
0.15 0.2 0.25 0.3 0.35 0.4
VDS - Drain-to-Source Voltage (V)
0.45
0.5
0
0.5
D002
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage (V)
3.5
4
D003
VDS = 5 V
Figure 2. Saturation Characteristics
4
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Figure 3. Transfer Characteristics
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SLPS638 – NOVEMBER 2016
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
9
8
C - Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
10000
1000
2
1
100
0
0
20
40
60
80
100
Qg - Gate Charge (nC)
VDS = 10 V
120
0
140
4
8
D004
Figure 4. Gate Charge
40
D005
Figure 5. Capacitance
8
RDS(on) - On-State Resistance (m:)
2.1
VGS(th) - Threshold Voltage (V)
36
ID = 100 A
2.3
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
-75
12
16
20
24
28
32
VDS - Drain-to-Source Voltage (V)
TC = 25°C, I D = 100 A
TC = 125°C, I D = 100 A
7
6
5
4
3
2
1
0
-50
-25
0
25 50 75 100 125 150 175 200
TC - Case Temperature (°C)
D012
D006
0
2
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
100
2
VGS = 4.5 V
VGS = 10 V
ISD - Source-to-Drain Current (A)
Normalized On-State Resistance
2.2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
-75
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
0.0001
-50
-25
0
25 50 75 100 125 150 175 200
TC - Case Temperature (°C)
D008
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7 0.8
VSD - Source-to-Drain Voltage (V)
0.9
1
D009
ID = 100 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
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SLPS638 – NOVEMBER 2016
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1000
100
10
1
DC
10 ms
1 ms
0.1
0.1
100 µs
10 µs
1
10
VDS - Drain-to-Source Voltage (V)
100
10
TC = 25qC
TC = 125qC
1
0.01
0.1
TAV - Time in Avalanche (ms)
D010
1
D011
Single pulse, max RθJC = 0.6°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain-to-Source Current (A)
240
200
160
120
80
40
0
-50
-25
0
25
50
75 100 125
TC - Case Temperature (°C)
150
175
200
D012
Max RθJC = 0.6°C/W
Figure 12. Maximum Drain Current vs Temperature
6
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SLPS638 – NOVEMBER 2016
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD18510KTT
SLPS638 – NOVEMBER 2016
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 KTT Package Dimensions
15.5
14.7
9.25
9.05
A
B
3
10.26
10.06
2X 5.08
2
1
2[.0]X 1.36
1.23
2[.0]X 0.9
0.77
1.75 MAX
0.25
C A
B
1.4
1.17
0.47
0.34
C
4.7
4.4
8
0
0.25
0
1.32
1.22
2.6
2
0.25
GAGE PLANE
7.48
7.08
8°
0°
8.55
8.15
0.25
GAGE PLANE
NOTE 3
2.6
2
OPTIONAL LEAD FORM
EXPOSED
THERMAL PAD
Notes:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Features may not exist and shape may vary per different assembly sites.
Table 1. Pin Configuration
POSITION
8
DESIGNATION
Pin 1
Gate
Pin 2 / Tab
Drain
Pin 3
Source
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7.2 Recommended PCB Pattern
PKG
(3.4)
(6.9)
(R0.05) TYP
PKG
SYMM
(5.08)
(8.55)
2X (1.05)
2X (3.82)
(7.48)
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
7.3 Recommended Stencil Opening (0.125 mm Stencil Thickness)
(1.17) TYP
42X (0.97)
(0.48) TYP
2X (3.82)
2X (1.05)
42X (0.95)
(R0.05) TYP
(1.15) TYP
SYMM
(5.08)
(6.9)
PKG
Notes:
1. This package is designed to be soldered to a thermal pad on the board. See PowerPAD™ Thermally
Enhanced Package (SLMA002) and PowerPAD™
Made Easy (SLMA004) for more information.
2. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
3. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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16-Dec-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD18510KTT
ACTIVE
DDPAK/
TO-263
KTT
3
500
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
-55 to 175
CSD18510KTT
CSD18510KTTT
ACTIVE
DDPAK/
TO-263
KTT
3
50
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
-55 to 175
CSD18510KTT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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16-Dec-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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