LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
LM25088/LM25088Q Wide Input Range Non-Synchronous Buck Controller
Check for Samples: LM25088
FEATURES
DESCRIPTION
•
The LM25088 high voltage non-synchronous buck
controller features all the necessary functions to
implement an efficient high voltage buck converter
using a minimum number of external components.
The LM25088 can be configured to operate over an
ultra-wide input voltage range of 4.5V to 42V. This
easy to use controller includes a level shifted gate
driver capable of controlling an external N-channel
buck switch. The control method is based upon peak
current mode control utilizing an emulated current
ramp. The use of an emulated control ramp reduces
noise sensitivity of the pulse-width modulation circuit,
allowing reliable control of very small duty cycles
necessary in high input voltage/low output voltage
applications. The LM25088 switching frequency is
programmable from 50 kHz to 1 MHz.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LM25088Q is an Automotive Grade Product
that is AEC-Q100 Grade 1 Qualified (-40°C to
+125°C Operating Junction Temperature)
Emulated Current Mode Control
Drives External High-Side N-Channel MOSFET
Ultra-Wide Input Voltage Range from 4.5V to
42V
Low IQ Shutdown and Standby Modes
High Duty Cycle Ratio Feature for Reduced
Dropout Voltage
Spread Spectrum EMI Reduction (LM25088-1)
Hiccup Timer for Overload Protection
(LM25088-2)
Adjustable Output Voltage from 1.205V with
1.5% Feedback Reference Accuracy
Wide Bandwidth Error Amplifier
Single Resistor Oscillator Frequency Setting
Oscillator Synchronization Capability
Programmable Soft-Start
High Voltage, Low Dropout Bias Regulator
Thermal Shutdown Protection
The LM25088 is available in two versions: The
LM25088-1 provides a +/-5% frequency dithering
function to reduce the conducted and radiated EMI,
while the LM25088-2 provides a versatile restart timer
for overload protection. Additional features include a
low dropout bias regulator, tri-level enable input to
control shutdown and standby modes, soft-start and
oscillator synchronization capability. The device is
available in a thermally enhanced HTSSOP-16 pin
package.
PACKAGE
•
HTSSOP-16
Simplified Application Schematic
VIN (4.5V-42V)
RUV2
VIN
EN
BOOT
CBOOT
Q
CIN
RUV1
HG
L
VOUT
SW
DITH/RES
CDITHER/RESTART
LM25088
VCC
RFB2
D
COUT1
CS
COUT2
RFB1
Rs
RRAMP
CVCC
CRAMP
CSS
RAMP
CSG
SS
OUT
RT/SYNC
FB
RRT
RCOMP
GND
CCOMP
COMP
CHF
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
Connection Diagram
VIN
VCC
VIN
VCC
EN
BOOT
EN
BOOT
SS
HG
SS
HG
RAMP
RAMP
SW
HTSSOP-16
SW
HTSSOP-16
CS
RT
GND
CS
RT
GND
CSG
EP
CSG
EP
COMP
DITH
COMP
RES
FB
OUT
FB
OUT
Figure 1. Top View (Dither version)
LM25088-1
Figure 2. Top View (Restart version)
LM25088-2
PIN DESCRIPTIONS
2
Pin(S)
Name
Description
1
VIN
Input supply voltage
Application Information
2
EN
Enable input
3
SS
Soft-start
When SS is below the internal 1.2V reference, the SS voltage will control the
error amplifier. An internal 11 µA current source charges an external capacitor to
set the start-up rate of the controller. The SS pin is held low in the standby, VCC
UV and thermal shutdown states. The SS pin can be used for voltage tracking by
connecting this pin to a master voltage supply less than 1.2V. The applied voltage
will act as the reference for the error amplifier.
4
RAMP
Ramp control signal
An external capacitor connected between this pin and the GND pin sets the ramp
slope used for emulated current mode control. Recommended capacitor range
100 pF to 2000 pF. See the Applications Information section for selection of
capacitor value.
5
RT/SYNC
IC supply voltage. The operating range is 4.5V to 42V.
If the EN pin voltage is below 0.4V the regulator will be in a low power state. If
the EN pin voltage is between 0.4V and 1.2V the controller will be in standby
mode. If the EN pin voltage is above 1.2V the controller will be operational. An
external voltage divider can be used to set a line under voltage shutdown
threshold. If the EN pin is left open, a 5µA pull-up current forces the pin to the
high state and enables the controller.
Internal oscillator frequency The internal oscillator is programmed with a single resistor between this pin and
set input and synchronization the GND pin. The recommended frequency range is 50 kHz to 1 MHz. An
input
external synchronization signal, which is higher in frequency than the
programmed frequency, can be applied to this pin through a small coupling
capacitor. The RT resistor to ground is required even when using external
synchronization.
6
GND
Ground
7
COMP
Output of the internal error
amplifier
Ground return.
The loop compensation network should be connected between this pin and the
FB pin.
8
FB
Feedback signal from the
regulated output
This pin is connected to the inverting input of the internal error amplifier. The
regulation threshold is 1.205V.
9
OUT
Output voltage connection
Connect directly to the regulated output voltage.
10
DITH
Frequency Dithering (
LM25088-1 Only)
A capacitor connected between DITH pin and GND is charged and discharged by
27 µA current sources. As the voltage on the DITH pin ramps up and down, the
oscillator frequency is modulated between -5% to +5% of the nominal frequency
set by the RT resistor. Grounding the DITH pin will disable the frequency
dithering mode.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
PIN DESCRIPTIONS (continued)
Pin(S)
Name
Description
10
RES
Hiccup Mode Restart (
LM25088-2 Only)
Application Information
The RES pin is normally connected to an external capacitor that sets the timing
for hiccup mode current limiting. In normal operation, a 25 µA current source
discharges the RES pin capacitor to ground. If cycle-by-cycle current limit
threshold is exceeded during any PWM cycle, the current sink is disabled and
RES capacitor is charged by an internal 50 µA current. If the RES voltage
reaches 1.2V, the HG pin gate drive signal will be disabled and the RES pin
capacitor will be discharged by a 1 µA current sink. Normal operation will resume
when the RES pin falls below 0.2V.
11
CSG
Current Sense Ground
Low side reference for the current sense resistor.
12
CS
Current sense
Current measurement connection for the re-circulating diode. An external sense
resistor and an internal sample/hold circuit sense the diode current at the
conclusion of the buck switch off-time. This current measurement provides the
DC offset level for the emulated current ramp.
13
SW
Switching node
Connect to the source terminal of the external MOSFET switch.
14
HG
High Gate
15
BOOT
Input for bootstrap capacitor
An external capacitor is required between the BOOT and the SW pins to provide
bias to the MOSFET gate driver. The capacitor is charged from VCC via an
internal diode during the off-time of the buck switch.
16
VCC
Output of the bias regulator
VCC tracks VIN up to the regulation level (7.8V Typ). A 0.1 µF to 10 µF ceramic
decoupling capacitor is required. An external voltage between 8.3V and 13V can
be applied to this pin to reduce internal power dissipation.
Connect to the gate terminal of the external MOSFET switch.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
VIN, VOUT to GND
45V
BOOT to GND
60V
SW to GND
-2V to 45V
VCC to GND
-0.3V to 16V
HG to SW
-0.3V to BOOT+0.3V
EN to GND
14V
BOOT to SW
-0.3V to 16V
CS, CSG to GND
-0.3V to 0.3V
All other inputs to GND
ESD Rating
-0.3V to 7V
Human Body Model (4)
Junction Temperature
(1)
(2)
(3)
(4)
2 kV
−65°C to + 150°C
Storage Temperature Range
+ 150°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
For detailed information on soldering plastic VSSOP packages refer to the Packaging Data Book (SNOA549) available from TI.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Operating Ratings (1)
VIN Voltage
4.5V to 42V
VCC Voltage (externally supplied)
8.3V to 13V
−40°C to + 125°C
Operation Junction Temperature
(1)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
3
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VVIN =
24V, VVCC= 8V, VEN = 5V RRT = 31.6 kΩ, No load on HG. See note (1).
Symbol
Typ (1)
Max
Units
VFB = 1.3V
3.2
4.5
mA
VEN = 1V
2.5
3.0
mA
VEN = 0V
14
24
µA
7.8
8.2
V
Parameter
Conditions
VIN Operating Current
VIN Standby Current
VIN Shutdown Current
Min
VIN SUPPLY
IBIAS
ISTANDBY
ISHUTDOWN
VCC REGULATOR
VVCC(Reg)
VCC Regulation
VVCC = open
7.4
VVCC(Reg)
VCC Regulation
VVIN = 4.5V,VVCC=open
4.3
VCC Sourcing Current Limit
VVCC = 0
25
VCC Under-Voltage Lockout Threshold
Positive going VVCC
3.7
VVCC(UV)
VCC Under-Voltage Hysteresis
4.5
30
4
V
mA
4.2
200
V
mV
ENABLE THRESHOLDS
EN Shutdown Threshold
VEN Rising
EN Shutdown Hysteresis
VEN Falling
EN Standby Threshold
VEN Rising
EN Standby Hysteresis
VEN Falling
EN Pull-up Current Source
VEN = 0V
SS Pull-up Current Source
VSS = 0V
FB to SS Offset
VFB = 1.3V
320
400
480
100
1.1
1.2
mV
mV
1.3
V
120
mV
5
µA
SOFT- START
8
11
13
150
µA
mV
ERROR AMPLIFIER
VREF
FB Reference Voltage
Measured at FB Pin
FB = COMP
FB Input Bias Current
VFB = 1.2V
COMP Sink/Source Current
1.187
1.205
1.223
V
18
100
nA
3
mA
AOL
DC Gain
60
dB
FBW
Unity gain bandwidth
3
MHz
PWM COMPARATORS
THG(OFF)
Forced HG Off-time
TON(MIN)
Minimum HG On-time
185
VVIN = 36V
COMP to PWM comparator offset
280
365
ns
55
ns
930
mV
OSCILLATOR (RT Pin)
LM25088-2 (Non-Dithering)
Fnom1
Nominal Oscillator Frequency
Fnom2
RRT =31.6 kΩ
180
200
220
kHz
RRT = 11.3 kΩ
430
500
565
kHz
LM25088-1 (Dithering)
Fmin
Dithering Range
Fmax
Minimum Dither Frequency
Fnom-5%
kHz
Maximum Dither Frequency
Fnom+5%
kHz
SYNC
SYNC positive threshold
2.3
SYNC Pulse Width
15
V
150
ns
136
mV
CURRENT LIMIT
VCS(TH)
(1)
4
Cycle by cycle sense voltage threshold
VRAMP = 0V
Cycle by Cycle Current Limit Delay
VRAMP = 2.5V
112
120
280
ns
Typical specifications represent the most likely parametric norm at 25°C operation.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VVIN =
24V, VVCC= 8V, VEN = 5V RRT = 31.6 kΩ, No load on HG. See note (1).
Symbol
Parameter
Conditions
Buck Switch VDS protection
VIN to SW
Min
Typ (1)
Max
1.5
Units
V
CURRENT LIMIT RESTART (RES Pin)
Vresup
RES Threshold Upper (rising)
Vresdown
RES Threshold Lower (falling)
VCS = 0.125
1.1
1.2
1.3
V
0.1
0.2
0.3
V
Icharge
Charge source current
VCS >= 0.125
40
50
65
µA
Idischarge
Discharge sink current
VCS < 0.125
20
27
34
µA
Irampdown
Discharge sink current -(post fault)
0.8
1.2
1.6
µA
RAMP GENERATOR
IRAMP1
RAMP Current 1 (2)
VVIN = 36V, VOUT = 10V
135
165
195
µA
IRAMP2
RAMP Current 2 (2)
VVIN = 10V, VOUT = 10V
18
25
30
µA
VOUT Bias Current
VOUT = 24V
125
µA
RAMP Output Low Voltage (2)
VVIN = 36V, VOUT = 10V
200
mV
HIGH SIDE (HG) GATE DRIVER
VOLH
HG Low-state Output Voltage
IHG = 100 mA
115
VOHH
HG High-state Output Voltage
IHG = -100 mA, VOHH = VBOOT - VHG
240
mV
HG Rise Time
Cload = 1000 pF
12
ns
HG Fall Time
Cload = 1000 pF
IOHH
Peak HG Source Current
VHG = 0V
IOLH
Peak HG Sink Current
Pre RDS(ON)
215
mV
6
ns
1.5
A
VHG = VVCC
2
A
BOOT UVLO
BOOT to SW
3
V
Pre-Charge Switch ON- resistance
IVCC = 1 mA
Pre-Charge switch ON time
72
Ω
300
ns
°C
THERMAL
TSD
(2)
Thermal Shutdown Temperature
Junction Temperature Rising
165
Thermal Shutdown Hysterisis
Junction Temperature Falling
25
°C
θJC
Thermal Resistance
Junction to Case
6
°C /W
θJA
Thermal Resistance
Junction to Ambient
40
°C /W
RAMP and COMP are output pins. As such they are not specified to have an external voltage applied.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
5
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
Typical Performance Characteristics
6
Typical Application Circuit Efficiency
VCC
vs
VIN
Figure 3.
Figure 4.
VVCC
vs
IVCC
Shutdown Current
Figure 5.
Figure 6.
Frequency
vs
RRT
Frequency
vs
VVCC
Figure 7.
Figure 8.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
Typical Performance Characteristics (continued)
VFB
vs
Temperature
Forced-Off Time
vs
Temperature
Figure 9.
Figure 10.
Soft-Start
vs
Temperature
Current-Limit
vs
Temperature
Figure 11.
Figure 12.
Frequency
vs
Temperature
150
40
120
30
90
20
60
10
30
0
0
-10
1E+04
1E+05
1E+06
PHASE (°)
GAIN (dB)
Error Amplifier Gain/Phase
50
-30
1E+07
FREQUENCY (Hz)
Figure 13.
Figure 14.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
7
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
Block Diagram
LM25088
VIN
VIN (4.5V-42V)
VIN
VCC
7.7V
Regulator
C VCC
5V
1.2V
RUV2
CIN
5 uA
STANDBY
THERMAL
SHUTDOWN
UVLO
EN
CFT
RUV1
BOOT
SHUTDOWN
UVLO DIS
CBOOT
0.4V
11 uA
SS
5V
CSS
0.9V
DRIVER
CLK
STANDBY
S
Q
R
Q
HG
C COMP
FB
MINIMUM
OFF- TIME
LOGIC
ERROR
AMP
I- LIMIT
VIN
+
COMP
DITHER
LM5088 -1 ONLY
DITHER
CLK
1.2
R COMP
FREQUENCY
DITHERING
L
VOUT
SW
PWM
1.205V
CHF
Q
LEVEL
SHIFT
D
CLK
TRACK
SAMPLE
and
HOLD
A = -10
CS
COUT
Rs
CSG
CLK
CLK
RAMP GENERATOR
GND
OSCILLATOR
Ir
HICCUP RESTART
LM5088 - 2 ONLY
R FB2
R FB1
OUT
HICCUP
RESTART
LOGIC
RES
CRES/DITH
RT
RAMP
R RT
CRAMP
SYNC
CSYNC
Figure 15. Block Diagram
DETAILED OPERATION
The LM25088 Wide Input Range Buck Controller features all the functions necessary to implement an efficient
high voltage step-down converter using a minimum number of external components. The control method is
based on peak current mode control utilizing an emulated current ramp. Peak current mode control provides
inherent line voltage feed-forward, cycle-by-cycle current limiting and ease of loop compensation. The use of an
emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing
of very small duty cycles necessary in high input voltage applications. The operating frequency is user
programmable from 50 kHz to 1 MHz. The LM25088-1 provides a ±5% frequency dithering function to reduce the
conducted and radiated EMI, while the LM25088-2 provides a versatile restart timer for overload protection.
Additional features include the low dropout bias regulator, tri-level enable input to control shutdown and standby
modes, soft-start, and voltage tracking and oscillator synchronization capability. The device is available in a
thermally enhanced HTSSOP-16 pin package.
The functional block diagram and typical application schematic of the LM25088 are shown in Figure 15. The
LM25088 is well suited for a wide range of applications where efficient step-down of high, unregulated input
voltage is required. The LM25088’s typical applications include Telecom, Industrial and Automotive.
High Voltage Low-Dropout Regulator
The LM25088 contains a high voltage, low-dropout regulator that provides the VCC bias supply for the controller
and the bootstrap MOSFET gate driver. The input pin (VIN) can be connected directly to an input voltage as high
as 42V. The output of the VCC regulator (7.8V) is internally current limited to 25 mA. Upon power up, the
regulator sources current into the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds
the upper VCC UV threshold of 4.0V and the EN pin is greater than 1.2 Volts, the output (HG) is enabled and a
soft-start sequence begins. The output is terminated if VCC falls below its lower UV threshold (3.8V) or the EN
pin falls below 1.1V. When VIN is less than VCC regulation point of 7.8V, then the internal pass device acts as a
switch. Thereby, VCC tracks VIN with a voltage drop determined by the RDS(ON) of the internal switch and
operating current of the controller. The required VCC capacitor value is dependant on system startup
characteristics with a minimum value no less than 0.1 µF.
8
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary
voltage is greater than 8.2V, the internal regulator will be disabled. The VCC regulator series pass transistor
includes a diode between VCC and VIN that should not be forward biased in normal operation.
In high voltage applications, additional care should be taken to ensure that the VIN pin does not exceed the
absolute maximum voltage rating of 45V. During line or load transients, voltage ringing on the VIN pin that
exceeds the absolute maximum ratings may damage the IC. Both careful PC board layout and the use of high
quality bypass capacitors located close to the VIN and GND pins are essential.
Line Under-Voltage Detector
The LM25088 contains a dual level under-voltage lockout (UVLO) circuit. When the EN pin is below 0.4V, the
controller is in a low current shutdown mode. When the EN pin is greater than 0.4V but less than 1.2V, the
controller is in a standby mode. In standby mode the VCC regulator is active but the output switch is disabled
and the SS pin is held low. When the EN pin exceeds 1.2V and VCC exceeds the VCC UV threshold, the SS pin
and the output switch is enabled and normal operation begins. An internal 5 µA pull-up current source at the EN
pin configures the controller to be fully operational if the EN pin is left open.
An external VIN UVLO set-point voltage divider from VIN to GND can be used to set the minimum startup input
voltage of the controller. The divider must be designed such that the voltage at the EN pin exceeds 1.2V (typ)
when VIN is in the desired operating range. The internal 5 µA pull-up current source must be included in
calculations of the external set-point divider. 100 mV of hysteresis is included for both the shutdown and standby
thresholds. The EN pin is internally connected to a 1 kΩ resistor and an 8V zener clamp. If the voltage at the EN
pin exceeds 8V, the bias current for the EN pin will increase at the rate of 1mA/V. The voltage at the EN pin
should never exceed 14V.
Oscillator and Sync Capability
The LM25088 oscillator frequency is set by a single external resistor connected between the RT pin and the
GND pin. The RT resistor should be located very close to the device. To set a desired oscillator frequency (fSW),
the necessary value of RT resistor can be calculated from the following equation:
1
- 280 ns
fSW
RRT =
152 pF
(1)
The RT pin can also be used to synchronize the internal oscillator to an external clock. The internal oscillator is
synchronized to an external clock by AC coupling a positive edge into the RT/SYNC pin. The RT/SYNC pin
voltage must exceed 3V to trip the internal clock synchronization pulse detector. The free-running frequency
should be set nominally 15% below the external clock frequency and the pulse width applied to the RT/SYNC pin
must be less than 150ns. Synchronization to an external clock more than twice the free-running frequency can
produce abnormal behavior of the pulse-width modulator.
LM25088
5.0V
VIN
5 PA
RUV2
1.2V
STANDBY
EN
1 k:
RUV1
0.4V
8V
SHUTDOWN
Figure 16. Basic Enable Configuration
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
9
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
Error Amplifier and PWM Comparator
The internal high gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision voltage reference (1.205V). The output of the error amplifier is
connected to the COMP pin allowing the user to connect loop compensation components. Generally a type II
network, as illustrated in Figure 15, is sufficient. This network creates a pole at DC, a mid-band zero for phase
boost and a high frequency pole for noise reduction. The PWM comparator compares the emulated current
signal from the RAMP generator to the error amplifier output voltage at the COMP pin. A typical control loop
gain/phase plot is shown in Typical Performance Characteristics section of this document.
Ramp Generator
The ramp signal used for the pulse width modulator in current mode control is typically derived directly from the
buck switch current. This signal corresponds to the positive slope portion of the buck inductor current. Using this
signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides
inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for
PWM control is the large leading edge spike due to circuit parasitics which must be filtered or blanked. Also, the
current measurement may introduce significant propagation delays. The filtering time, blanking time and
propagation delay limit the minimum achievable pulse width. In applications where the input voltage may be
relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles is necessary
for regulation. The LM25088 utilizes a unique ramp generator which does not actually measure the buck switch
current but rather reconstructs or emulates the signal. Emulating the inductor current provides a ramp signal that
is free of leading edge spikes and measurement or filtering delays. The current reconstruction is comprised of
two elements; a sample & hold DC level and an emulated current ramp.
RAMP
(5 PA/V x (VIN ± VOUT) + 25 PA) x
TON
CRAMP
Sample and Hold
DC Level
10 x R S V/A
TON
Figure 17. Composition of Current Sense Signal
10
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
The sample & hold DC level illustrated in Figure 17 is derived from a measurement of the re-circulating (or freewheeling) diode current. The diode current flows through the current sense resistor connected between the CS
and CSG pins. The voltage across the sense resistor is sampled and held just prior to the onset of the next
conduction interval of the buck switch. The diode current sensing and sample & hold provide the DC level for the
reconstructed current signal. The positive slope inductor current ramp is emulated by an external capacitor
connected from the RAMP pin to GND and an internal voltage controlled current source. The ramp current
source that emulates the inductor current is a function of the VIN and VOUT voltages per the following equation:
IRAMP = 5 µA/V x (VIN x VOUT) + 25 µA
(2)
Proper selection of the RAMP capacitor depends upon the selected value of the output inductor and the current
sense resistor (RS). For proper current emulation, the DC sample & hold value and the ramp amplitude must
have the same dependence on the load current. That is:
gm x L
CRAMP =
RS x A
where
•
•
gm is the ramp current generator transconductance (5 µA/V)
A is the gain of the current sense amplifier (10V/V)
(3)
The RAMP capacitor should connected directly to the RAMP and GND pins of the IC.
For duty cycles greater than 50%, peak current mode control circuits are subject to sub-harmonic oscillation.
Sub-harmonic oscillation is normally characterized by alternating wide and narrow pulses at the SW pin. Adding
a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 25 µA
offset current supplied by the emulated current source provides a fixed slope to the ramp signal. In some high
output voltage, high duty cycles applications; additional slope compensation may be required. In these
applications, a pull-up resistor may be added between the RAMP and VCC pins to increase the ramp slope
compensation. A formula to configure pull-up resistor is shown in Applications Information section.
Dropout Voltage Reduction
The LM25088 features unique circuitry to reduce the dropout voltage. Dropout voltage is defined as the
difference between the minimum input voltage to maintain regulation and the output voltage (VINmin - Vout).
Dropout voltage thus determines the lowest input voltage at which the converter maintains regulation. In a buck
converter, dropout voltage primarily depends upon the maximum duty cycle. The maximum duty cycle is
dependant on the oscillator frequency and minimum off-time.
An approximation for the dropout voltage is:
TOFF(max)
Dropout_Voltage = VOUT x
TOSC - TOFF(max)
where
•
•
•
TOSC = 1/fSW
TOFF (max) is the forced off-time (280 ns typical, 365 ns maximum)
fSW and TOSC are the oscillator frequency and oscillator period, respectively
(4)
From the above equation, it can be seen that for a given output voltage, reducing the dropout voltage requires
either reducing the forced off-time or oscillator frequency (1/TOSC). The forced off-time is limited by the time
required to replenish the bootstrap capacitor and time required to sample the re-circulating diode current. The
365 ns forced off-time of the LM25088 controller is a good trade-off between these two requirements. Thus the
LM25088 reduces dropout voltage by dynamically decreasing the operating frequency during dropout. The
Dynamic Frequency Control (DFC) is achieved using a dropout monitor, which detects a dropout condition and
reduces the operating frequency. The operating frequency will continue to decrease with decreasing input
voltage until the frequency falls to the minimum value set by the DFC circuitry.
fSW(minDFC) ≊ 1/3 x fSW(nominal)
(5)
If the VIN voltage continues to fall below this point, output regulation can no longer be maintained. The oscillator
frequency will revert back to the nominal operating frequency set by the RT resistor when the input voltage
increases above the dropout range. DFC circuitry does not affect the PWM during normal operating conditions.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
11
LM25088
www.ti.com
VIN
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
VOUT
Dropout
CLK
Regulation
Point
Forced
off-time
ON-TIME
Forced
off-time
TON(max)
Extended
TON(max)
TON(maxDFC)
increased to
reduce dropout
fSW(minDFC)
Normal Operation
Transition Region
Low Dropout Mode
Figure 18. Dropout Voltage Reduction using Dynamic Frequency Control
Frequency Dithering (LM25088-1 Only)
Electro-Magnetic Interference (EMI) emissions are fundamentally associated with switch-mode power supplies
due to sharp voltage transitions, diode reverse recovery currents and the ringing of parasitic L-C circuits. These
emissions will conduct back to the power source or radiate into the environment and potentially interfering with
nearby electronic systems. System designers typically use a combination of shielding, filtering and layout
techniques to reduce the EMI emissions sufficiently to satisfy EMI emission standards established by regulatory
bodies. In a typical fixed frequency switching converter, narrowband emissions typically peak at the switching
frequency with the successive harmonics having less energy. Dithering the oscillator frequency spreads the EMI
energy over a range of frequencies, thus reducing the peak levels. Dithering can also reduce the system cost by
reducing the size and quantity of EMI filtering components.
The LM25088-1 provides an optional frequency dithering function which is enabled by connecting a capacitor
from the dither pin (DITH) to GND. Connecting the DITH pin directly to GND disables frequency dithering causing
the oscillator to operate at the frequency established by the RT resistor. As shown in Figure 19, the Cdither
capacitor is used to generate a triangular wave centered at 1.2V. This triangular waveform is used to manipulate
the oscillator circuit such that the oscillator frequency modulates from -5% to +5% of the nominal operating
frequency set by the RT resistor. The Cdither capacitor value sets the rate of the low frequency modulation i.e., a
lower value Cdither capacitor will modulate the oscillator frequency from -5% to +5% at a faster rate than a higher
value capacitor. For the dither circuit to work effectively the modulation rate must be much less than the oscillator
frequency (fSW) , Cdither should be selected such that;
100 x 25 PA
Cdither t
fSW x 0.12V
(6)
12
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
+5V
LM25088
25 PA
1.14V
1.26V
+
-
1.20V
1.14V
R
Q
S
Q
DITHER
C dither
50 PA
1. 26V
+
-
Oscillator
Tosc - 't
Tosc
Tosc +'t
Figure 19. Frequency Dithering Scheme
Figure 20. Conducted Emissions Measured at the Input of a LM25088 Based Buck Converter
Figure 20 shows the conducted emissions on the LM25088 evaluation board input power line. It can be seen
from the above picture that, the peak emissions with non-dithering operation are centered narrowly at the
operating frequency of the converter. With dithering operation, the conducted emissions are spread around the
operating frequency and the maximum amplitude is reduced by approximately 10dB. (Figure 20 was captured
using a Chroma DC power supply model number 62006P and an Agilent network analyzer model number
4395A).
Cycle-by-Cycle Current Limit
The LM25088 contains a current limit feature that protects the circuit from extended over current conditions. The
emulated current signal is directly proportional to the buck switch current and is applied to the current limit
comparator. If the emulated current exceeds 1.2V, the PWM cycle is terminated. The peak inductor current
required to trigger the current limit comparator is given by:
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
13
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
1.2V - 25 PA x
IPEAK =
www.ti.com
VOUT
VIN x fSW x CRAMP
A x RS
or
IPEAK #
0.12V
RS
where
•
•
•
A = 10V/V is the current sense amplifier gain
CRAMP is the Ramp capacitor
RS is the sense resistor
25 PA x
•
•
VOUT
VIN x fSW x CRAMP
is the voltage ramp added for slope compensation
1.2V is the reference of the current limit comparator
(7)
Since the current that charges the RAMP capacitor is proportional to VIN-VOUT, if the output is suddenly
shorted, the VOUT term is zero and the RAMP charging current increases. The increased RAMP charging
current will immediately reduce the PWM duty cycle.The LM25088 also includes a buck switch protection
scheme. A dedicated comparator monitors the drain to source voltage of the buck FET when it is turned ON, if
the VDS exceeds 1.5V, the comparator turns of the buck FET immediately. This feature will help protect the buck
FET in catastrophic conditions such as a sudden saturation of the inductor.
Overload Protection Timer (LM25088-2 Only)
To further protect the external circuitry during a prolonged over current condition, the LM25088-2 provides a
current limit timer to disable the switching regulator and provide a delay before restarting (hiccup mode). The
number of current limit events required to trigger the restart mode is programmed by an external capacitor at the
RES pin. During each PWM cycle, as shown in Figure 22, the LM25088 either sinks current from or sources
current into the RES capacitor. If the emulated current ramp exceeds the 1.2V current limit threshold, the present
PWM cycle is terminated and the LM25088 sources 50 µA into the RES pin capacitor during the next PWM clock
cycle. If a current limit event is not detected in a given PWM cycle, the LM25088 disables the 50 µA source
current and sinks 27 µA from the RES pin capacitor during the next cycle. In an overload condition, the LM25088
protects the converter with cycle-by-cycle current limiting until the voltage at RES pin reaches 1.2V. When RES
reaches 1.2V, a hiccup mode sequence is initiated as follows:
• The SS capacitor is fully discharged.
• The RES capacitor is discharged with 1.2 µA
• Once the RES capacitor reaches 0.2V, a normal soft-start sequence begins. This provides a time delay
before restart.
• If the overload condition persists after restart, the cycle repeats.
• If the overload condition no longer exists after restart, the RES pin is held at ground by the 27 µA discharge
current source and normal operation resumes.
The overload protection timer is very versatile and can be configured for the following modes of protection:
1. 1. Cycle-by-Cycle only: The hiccup mode can be completely disabled by connecting the RES pin to GND.
In this configuration, the cycle-by-cycle protection will limit the output current indefinitely and no hiccup
sequence will occur.
2. 2. Delayed Hiccup: Connecting a capacitor to the RES pin provides a programmed number of cycle-bycycle current limit events before initiating a hiccup mode restart, as previously described. The advantage of
this configuration is that a short term overload will not cause a hiccup mode restart but during extended
overload conditions, the average dissipation of the power converter will be very low.
3. 3. Externally Controlled Hiccup: The RES pin can also be used as an input. By externally driving the pin to
a level greater than the 1.2V hiccup threshold, the controller will be forced into the delayed restart sequence.
For example, the external trigger for a delayed restart sequence could come from an over-temperature
protection or an output over-voltage sensor.
14
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
LM25088
5.0V
Current
limit cycle
I- Limit
50 PA
Hiccup
current
source
logic
RES
C RES
Post-fault
Discharge
current
27 PA
1.2 PA
Non - current
limit cycle
Q
S
SS begins
Restart
Q
R
1.2V
+
-
HG OFF
SS = 0
+
CLK
0.2V
Figure 21. Current Limit Restart Circuit
Current Limit Persistent
Charge Restart cap
with 50 PA current
1.2V
Discharge Restart
cap with 1.2 PA
Current Limit Detected
at CS
0.2V
RES
0V
FB+120 mV
SS
11 PA
HG
t1
t2
Figure 22. Current Limit Restart Timing Diagram
Soft-Start
The soft-start (SS) feature forces the output to rise linearly until it reaches the steady-state operating voltage set
by the feedback resistors. The LM25088 will regulate the FB pin to the SS pin voltage or the internal 1.205V
reference, which ever is lower. At the beginning of the soft-start sequence VSS = 0V and, an internal 11 µA
current source gradually increases the voltage of the external soft-start capacitor (CSS). An internal amplifier
clamps the SS pin voltage at 120 mV above the FB voltage. This feature provides soft-start controlled recovery
with reduced output overshoot in the event that the output voltage momentarily dips out of regulation.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
15
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
HG Output
The LM25088 provides a high current, high-side driver and associated level shift circuit to drive an external NChannel MOSFET. The gate driver works in conjunction with an internal diode and external bootstrap capacitor.
A ceramic bootstrap capacitor is recommended, and should be connected directly between the BOOT and SW
pins. During the off-time of the buck switch, the bootstrap capacitor charges from VCC through an internal diode.
When operating with a high PWM duty cycle, the HG output will be forced-off each cycle for 365 ns (max) to
ensure that BOOT capacitor is recharged. A “pre-charge” circuit, comprised of a MOSFET between SW and
GND, is turned ON during the forced off-time to help replenish the BOOT capacitor. The pre-charge circuit
provides charge to the BOOT capacitor under light load or pre-biased load conditions when the SW voltage does
not remain low during the entire off-time.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum
operating temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power
reset state, disabling the output driver and the bias supply of the controller. The feature prevents catastrophic
failures from accidental device over-heating.
Applications Information
EXTERNAL COMPONENTS
The procedure for calculating the external components is illustrated with the following design example. The Bill of
Materials for this design is listed in Table 1.The circuit shown in Figure 28 and Figure 29 is configured for the
following specifications:
• Output Voltage = 5V
• Input Voltage = 5.5V to 36V
• Maximum Load Current = 7A
• Switching Frequency = 250 kHz
TIMING RESISTOR
The RT resistor sets the oscillator switching frequency. Higher frequencies result in smaller size components
such as the inductor and filter capacitors. However, operating at higher frequencies also results in higher
MOSFET and diode switching losses. Operation at 250 kHz was selected for this example as a reasonable
compromise between size and efficiency.
The value of RT resistor can be calculated as follows:
1
- 280 ns
250 kHz
= 24.5 k:
RRT =
152 pF
(8)
The nearest standard value of 24.9Ω was chosen for RT.
OUTPUT INDUCTOR
The inductor value is determined based on the operating frequency, load current, ripple current and the input and
output voltages.
Knowing the switching frequency (fSW), maximum ripple current (IPP), maximum input voltage (VIN(max)) and the
nominal output voltage (VOUT), the inductor value can be calculated as follows:
L=
16
VOUT
VOUT
x 1IPP x fSW
VIN(max)
(9)
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
I PP
IO
0
T = 1/FSW
Figure 23. Inductor Current
The maximum ripple current occurs at the maximum input voltage. Typically, IPP is selected between 20% and
40% of the full load current. Higher ripple current will result in a smaller inductor. However, it places more burden
on the output capacitor to smooth out the ripple current to achieve low output ripple voltage. For this example
40% ripple was chosen for a smaller sized inductor.
5V
x 1 - 5V = 6.2 PH
L=
0.4 x 7A x 250 kHz
36V
(10)
The nearest standard value of 6.8 µH will be used. To prevent saturation, the inductor must be rated for the peak
current. During normal operation, the peak current occurs at maximum load current (plus maximum ripple). With
properly scaled component values, the peak current is limited to VCS(TH)/RS During overload conditions. At the
maximum input voltage with a shorted output, the chosen inductor must be evaluated at elevated temperature. It
should be noted that the saturation current rating of inductors drops significantly at elevated temperatures.
CURRENT SENSE RESISTOR
The current limit value (ILIM) is set by the current sense resistor (RS).
RS can be calculated by
VCS /A
RS =
(1 + margin) x (IOUT + 0.5 x IPP) +
=
VOUT
L x fSW
0.12
5V
(1 + 0.1) x (7A + 0.5 x 2.8) +
6.8 PH x 250 kHz
# 10 m:
(11)
Some ‘margin’ beyond the maximum load current is recommended for the current limit threshold. In this design
example, the current limit is set at 10% above the maximum load current, resulting in a RS value of 10 mΩ. The
CS and CSG pins should be Kelvin connected to the current sense resistor.
RAMP CAPACITOR
With the inductor and sense resistor value selected, the value of the ramp capacitor (CRAMP) necessary for the
emulation ramp circuit is given by:
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
17
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
CRAMP =
www.ti.com
gm x L
A x RS
where
•
•
•
L is the value of the output inductor
gm is the ramp generator transconductance (5 µA/V)
A is the current sense amplifier gain (10V/V)
(12)
For the current design example, the ramp capacitor is calculated as:
5 PA/V x 6.8 PH
= 340 pF
CRAMP =
10V/V x 10 m:
(13)
The next lowest standard value 270 pF was selected for CRAMP. An NPO capacitor with 5% or better tolerance is
recommended. It should be noted that selecting a capacitor value lower than the calculated value will increase
the slope compensation. Furthermore, selecting a ramp capacitor substantially lower or higher than the
calculated value will also result in incorrect PWM operation.
For VOUT > 5V, internal slope compensation provided by the LM25088 may not be adequate for certain
operating conditions especially at low input voltages. A pull-up resistor may be added from VCC to RAMP the pin
to increase the slope compensation. Optimal slope compensation current may be calculated from
IOS = VOUT x 5 µA/V
(14)
and RRAMP is given by
VVCC - VRAMP
RRAMP =
IOS - 25 PA
(15)
VCC
R RAMP
RAMP
C RAMP
Figure 24. Additional Slope Compensation for VOUT > 5V
OUTPUT CAPACITORS
The output capacitors smooth the inductor current ripple and provide a source of charge for load transient
conditions. The output capacitor selection is primarily dictated by the following specifications:
1. Steady-state output peak-peak ripple (ΔVPK-PK)
2. Output voltage deviation during transient condition (ΔVTransient)
For the 5V output design example, ΔVPK-PK = 50 mV (1% of VOUT) and ΔTTransient = 100 mV (2% of VOUT) was
chosen. The magnitude of output ripple primarily depends on ESR of the capacitors while load transient voltage
deviation depends both on the output capacitance and ESR.
When a full load is suddenly removed from the output, the output capacitor must be large enough to prevent the
inductor energy to raise the output voltage above the specified maximum voltage. In other words, the output
capacitor must be large enough to absorb the inductor’s maximum stored energy. Equating, the stored energy
equations of both the inductor and the output capacitor it can be shown that:
L x IO +
CO =
18
'IPP
2
2
('V + VOUT)2 - VOUT2
(16)
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
Evaluating, the above equation with a ΔVout of 100 mV results in an output capacitance of 475 µF. As stated
earlier, the maximum peak to peak ripple primarily depends on the ESR of the output capacitor and the inductor
ripple current. To satisfy the ΔVPK-PK of 50 mV with 40% inductor current ripple, the ESR should be less than 15
mΩ. In this design example a 470 µF aluminum capacitor with an ESR of 10 mΩ is paralleled with two 47 µF
ceramic capacitors to further reduce the ESR.
INPUT CAPACITORS
The input power supply typically has large source impedance at the switching frequency. Good quality input
capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current
during the on-time. When the buck switch turns ON, the current into the external FET steps to the valley of the
inductor current waveform at turn-on, ramps up to the peak value, and then drops to zero at turn-off. The input
capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the
ripple current is IRMS > IOUT/2.
Quality ceramic capacitors with a low ESR should be selected for the input filter. To allow for capacitor
tolerances and voltage rating, five 2.2 µF, 100V ceramic capacitors were selected. With ceramic capacitors, the
input ripple voltage will be triangular and will peak at 50% duty cycle. Taking into account the capacitance
change with DC bias a worst case input peak-to-peak ripple voltage can be approximated as:
IOUT
7A
= 636 mV
=
'VIN =
4 x fSW x CIN 4 x 250 kHz x 11 PF
(17)
When the converter is connected to an input power source, a resonant circuit is formed by the line impedance
and the input capacitors. This can result in an overshoot at the VIN pin and could result in VIN exceeding its
absolute maximum rating. Because of those conditions, it is recommended that either an aluminum type
capacitor with an ESR or increasing CIN>10 x LIN While using aluminum type capacitor care should be taken to
not exceed its maximum ripple current rating. Tantalum capacitors must be avoided at the input as they are
prone to shorting.
VCC CAPACITOR
The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value
should be no smaller than 0.1 µF, and should be a good quality, low ESR, ceramic capacitor. A value of 1 µF
was selected for this design.
BOOTSTRAP CAPACITOR
The bootstrap capacitor between HB and SW pins supplies the gate current to charge the high-side MOSFET
gate at each cycle’s turn-on as well as supplying the recovery charge for the bootstrap diode (D1).The peak
current can be several amperes. The recommended value of the bootstrap capacitor is at least 0.022 µF and
should be a good quality, low ESR, ceramic capacitor located close to the pins of the IC. The absolute minimum
value for the bootstrap capacitor is calculated as:
CHB t
Qg
'VHB
where
•
•
Qg is the high-side MOSFET gate charge
ΔVHB is the tolerable voltage droop on CHB, which is typically less than 5% of the VCC
(18)
A value of 0.1 µF was selected for this design.
SOFT-START CAPACITOR
The capacitor at the SS capacitor determines the soft-start time, the output voltage to reach the final regulated
value. The value of CSS for a given time is determined from:
CSS =
tSS x 11 PA
1.205V
(19)
For this design example, a value of 0.022 µF was chosen for a soft start time of approximately 2 ms.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
19
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
OUTPUT VOLTAGE DIVIDER
RFB1 and RFB2 set the output voltage level, the ratio of these resistors can be calculated from:
RFB2 VOUT
-1
=
RFB1 1.205V
(20)
1.62 kΩ was chosen for RFB1 in this design which results in a RFB2 value of 5.11 kΩ. A reasonable guide is to
select the value of RFB1 value such that the current through the resistor (1.2V/ RFB1) is in between 1 mA and 100
µA.
UVLO DIVIDER
A voltage divider can be connected to the EN pin to the set the minimum startup voltage (VIN(min)) of the
regulator. If this feature is required, set the value of RUV2 between 10 kΩ and 100 kΩ and then calculate RUV1
from:
RUV2
RUV1 = 1.2V x
(VIN(min) + (5 PA x RUV2) - 1.2V)
(21)
In this design, for a VIN(min) of 5V, RUV2 was selected to be 54.9 kΩ resulting in a RUV1value of 16.2 kΩ. it is
recommended to install a capacitor parallel to RUV1 for filtering. If the EN pin is left open, the LM25088 will begin
operation once the upper VCC UV threshold of 4.0V (typ) is reached.
RESTART CAPACITOR (LM5008-2 only)
The basic operation of the hiccup mode current limit is described in the functional description. In the LM25088-2
application example the RES pin is configured for delayed hiccup mode. Please refer to the functional description
to configure this pin in alternate configurations and also refer Figure 22 for the timing diagram. The delay time to
initiate a hiccup cycle (t1) is programmed by the selection of RES pin capacitor. In the case of continuous cycleby-cycle current limit detection at the CS pin, the time required for CRES to reach the 1.2V is given by
Trestart_delay =
CRES x 1.2V
= CRES x 24k
50 PA
(22)
The cool down time (t2) is set by the time taken to discharge the RES cap with 1.2 µA current source. This
feature will reduce the input power drawn by the converter during a prolonged over current condition. In this
application 500 µs of delay time was selected. The minimum value of CRES capacitor should be no less than
0.022 µF.
MOSFET SELECTION
Selection of the Buck MOSFET is governed by the same tradeoffs as the switching frequency. Losses in power
MOSFETs can be broken down into conduction losses and switching losses. The conduction loss is given by:
PDC = D x (IO2 x RDS(ON) x 1.3)
(23)
Where, D is the duty cycle and IO is the maximum load current. The factor 1.3 accounts for the increase in
MOSFET on-resistance due to heating. Alternatively, for a more precise calculation, the factor of 1.3 can be
ignored and the on-resistance of the MOSFET can be estimated using the RDS(ON) vs. Temperature curves in the
MOSFET datasheet.
The switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition
period both current and voltage are present in the MOSFET. The switching loss can be approximated as:
PSW = 0.5 x VIN x IO x (tR + tF) x fSW
where
•
tR and tF are the rise and fall times of the MOSFET
(24)
The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed on the
scope. Another loss, which is associated with the buck MOSFET is the “gate-charging loss”. This loss differs
from the above two losses in the sense that it is dissipated in the LM25088 and not in the MOSFET itself. Gate
charging loss, PGC, results from the current driving charging the gate capacitance of the power MOSFETs and is
approximated as:
PGC = VCC x Qg x fSW
20
(25)
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
For this example with the maximum input voltage of 36V, the Vds breakdown rating of the selected MOSFET
must be greater than 36V plus any ringing across drain to source due to parasitics. In order to minimize switching
time and gate drive losses, the selected MOSFET must also have low gate charge (Qg). A good choice of
MOSFET for this design example is the SI7848DP which has a total gate charge of 30nC and rise and fall times
of 10 ns and 12 ns respectively.
DIODE SELECTION
A Schottky type re-circulating diode is required for all LM25088 applications. The near ideal reverse recovery
current transients and low forward voltage drop are particularly important diode characteristics for high input
voltage and low output voltage applications common to LM25088. The diode switching loss is minimized in a
Schottky diode because of near ideal reverse recovery. The conduction loss can be approximated by:
Pdc_diode = (1 - D) x IO x VF
where
•
VF is the forward drop of the diode
(26)
The worst case is to assume a short circuit load condition. In this case, the diode will carry the output current
almost continuously. The reverse breakdown rating should be selected for the maximum input voltage level plus
some additional safety margin to withstand ringing at the SW node. For this application a 45V On Semiconductor
Schottky diode (MBRB1545) with a specified forward drop of 0.5V at 7A at a junction temperature of 50°C was
selected. For output loads of 5A and greater and high input voltage applications, a diode in a D2PAK package is
recommended to support the worst case power dissipation
SNUBBER COMPONENTS SELECTION
Excessive ringing and spikes can cause erratic operation and couple spikes and noise to the output. Voltage
spikes beyond the rating of the LM25088 or the re-circulating diode can damage these devices. A snubber
network across the power diode reduces ringing and spikes at the switching node. Selecting the values for the
snubber is best accomplished through empirical methods. First, make sure that the lead lengths for the snubber
connections are very short. For the current levels typical for the LM25088, a resistor value between 3 and 10Ω
should be adequate. As a rule of thumb, a snubber capacitor which is 4~5 times the Schottky diode’s junction
capacitance will reduce spikes adequately. Increasing the value of the snubber capacitor will result in more
damping but also results in higher losses. The resistor’s power dissipation is independent of the resistance value
as the resistor dissipates the energy stored by the snubber capacitor. The resistor’s power dissipation can be
approximated as:
PR_SNUB = CSNUB x VINmax2 x fSW
(27)
ERROR AMPLIFIER COMPENSATION
RCOMP, CCOMP and CHF configure the error amplifier gain characteristics to accomplish a stable voltage loop gain.
One advantage of current mode control is the ability of to close the loop with only two feedback components
RCOMP and CCOMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For
this example, the modulator can be treated as an ideal voltage-to-current (transconductance) converter, The DC
modulator gain of the LM25088 can be modeled as:
DC Gain (MOD) = RLOAD/ (A x RS)
(28)
The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD) and the output
capacitance (COUT). The corner frequency of this pole is:
For, RLOAD = 5V/7A = 0.714Ω and COUT = 500 µF (effective), then FP(MOD) = 550 Hz.
DC Gain(MOD) = 0.714/ (10 x 10 mΩ) = 7.14 = 17dB
(29)
For the 5V design example the modulator gain vs. frequency characteristic was measured as shown in Figure 25.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
21
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
60
200
160
40
120
GAIN (dB)
PHASE (°)
80
20
40
0
0
-40
-20
-80
-120
-40
-160
-60
-200
1.E+01
1.E+02
1.E+03
1.E+04 1.E+05
FREQUENCY (Hz)
Figure 25. Modular Gain Phase
Components RCOMP and CCOMP configure the error amplifier as a type II compensation configuration. The DC
gain of the amplifier is 80dB which has a pole at low frequency and a zero at FZero = 1/(2π x RCOMP x CCOMP).
The error amplifier zero is set such that it cancels the modulator pole leaving a single pole response at the
crossover frequency of the voltage loop. A single pole response at the crossover frequency yields a very stable
loop with 90° of phase margin. For the design example, a target loop bandwidth (crossover frequency) of 15 kHz
was selected. The compensation network zero (FZero) should be at least an order of magnitude lower than the
target crossover frequency. This constrains the product of RCOMP and CCOMP for a desired compensation network
zero 1/ (2π x RCOMP x CCOMP) to be less than 1.5 kHz. Increasing RCOMP, while proportionally decreasing CCOMP,
decreases the error amp gain. For the design example CCOMP was selected to be 0.015 µF and RCOMP was
selected to be 18 kΩ. These values configure the compensation network zero at 0.6 kHz. The error amp gain at
frequencies greater than FZero is RCOMP /RFB2, which is approximately 3.56 (11dB).
60
200
160
40
120
GAIN (dB)
40
0
0
-40
-20
PHASE (o)
80
20
-80
-120
-40
-160
-60
1.E+02
1.E+03
1.E+04
1.E+05
-200
1.E+06
FREQUENCY (Hz)
Figure 26. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.
If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be
configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier
compensation components can be designed with the suggested guidelines. Step load transient tests can be
performed to verify performance. The step load goal is minimum overshoot with a damped response. CHF can be
added to the compensation network to decrease noise susceptibility of the error amplifier. The value of CHF must
be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer function. A good
approximation of the location of the pole added by CHF is FP2 = FZero x CCOMP/ CHF. Using CHF is recommended to
minimize coupling of any switching noise into the modulator. The value of CHF was selected as 100 pF for this
design example.
22
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
60
200
160
40
120
GAIN (dB)
40
0
0
-40
-20
PHASE (°)
80
20
-80
-120
-40
-160
-60
1.E+02
1.E+03
1.E+04
-200
1.E+05
FREQUENCY (Hz)
Figure 27. Overall Loop Gain and Phase
PCB BOARD LAYOUT AND THERMAL CONSIDERATIONS
In a buck regulator there are two loops where currents are switched very fast. The first loop starts from the input
capacitors, through the buck MOSFET, to the inductor then out to the load. The second loop starts from the
output capacitor ground, to the regulator PGND pins, to the current sense resistor, through the Schottky diode, to
the inductor and then out to the load. Minimizing the area of these two loops reduces the stray inductance and
minimizes noise which can cause erratic operation. A ground plane is recommended as a means to connect the
input filter capacitors of the output filter capacitors and the PGND pin of the regulator. Connect all of the low
power ground connections (CSS, RT, CRAMP) directly to the regulator GND pin. Connect the GND pin and PGND
pins together through to topside copper area covering the entire underside of the device. Place several vias in
this underside copper area to the ground plane. The input capacitor ground connection should be as close as
possible to the current sense ground connection.
In a buck converter, most of the losses can be attributed to MOSFET conduction and switching loss, recirculating diode conduction loss, inductor DCR loss and LM25088 VIN and VCC loss. The other dissipative
components in a buck converter produce losses but these other losses collectively account for about 2% of the
total loss. Formulae to calculate all the major losses are described in their respective sections of this datasheet.
The easiest method to determine the power dissipated within the LM25088 is to measure the total conversion
losses (Pin-Pout), then subtract the power losses in the Schottky diode, MOSFET, output inductor and snubber
resistor. When operating at 7A of output current and at 36V, the power dissipation of the LM25088 is
approximately 550 mW. The junction to ambient thermal resistance of the LM25088 mounted in the evaluation
board is approximately 40°C with no airflow. At 25°C ambient temperature and no airflow, the predicted junction
temperature will be 25+40*0.55 = 47°C. The LM25088 has an exposed thermal pad to aid in power dissipation.
Adding several vias under the device will greatly reduce the controller junction temperature. The junction to
ambient thermal resistance will vary with application. The most significant variables are the area of copper in the
PC board; the number of vias under the IC exposed pad and the amount of forced air cooling. The integrity of
solder connection from the IC exposed pad to the PC board is critical. Excessive voids will greatly diminish the
thermal dissipation capacity.
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
23
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
Figure 28. LM25088-1 Application Schematic
24
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
LM25088
www.ti.com
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
Figure 29. LM25088-2 Application Schematic
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
25
LM25088
SNVS609G – DECEMBER 2008 – REVISED MARCH 2011
www.ti.com
Table 1. Bill of Materials for LM25088-1 and LM25088-2 Evaluation Boards
Part
Value
Package
Manufacturer
Manufacturer Part Number
C1,C2,C3,C4
,C5
2.2µF
C1210
Murata
GRM32ER72A225KA35L
Description
CAP CER 2.2µF 100V X7R
1210
C6,C19
0.1µF
C0805
TDK Corporation
C2012X7R2A104K
CAP CER .10µF 100V X7R
10% 0805
C7
1µF
C0603
Murata
GRM188R71C105KA12D
CAP CER 1µF 16V X7R 0603
C8,C11
100pF
C0603
AVX Corporation
06031A101FAT2A
CAP CERM 100pF 1% 100V
NP0 0603
C9
270pF
C0603
Murata
GRM1885C2A271JA01D
CAP CER 270pF 100V 5%
C0G 0603
C13
0.1µF
C0603
Murata
GRM188R72A104KA35D
CAP CER .1µF 100V X7R
0603
C10
0.022µF
C0603
Murata
GRM188R71C223KA01D
CAP CER 22000pF 16V 10%
X7R 0603
C12
0.015µF
C0603
Murata
GRM188R71H153KA01D
CAP CER 15000pF 50V 10%
X7R 0603
C15
470µF
0.327x0.327x0.30
3
Nippon-Chemicon
APXF6R3ARA471MH80G
CAP 470UF 6.3V ELECT
POLY SMD
C17,C18
47µF
C1210
Murata
GRM32ER61A476KE20L
CAP CER 47µF 10V X5R
1210
C20
1000pF
C0805
Murata
GRM2195C2A102JA01D
CAP CER 1000pF 100V 5%
C0G 0805
C16
NU
0.327x0.327x0.30
3
NU
NU
NU
NU
C21
NU
C0603
NU
NU
C14(LM2508
8-1)
0.1µF
C0603
Murata
GRM188R72A104KA35D
CAP CER .1µF 100V X7R
0603
C14(LM2508
8-2)
0.022µF
C0603
Murata
GRM188R71C223KA01D
CAP CER 22000pF 16V 10%
X7R 0603
D1
Schottky Diode
D2PAK
On Semi
MBRB1545CT
D2
NU
SOD123
NU
NU
L1
6.8µH
HC9 series
Coiltronics
HC9-6R8-R
Q1
MOSFET
SO-8
Vishay IR
SI7848DP
R1
54.9k Ohm
R0805
Rohm
MCR10EZHF5492
RES 54.9 kΩ 1/8W 1% 0805
SMD
R2
16.2k Ohm
R0603
Rohm
MCR03EZPFX1622
RES 16.2 kΩ 1/10W 1% 0603
SMD
R3
24.9k Ohm
R0603
Rohm
MCR03EZPFX2492
RES 24.9 kΩ 1/10W 1% 0603
SMD
R4
18.2k Ohm
R0603
Rohm
MCR03EZPFX1822
RES 18.2 kΩ 1/10W 1% 0603
SMD
R5
10m Ohm
R0815
Susumu Co Ltd
RL3720WT-R010-F
RES .01Ω 1W 1% 0815 SMD
R6
5.1 Ohm
R2512
Panasonic - ECG
ERJ-1TRQF5R1U
RES 5.1Ω 1W 1% 2512 SMD
R7
10 Ohm
R0805
Rohm
MCR10EZHF10R0
RES 10.0Ω 1/8W 1% 0805
SMD
R8
5.11k Ohm
R0603
Rohm
MCR03EZPFX5111
RES 5.11 kΩ 1/10W 1% 0603
SMD
R9
1.62k Ohm
R0603
Rohm
MCR03EZPFX1621
RES 1.62 kΩ 1/10W 1% 0603
SMD
R0603
Schottky Rectifiers 15A 45V
NU
INDUCTOR HIGH CURRENT
6.8µH
MOSFET N-CH 40V PWR
PAK SO8
R10
NU
NU
NU
J1,J2,J3,J4
Terminal_Turret
Keystone
1509
Terminal, Turret
TP1,TP2
Slotted test
point
Keystone
1040
Terminal test point slotted
U1
PWM IC
TI
LM25088-1/LM25088-2
26
HTSSOP16_EP
Submit Documentation Feedback
NU
ECM Buck Controller
Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LM25088
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM25088MH-1/NOPB
ACTIVE
HTSSOP
PWP
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L25088
MH-1
LM25088MH-2/NOPB
ACTIVE
HTSSOP
PWP
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L25088
MH-2
LM25088MHX-1/NOPB
ACTIVE
HTSSOP
PWP
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L25088
MH-1
LM25088MHX-2/NOPB
ACTIVE
HTSSOP
PWP
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L25088
MH-2
LM25088QMH-1/NOPB
ACTIVE
HTSSOP
PWP
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L25088
QMH-1
LM25088QMH-2/NOPB
ACTIVE
HTSSOP
PWP
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L25088
QMH-2
LM25088QMHX-1/NOPB
ACTIVE
HTSSOP
PWP
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L25088
QMH-1
LM25088QMHX-2/NOPB
ACTIVE
HTSSOP
PWP
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L25088
QMH-2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Jan-2013
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM25088, LM25088-Q1 :
• Catalog: LM25088
• Automotive: LM25088-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM25088MHX-1/NOPB
HTSSOP
PWP
16
2500
330.0
12.4
LM25088MHX-2/NOPB
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.95
8.3
1.6
8.0
12.0
Q1
HTSSOP
PWP
16
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
LM25088QMHX-1/NOPB HTSSOP
PWP
16
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
LM25088QMHX-2/NOPB HTSSOP
PWP
16
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM25088MHX-1/NOPB
HTSSOP
PWP
16
2500
349.0
337.0
45.0
LM25088MHX-2/NOPB
HTSSOP
PWP
16
2500
349.0
337.0
45.0
LM25088QMHX-1/NOPB
HTSSOP
PWP
16
2500
349.0
337.0
45.0
LM25088QMHX-2/NOPB
HTSSOP
PWP
16
2500
349.0
337.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
PWP0016A
MXA16A (Rev A)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
LM25088MH-1EVAL LM25088MH-2EVAL