CMOSIS / AWAIBA is now Member of the ams Group The technical content of this CMOSIS / AWAIBA document is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Premstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: [email protected] Please visit our website at www.ams.com Reference:CMV20000-datasheet-v2.3 Page 1 of 47 CMV20000 Datasheet 20 Megapixel global shutter CMOS image sensor Datasheet © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 2 of 47 CMV20000 Datasheet Change record Issue 1 1.1 2 2.1 Date 24/11/211 24/5/2013 19/06/2013 12/08/2013 2.2 05/06/2014 2.3 20/05/2015 Modification Origination Changed VDD20 from 2.0V to 2.1V Removed draft, confidential and preliminary annotations Updated: - FOT, Read out time and exposure time calculations - SPI read out delay (left - right) - VDD20 maximum range to 2.2V - CLK_IN is optional Added: - Angular response - Digital test signals - Detailed frame timing - LVDS output skew Updated: - QE and spectral response for mono devices - Remarks in register overview Added: - QE and spectral response for color devices Updated: - Supply currents - SPI_OUT not tri-state - Reg89[12:8] [11:8] - PGA gain made relative - Reg103 = 72 64 Added: - ADC_gain vs. actual gain - Excessive light precaution - Test Pattern image example Disclaimer CMOSIS reserves the right to change the product, specification and other information contained in this document without notice. Although CMOSIS does its best efforts to provide correct information, this is not warranted. Since the CMV20000 started its design life as a custom imager for traffic applications, the sale of the imager for these applications is excluded. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 3 of 47 CMV20000 Datasheet Table of Contents 1 Introduction ...........................................................................................................................................................6 1.1 Overview ........................................................................................................................................................ 6 1.2 features .......................................................................................................................................................... 6 1.3 Specifications.................................................................................................................................................. 6 2 Sensor architecture ................................................................................................................................................7 2.1 Pixel array....................................................................................................................................................... 8 2.2 Analog front-end electronics (AFE) .................................................................................................................. 8 2.3 LVDS block ...................................................................................................................................................... 8 2.4 Sequencer ...................................................................................................................................................... 8 2.5 SPI .................................................................................................................................................................. 8 2.6 Temperature sensor ....................................................................................................................................... 8 3 Driving the CMV20000 ...........................................................................................................................................9 3.1 Supply settings ............................................................................................................................................... 9 3.2 Biasing ............................................................................................................................................................ 9 3.3 Digital input pins............................................................................................................................................. 9 3.4 electrical IO specifications............................................................................................................................. 10 3.4.1 Digital IO CMOS/TTL DC specifications ................................................................................................................ 10 3.4.2 LVDS receiver specifications ............................................................................................................................... 10 3.4.3 LVDS driver specifications .................................................................................................................................. 10 3.5 Input clock .................................................................................................................................................... 10 3.6 Frame rate calculation .................................................................................................................................. 11 3.7 Start-up sequence......................................................................................................................................... 11 3.8 Reset sequence ............................................................................................................................................ 12 3.9 SPI programming .......................................................................................................................................... 12 3.9.1 SPI write ............................................................................................................................................................ 12 3.9.2 SPI read ............................................................................................................................................................. 13 3.10 Requesting a frame ....................................................................................................................................... 14 3.10.1 Internal exposure control ................................................................................................................................... 14 3.10.2 External exposure control .................................................................................................................................. 15 4 Reading out the sensor ........................................................................................................................................ 16 4.1 LVDS low-level pixel timing ........................................................................................................................... 16 4.2 LVDS readout timing ..................................................................................................................................... 16 4.2.1 16 output channels ............................................................................................................................................ 16 4.2.2 8 output channels .............................................................................................................................................. 17 © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 4 of 47 CMV20000 Datasheet 4.3 Pixel remapping ............................................................................................................................................ 17 4.3.1 16 outputs ......................................................................................................................................................... 17 4.3.2 8 outputs ........................................................................................................................................................... 18 4.4 Control channel ............................................................................................................................................ 18 4.4.1 DVAL, LVAL, FVAL............................................................................................................................................... 18 4.4.2 Digital Test pins ................................................................................................................................................. 19 4.5 Training data ................................................................................................................................................ 19 4.6 Test pattern.................................................................................................................................................. 20 5 Image sensor programming.................................................................................................................................. 22 5.1 Exposure modes ........................................................................................................................................... 22 5.1.1 Frame timing ..................................................................................................................................................... 22 5.2 High dynamic range mode ............................................................................................................................ 22 5.2.1 Piecewise linear response .................................................................................................................................. 22 5.2.1.1 Piecewise linear response with internal exposure mode ...................................................................... 24 5.2.1.2 piecewise linear response with external exposure mode ...................................................................... 24 5.3 Windowing ................................................................................................................................................... 25 5.3.1 Single window ................................................................................................................................................... 25 5.3.2 Multiple windows .............................................................................................................................................. 26 5.4 Image flipping ............................................................................................................................................... 27 5.5 Image subsampling ....................................................................................................................................... 27 5.5.1 Simple subsampling ........................................................................................................................................... 27 5.5.2 Advanced subsampling ...................................................................................................................................... 28 5.6 Number of frames ........................................................................................................................................ 29 5.7 Output mode ................................................................................................................................................ 29 5.8 FOT multiplier ............................................................................................................................................... 29 5.9 Training pattern ............................................................................................................................................ 30 5.10 Test pattern.................................................................................................................................................. 30 5.11 Data rate ...................................................................................................................................................... 30 5.12 Power control ............................................................................................................................................... 30 5.13 Offset and gain ............................................................................................................................................. 30 5.13.1 Offset ................................................................................................................................................................ 30 5.13.2 Gain .................................................................................................................................................................. 31 5.14 Temperature ................................................................................................................................................ 31 6 Register overview ................................................................................................................................................ 32 7 Mechanical specifications .................................................................................................................................... 35 7.1 Package drawing ........................................................................................................................................... 35 7.2 Assembly drawing......................................................................................................................................... 36 7.3 Cover glass ................................................................................................................................................... 37 © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 5 of 47 CMV20000 Datasheet 7.4 Color filters................................................................................................................................................... 37 7.5 QE and Spectral Response............................................................................................................................. 38 7.6 Angular Response ......................................................................................................................................... 39 8 Pin list .................................................................................................................................................................. 40 9 Specification overview ......................................................................................................................................... 43 10 Ordering info ........................................................................................................................................................ 44 11 Handling and soldering procedure ....................................................................................................................... 45 11.1 Soldering ...................................................................................................................................................... 45 11.1.1 Wave soldering .................................................................................................................................................. 45 11.1.2 Reflow soldering ................................................................................................................................................ 45 11.1.3 Soldering recommendations .............................................................................................................................. 45 11.2 Handling image sensors ................................................................................................................................ 46 11.2.1 ESD ................................................................................................................................................................... 46 11.2.2 Glass cleaning .................................................................................................................................................... 46 11.2.3 Image sensor storing.......................................................................................................................................... 46 11.2.4 Excessive light.................................................................................................................................................... 46 12 Additional information......................................................................................................................................... 47 © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 6 of 47 CMV20000 Datasheet 1 INTRODUCTION 1.1 OVERVIEW The CMV20000 is a global shutter CMOS image sensor with 5120 by 3840 pixels. The image array consists of 6.4μm x 6.4μm pipelined global shutter pixels which allow exposure during read out, while performing CDS operation. The image sensor has sixteen 12-bit digital LVDS outputs (serial). The image sensor also integrates a programmable gain amplifier and offset regulation. Each channel runs at 480 Mbps maximum which results in 30 fps frame rate at full resolution. Higher frame rates can be achieved in row-windowing mode or row-subsampling mode. These modes are all programmable using the SPI interface. All internal exposure and read out timings are generated by a programmable on-board sequencer. External triggering and exposure programming is also possible. Extended optical dynamic range can be achieved by multiple integrated high dynamic range modes. Features 1.2 FEATURES 5120 * 3840 active pixels on a 6.4um pitch frame rate 30 Frames/sec row windowing capability Window, X-Y mirroring function Master clock 40MHz 16 LVDS-outputs @ 480MHz, or 8 LVDS-outputs at 15FPS LVDS control line with frame and line information LVDS DDR output clock to sample data on the receiving end 12 bit ADC output High Dynamic Range mode supported Power dissipation control On chip temperature sensor On chip timing generation SPI-control Ceramic PGA package (143 pins) 1.3 SPECIFICATIONS Full well charge: 15KeSensitivity: 8.3 V/lux.s (with microlenses @ 550nm) Dark noise: 8e- RMS Conversion factor: 110µV/e (@ pixel); 0.25DN/e Dynamic range: 66 dB Extended dynamic range: Piecewise linear response Parasitic light sensitivity: 1/50 000 Dark current: 125 e/s (@ 25C die temp) Fixed pattern noise: <0.2% of full swing, standard deviation on full image Power consumption: 1100mW © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 7 of 47 CMV20000 Datasheet 2 SENSOR ARCHITECTURE Figure 1 shows the image sensor architecture. The internal sequencer generates the necessary signals for image acquisition. The image is stored in the pixel (global shutter) and they are read out sequentially, row-by-row into the analog front-end electronics (AFE) of the columns. On the pixel output, an analog gain of x2.0, x2.4, x2.8 and x3.2 is possible (or 1.6, 1.9, 2.25, 2.55 when column calibration is on). The pixel value then passes to a column ADC cell, in which ADC conversion is performed. The digital signals are then read out over multiple LVDS channels. Each LVDS channel reads out 640 adjacent columns of the array. The AFE and LVDs drivers are doubled on opposite sides of the sensor, resulting in 2 rows being read out at the same when all 16 outputs are used. In the Y-direction, rows of interest are selected through a row-decoder which allows a flexible windowing. Control registers are foreseen for the programming of the sensor. These register parameters are uploaded via a four-wire SPI interface. A temperature sensor which can be read out over the SPI interface is also included. 8 outputs LVDS block (drivers, multiplexers) Pixel (4095,3071) Analog front end (AFE) (gain, offset, ADCs) External driving signals sequencer Active pixel area 5120 rows 3840 columns Pixel (0,0) Input clock Analog front end (AFE) (gain, offset, ADCs) SPI SPI signals Temp sensor LVDS block (drivers, multiplexers) 8 outputs FIGURE 1: BASIC SENSOR ARCHITECTURE The most important blocks are described more in detail in the following sections. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 8 of 47 CMV20000 Datasheet 2.1 PIXEL ARRAY The CMV20000 sensor has 5120*3840 active pixels with a 6.4um pitch surrounded by two dummy rows and columns. These dummy pixels at the side will ensure that the optical performance, of the active pixels at the edges, is the same as the one in the active array. These dummy pixels cannot be read out and will be set permanent into reset. The pixels are designed to achieve maximum sensitivity with low noise and low PLS specifications. Micro lenses are placed on top of the pixels for improved fill factor and quantum efficiency. 2.2 ANALOG FRONT-END ELECTRONICS (AFE) The analog front end consists of 2 major parts, a column amplifier block and a column ADC block. The column amplifier prepares the pixel signal for the column ADC and applies analog gain if desired (programmable using the SPI interface). The column ADC converts the analog pixel value to a 12 bit value and can apply a gain. A digital offset can also be applied to the output of the column ADC’s. All gain and offset settings can be programmed using the SPI interface. 2.3 LVDS BLOCK The LVDS block converts the digital data coming from the column ADC into standard serial LVDS data running at maximum 480Mbps. The sensor has 18 LVDS output pairs: 16 data channels 1 control channel 1 clock channel The 16 data channels are used to transfer 12-bit data words from sensor to receiver. The output clock channel transports a DDR clock, synchronous to the data on the other LVDS channels. This clock can be used at the receiving end to sample the data. The data on the control channel contains status information on the validity of the data on the data channels, among other useful sensor status information. Details on the LVDS timing and format can be found in section 4 of this document. 2.4 SEQUENCER The on-chip sequencer will generate all required control signals to operate the sensor from only a few external control clocks. This sequencer can be activated and programmed through the SPI interface. A detailed description of the SPI registers and sensor (sequencer) programming can be found in section 5 of this document. 2.5 SPI The SPI interface is used to load the sequencer registers with data. The data in these registers is used by the sequencer while driving and reading out the image sensor. Features like windowing, sub sampling, gain and offset are programmed using this interface. The data in the on-chip registers can also be read back for test and debug of the surrounding system. Section 5 contains more details on register programming and SPI timing. 2.6 TEMPERATURE SENSOR A 16-bit digital temperature sensor is included in the image sensor and can be controlled by the SPI-interface. The onchip temperature can be obtained by reading out a dedicated SPI register (address 101-102). A calibration of the temperature sensor is needed by the surrounding system (for absolute temperature measurements). © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 9 of 47 CMV20000 Datasheet 3 DRIVING THE CMV20000 3.1 SUPPLY SETTINGS The CMV20000 image sensor has the following supply settings: Supply name Recommended Absolute Min - Max Value Range VDD20 2.1V 1.6 - 2.2V VDD33 3.3V 3V - 3.6V VDDpix 3.0V 2.3V - 3.6V Vres_h 3.3V 3.0V - 3.6V See pin list for exact pin numbers for every supply. Current typical Current peak 800mA 170mA 20mA 5mA 1A 0.6A 8A 0.1A The peak current of VDD20 is drawn during read out, while the other supplies draw it during FOT. All supplies should have enough decoupling, especially VDDPIX. Application note AN03 has more details about these peaks waveforms. 3.2 BIASING For optimal performance, some pins need to be decoupled to ground or to VDD. Please refer to the pin list for a detailed description for every pin and the appropriate decoupling if applicable. 3.3 DIGITAL INPUT PINS The table below gives an overview of the external pins used to drive the sensor Pin name CLK_IN LVDS_CLK_N/P SYS_RES_N FRAME_REQ SPI_IN SPI_EN SPI_CLK T_EXP1 Description Master input clock, frequency range is (LVDS_CLK / 12). This clock is optional. High speed LVDS input clock, frequency range between 120 and 480 MHz System reset pin, active low signal. Resets the onboard sequencer and must be kept low during startup Frame request pin. When a rising edge is detected on this pin the programmed number of frames is captured and sent by the sensor Data input pin for the SPI interface. The data to program the image sensor is sent over this pin. SPI enable pin. When this pin is high the data should be written/read on the SPI SPI clock. This is the clock on which the SPI runs (max 20Mz) Input pin which can be used to program the exposure time externally. Optional © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 10 of 47 CMV20000 Datasheet 3.4 ELECTRICAL IO SPECIFICATIONS 3.4.1 DIGITAL IO CMOS/TTL DC SPECIFICATIONS Parameter VIH VIL VOH VOL Description High level input voltage Low level input voltage High level output voltage Low level output voltage Conditions VDD=3.3V IOH=-2mA VDD=3.3V IOL=2mA 2.0 min typ max VDD33 V Units GND 0.8 V 2.4 V 0.4 V 3.4.2 LVDS RECEIVER SPECIFICATIONS Parameter VID VIC IID ∆IID Description Differential input voltage Receiver input range Receiver input current Receiver input current difference Conditions Steady state 100 min Steady state 0.0 typ 350 VINP|INN=1.2V±50mV, 0≤ VINP|INN≤2.4V |IINP – IINN| max Units 600 mV 2.4 V 20 µA 6 µA 3.4.3 LVDS DRIVER SPECIFICATIONS Parameter VOD ∆VOD VOC ∆VOC IOS,GND IOS,PN Description Differential output voltage Difference in VOD between complementary output states Common mode voltage Difference in VOC between complementary output states Output short circuit current to ground Output short circuit current Conditions Steady State, RL = 100Ω Steady State, RL = 100Ω min typ Units mV 50 mV 1.375 V 50 mV VOUTP=VOUTN=GND 24 mA VOUTP=VOUTN 12 mA 1.125 350 max 454 Steady State, RL = 100Ω Steady State, RL = 100Ω 247 1.25 3.5 INPUT CLOCK The high speed LVDS input clock (LVDS_CLK_N/P) defines the output data rate of the CMV20000. The master clock (CLK_IN) must be 12 times slower and this clock but is optional. The maximum data rate of the output is 480Mbps which results in a LVDS_CLK_N/P of 480MHz (and a CLK_IN of 40MHz). The minimum frequencies are 10MHz for CLK_IN and 120MHz for LVDS_CLK_N/P. Any frequency between the minimum and maximum can be applied by the user and will result in a corresponding output data rate. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 11 of 47 CMV20000 Datasheet 3.6 FRAME RATE CALCULATION The frame rate of the CMV20000 is defined by 2 main factors. 1. 2. Exposure time Read out time For ease of use we will assume that the exposure time is shorter than the read out time. By assuming this, the frame rate is completely defined by the read out time (because the exposure time happens in parallel with the read-out time). The read-out time (and thus the frame rate) is defined by: 1. 2. 3. Output clock speed: max 480Mbps Number of lines read-out Number of outputs used: max 16 LVDS outputs (8 on the top and 8 on the bottom) This means that if any of the parameters above is changed, it will have an impact on the frame rate of the CMV20000. In normal operation (16 outputs @ 480Mbps, 12 bit and full resolution) this will result in 30 fps. Total readout time is composed of two parts: FOT (frame overhead time) + image readout time. 𝐹𝑂𝑇 = ((80 ∗ 𝑟𝑒𝑔82 + 𝑟𝑒𝑔82 ) + (2 ∗ 641)) ∗ 𝑐𝑙𝑘_per 8 So for reg82 = 80 and running at 480MHz this becomes: 𝐹𝑂𝑇 = (6410 + 1282) ∗ 25𝑛𝑠 = 192.3µ𝑠 The image read out time equals to 𝑅𝑒𝑎𝑑 𝑂𝑢𝑡 𝑇𝑖𝑚𝑒 = 641 ∗ 𝑐𝑙𝑘_per ∗ 𝑛𝑟_lines # 𝑠𝑖𝑑𝑒𝑠 𝑢𝑠𝑒𝑑 So for full resolution and running at 480MHz with both output sides used this becomes: 𝑅𝑒𝑎𝑑 𝑂𝑢𝑡 𝑇𝑖𝑚𝑒 = 641 ∗ 25𝑛𝑠 ∗ 3840 = 30.768𝑚𝑠 2 This results in a total frame time of: 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 = 𝐹𝑂𝑇 + 𝑅𝑒𝑎𝑑 𝑂𝑢𝑡 𝑡𝑖𝑚𝑒 So for the default settings this becomes: 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 = 192.3µ𝑠 + 30768 µ𝑠 = 30.96𝑚𝑠 And the frame rate becomes: 𝐹𝑟𝑎𝑚𝑒 𝑟𝑎𝑡𝑒 = 1 1 = = 32.3𝑓𝑝𝑠 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 0.03096𝑠 See chapter 5.1.1 for detailed frame timing. Clk_per is the period of the pixel clock. This pixel clock frequency is equal to 1/12th (40MHz) of the LVDS input clock frequency (480MHz). 3.7 START-UP SEQUENCE The following sequence should be followed when the CMV20000 is started up in default output mode (480Mbps, 12bit resolution). © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 12 of 47 CMV20000 Datasheet Stable time 1μs Supply CLK_IN 1μs SYS_RES_N FRAME_REQ FIGURE 2: START-UP SEQUENCE FOR 480MBPS @ 12-BIT The CLK_IN and LVDS_CLK_N/P should only start after the rise time of the supplies (VDD33, VDD20, Vddpix and Vres_h go high together). The external reset pin should be released at least 1μs after the supplies have become stable. The first frame can be requested 1μs after the reset pin has been released. An optional SPI upload (to program the sequencer) is possible 1μs after the reset pin has been released. In this case the FRAME_REQ pulse must be postponed until after the SPI upload has been completed. 3.8 RESET SEQUENCE If a sensor reset is necessary while the sensor is running the following sequence should be followed. CLK_IN 1μs SYS_RES_N FRAME_REQ FIGURE 3: RESET SEQUENCE The on-board sequencer will be reset and all programming registers will return to their default start-up values when a falling edge is detected on the SYS_RES_N pin. After the reset there is a minimum time of 1μs needed before a FRAME_REQ pulse can be sent. All recommended register settings must be reloaded after a reset sequence. 3.9 SPI PROGRAMMING Programming the sensor is done by writing the appropriate values to the on-board registers. These registers can be written over a simple serial interface (SPI). The details of the timing and data format are described below. The data written to the programming registers can also be read out over this same SPI interface. The SPI out doesn’t have a tri-state, so multiple SPI outputs cannot be on the same bus without a buffer. 3.9.1 SPI WRITE The timing to write data over the SPI interface can be found below. SPI_EN ½ CLK 1 CLK SPI_CLK SPI_IN C=’1' A6 A5 A4 A3 A2 A1 A0 D7 D6 FIGURE 4: SPI WRITE TIMING © 2015 CMOSIS bvba D5 D4 D3 D2 D1 D0 Reference:CMV20000-datasheet-v2.3 Page 13 of 47 CMV20000 Datasheet The data is sampled by the CMV20000 on the rising edge of the SPI_CLK. The SPI_CLK has a maximum frequency of 20MHz. The SPI_EN signal has to be high for half a clock period before the first databit is sampled. SPI_EN has to remain high for 1 clock period after the last databit is sampled. One write action contains 16 databits: One control bit: First bit to be sent, indicates whether a read (‘0’) or write (‘1’) will occur on the SPI interface. 7 address bits: These bits form the address of the programming register that needs to be written. The address is sent MSB first. 8 data bits: These bits form the actual data that will be written in the register selected with the address bits. The data is written MSB first. When several sensor registers need to be written, the timing above can be repeated with SPI_EN remaining high all the time. See the figure below for an example of 2 registers being written in burst. ½ CLK SPI_EN 1 CLK SPI_CLK SPI_IN C=’1' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C=’1' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 5: SPI WRITE TIMING FOR 2 REGISTERS IN BURST The sample and hold time is 1/4th of the SPI clock period. 3.9.2 SPI READ The timing to read data from the registers over the SPI interface can be found below. SPI_EN ½ CLK 1 CLK SPI_CLK SPI_IN SPI_OUT C=’0' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 6: SPI READ TIMING To indicate a read action over the SPI interface, the control bit on the SPI_IN pin is made ‘0’. The address of the register being read out is sent immediately after this control bit (MSB first). After the LSB of the address bits, the data is launched on the SPI_OUT pin on the falling edge of the SPI_CLK. This means that the data should be sampled by the receiving system on the rising edge of the SPI_CLK. The data comes over the SPI_OUT with MSB first. The CMV20000 has to SPI read out pins: SPI_OUT_LEFT (pin T1) and SPI_OUT_RIGHT (pin R18). SPI_OUT_LEFT will read out every register, while SPI_OUT_RIGHT will only read out registers 103 to 126. Because of the large sensor there is some SPI read out delay. This delay is fixed and independent of the sensor or SPI clock. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 14 of 47 CMV20000 Datasheet 12.5ns SPI_CLK 40MHz A1 SPI_IN A0 2.5ns 10ns SPI_OUT_LEFT registers 0 - 102 D7 D6 26ns SPI_OUT_LEFT registers 103 - 126 D7 20ns SPI_OUT_RIGHT registers 103 - 126 D7 D6 D6 FIGURE 7: SPI DELAY So when sampling on the rising SPI_CLK edge it is advised to have a SPI_CLK of 10MHz maximum. 3.10 REQUESTING A FRAME After starting up the sensor (see section 3.7), a number of frames can be requested by sending a FRAME_REQ pulse. The number of frames can be set by programming the appropriate register (addresses 22 and 23). The default number of frames to be grabbed is 1. In internal-exposure-time mode, the exposure time will start after this FRAME_REQ pulse. In the external-exposuretime mode, the read-out will start after the FRAME_REQ pulse. Both modes are explained into detail in the sections below. 3.10.1 INTERNAL EXPOSURE CONTROL In this mode, the exposure time is set by programming the appropriate registers (address 32-33) of the CMV20000. After the high state of the FRAME_REQ pulse is detected, the exposure time will start immediately. When the exposure time ends (as programmed in the registers), the pixels are being sampled and prepared for read-out. This sequence is called the frame overhead time (FOT). Immediately after the FOT, the frame is read-out automatically. If more than one frame is requested, the exposure of the next frame starts already during the read-out of the previous one. See the diagram below for more details. FRAME_REQ Frame1_cycle Exposure time FOT Frame2_cycle Read-out time Exposure time FOT Read-out time FIGURE 8: REQUEST FOR 2 FRAMES IN INTERNAL- EXPOSURE-TIME MODE When the exposure time is shorter than the read-out time, the FOT and read-out of the next frame will start immediately after the read-out of the previous frame. FRAME_REQ Frame1_cycle Frame2_cycle Exposure time FOT Read-out time Exposure time FOT Read-out time FIGURE 9: REQUEST FOR 2 FRAMES IN INTERNAL-EXPOSURE-TIME MODE WITH EXPOSURE TIME < READ-OUT TIME © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 15 of 47 CMV20000 Datasheet 3.10.2 EXTERNAL EXPOSURE CONTROL The exposure time can also be programmed externally by using the T_EXP1 input pin. This mode needs to be enabled by setting the appropriate register (address 81). In this case, the exposure starts when a high state is detected on the T_EXP1 pin. When a high state is detected on the FRAME_REQ input, the exposure time stops and the read-out will start automatically. A new exposure can start by sending a pulse to the T_EXP1 pin during or after the read-out of the previous frame. T_EXP1 FRAME_REQ Frame1_cycle Exposure time FOT Read-out time Frame2_cycle Exposure time FIGURE 10: REQUEST FOR 2 FRAMES USING EXTERNAL-EXPOSURE-TIME MODE © 2015 CMOSIS bvba FOT Read-out time Reference:CMV20000-datasheet-v2.3 Page 16 of 47 CMV20000 Datasheet 4 READING OUT THE SENSOR The CMV20000 has LVDS (low voltage differential signaling) outputs to transport the image data to the surrounding system. Next to 16 data channels, the sensor also has two other LVDS channels for control and synchronization of the image data. In total, the sensor has 18 LVDS output pairs (2 pins for each LVDS channel): 16 Data channels 1 Control channel 1 Clock channel This means that a total of 36 pins of the CMV20000 are used for the LVDS outputs (32 for data + 2 for LVDS clock + 2 for control channel). See the pin list for the exact pin numbers of the LVDS outputs. The 16 data channels are used to transfer the 12-bit pixel data from the sensor to the receiver in the surrounding system. The output clock channel transports a clock, synchronous to the data on the other LVDS channels. This clock can be used at the receiving end to sample the data. This clock is a DDR clock which means that the frequency will be half of the output data rate. When 480Mbps output data rate is used, the LVDS output clock will be 240MHz. The data on the control channel contains status information on the validity of the data on the data channels. Information on the control channel is grouped in 12-bit words that are transferred synchronous to the 16 data channels. 4.1 LVDS LOW-LEVEL PIXEL TIMING The figure below shows the timing for transfer of 12-bit pixel data over one LVDS output. To make the timing more clear, the figure shows only the p-channel of each LVDS pair. The data is transferred LSB first, with the transfer of bit D[0] during the high phase of the DDR output clock. T1 LVDS_CLOCK_OUT DATA_OUT D(0) D(1) D2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(0) D(1) D2) D(3) FIGURE 11: 10: 12-BIT PIXEL DATA ON AN LVDS CHANNEL The time ‘T1’ in the diagram above is 1/12th of the period of the input clock (CLK_IN) of the CMV20000. If a frequency of 40MHz is used for CLK_IN (max), this results in a 240MHz LVDS_CLOCK_OUT. 4.2 LVDS READOUT TIMING The readout of image data is grouped in bursts of 640 pixels per channel (2 rows at the same time). Each pixel is 12 bits of data (see section 4.1.1). One complete pixel period equals one period of the master clock input. For details on pixel remapping and pixel vs channel location please see section 4.1.3 of this document. An overhead time exists between two bursts of 640 pixels. This overhead time has the length of one pixel read-out (i.e. the length of 12 bits at the selected data rate) or one master clock cycle. 4.2.1 16 OUTPUT CHANNELS By default, all 16 data output channels are used to transmit the image data. This means that two entire rows of image data are transferred in one slot of 640 pixel periods (16/2 x 640 = 5120). Next figure shows the timing for the top and bottom LVDS channels. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 17 of 47 CMV20000 Datasheet DATA_OUT_BOTTOM IDLE OH 640 OH Row 0 DATA_OUT_TOP IDLE OH 640 OH Row 2 640 OH Row 1 640 Row 4 640 OH Row 3 640 Row 5 FIGURE 12: OUTPUT TIMING IN DEFAULT 16 CHANNEL MODE Only when 16 data outputs, running at 480Mbps, are used, the frame rate of 30fps can be achieved (default). 4.2.2 8 OUTPUT CHANNELS The CMV20000 has the possibility to use only 8 LVDS output channels. This setting can be programmed in the register with address 80 (see section 5.7). In such multiplexed output mode, only the 8 bottom LVDS channels are used. The readout of one row takes 1*640 periods. . This means that ne entire rows of image data are transferred in one slot of 640 pixel periods (8 x 640 = 5120). Next figure shows the timing for the bottom LVDS channels. DATA_OUT_BOTTOM IDLE OH 640 OH Row 0 640 OH Row 1 640 Row 2 FIGURE 13: OUTPUT TIMING IN 8 CHANNEL MODE In this 2 channel mode, the frame rate is reduced with a factor of 2 compared to 4 channel mode. 4.3 PIXEL REMAPPING Depending on the number of output channels, the pixels are read out by different channels and come out at a different moment in time. With the details from the next sections, the end user is able to remap the pixel values at the output to their correct image array location. 4.3.1 16 OUTPUTS The figure below shows the location of the image pixels versus the output channel of the image sensor. Channel 1 bot IDLE Pixel 0 to 639 Pixel 0 to 639 Channel 2 bot IDLE Pixel 640 to 1279 Pixel 640 to 1279 … Channel 8 bot … IDLE … Pixel 4480 to 5119 Pixel 4480 to 5119 Row 0 Row 2 Channel 1 top IDLE Pixel 0 to 639 Pixel 0 to 639 Channel 2 top IDLE Pixel 640 to 1279 Pixel 640 to 1279 … Channel 8 top … IDLE … Pixel 4480 to 5119 Pixel 4480 to 5119 Row 1 Row 3 FIGURE 14: PIXEL REMAPPING FOR 16 OUTPUT CHANNELS © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 18 of 47 CMV20000 Datasheet 16 bursts (8 x 2) of 640 pixels happen in parallel on the data outputs. This means that two complete rows are read out in one burst. The amount of rows that will be read out depends on the value in the corresponding register. By default there are 3840 rows being read out. 4.3.2 8 OUTPUTS When only 8 outputs are used, the pixel data is placed on the outputs as detailed in the figure below. 8 bursts of 640 pixels happen in parallel on the data outputs. This means that one complete row is read out in one burst. The time needed to read out two rows is doubled compared to when 16 outputs are used. The top LVDS channels are not being used in this mode, so they can be turned off by setting the correct bits in the register with address 95-97. Turning off these channels will reduce the power consumption of the chip. The amount of rows that will be read out depends on the value in the corresponding register. By default there are 3840 rows being read out. Channel 1 bot IDLE Pixel 0 to 639 Pixel 0 to 639 Channel 2 bot IDLE Pixel 640 to 1279 Pixel 640 to 1279 … Channel 8 bot … IDLE … Pixel 4480 to 5119 Pixel 4480 to 5119 Row 0 Row 1 FIGURE 15: PIXEL REMAPPING FOR 8 OUTPUT CHANNELS 4.4 CONTROL CHANNEL The CMV20000 has one LVDS output channel dedicated for the valid data synchronization and timing of the output channels. The end user must use this channel to know when valid image data or training data is available on the data output channels. The control channel transfers status information in 12-bit word format. Every bit of the word has a specific function. Next table describes the function of the individual bits. Bit Function Description [0] DVAL Indicates valid pixel data on the outputs [1] LVAL Indicates validity of the readout of a row [2] FVAL Indicates the validity of the readout of a frame [3] ‘0’ Constant zero [4] ‘0’ Constant zero [5] FOT Indicates when the sensor is in FOT (sampling of image data in pixels) (*) [6] INTE1 Indicates when pixels of integration block 1 are integrating (*) [7] INTE2 Indicates when pixels of integration block 2 are integrating (*) [8] ‘0’ Constant zero [9] ‘1’ Constant one [10] ‘0’ Constant zero [11] ‘0’ Constant zero (*)Note: The status bits are purely informational. These bits are not required to know when the data is valid. The DVAL, LVAL and FVAL signals are sufficient to know when to sample the image data. 4.4.1 DVAL, LVAL, FVAL The first three bits of the control word must be used to identify valid data and the readout status. Next figure shows the timing of the DVAL, LVAL and FVAL bits of the control channel with an example of the readout of a frame of 6 rows (default is 3840 rows). This example uses the default mode of 16 outputs (8 outputs on each side). © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 19 of 47 CMV20000 Datasheet DATA_OUT IDLE OH 640 OH 640 OH 640 DVAL LVAL FVAL FIGURE 16: DVAL, LVAL AND FVAL TIMING IN 16 OUTPUT MODE 4.4.2 DIGITAL TEST PINS Pins D1 (Tdig2) and D3 (Tdig1) can be used as digital outputs to monitor the state of the sensor. Register 92 can be used to select a signal on these pins. Reg92[6:4] 0 3 7 Tdig2 LVAL INTE_1 CLK_OUT (=LVDS_CLK/12) Reg92[3:0] 0 2 3 Tdig1 FVAL FOT INTE_2 4.5 TRAINING DATA To synchronize the receiving side with the LVDS outputs of the CMV20000, a known data pattern can be put on the output channels. This pattern can be used to “train” the LVDS receiver of the surrounding system to achieve correct word alignment of the image data. Such a training pattern is put on all 16 data channel outputs when there is no valid image data to be sent (so, also in between bursts of 640 pixels). The training pattern is a 12-bit data word that replaces the pixel data. The sensor has a 12-bit sequencer register (address 90-90) that can be loaded through the SPI to change the contents of the 12-bit training pattern. The control channel does not send a training pattern, because it is used to send control information at all time. Word alignment can be done on this channel when the sensor is idle (not exposing or sending image data). In this case all bits of the control word are zero, except for bit [9]. The figure below shows the location of the training pattern (TP) on the data channels and control channels when the sensor is in idle mode and when a frame of 6 rows is read-out. The default mode of 16 outputs is selected. DVAL Sensor in idle mode LVAL FVAL Data channels Training pattern Control channel Training pattern TP 640 TP 640 TP 640 Control information FIGURE 17: TRAINING PATTERN LOCATION IN THE DATA CHANNEL AND CONTROL CHANNEL. The LVDS outputs are not aligned with the LVDS output clock. Every channel (per odd/even side) has a skew of +600ps compared to the previous channel. The control channel and both odd and even channels 1 are aligned with the clock. This skew will become larger than a LVDS clock period and therefor bit and word alignment is needed in the receiving side. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 20 of 47 CMV20000 Datasheet T1 LVDS CLOCK_OUT CTR D(0) D(1) D2) OUT1E D(0) D(1) D2) OUT1O D(0) D(1) D2) OUT2E D(0) D(1) D2) D(0) D(1) D2) 600ps OUT2O 600ps OUT3E D(0) D(1) D2) D(0) D(1) D2) 1200ps OUT3O 1200ps ... OUT8E D(0) 4200ps OUT8O D(0) 4200ps FIGURE 18: LVDS OUTPUT SKEW 4.6 TEST PATTERN Instead of sending image data, the sensor can generate a fixed two-dimensional test image (after sending a frame request), if the test pattern mode is enabled. This setting can be programmed in the register by setting register 83[0] to 1. The test pattern is the sum of the row number, the pixel number and the data output channel number. Next figure shows an example of the test pattern data. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 21 of 47 CMV20000 Datasheet DATA_OUT_ BOT_0 IDLE TP 0,1,...639 TP Row 0 DATA_OUT_ BOT_1 IDLE TP ... DATA_OUT_ BOT_7 IDLE TP 1,2,...640 IDLE TP TP IDLE TP ... DATA_OUT_ TOP_7 IDLE TP 3,4,...642 4,5,...643 TP Row 4 TP 5,6,...644 6,7,...645 Row 6 TP 7,8,...646 Row 0 Row 2 Row 4 Row 6 ... ... ... ... 7,8,...646 TP 1,2,...640 2,3,...641 9,10,...648 TP Row 2 TP Row 1 DATA_OUT_ TOP_1 TP Row 2 Row 0 DATA_OUT_ TOP_0 2,3,...641 3,4,...642 4,5,...643 TP Row 4 TP Row 3 TP 11,12,...650 5,6,...644 Row 6 TP Row 5 TP 6,7,...645 13,14,...652 7,8,...646 Row 7 TP 8,9,...647 Row 1 Row 3 Row 5 Row 7 ... ... ... ... 8,9,...647 Row 1 TP 10,11,...649 TP Row 3 FIGURE 19: TEST PATTERN DATA FIGURE 20: TEST PATTERN IMAGE © 2015 CMOSIS bvba 12,13,...651 Row 5 TP 14,15,...653 Row 7 Reference:CMV20000-datasheet-v2.3 Page 22 of 47 CMV20000 Datasheet 5 IMAGE SENSOR PROGRAMMING This section explains how the CMV20000 can be programmed using the on-board sequencer registers. 5.1 EXPOSURE MODES The exposure time can be programmed in two ways, externally or internally. Externally, the exposure time is defined as the time between the rising edge of T_EXP1 and the rising edge of FRAME_REQ (see section 3.10 for more details). Internally, the exposure time is set by uploading the desired value to the corresponding sequencer register. The table below gives an overview of the registers involved in the exposure mode. Register name Exp_ext Register address 81[0] Exp_time 32-33 Exposure time settings Default value Description of the value 0 0: Exposure time is defined by the value uploaded in the sequencer register (32-33) 1: Exposure time is defined by the pulses applied to the T_EXP1 and FRAME_REQ pins. 3840 When the Exp_ext register is set to ‘0’, the value in this register defines the exposure time according to the formula below. Minimum = 1. 𝐴𝑐𝑡𝑢𝑎𝑙 𝐸𝑥𝑝𝑜𝑠𝑢𝑟𝑒 𝑡𝑖𝑚𝑒 = (((𝐸𝑥𝑝_time − 1) ∗ 641) + 1 + (47 ∗ 𝑟𝑒𝑔82)) ∗ 𝑐𝑙𝑘_𝑝𝑒𝑟 Here clk_per is the period of the input LVDS_CLK multiplied by 12 (so for 480MHz this is 25ns). The minimum exposure time then becomes 94µs. 5.1.1 FRAME TIMING A detailed view of the frame timing can be seen below. Actual exposure time (Exp_time - 1) * 641 + 1) * clk_per 47*80*clk_per Frame_REQ INTE_1 Actual FOT 6410 * clk_per 1282 * clk_per FOT FVAL 641 * (#lines / #sides) * clk_per 5.2 HIGH DYNAMIC RANGE MODE 5.2.1 PIECEWISE LINEAR RESPONSE The CMV20000 has the possibility to achieve a high optical dynamic range by using a piecewise linear response. This feature will clip illuminated pixels which reach a programmable voltage, while leaving the darker pixels untouched. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 23 of 47 CMV20000 Datasheet The clipping level can be adjusted 2 times within one exposure time to achieve a maximum of 3 slopes in the response curve. More details can be found in the figure below. Pixel reset Pixel sample Vhigh Vlevel_s2 Vlevel_s3 Vlow Exp_s2 Exp_s3 Total exposure time FIGURE 21: PIECEWISE LINEAR RESPONSE DETAILS In the figure above, the red lines represent a pixel on which a large amount of light is falling. The blue line represents a pixel on which less light is falling. As shown in the figure, the bright pixel is held to a programmable voltage for a programmable time during the exposure time. This happens two times to make sure that at the end of the exposure time the pixel is not saturated. The darker pixel is not influenced and will have a normal response. The Vlevel_s2/3 voltages and different exposure times are programmable using the sequencer registers. Using this feature, a response as detailed in the figure below can be achieved. The placement of the kneepoints in X is controlled by the Vlevel_s2/3 programming, while the slope of the segments is controlled by the programmed exposure times. Saturation level Output signal Kneepoint slope 3 Kneepoint slope 2 # of electrons FIGURE 22: PIECEWISE LINEAR RESPONSE © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 24 of 47 CMV20000 Datasheet 5.2.1.1 P IECEWISE LINEAR RESPONSE WITH INTERNAL EXPOSURE MODE The following registers need to be programmed when a piecewise linear response in internal exposure mode is desired. Register name Exp_time Register address 32-33 Nr_slopes 37[1:0] Exp_s2 39-40 Exp_s3 42-43 Vlevel_s2 114[6:0] Vlevel_s3 115[6:0] HDR settings – PLR Default value Description of the value 3840 The value in this register defines the total exposure time according following formula: ((Exp_time - 1) x 641 + 1 + 47 x FOT_mult) x clk_per, where clk_per is the period of the master input clock. 1 The value in this register defines the number of slopes (min=1, max=3). 0 The value in this register defines the exposure time from the start of the second slope to the end of the total exposure time. Formula: ((Exp_s2 - 1) x 641 + 1 + 47 x FOT_mult) x clk_per, where clk_per is the period of the master input clock. 0 The value in this register defines the exposure time from the start of the third slope to the end of the total exposure time. Formula: ((Exp_s3 - 1) x 641 + 1 + 47 x FOT_mult) x clk_per, where clk_per is the period of the master input clock. 64 Bit[6] = enable Bit[5:0] dac value Low level voltage during dual slope operation. The value in this register defines the Vlevel_s2 voltage (DAC setting). The DAC range goes from 0 to 2.1V. 64 Bit[6] = enable Bit[5:0] dac value Low level voltage during triple slope operation. The value in this register defines the Vlevel_s3 voltage (DAC setting). The DAC range goes from 0 to 2.1V. 5.2.1.2 PIECEWISE LINEAR RESPONSE WITH EXTERNAL EXPOSURE MODE When external exposure time is used and a piecewise linear response is desired, the following registers should be programmed. Register name Nr_slopes_ex Register address 15[1:0] Vlevel_s2_ex 112[6:0] Vlevel_s3_ex 113[6:0] HDR settings – PLR Default value Description of the value 1 The value in this register defines the number of slopes (min=1, max=3). 64 Bit[6] = enable Bit[5:0] dac value Low level voltage during dual slope operation. The value in this register defines the Vlevel_s2 voltage (DAC setting). The DAC range goes from 0 to 2.1V. 64 Bit[6] = enable Bit[5:0] dac value Low level voltage during triple slope operation. The value in this register defines the Vlevel_s3 voltage (DAC setting). The DAC range goes from 0 to 2.1V. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 25 of 47 CMV20000 Datasheet The timing that needs to be applied in this external exposure mode looks like the one below. T_EXP1 FRAME_RE Q Total exposure time Exposure s2 Exposure s3 FIGURE 23: PIECEWISE LINEAR RESPONSE WITH EXTERNAL EXPOSURE MODE 5.3 WINDOWING To limit the amount of data or to increase the frame rate of the sensor, windowing in Y direction is possible. The number of lines and start address can be set by programming the appropriate registers. The CMV20000 has the possibility to read out multiple (max=8) predefined subwindows in one read-out cycle. The default mode is to read-out one window with the full frame size (5120 x 3840). 5.3.1 SINGLE WINDOW When a single window is read out, the start address and size can be uploaded in the corresponding registers. The default start address is 0 and the default size is 3840 (full frame). Register address 24-25 Number_lines_single 26-27 Windowing – single window Default value Description of the value 0 The value in this register defines the start address of the window in Y (min=0, max=3839) 3840 The value in this register defines the number of lines read out by the sensor (min=1, max=3840) 3840 Register name Start_single Number_lines_single Start_single 5120 FIGURE 24: SINGLE WINDOW SETTINGS © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 26 of 47 CMV20000 Datasheet 5.3.2 MULTIPLE WINDOWS The CMV20000 can read out a maximum of 8 different subwindows in one read-out cycle. The location and length of these subwindows must be programmed in the correct registers. The total number of lines to be read-out (sum of all windows) needs to be specified in the Number_lines register. The registers which need to be programmed for the multiple windows can be found in the table below. Register name Multwin_en Register address 44 Number_lines 45-46 Start1 47-48 Number_lines1 63-64 Start2 49-50 Number_lines2 65-66 Start3 51-52 Number_lines3 67-68 Start4 53-54 Number_lines4 69-70 Start5 55-56 Number_lines5 71-72 Start6 57-58 Number_lines6 73-74 Start7 59-60 Number_lines7 75-76 Start8 61-62 Number_lines8 77-78 Windowing – multiple windows Default value Description of the value 0 0: multiple windows mode disabled 1: multiple windows mode enabled 0 The value in this register defines the total number of lines read-out by the sensor (min=1, max=3840) 0 The value in this register defines the start address of the first window in Y (min=0, max=3839) 0 The value in this register defines the number of lines of the first window (min=1, max=3840) 0 The value in this register defines the start address of the second window in Y (min=0, max=3839) 0 The value in this register defines the number of lines of the second window (min=1, max=3840) 0 The value in this register defines the start address of the third window in Y (min=0, max=3839) 0 The value in this register defines the number of lines of the third window (min=1, max=3840) 0 The value in this register defines the start address of the fourth window in Y (min=0, max=3839) 0 The value in this register defines the number of lines of the fourth window (min=1, max=3840) 0 The value in this register defines the start address of the fifth window in Y (min=0, max=3839) 0 The value in this register defines the number of lines of the fifth window (min=1, max=3840) 0 The value in this register defines the start address of the sixth window in Y (min=0, max=3839) 0 The value in this register defines the number of lines of the sixth window (min=1, max=3840) 0 The value in this register defines the start address of the seventh window in Y (min=0, max=3839) 0 The value in this register defines the number of lines of the seventh window (min=1, max=3840) 0 The value in this register defines the start address of the eighth window in Y (min=0, max=3839) 0 The value in this register defines the number of lines of the eighth window (min=1, max=3840) © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 27 of 47 CMV20000 Datasheet Number_lines4 3840 start4 Number_lines3 start3 Number_lines2 start2 Number_lines1 start1 5120 Number_lines = Number_lines1 + Number_lines2 + Number_lines3 + Number_lines4 FIGURE 25: EXAMPLE OF 4 SUBWINDOWS READ-OUT 5.4 IMAGE FLIPPING The image coming out of the image sensor, can be flipped in X and/or Y direction. This means that if flipping is enabled in both directions the upper right pixel is read out first (instead of lower left). The following registers are involved in image flipping Register name Image_flipping Register address 85[1:0] Image flipping Default value Description of the value 0 0: No image flipping 1: Image flipping in X 2: Image flipping in Y 3: Image flipping in X and Y 5.5 IMAGE SUBSAMPLING To maintain the same field of view but reduce the amount of data coming out of the sensor, a subsampling mode is implemented on the chip. Different subsampling schemes can be programmed by setting the appropriate registers. These subsampling schemes can take into account whether a color or monochrome sensor is used to preserve the Bayer pattern information. The registers involved in subsampling are detailed below. A distinction is made between a simple and advanced mode (can be used for color devices). Subsampling can be enabled in every windowing mode. 5.5.1 SIMPLE SUBSAMPLING Register name Number_lines_single Register address 26-27 Sub_s Sub_a 28-29 30-31 Image subsampling - simple Default value Description of the value 3840 The value in this register defines the total number of lines read out by the sensor (min=1, max=3840) 0 Number of rows to skip (min=0, max=3839) 0 Identical to Sub_s © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 28 of 47 CMV20000 Datasheet The figures below give two subsampling examples (skip 4x and skip 1x). Sub_s = 4 Sub_a = 4 Number_lines = sum of red lines Sub_s = 1 Sub_a = 1 Number_lines = sum of red lines FIGURE 26: SUBSAMPLING EXAMPLES (SKIP 4X AND SKIP 1X) 5.5.2 ADVANCED SUBSAMPLING When a color sensor is used, the subsampling scheme should take into account that a Bayer color filter is applied on the sensor. This Bayer pattern should be preserved when subsampling is used. This means that the number of rows to be skipped should always be a multiple of two. An advanced subsampling scheme can be programmed to achieve these requirements. Of course, this advanced subsampling scheme can also be programmed in a monochrome sensor. See the table of registers below for more details. Register name Number_lines_single Register address 26-27 Sub_s Sub_a 28-29 30-31 Image subsampling - advanced Default value Description of the value 3840 The value in this register defines the total number of lines read out by the sensor (min=1, max=3840) 0 Should be ‘0’ at all times 0 Number of rows to skip, it should be an even number between (0 and 3838). The figures below give two subsampling examples (skip 4x and skip 2x) in advanced mode. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 29 of 47 CMV20000 Datasheet Sub_s = 0 Sub_a = 2 Sub_s = 0 Sub_a = 4 Number_lines = sum of red lines Number_lines = sum of red lines FIGURE 27: SUBSAMPLING EXAMPLES IN ADVANCED MODE (SKIP 4X AND SKIP2X) 5.6 NUMBER OF FRAMES When internal exposure mode is selected, the number of frames sent by the sensor after a frame request can be programmed in the corresponding sequencer register. Register name Number_frames Register address 22-23 Number of frames Default value Description of the value 1 The value in this register defines the number of frames grabbed and sent by the image sensor in internal exposure mode (min =1, max = 65535) 5.7 OUTPUT MODE When LVDS output mode is selected, the number of LVDS channels can be selected by programming the appropriate sequencer register. The pixel remapping scheme and the read-out timing for each mode can be found in section 4 of this document. Register name Output_mode Register address 80 Output mode Default value 0 0: 16 outputs 1: 8 outputs Description of the value 5.8 FOT MULTIPLIER The length of the FOT can be programmed using the register below. It is not recommended to set it below 80 as loss in swing and increase in FPN can occur. Register name FOT_mult Register address 82 FOT multiplier Recommended Description of the value value 80 The value in this register defines the length of the FOT according to the following formula: (80 x FOT_mult + FOT_mult/8) x clk_per, where clk_per is the period of the master input clock (min=8, max=248, multiple of 8) © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 30 of 47 CMV20000 Datasheet 5.9 TRAINING PATTERN As detailed in section 4.5, a training pattern is sent over the LVDS data channels whenever no valid image data is sent. This training pattern can be programmed using the sequencer register. Register name Training_pattern Register address 90-91 Training pattern Default value Description of the value 85 The 12 LSBs of this 16 bit word are sent 5.10 TEST PATTERN As detailed in section 4.6, a test pattern can be generated whenever no training data is sent. This test pattern can be enabled using the register below. Register name Testpattern_en Register address 83 Test pattern Default value Description of the value 0 0: test pattern disabled 1: test pattern enabled 5.11 DATA RATE During start-up or after a sequencer reset, the data rate can be changed if a lower speed than 480Mbps is desired. This can be done by applying a lower master input clock (CLK_IN) and lowe LVDS_CLK_N/P to the sensor. See section 3.5 for more details on the input clock. See section 3.7 and 3.8 for details on how and when the data rate can be changed. 5.12 POWER CONTROL The power consumption of the CMV20000 can be regulated by disabling the LVDS data channels when they are not used (in 8 channel mode). Register name Channel_en Register address 95-96 Power control Default value Description of the value 262143 Bits 0-7 enable/disable the bottom data output channels Bits 8-15 enable/disable the top data output channels Bit 16 enables/disables the clock channel Bit 17 enables/disables the control channel Bit 18 enables/disables the clock receiver 0: disabled 1: enabled 5.13 OFFSET AND GAIN 5.13.1 OFFSET A digital offset can be applied to the output signal. The dark level offset can be programmed by setting the desired value in the sequencer registers. The offset register is a 12 bit 2’s complement representation of the actual desired offset to be added or subtracted from a fixed value of 1296. Default offset register value of 2840 is the 2’s complement representation of -1256 default dark level is 1296 + (-1256) = 40. Offset Register name Offset Register address 88-89 Default value 2840 Description of the value The value in this register defines the dark level offset applied to the output signal © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 31 of 47 CMV20000 Datasheet 5.13.2 GAIN An analog gain and ADC gain can be applied to the output signal. The analog gain is applied by a PGA in every column. The digital gain is applied by the ADC. The ADC gain has to be changed when changing the clock speed from 480MHz. Register name Gain Default value PGA_gain Register address 93 bits[3:2] 0 ADC_gain 126 bits[5:0] 32 Description of the value 0: x0.8 1: x1 (recommended) 2: x1.2 3: x1.4 32 Below is the ADC_gain setting vs. the actual gain. When for example you run the sensor at 240MHz, you have to use an actual gain of 480/240 = x2 or value 48 to compensate (the ADC conversion is dependent on the clock speed). FIGURE 28: ADC_GAIN VS ACTUAL GAIN 5.14 TEMPERATURE The register below contains the temperature data. Register name Temperature Register address 101-102 Temperature Default Description of the value value 0 This register contains the temperature data © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 32 of 47 CMV20000 Datasheet 6 REGISTER OVERVIEW The table below gives an overview of all the sensor registers. The registers with the remark “Do not change” should not be changed. Address Default 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 1 0 0 0 0 15 0 0 0 0 32 0 32 0 0 1 0 0 0 0 0 0 1 0 0 0 0 15 0 0 0 0 0 15 0 15 0 1 0 0 0 0 0 0 0 0 Bit[7] Bit[6] Bit[5] Register overview Value Bit[4] Bit[3] Bit[2] Remark Bit[1] Bit[0] Do not change Do not change Do not change Do not change Do not change Do not change Do not change Do not change Do not change Do not change Do not change Do not change Do not change Do not change Do not change Nr_slopes_ex[1:0] Do not change Do not change Do not change Do not change Do not change Do not change Number_frames[7:0] Number_frames[15:8] Start_single[7:0] Start_single[15:8] Number_lines_single[7:0] Number_lines_single[15:8] Sub_s[7:0] Sub_s[15:8] Sub_a[7:0] Sub_a[15:8] Exp_time[7:0] Exp_time[15:8] Do not change Do not change Do not change Nr_slopes[1:0] Do not change Exp_s2[7:0] Exp_s2[15:8] Do not change Exp_s3[7:0] Exp_s3[15:8] Multwin_en Number_lines[7:0] © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 33 of 47 CMV20000 Datasheet Address Default Bit[7] 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 129 0 0 254 24 11 85 0 0 0 136 255 255 3 Bit[6] Bit[5] Register overview Value Bit[4] Bit[3] Bit[2] Number_lines[15:8] Start1[7:0] Start1[15:8] Start2[7:0] Start2[15:8] Start3[7:0] Start3[15:8] Start4[7:0] Start4[15:8] Start5[7:0] Start5[15:8] Start6[7:0] Start6[15:8] Start7[7:0] Start7[15:8] Start8[7:0] Start8[15:8] Number_lines1[7:0] Number_lines1[15:8] Number_lines2[7:0] Number_lines2[15:8] Number_lines3[7:0] Number_lines3[15:8] Number_lines4[7:0] Number_lines4[15:8] Number_lines5[7:0] Number_lines5[15:8] Number_lines6[7:0] Number_lines6[15:8] Number_lines7[7:0] Number_lines7[15:8] Number_lines8[7:0] Number_lines8[15:8] Remark Bit[1] Bit[0] Do not change Output_mode Exp_ext FOT_mult[7:0] Testpattern_en Set to 131 Image_flipping[1:0] Set to 3 Set to 0 Offset[7:0] Offset[11:8] Training_pattern[7:0] Training_pattern[15:8] Do not change PGA_Gain[3:2) Set to 72 Channel_en[7:0] Channel_en[15:8] Channel_en[18:16] © 2015 CMOSIS bvba Set to 7 Reference:CMV20000-datasheet-v2.3 Page 34 of 47 CMV20000 Datasheet Address Default Bit[7] Bit[6] Bit[5] Register overview Value Bit[4] Bit[3] Bit[2] Remark Bit[1] 98 0 99 0 100 0 101 0 Temp[7:0] 102 0 Temp[15:8] 103 136 104 136 105 136 106 96 107 96 108 96 109 96 110 64 111 64 112 64 Vlevel_s2_ex[6:0] 113 64 Vlevel_s3_ex[6:0] 114 64 Vlevel_s2[6:0] 115 64 Vlevel_s3[6:0] 116 96 117 96 118 96 119 96 120 96 121 255 122 255 123 64 124 0 125 0 126 32 ADC_gain[5:0] 127 32 Note: The default value of the “do not change” registers should not be overwritten. © 2015 CMOSIS bvba Bit[0] Do not change Do not change Do not change Do not change Do not change Set to 64 Set to 102 Set to 68 Do not change Do not change Set to 228 Set to 210 Do not change Do not change Set to 91 Set to 91 Do not change Do not change Do not change Set to 47 Do not change Set to 102 Do not change Do not change Do not change Reference:CMV20000-datasheet-v2.3 Page 35 of 47 CMV20000 Datasheet 7 MECHANICAL SPECIFICATIONS 7.1 PACKAGE DRAWING TOP VIEW BOTTOM VIEW FIGURE 29: PACKAGE DRAWING OF THE CMV20000. ALL DISTANCES IN MM. Package tolerances and alignment are: Tilt image sensor : +/- 0.05 degree Rotation image sensor : +/- 0.3 degree Placement image sensor : +/- 150 um Alignment image sensor to the top of the package : 1 mm +/- 0.13 mm Pin alignment tolerances are specified as 1% however tolerances measured are 0.18% max. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 36 of 47 CMV20000 Datasheet 7.2 ASSEMBLY DRAWING FIGURE 30: ASSEMBLY DRAWING OF CMV20000 © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 37 of 47 CMV20000 Datasheet 7.3 COVER GLASS The cover glass of the CMV20000 has following specifications: Reflection(abs) <= 1.5% @ 400 – 900 nm (per surface), Angle Off Interest = 15O 2 sides AR-coated When a color sensor is used an IR-cutoff filter should be placed in the optical path of the sensor. 7.4 COLOR FILTERS When a color version of the CMV20000 is used, the color filters are applied in a Bayer pattern. The color version of the CMV20000 always has micro lenses. The use of an IR cut-off filter in the optical path of the CMV20000 image sensor is necessary to obtain good color separation when using light with an IR component. A RGB Bayer pattern is used on the CMV20000 image sensor. The order of the RGB filter can be found in the drawing below. FIGURE 31: RGB BAYER PATTERN ORDER © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 38 of 47 CMV20000 Datasheet 7.5 QE AND SPECTRAL RESPONSE The typical QE and spectral response of the CMV20000 color/monochrome with micro lenses and cover glass can be found below. Quantum Efficiency 80 BLUE GREEN1 GREEN2 70 RED Mono 60 40 30 20 10 0 350 450 550 650 750 Wavelength [nm] 850 950 1050 FIGURE 32: TYPICAL QE OF THE CMV20000 Spectral Response 0.35 BLUE GREEN1 GREEN2 RED 0.30 Mono 0.25 Spectral Response [A\W] Quantum Efficiency [%] 50 0.20 0.15 0.10 0.05 0.00 350 450 550 650 750 Wavelength [nm] 850 FIGURE 33: TYPICAL SPECTRAL RESPONSE OF THE CMV20000 © 2015 CMOSIS bvba 950 1050 Reference:CMV20000-datasheet-v2.3 Page 39 of 47 CMV20000 Datasheet 7.6 ANGULAR RESPONSE 100 Horizontal 90 Vertical 80 70 Relative response [%] 60 50 40 30 20 10 -45 -35 -25 -15 0 -5 5 Angle of incoming light [°] FIGURE 34: ANGULAR RESPONSE © 2015 CMOSIS bvba 15 25 35 45 Reference:CMV20000-datasheet-v2.3 Page 40 of 47 CMV20000 Datasheet 8 PIN LIST Pin number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C16 C17 C18 D1 Pin name Description Type OUTE1_P VDD20 OUTE2_P VDD20 OUTE3_P VDDPIX OUTE4_P GND OUTE5_N VDD20 OUTE6_N VDDPIX OUTE7_N GND OUTE8_N VDD20 CMD_LVDS DIO2 OUTE1_N GND OUTE2_N GND OUTE3_N GND OUTE4_N VDD33 OUTE5_P GND OUTE6_P GND OUTE7_P VDD33 OUTE8_P GND CMD_COL_AMPL TANA OUTCTR_N DIO1 GND CMDN CMD_COL_PC TDIG2 LVDS output Supply LVDS output Supply LVDS output Supply LVDS output Ground LVDS output Supply LVDS output Supply LVDS output Ground LVDS output Supply Bias Test LVDS output Ground LVDS output Ground LVDS output Ground LVDS output Supply LVDS output Ground LVDS output Ground LVDS output Supply LVDS output Ground Bias Analog output LVDS output Test Ground Bias Bias Digital output D2 D3 OUTCTR_P TDIG1 D16 D17 D18 E1 CMDP CMDP_INV CMD_ADC Extra1 LVDS positive output data even rows channel1 bottom 2.1V supply LVDS positive output data even rows channel2 bottom 2.1V supply LVDS positive output data even rows channel3 bottom 2.3V -> 3.3V DEFAULT 2.8V supply LVDS positive output data even rows channel4 bottom Ground pin LVDS negative output data even rows channel5 bottom 2.1V supply LVDS negative output data even rows channel6 bottom 2.3V -> 3.3V DEFAULT 2.8V supply LVDS negative output data even rows channel7 bottom Ground pin LVDS negative output data even rows channel8 bottom 2.1V supply decouple with 470nF to ground Diode 2 for test (connect to GND) LVDS negative output data even rows channel1 bottom Ground pin LVDS negative output data even rows channel2 bottom Ground pin LVDS negative output data even rows channel3 bottom Ground pin LVDS negative output data even rows channel4 bottom 3.3V supply LVDS positive output data even rows channel5 bottom Ground pin LVDS positive output data even rows channel6 bottom Ground pin LVDS positive output data even rows channel7 bottom 3.3V supply LVDS positive output data even rows channel8 bottom Ground pin decouple with 470nF to ground Test pin for analog signals ( can be left floating ) LVDS negative control output channel Diode 1 for test (connect to GND) Ground pin decouple with 470nF to ground decouple with 470nF to ground Test pin Test pin for digital signals ( can be left floating or route to an input pin of the FPGA )for digital signals LVDS positive control output channel Test pin for digital signals ( can be left floating or route to an input pin of the FPGA ) decouple with 470nF to VDD33 decouple with 470nF to VDD33 decouple with 470nF to VDD33 Leave floating © 2015 CMOSIS bvba LVDS output Digital output Bias Bias Bias Reference:CMV20000-datasheet-v2.3 Page 41 of 47 CMV20000 Datasheet Pin number E2 E3 E16 E17 E18 F1 F2 F3 F16 F17 F18 G1 G2 G3 G16 G17 G18 H1 H2 H3 H16 H17 H18 J1 J2 J3 J16 J17 Pin name Description Extra2 FRAME_REQ VBGAP VBGAP_LOW CMD_COL_LOAD STRB_EXP1 VDD20 GND GND VDD20 REF_ADC VDDPIX GND VDD33 VDD33 GND VDDPIX Extra6 T_EXP1 GND GND VREF CMD_RAMP PLL_REF PLL_REF_LOW GND GND VRAMP2 J18 K1 K2 K3 K16 K17 K18 L1 L2 L3 L16 L17 L18 M1 M2 M3 M16 M17 M18 N1 N2 N3 N16 N17 VRAMP1 VDDPIX GND VDD33 VDD33 GND VDDPIX LVDS_CLK_P VDD20 GND GND VDD20 SIG_ADC LVDS_CLK_N CLK_IN SYS_RES_N VTF_LOW3 VTF_LOW2 VTF_LOW1 Extra3 OUTCLK_P Extra4 VRES_L VRES_H Connect to GND Frame request decouple with 470nF to VBGAP_LOW decouple to VBGAP see pin E16 decouple with 470nF to ground Output strobe pin for the exposure time 2.1V supply Ground pin Ground pin 2.1V supply Ref for ADC testing (decouple with 470nF to ground) 2.3V -> 3.3V DEFAULT 2.8V supply Ground pin 3.3V supply 3.3V supply Ground pin 2.3V -> 3.3V DEFAULT 2.8V supply Connect to GND Input pin for external exposure mode Ground pin Ground pin Ref for column amps (decouple with 470nF to ground) decouple with 470nF to VDD33 decouple with 470nF to PLL_REF_LOW decouple to PLL_REF see pin J1 Ground pin Ground pin Start voltage second ramp (decouple with 470nF to ground) Start voltage first ramp (decouple with 470nF to ground) 2.3V -> 3.3V DEFAULT 2.8V supply Ground pin 3.3V supply 3.3V supply Ground pin 2.3V -> 3.3V DEFAULT 2.8V supply LVDS input clock P 2.1V supply Ground pin Ground pin 2.1V supply Sig for ADC testing (decouple with 470nF to ground) LVDS input clock N Master input clock Input pin for sequencer reset Transfer low voltage 3 (decouple with 470nF to ground) Transfer low voltage 2 (decouple with 470nF to ground) Transfer low voltage 1 (decouple with 470nF to ground) Connect to GND LVDS positive clock output channel connect to GND Res low voltage (decouple with 470nF to ground) 3.3V supply or highest supply voltage © 2015 CMOSIS bvba Type Digital input Bias Bias Bias Digital output Supply Ground Ground Supply Bias Supply Ground Supply Supply Ground Supply Digital input Ground Ground Bias Bias Bias Bias Ground Ground Bias Bias Supply Ground Supply Supply Ground Supply LVDS input Supply Ground Ground Supply Bias LVDS input Digital input Digital input Bias Bias Bias LVDS output Bias Supply Reference:CMV20000-datasheet-v2.3 Page 42 of 47 CMV20000 Datasheet Pin number N18 P1 P2 P3 P16 P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 Pin name Description Type VPCH_L SPI_EN OUTCLK_N SPI_IN GND GND VPCH_H SPI_CLK OUTO1_N GND OUTO2_N GND OUTO3_N GND OUTO4_N VDD33 OUTO5_P GND OUTO6_P GND OUTO7_P VDD33 OUTO8_P GND SPI_OUT_RIGHT Bias Digital input LVDS output Digital input Ground Ground Bias Digital input LVDS output Ground LVDS output Ground LVDS output Ground LVDS output Supply LVDS output Ground LVDS output Ground LVDS output Supply LVDS output Ground Digital output T1 SPI_OUT_LEFT Precharge low voltage (decouple with 470nF to ground) SPI enable LVDS negative clock output channel SPI data input pin Ground pin Ground pin Precharge high voltage (decouple with 470nF to ground) SPI clock input pin LVDS negative output data odd rows channel1 top Ground pin LVDS negative output data odd rows channel2 top Ground pin LVDS negative output data odd rows channel3 top Ground pin LVDS negative output data odd rows channel4 top 3.3V supply LVDS positive output data odd rows channel5 top Ground pin LVDS positive output data odd rows channel6 top Ground pin LVDS positive output data odd rows channel7 top 3.3V supply LVDS positive output data odd rows channel8 top Ground pin SPI data output pin at the right, this is a backup SPI data output pin. Only the spi output data of register >= address 103 are available at this pin. Should be routed to the FPGA as well SPI data output pin at the left, this is the main SPI data output pin containing the SPI output data of all registers. T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 OUTO1_P VDD20 OUTO2_P VDD20 OUTO3_P VDDPIX OUTO4_P GND OUTO5_N VDD20 OUTO6_N VDDPIX OUTO7_N GND OUTO8_N VDD20 Extra5 LVDS positive output data odd rows channel1 top 2.1V supply LVDS positive output data odd rows channel2 top 2.1V supply LVDS positive output data odd rows channel3 top 2.3V -> 3.3V DEFAULT 2.8V supply LVDS positive output data odd rows channel4 top Ground pin LVDS negative output data odd rows channel5 top 2.1V supply LVDS negative output data odd rows channel6 top 2.3V -> 3.3V DEFAULT 2.8V supply LVDS negative output data odd rows channel7 top Ground pin LVDS negative output data odd rows channel8 top 2.1V supply connect to GND LVDS output Supply LVDS output Supply LVDS output Supply LVDS output Ground LVDS output Supply LVDS output Supply LVDS output Ground LVDS output Supply © 2015 CMOSIS bvba Digital output Reference:CMV20000-datasheet-v2.3 Page 43 of 47 CMV20000 Datasheet 9 SPECIFICATION OVERVIEW Specification Effective pixels Pixel pitch Imager size Full well charge Conversion gain Temporal noise (analog domain) Dynamic range Pixel type Value 5120 x 3840 6.4 x 6.4 µm2 2 32.77x24.58m m 15 Ke0.25 DN/e8 e- Shutter type Pipelined global shutter 1/50 000 Parasitic light sensitivity Shutter efficiency Color filters Micro lenses QE * FF Dark current signal DSNU Fixed pattern noise (RMS) PRNU (RMS) LVDS Output channel Frame rate 66 dB Global shutter pixel Optional Yes 60.00% 125e/s @ RT 10e/s <0.2% full swing 1% 16 30 frames/s PGA Programmable Registers Yes Sensor parameters Supported HDR modes ADC Interface I/O logic levels Multi-slope Power Package Operating range Cover glass Allows fixed pattern noise correction and reset (kTC) noise canceling through correlated double sampling. Exposure of next image during readout of the previous image. @ 550 nm with micro lenses. On-chip Clock inputs Pinned photodiode pixel. At recommended settings Pipelined global shutter (GS) with correlated double sampling ( CDS ) RGB Bayer Timing generation Supply voltages Comment 12bit LVDS LVDS = 2.1V Logic levels = 3.3V 2.1 & 3.3 V 40MHz CLK_IN 480MHz LVDS_CLK_N/P 1100 mW Ceramic package -20C to +70C Each data output running @ 480 Mbit/s. 8 outputs selectable at half frame rate Using a 12bit/pixel and 480 Mbit/s LVDS. Higher frame rate possible in row windowing mode. Possibility to control exposure time through external pin. 4 analog gain settings Window coordinates, Timing parameters, Gain & offset, Exposure time, flipped readout in x and y direction … Multiple slopes with partial reset of the pixel. Column ADC Serial output data + synchronization signals 3.3V for the pixel array and analog circuits 2.1V for digital circuits and the LVDS drivers Custom ceramic PGA ( 143 pins ) Dark current and noise performance will degrade at higher temperature 2 sides ARC © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 44 of 47 CMV20000 Datasheet 10 ORDERING INFO Part Number Chroma Microlens Package Glass CMV20000-1E5M1PA CMV20000-1E5C1PA Mono RGB Bayer yes yes Ceramic PGA Ceramic PGA AR coated AR coated On request the package and cover glass can be customized. For options, pricing and delivery time please contact [email protected]. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 45 of 47 CMV20000 Datasheet 11 HANDLING AND SOLDERING PROCEDURE 11.1 SOLDERING 11.1.1 WAVE SOLDERING Wave soldering is possible but not recommended. Solder dipping can cause damage to the glass and harm the imaging capability of the device. See the figure below for the wave soldering profile. Max 10 s Temperature (C) 260 25 Time (s) 11.1.2 REFLOW SOLDERING The figure below shows the maximum recommended thermal profile for a reflow soldering system. If the temperature/time profile exceeds these recommendations, damage to the image sensor can occur. 60 to 80 seconds 10 to 20 sec Temperature (C) 250 220 200 150 60 to 180 seconds 25 Maximum 6 min Time (s) 11.1.3 SOLDERING RECOMMENDATIONS Image sensors with color filter arrays (CFA) and micro-lenses are especially sensitive to high temperatures. Prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. Best solution will be © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 46 of 47 CMV20000 Datasheet flow soldering or manual soldering of a socket (through hole or BGA) and plug in the sensor at latest stage of the assembly/test process. 11.2 HANDLING IMAGE SENSORS General application note AN03 contains more details and procedures. 11.2.1 ESD The following are the recommended minimum ESD requirements when handling image sensors. 1. 2. 3. Ground workspace (tables, floors…) Ground handling personnel (wrist straps, special footwear…) Minimize static charging (control humidity, use ionized air, wear gloves…) 11.2.2 GLASS CLEANING When cleaning of the cover glass is needed we recommend the following two methods. 1. 2. Blowing off the particles with ionized nitrogen Wipe clean using IPA (isopropyl alcohol) and ESD protective wipes. 11.2.3 IMAGE SENSOR STORING Image sensors should be stored under the following conditions 1. 2. 3. 4. Dust free Temperature 20°C to 40°C Humidity between 30% and 60%. Avoid radiation, electromagnetic fields, ESD, mechanical stress 11.2.4 EXCESSIVE LIGHT Excessive light falling on the sensor can cause heating up the micro lenses and color filters. This heat can cause deforming of the lenses and/or deterioration of the lenses and color filters by making them more opaque, increasing the heat up even more. Avoid shining high intensity light upon the sensors for extended periods of time. In case of lasers, they can cause heat up but can also damage the silicon die itself. © 2015 CMOSIS bvba Reference:CMV20000-datasheet-v2.3 Page 47 of 47 CMV20000 Datasheet 12 ADDITIONAL INFORMATION For any additional questions related to the operation and specification of the CMV20000 imagers or feedback with respect to the present data sheet please contact [email protected]. © 2015 CMOSIS bvba