ON NCP720BMT150TBG Very low dropout bias rail cmos voltage regulator Datasheet

NCP720
350mA, Very Low Dropout
Bias Rail CMOS Voltage
Regulator
The NCP720 is a 350 mA VLDO equipped with NMOS pass
transistor and a separate bias supply voltage (VBIAS). The device
provides very stable, accurate output voltage with low noise suitable
for space constrained, noise sensitive applications. In order to
optimize performance for battery operated portable applications, the
NCP720 features low IQ consumption. The WDFN6 2 mm x 2 mm
package is optimized for use in space constrained applications.
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T
MARKING
DIAGRAM
WDFN6
CASE 511BR
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range: 0.8 V to 5.5 V
Bias Voltage Range: 2.4 V to 5.5 V
Fixed Output Voltage Device
Output Voltage Range: 0.8 V to 2.1 V
±2% Accuracy over Temperature
Ultra−Low Dropout: 110 mV typically at 350 mA
Very Low Bias Input Current of Typ. 80 mA
Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA
Low Noise, High PSRR
Built−In Soft−Start with Monotonic VOUT Rise
Stable with a 2.2 mF Ceramic Capacitor
Available in WDFN6 − 2 mm x 2 mm Package
These are Pb−Free Devices
Typical Applications
1
XX M
XX = Specific Device Code
M = Date Code
PIN CONNECTIONS
OUT
6
1
NC
2
EN
3
Thermal
Pad
IN
5
GND
4
BIAS
(Top VIew)
• Battery−powered Equipment
• Smartphones, Tablets
• Cameras, DVRs, STB and Camcorders
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 8 of this data sheet.
VBIAS
NCP720
BIAS
VIN
OUT
IN
VOUT
1.5 V @ 350 mA
2.2 mF
EN
GND
VEN
Figure 1. Typical Application Schematics
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 1
1
Publication Order Number:
NCP720/D
NCP720
CURRENT
LIMIT
IN
OUT
ENABLE
BLOCK
EN
UVLO
BIAS
VOLTAGE
REFERENCE
+
−
THERMAL
LIMIT
GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
1
OUT
Regulated Output Voltage pin
2
N/C
Not internally connected
3
EN
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode.
4
BIAS
Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage Lockout Circuit.
5
GND
Ground pin
6
IN
Pad
Description
Input Voltage Supply pin
Should be soldered to the ground plane for increased thermal performance.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
−0.3 to 6
V
VOUT
−0.3 to (VIN+0.3) ≤ 6
V
VEN, VBIAS
−0.3 to 6
V
Output Short Circuit Duration
tSC
unlimited
s
Maximum Junction Temperature
TJ
150
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Input Voltage (Note 1)
Output Voltage
Chip Enable and Bias Input
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, WDFN6 2 mm x 2 mm Thermal Resistance, Junction−to−Air (Note 3)
RqJA
65
°C/W
3. This data was derived by thermal simulations based on the JEDEC JESD51 series standards methodology. Only a single device mounted
at the center of a high*K (2s2p) 3in x 3in multilayer board with 1−ounce internal planes and 2−ounce copper on top and bottom. Top copper
layer has a dedicated 125 sqmm copper area.
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2
NCP720
ELECTRICAL CHARACTERISTICS
Over Operating Temperature Range (TJ = −40°C to +125°C), VBIAS = (VOUT + 1.4 V) or 2.5 V, whichever is greater; VIN ≥ VOUT + 0.5 V,
IOUT = 1 mA, VEN = 1.1 V, COUT = 2.2 mF, unless otherwise noted. Typical values are at TJ = +25°C.
Parameter
Test Conditions
Symbol
Min
Operating Input Voltage Range
VIN
Operating Bias Voltage Range
VBIAS
Output Voltage Range (Note 4)
Output
Voltage
Accuracy
Nominal
TJ = +25°C
Max
Unit
VOUT +
VDO_IN
5.5
V
(VOUT + 1.4)
≥ 2.4
5.5
V
0.8
2.1
V
±0.5
VOUT
V
+ 1.4 V ≤ VBIAS ≤ 5.5 V,
Over VBIAS, VIN, IOUT, OUT
VOUT + 0.5 V ≤ VIN ≤ 4.5 V,
TJ = –40°C to +125°C
0mA ≤ IOUT ≤ 350 mA
VOUT
Typ
-2
%
+2
%
DVOUT/DVIN
5.0
mV/V
DVOUT/DVBIAS
16
mV/V
0 mA ≤ IOUT ≤ 350 mA (no load to full load) DVOUT/DIOUT
–1.0
mV/mA
VIN Dropout Voltage (Note 5)
VIN = VOUT(NOM) – 0.1 V,
(VBIAS – VOUT(NOM)) = 1.4 V,
IOUT = 350 mA
110
VBIAS Dropout Voltage (Note 6)
VIN = VOUT(NOM) + 0.3 V, IOUT = 350 mA
Output Current Limit
VOUT = 0.9 x VOUT(NOM)
ICL
Bias Pin Current
IOUT = 0 mA to 350 mA
Shutdown Current (IGND)
VEN ≤ 0.4 V, TJ = -40°C to +85°C
VIN Line Regulation
VIN = (VOUT + 0.5 V) to 4.5 V, IOUT = 1mA
VBIAS Line Regulation
VBIAS = (VOUT + 1.4 V) or 2.5 V (whichever is greater) to 5.5 V, IOUT = 1 mA
Load Regulation
VIN – VOUT ≥ 0.5 V,
VIN Power-Supply Rejection Ratio VBIAS = VOUT + 1.4 V,
IOUT = 350 mA
VBIAS Power-Supply Rejection
Ratio
Output Noise Voltage
VDO_IN
VDO_BIAS
VIN – VOUT ≥ 0.5 V,
VBIAS = VOUT + 1.4 V,
IOUT = 350 mA
mA
IBIAS
80
110
mA
ISHDN
0.5
2.0
mA
56
65
PSRR (VIN)
37
f = 1 MHz
25
f = 10 Hz
65
f = 100 Hz
65
f = 1 kHz
f = 10 kHz
70
PSRR (VBIAS)
35
f = 1 MHz
24
VN
Enable Pin Low (disabled)
Enable Pin Current
VEN = 5.5 V
Undervoltage Lock-out
VBIAS rising
Hysteresis
VBIAS falling
100 +
tSTR
VEN(HI)
1.1
VEN(LO)
0
IEN
Reset, temperature decreasing
Operating Junction Temperature
mA
140
ms
V
0.4
V
1
mA
1.6
TSD
TJ
ILOAD
0.3
UVLO
Shutdown, temperature increasing
mVRMS
40
IVIN_INRUSH
VOUT = 95% VOUT(NOM), IOUT = 350 mA,
COUT = 2.2 mF
dB
50
f = 100 kHz
BW = 10 Hz to 100 kHz
dB
46
f = 100 kHz
Enable Pin High (enabled)
Thermal Shutdown Temperature
V
800
f = 100 Hz
Inrush Current on VIN
Startup Time
1.4
525
52
f = 10 kHz
mV
1.15
420
f = 10 Hz
f = 1 kHz
200
V
0.2
V
+160
°C
°C
+140
–40
+125
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. VOUT nominal value is factory programmable.
5. Measured for devices with VOUT(NOM) ≥ 1.2V.
6. VBIAS – VOUT with VOUT = VOUT(NOM) – 0.1V.
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NCP720
APPLICATIONS INFORMATION
.
VBAT
NCP720
EN
DC/DC
BIAS
LX
IN
EN
Processor
OUT
IN
LOAD
GND
FB
GND
I/O
I/O
To other circuits
Figure 3. Typical Application: Low−Voltage Post−Regulator with ON/OFF functionality
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NCP720
TYPICAL CHARACTERISTICS
VOUT(NOMINAL) = 1.5 V, VBIAS = (VOUT + 1.4 V) or 2.5 V, whichever is greater, VIN = VOUT + 0.5 V, IOUT = 1 mA,
VEN = 1.1 V, COUT = 2.2 mF, TJ = 25°C unless otherwise noted.
Figure 4. VIN Dropout Voltage vs. Output
Current
Figure 5. VBIAS Dropout Voltage vs.
Temperature
Figure 6. Output Voltage vs. Temperature
Figure 7. Bias Pin Current vs. VBIAS Input
Voltage
Figure 8. Bias Pin Current vs. Output Current
Figure 9. Bias Pin Current vs. Temperature
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NCP720
TYPICAL CHARACTERISTICS
VOUT(NOMINAL) = 1.5 V, VBIAS = (VOUT + 1.4 V) or 2.5 V, whichever is greater, VIN = VOUT + 0.5 V, IOUT = 1 mA,
VEN = 1.1 V, COUT = 2.2 mF, TJ = 25°C unless otherwise noted.
Figure 10. Shutdown Current vs. VBIAS Input
Voltage
Figure 11. Current Limit vs. VBIAS Input
Voltage
Figure 12. Current Limit vs. VIN Input Voltage
Figure 13. VIN Power Supply Ripple Rejection
vs. Frequency
VOUT
50mV/div
300 mA
IOUT
100mA/div
tRISE = 1 ms
0 mA
Figure 14. VBIAS Power Supply Ripple
Rejection vs. Frequency
Figure 15. Load Transient Response
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NCP720
APPLICATIONS INFORMATION
example), the recommended CIN = 1 mF and CBIAS = 0.1 mF
or greater. Ceramic capacitors are recommended. For the
best performance all the capacitors should be connected to
the NCP720 respective pins directly in the device PCB
copper layer, not through vias having not negligible
impedance.
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
The NCP720 dual−rail very low dropout voltage regulator
is using NMOS pass transistor for output voltage regulation
from VIN voltage. All the low current internal controll
circuitry is powered from the VBIAS voltage.
The use of an NMOS pass transistor offers several
advantages in applications. Unlike a PMOS topology
devices, the output capacitor has reduced impact on loop
stability. VIN to VOUT operating voltage difference can be
very low compared with standard PMOS regulators in very
low VIN applications.
The NCP720 offers built−in Soft−Start with monotonic
VOUT rise. The controlled voltage rising limits the inrush
current.
The Enable (EN) input is equipped with internal
hysteresis.
NCP720 is a Fixed Voltage linear regulator.
Enable Operation
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. If the enable function is not to be used
then the pin should be connected to VIN or VBIAS. When
enabled, the device consumes roughly 20 mA from Vin
supply per 1 V nominal output voltage. That is why using the
enable / disable function in power saving applications is
recommended.
Dropout Voltage
Because of two power supply inputs VIN and VBIAS and
one VOUT regulator output, there are two Dropout voltages
specified.
The first, the VIN Dropout voltage is the voltage
difference (VIN – VOUT) at which the regulator output no
longer maintains regulation against further reductions in
input voltage. VBIAS is high enough, specific value is
published in the Electrical Characteristics table.
The second, VBIAS dropout voltage is the voltage
difference (VBIAS – VOUT) at which the regulator output no
longer maintains regulation against further reductions in
VBIAS voltage. VIN is high enough.
Current Limitation
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated , the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
Input and Output Capacitors
The device is designed to be stable for ceramic output
capacitors with Effective capacitance in the range from
2.2 mF to 10 mF. The device is also stable with multiple
capacitors in parallel, having the total effective capacitance
in the specified range.
In applications where no low input supplies impedance
available (PCB inductance in VIN and/or VBIAS inputs as
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7
NCP720
ORDERING INFORMATION
Nominal Output
Voltage
Marking
NCP720BMT100TBG
1.00 V
JC
NCP720BMT105TBG
1.05 V
JD
NCP720BMT1110TBG
1.10 V
JE
NCP720BMT115TBG
1.15 V
JF
NCP720BMT120TBG
1.20 V
JG
NCP720BMT125TBG
1.25 V
JH
NCP720BMT130TBG
1.30 V
JJ
NCP720BMT135TBG
1.35 V
JK
NCP720BMT140TBG
1.40 V
JL
NCP720BMT145TBG
1.45 V
JM
NCP720BMT150TBG
1.50 V
JA
NCP720BMT160TBG
1.60 V
JP
NCP720BMT170TBG
1.70 V
JQ
NCP720BMT180TBG
1.80 V
JR
Device
Package
Shipping†
WDFN6
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
To order other package and voltage variants, please contact your ON sales representative
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8
NCP720
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511BR
ISSUE O
D
PIN ONE
REFERENCE
0.10 C
EXPOSED Cu
MOLD CMPD
DETAIL B
ÍÍÍ
ÍÍÍ
ÍÍÍ
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25 mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÇÇÇ
ÉÉÉ
A
B
ALTERNATE
CONSTRUCTIONS
E
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
L
L
L1
TOP VIEW
DETAIL A
DETAIL B
0.05 C
ALTERNATE
CONSTRUCTIONS
A3
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
2.00 BSC
1.50
1.70
2.00 BSC
0.90
1.10
0.65 BSC
0.20
0.40
--0.15
A
6X
0.05 C
A1
NOTE 4
C
SIDE VIEW
RECOMMENDED
MOUNTING FOOTPRINT
SEATING
PLANE
1.72
6X
0.45
D2
DETAIL A
1
L
3
1.12
E2
6
4
6X
e
BOTTOM VIEW
PACKAGE
OUTLINE
b
0.10
M
C A
0.05
M
C
2.30
1
B
6X
NOTE 3
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
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For additional information, please contact your local
Sales Representative
NCP720/D
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