LM1815 www.ti.com SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 LM1815 Adaptive Variable Reluctance Sensor Amplifier Check for Samples: LM1815 FEATURES DESCRIPTION • • • • • • The LM1815 is an adaptive sense amplifier and default gating circuit for motor control applications. The sense amplifier provides a one-shot pulse output whose leading edge coincides with the negativegoing zero crossing of a ground referenced input signal such as from a variable reluctance magnetic pick-up coil. 1 2 • Adaptive Hysteresis Single Supply Operation Ground Referenced Input True Zero Crossing Timing Reference Operates from 2V to 12V Supply Voltage Handles Inputs from 100 mVP-P to over 120VP-P with External Resistor CMOS Compatible Logic APPLICATIONS • • • • • Position Sensing with Notched Wheels Zero Crossing Switch Motor Speed Control Tachometer Engine Testing In normal operation, this timing reference signal is processed (delayed) externally and returned to the LM1815. A Logic input is then able to select either the timing reference or the processed signal for transmission to the output driver stage. The adaptive sense amplifier operates with a positivegoing threshold which is derived by peak detecting the incoming signal and dividing this down. Thus the input hysteresis varies with input signal amplitude. This enables the circuit to sense in situations where the high speed noise is greater than the low speed signal amplitude. Minimum input signal is 150mVP-P. Connection Diagram Figure 1. Top View 14-Lead SOIC or PDIP See D or NFF0014A Package These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated LM1815 SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) Supply Voltage 12V Power Dissipation (3) 1250 mW Operating Temperature Range −40°C ≤ TA ≤ +125°C Storage Temperature Range −65°C ≤ TJ ≤ +150°C Junction Temperature +150°C Input Current ±30 mA Lead Temperature (Soldering, 10 sec.) (1) (2) (3) 260°C “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. For operation at elevated temperatures, the device must be derated based on a 150°C maximum junction temperature and a thermal resistance of 80°C/W (DIP), 120°C/W (SO-14) junction to ambient. Electrical Characteristics (TA = 25°C, VCC = 10V, unless otherwise specified, see Figure 17) Parameter Conditions Operating Supply Voltage Min 2.5 Typ Max Units 10 12 V 3.6 6 mA 100 130 µs 5 µA Supply Current Pin 3 = -0.1V, Pin 9 = 2V, Pin 11 = 0.8V Reference Pulse Width fIN = 1Hz to 2kHz, R = 150kΩ, C = 0.001µF Logic Input Bias Current VIN = 2V, (Pin 9 and Pin 11) Signal Input Bias Current VIN = 0V dc, (Pin 3) Logic Threshold (Pin 9 and Pin 11) 0.8 1.1 VOUT High RL = 1kΩ, (Pin 10) 7.5 8.6 VOUT Low ISINK = 0.1mA, (Pin 10) 0.3 0.4 V Output Leakage Pin 12 V12 = 11V 0.01 10 µA Saturation Voltage P12 I12 = 2mA 0.2 0.4 V Input Zero Crossing Threshold All Modes, VSIGNAL = 1V pk-pk -25 0 25 mV (1) Mode 1, Pin 5 = Open 30 45 60 mV (1) Mode 2, Pin 5 = VCC 200 300 450 mV (1) Mode 3, Pin 5 = Gnd -25 0 25 mV (1) Mode 1, Pin 5 = Open VSIGNAL ≥ 230mV pk-pk (2) 40 80 90 % (1) Minimum Input Arming Threshold Adaptive Input Arming Threshold (1) (2) 2 70 -200 nA 2.0 V V Mode 2, Pin 5 = VCC VSIGNAL ≥ 1.0V pk-pk (2) 80 % (1) Mode 3, Pin 5 = Gnd VSIGNAL ≥ 150mV pk-pk (2) 80 % (1) The Min/Typ Max limits are relative to the positive voltage peak seen at VIN Pin 3. Tested per Figure 17, VSIGNAL is a Sine Wave; FSIGNAL is 1000Hz. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM1815 LM1815 www.ti.com SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 Typical Performance Characteristics Mode 1 Minimum Arming Threshold vs Temperature Mode 2 Minimum Arming Threshold vs Temperature Figure 2. Figure 3. Mode 3 Minimum Arming Threshold vs Temperature Mode 1 Minimum Arming Threshold vs VCC Figure 4. Figure 5. Mode 2 Minimum Arming Threshold vs VCC Pin 3 VIN vs VSIGNAL Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM1815 3 LM1815 SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 4 Pin 3 VIN vs VSIGNAL, RIN = 10kΩ Pin 3 VIN vs VSIGNAL, RIN = 20kΩ Figure 8. Figure 9. Pin 3 VIN vs VSIGNAL, RIN = 50kΩ Pin 3 Bias Current vs Temperature Figure 10. Figure 11. Peak Detector Charge Current vs Temperature Peak Detector Charge Current vs VCC Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM1815 LM1815 www.ti.com SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Peak Detector Voltage vs Pin 3 VIN, Mode 1 Peak Detector Voltage vs Pin 3 VIN, Mode 2 Figure 14. Figure 15. Peak Detector Voltage vs Pin 3 VIN, Mode 3 Figure 16. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM1815 5 LM1815 SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 www.ti.com TRUTH TABLE Signal Input Pin 3 RC Timing Pin 14 Input Select Pin 11 Timing Input Pin 9 Gated Output Pin 10 ± Pulses RC L X Pulses = RC X X H H H X X H L L ± Pulses L L L Zero Crossing Figure 17. LM1815 Adaptive Sense Amplifier 6 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM1815 LM1815 www.ti.com SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 Schematic Diagram Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM1815 7 LM1815 SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 www.ti.com APPLICATION HINTS Figure 18. LM1815 Oscillograms INPUT VOLTAGE CLAMP The signal input voltage at pin 3 is internally clamped. Current limit for the Input pin is provided by an external resistor which should be selected to allow a peak current of ±3 mA in normal operation. Positive inputs are clamped by a 1kΩ resistor and series diode (see R4 and Q12 in the internal schematic diagram), while an active clamp limits pin 3 to typically 350mV below Ground for negative inputs (see R2, R3, Q10, and Q11 in the internal schematic diagram). Thus for input signal transitions that are more than 350mV below Ground, the input pin current (up to 3mA) will be pulled from the V+ supply. If the V+ pin is not adequately bypassed the resulting voltage ripple at the V+ pin will disrupt normal device operation. Likewise, for input signal transitions that are more than 500mV above Ground, the input pin current will be dumped to Ground through device pin 2. Slight shifts in the Ground potential at device pin 2, due to poor grounding techniques relative to the input signal ground, can cause unreliable operation. As always, adequate device grounding, and V+ bypassing, needs to be considered across the entire input voltage and frequency range for the intended application. INPUT CURRENT LIMITING As stated earlier, current limiting for the Input pin is provided by a user supplied external resistor. For purposes of selecting the appropriate resistor value the Input pin should be considered to be a zero ohm connection to ground. For applications where the input voltage signal is not symmetrical with relationship to Ground the worst case voltage peak should be used. Minimum Rext = [(Vin peak)/3mA] In the application example shown in Figure 17 (Rext = 18kΩ) the recommended maximum input signal voltage is ±54V (i.e. 108Vp-p). OPERATION OF ZERO CROSSING DETECTOR The LM1815 is designed to operate as a zero crossing detector, triggering an internal one shot on the negativegoing edge of the input signal. Unlike other zero crossing detectors, the LM1815 cannot be triggered until the input signal has crossed an "arming" threshold on the positive-going portion of the waveform. The arming circuit is reset when the chip is triggered, and subsequent zero crossings are ignored until the arming threshold is exceeded again. This threshold varies depending on the connection at pin 5. Three different modes of operation are possible: 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM1815 LM1815 www.ti.com SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 MODE 1, PIN 5 OPEN The adaptive mode is selected by leaving device pin 5 open circuit. For input signals of less than ±135mV (i.e. 270 mVp-p) and greater than typically ±75mV (i.e. 150mVp-p), the input arming threshold is typically at 45mV. Under these conditions the input signal must first cross the 45mV threshold in the positive direction to arm the zero crossing detector, and then cross zero in the negative direction to trigger it. If the signal is less than 30mV peak (minimum rating in Electrical Characteristics), the one shot is ensured to not trigger. Input signals of greater than ±230mV (i.e. 460 mVp-p) will cause the arming threshold to track at 80% of the peak input voltage. A peak detector capacitor at device pin 7 stores a value relative to the positive input peaks to establish the arming threshold. Input signals must exceed this threshold in the positive direction to arm the zero crossing detector, which can then be triggered by a negative-going zero crossing. The peak detector tracks rapidly as the input signal amplitude increases, and decays by virtue of the resistor connected externally at pin 7 track decreases in the input signal. If the input signal amplitude falls faster than the voltage stored on the peak detector capacitor there may be a loss of output signal until the capacitor voltage has decayed to an appropriate level. Note that since the input voltage is clamped, the waveform observed at pin 3 is not identical to the waveform observed at the variable reluctance sensor. Similarly, the voltage stored at pin 7 is not identical to the peak voltage appearing at pin 3. MODE 2, PIN 5 CONNECTED TO V+ The input arming threshold is fixed at 200mV minimum when device pin 5 is connected to the positive supply. The chip has no output for signals of less than ±200 mV (i.e. 400mVp-p) and triggers on the next negative-going zero crossing when the arming threshold is has been exceeded. MODE 3, PIN 5 GROUNDED With pin 5 grounded, the input arming threshold is set to 0V, ±25mV maximum. Positive-going zero crossings arm the chip, and the next negative-going zero crossing triggers it. This is the very basic form of zero-crossing detection. ONE SHOT TIMING The one shot timing is set by a resistor and capacitor connected to pin 14. The recommended maximum resistor value is 150kohms. The capacitor value can be changed as needed, as long as the capacitor type does not present any signfigant leakage that would adversely affect the RC time constant. The output pulse width is: pulse width = 0.673 x R x C (1) For a given One Shot pulse width, the recommended maximum input signal frequency is: Fin(max) = 1/(1.346 x R x C) (2) In the application example shown in Figure 17 (R=150kohms, C=0.001µF) the recommended maximum input frequency will typically be 5kHz. Operating with input frequencies above the recommended Fin (max) value may result in unreliable performance of the One Shot circuitry. For those applications where the One Shot circuit is not required, device pin 14 can be tied directly to Ground. LOGIC INPUTS In some systems it is necessary to externally generate pulses, such as during stall conditions when the variable reluctance sensor has no output. External pulse inputs at pin 9 are gated through to pin 10 when Input Select (pin 11) is pulled high. Pin 12 is a direct output for the one shot and is unaffected by the status of pin 11. Input/output pins 9, 11, 10, and 12 are all CMOS logic compatible. In addition, pins 9, 11, and 12 are TTL compatible. Pin 10 is not ensured to drive a TTL load. Pins 1, 4, 6 and 13 have no internal connections and can be grounded. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM1815 9 LM1815 SNOSBU8F – SEPTEMBER 2000 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM1815 PACKAGE OPTION ADDENDUM www.ti.com 19-Mar-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM1815M NRND SOIC D 14 55 TBD Call TI Call TI -40 to 125 LM1815M LM1815M/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM1815M LM1815MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM1815M LM1815N/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LM1815N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM1815MX/NOPB Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.35 2.3 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM1815MX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NFF0014A N0014A N14A (Rev G) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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